RVCE Dept. of ECE VLSI Design Lab Procedure

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Experiment:3

CMOS Inverter Dynamic Characteristics

3.1 Lab conduction procedures

Since this lab address 1. Linearizing Ron, and 2. Find the ratio Wp/Wn at which equal

rise time and fall time, it requires two design procedures.

3.2 Ron linearization procedure

Here the procedure for Ron of NMOS is given. This can be extended to PMOS to

calculate the equivalent resistance of it.

3.2.1 Creating Schematic

Create a schematic with the following specification as shown in Figure 3-1.

Figure 3-1: Circuit for calculating Req of NMOS

Library Name Cell Name Instance Name Properties / Comments

analoglib vpulse V0 Voltage 1 = 0 V

Voltage 2 = 1.8 V

Period = 20n s

Pulse Width = 10n s

C0 Capacitance = 5p F

Initial condition = 1.8 V

gpdk180 Nmos NM0 Default

3.2.2 Analysis setup

For this experiment only tran Analysis is required to plot.

RVCE Dept. of ECE VLSI Design Lab Procedure

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Transient plot:

Analysis setup

Select “tran” analysis.

Provide Stop time as 30n.

Check accuracy default as moderate and click OK.

Output definition

Select “Outputs → To be Plotted → Select on Schematic”

Select “vin” and “vout” nodes and press ESC.

Plot

Click the “Run” button.

Select “Tools → Calculator” in the waveform window.

Check wave radio button and select the “vin” node first and then select the “vout”

node from the schematic.

In the calculator window, select “Delay” function from the Special function sub-

window. Mirror the following parameters as shown below.

Evaluate the buffer.

3.3

ratio procedure

3.3.1 Creating Schematic

To build the schematic, modify the inverter cell built during experiment no. 1.

RVCE Dept. of ECE VLSI Design Lab Procedure

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Modify the inverter schematic of Experiment no.1.

In the CIW window, select “File → open” and select the design inverter schematic.

Modify the PMOS Total width parameter to “b*2u” (without quotes and no spacing

between the expression given in double quotes).

Click “Check and save”.

Create schematic

Create a schematic with the following specification as shown in .

Figure 3-2: Test Schematic for finding

ratio

Library Name Cell Name Instance Name Properties / Comments

analoglib vdc V0 DC Voltage = 0.9 V

V1 DC Voltage = 0.9 V

Vpulse V2 Voltage 1 = 0.9 V

Voltage 2 = -0.9 V

Period = 20n s

Pulse Width = 10n s

<your library> <first exp inverter

design cell>

Symbol

3.3.2 Analysis setup

For this experiment only tran Analysis is required to plot.

Transient plot:

“Variables → Copy From Cellview”. Define “1” for the “b” variable.

Analysis setup

Select “tran” analysis.

Provide Stop time as 30n.

Check accuracy default as moderate and click OK.

RVCE Dept. of ECE VLSI Design Lab Procedure

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Output definition

In ADE window, select “Outputs -> setup”

tPHL definition

Define “tPHL” for Name (opt) label.

Click “Open” to open the calculator, select “vt” radio button and go to test schematic.

Figure 3-3: Transient Voltage

Select first “vout” node and then “vin” node.

Return back to the calculator, and select “delay” function under special function.

Mirror the setting as shown in Figure 3-4.

Click “Apply”. Note: Don’t click on OK, because we need it to define tPLH variable.

Figure 3-4: settings for tPHL calculation

Switch back to “setting outputs” window by pressing “Alt+Tab” key and click on

“Get Expression”, the expression from the calculator buffer gets copied on to the Expression.

Click Add.

tPLH definition

In the same setting outputs window, click “New Expression” and define “tPLH” in the

Name (opt) label.

Switch back to calculator window and change “Edge Type 1” as Falling and “Edge

Type 2” as rising in the delay function. Click OK.

Again navigate to setting outputs window and click on “Get Expression”.

RVCE Dept. of ECE VLSI Design Lab Procedure

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Click Add.

tD definition

In the same setting outputs window, click “New Expression” and define “tD” in the

Name (opt) lable.

Switch back to calculator window and click on “+’ button in the key pad sub-window.

This will add the current tPLH expression, which is in the buffer, to the first stack expression,

tPHL.

Now to divide the sum of (tPLH + tPHL) expression, click on button, such that it

pushes the current buffer expression on to the stack.

Now enter “2” in the buffer and click on “/” divide button in the key pad sub-window.

Return back to the output settings window and click on “Get Expression” button.

Click Add and OK.

Delay plot

In the ADE window, click “Tools→ Parametric Analysis”. Enter the following details

as shown below.