extraction and comparison of interface trap formation...

Extraction and Comparison of Interface

Trap Formation During BTI Stress in SiC

Power MOSFETs Using Subthreshold

Characteristics

David R. Hughart, Jack D. Flicker, Stanley Atcitty,

Matthew J. Marinella, and Robert J. Kaplar

Sandia National Laboratories

This work was supported by Dr. Imre Gyuk of the United States Department of Energy, Office of Electricity Delivery and

Energy Reliability, Energy Storage Program

Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation,

a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s

National Nuclear Security Administration under contract DE-AC04-94AL85000.

2

Purpose

• Silicon Carbide (SiC) devices are theoretically

superior to Si for power electronics applications

• Reliability concerns have limited implementation

– High interface trap density

– Vth instability at elevated temperature and biases

• Evaluation of interface trap density on vertical SiC

power MOSFETs difficult without MOS capacitors

and processing information from the manufacturer

• The increase in interface trap density after stress

can be extracted solely from subthreshold I-V curves

3

Outline

• Introduction

• Method Overview

• Extraction with an Assumed Doping Density

– Normalizing Energy Levels and ∆DIT

• Sensitivity Analysis

– Doping Concentration

– Threshold Voltage

– Oxide Capacitance

• Improvements in ∆DIT for SiC MOSFETs

• Conclusions

4

Gate Oxide Reliability Has Limited

the Adoption of SiC MOSFETs Charge injection due to

small band offset at

SiO2/SiC interface

enhances VT shift

Diagram source: International Rectifier, “Power MOSFET Basics”

Critical gate

oxide

interfacial

region

R. Singh, Microelectronics Reliability 46, 713 (2006).

The typical SiC power MOSFET structure (vertical DMOS) is

not ideal for charge pumping since there is no body tie

5

Bias-Temperature Stress: ∆Vth and

Increase in MOS Interface State Density

Stress: VGS = +20 V, VDS = 0.1 V

Minimal degradation

at rated temp (125˚C) Commercial

1200 V

SiC MOSFET

Severe degradation

at high temp

S. DasGupta et al., Appl. Phys. Lett. 99, 023503 (2011).

6

Method Details

7

DIT at the Band Edges

• SiC has DIT profiles that rise sharply towards the band edges

• This causes the subthreshold slope to vary with gate voltage – Enables extraction of

DIT profiles G. Y. Chung et al., Appl. Phys. Lett. 76, 1713 (2000).

8

Method Overview

1) Establish a relationship between gate

voltage and surface potential

2) Solve for changes in VIT (voltage term for

the contribution of trapped interfacial

charge) for small intervals of surface

potential

3) Solve for DIT over these intervals based on ∆VIT and construct a DIT profile

9

Gate Voltage and Surface Potential

• Solve for ID0 at

threshold

– Determine Ith from

I-V curve

– Surface potential at

threshold known in

relation to doping

10 0 110

-10

10-9

10-8

10-7

I D (

A)

VG (V)

0 1 2 3 4 5 6 7 8 9 1010

-1010

-910

-810

-710

-610

-510

-410

-310

-210

-110

0

I D (

A)

VG (V)

Calculating DIT

0.0 0.1 0.2 0.3 0.4 0.5

1012

1013

DIT (

cm

-2 e

V-1)

Ec-E (eV)

11

Example Calculation

• Analysis of stresses performed on

commercially available parts

• No knowledge of process parameters

– Doping concentration assumed

• Three steps

– Extraction

– Normalization

– Subtraction

Extraction → Normalization → Subtraction

12

Extraction with Assumed Doping

• I-V curves for a SiC power MOSFET

0 1 2 3 4 5 6 7 8 9 1010

-1010

-910

-810

-710

-610

-510

-410

-310

-210

-110

0

Pre-stress

Post-stress

I D (

A)

VG (V)

-20 V for 30 min at 175C

VDS

= 100 mV

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

1012

1013 Post-stress

1017

cm-3

2 1017

cm-3

5 1017

cm-3

1018

cm-3

DIT (

cm

-2 e

V-1)

Ec-E (eV)

Pre-stress

• Variation in assumed doping values

causes shifts in the DIT profiles


13

Normalizing the Energy Level

• Varying the assumed doping changes the

bulk potential, altering φs at Vth

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

1012

1013 Post-stress

1017

cm-3

2 1017

cm-3

5 1017

cm-3

1018

cm-3

DIT (

cm

-2 e

V-1)

Ec-E (eV)

Pre-stress

• DIT profiles can be aligned by normalizing

the energy level to the Fermi level

0.0 0.1 0.2 0.3 0.4

1012

1013 Post-stress

1017

cm-3

2 1017

cm-3

5 1017

cm-3

1018

cm-3

DIT (

cm

-2 e

V-1)

EF,th

- E (eV)

Pre-stress


14

∆DIT Profiles

• Variations in assumed doping cause

changes in calculated DIT concentrations

• ∆DIT profiles are independent of assumed

doping concentration when referenced to EF,th

0.0 0.1 0.2 0.3 0.4

1012

1013 Post-stress

1017

cm-3

2 1017

cm-3

5 1017

cm-3

1018

cm-3

DIT (

cm

-2 e

V-1)

EF,th

- E (eV)

Pre-stress

0.0 0.1 0.2 0.3 0.4

1012

1013

1017

cm-3

2 1017

cm-3

5 1017

cm-3

1018

cm-3

D

IT (

cm

-2 e

V-1)

EF,th

- E (eV)


15

Sources of Uncertainty

• Doping

– Doping is required to calculate parameters

like bulk potential

• Threshold voltage

– There are multiple ways to extract threshold

voltage that can yield different voltages

• Oxide thickness (capacitance)

– The insulator capacitance is used to calculate

VIT and DIT

16

Doping and Threshold Voltage

Dependence

• Assumed doping primarily alters the

energy level at which Vth is set

• The choice of threshold voltage affects

DIT concentration at that energy level

17

Doping Dependence

• Varying doping varies EF,th → Normalize to EF,th

– Using ∆DIT eliminates magnitude changes

18

Threshold Voltage Dependence

• The choice of Vth determines the value of

DIT at threshold

– Varying Vth effectively shifts the curve and

removes data for voltages above Vth

19

Threshold Voltage Extraction

Methods

• Transconductance

Derivative

– Unaffected by

series

resistance

and mobility

degradation

• Transconductance

• Constant Current 0 1 2 3 4 50.00

0.02

0.04

0.06

0.08

0.10

Tra

nsco

nd

ucta

nce

(S

)

Voltage (V)

Max slope

Vth, gm

derivative

Vth, gm

20

∆DIT Profiles for Varying Vth

Extractions

• gm derivative method and gm method show similar trends

• Constant current (1 mA) uses lower Vth

– Less points used

• 10 mA results are unphysical – Constant current

may not be accurate method for these devices

0.0 0.1 0.2 0.3 0.4

1012

1013

Transconductance Derivative

Transconductance

Constant Drain Current (10 mA)

Constant Drain Current (1 mA)

D

IT (

cm

-2 e

V-1)

EF,th

- E (eV)

21

Capacitance Dependence

• Calculated ∆DIT

varies with oxide

capacitance

– Oxide thickness

• ∆DIT changes by

the ratio of the

assumed Cox

– 70nm/50nm = 1.4

• Typical oxide

thickness range

small

0.0 0.1 0.2 0.3 0.4

1012

1013

50 nm

70 nm

D

IT (

cm

-2 e

V-1)

EF,th

- E (eV)

22

∆DIT Comparison Between SiC

MOSFET Generations

• DIT has been

reduced from the 1st

to 2nd generation of

SiC MOSFETs 0 1 2 3 4 5 6 7 8 9 10

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

Pre-stress

Post-stress

I D (

A)

VG (V)

-20 V for 30 min at 175C

VDS

= 100 mV

0.0 0.1 0.2 0.3 0.4

1012

1013

2nd Gen

1st Gen

D

IT (

cm

-2 e

V-1)

EF,th

- E (eV)

• Less information for

1st gen

– Equivalent voltage

sweep covers fewer

energies due to DIT

– Fewer I-V data points

1st Gen

2nd Gen

23

Conclusions

• ∆DIT profiles can be extracted from SiC MOSFETs

using subthreshold I-V curves

– Independent of assumed doping

– No MOS capacitors needed

– Impact of oxide thickness is minimal if the range is small

– Can calculate DIT values with additional information

• The choice of threshold voltage extraction method

must be considered carefully

– Constant current method may be of limited use

• This method provides a fast and easy way to

evaluate the effects of BT stress on SiC MOSFETs

extraction and comparison of interface trap formation...

Documents