eyeq2™ vision system on a chip
Post on 13-Sep-2014
3.089 views
DESCRIPTION
EyeQ2, Mobileye's System-on-Chip (SoC) delivers a second generation solution for computationally intensive applications of real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems. The EyeQ2 reflects a new philosophy of vision based processing platforms, and includes an optimal combination for vision scalar and vector processing on a single die, based on Mobileye's algorithm knowledge.TRANSCRIPT
.
EyeQ2™
Vision System on a Chip
FeaturesBenefits:
•
•
•
•
•
Reduces the driver's load and increases driving safety
Low-cost — suitable for mass implementation
Compact size, single board solution
High reliability and availability
Performs a wide range of additional comfort functions
Mobileye
www.mobileye.comMobileye Technologies Limited. All rights reserved, 9/2007Mobi leye®, MOBILEYE AWS™, SeeQ® and EyeQ™ are trademarks of Mobileye Technologies Limited.Specifications are subject to change without notice.
Our Vision. Your Safety.
EyeQ2 ebug supports
In addition to the standard JTAG, the device supports high visibility by two debug ports: This enables to trace the CPUs internal activity as well as the internal Interconnect’s bus transactions. This allows the programmer to optimize the internal bandwidth and the 11 processors performance.
16bit Program & Data trace (PDtrace). Lossless / Stall-free tracing of MIPS two CPUs
16bit Request-Response Trace (RRT). Innovated Lossless and Stall-free internal buses bandwidth and latency.
EyeQ™ development platform EPM2
The following development platform enables:
Record EyeQ Image processing to the PC
Download video streams from the PC to EyeQ2
Download new code to EyeQ2 from the PC
Download Calibration to EyeQ2 from the PC
•
•
• • • •
EyeQ2™
Vision System on a Chip
The Interconnect:
The interconnect provides a high connectivity scheme needed for providing the required data bandwidth of the vision processing. The M Interconnect routes the 11 master ports to the four slave ports and enables concurrent operation of up to four 128bit OCP busses. If there is a bus contention on a slave port, the Interconnect decides on the winning master according to the priority scheme.
16 channel DMA:
The 16 channel DMA Controller is located on the Master Port. The DMA Controller is programmed by the MIPS34K CPU to support the captured video streams via the Video Interfaces block, drive the processed video via the video out interface and for on and off chip general data transactions.
Two Floating Point MIPS34K hyper threads RISC CPU
The VCE/VMP modules are:Classifier Engine - CEImage scaling & preprocessing unitsPattern classifier units
Tracker Engine-TrkImage warping and motion analysis unit
Pre-process, Window-PWImage Convolver and image pyramid unitsComputes vertical and& horizontal edge maps
Filter Engine-FFeatures based classifier unit
Disparity Finder Engine-dFPowerful stereo engineProgrammable search, 2 pixel/clock
Vector Microcode module -VMP:A generic vector processing unit without cacheVector Microcode machine
Very Long Instruction Word (VLIW)Each field is a Single Instruction Multi Data (SIMD)Each Instruction takes one clockPipeline is handled by the programmer
Program and Data memories are localNo cacheDeterministic accesses
Instruction example (dx):{ R0=Read0; Next0; R1=R0;(R2, R0)=COMB(R1, R0); R3=HSUB(R1, R2); Write1(R3); Next1; Cont(0) }
• • •
•
• •
•
• •
• •
• •
Main features are:
Memory to memory, peripheral to memory, and peripheral to peripheral transfers
Scatter or qather DMA is supported through the use of linked lists
64bit AHB bus width
VCE engine
Local Memoryfor input or results images
DMA Channels
Short queuefor 8 vision tasks/results
32 bit OCP Slave Port"commands"
64 bit OCP Master Port "images"
computing of major time-consuming image processing tasks. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. Ahigh-speed, 128bit width, 512Kbyte on-chip SRAM is located on this interconnect for fast image memory storage and retrieval.
Two MIPS34K hyper tread CPUs:
332 MHz operation
32KB Data and Instruction Caches
32KB and 8KB scratch pad memories
Four treads per Core
Interthread Unit for fast MIPS to MIPS communication
Floating Point Arithmetic Units
EyeQ2™ has two video in and one video out interfaces:
Video In
Supports a wide array of formats: Monochrome, Bayer, RGB, Y:Cb:Cr
Input frame size – up to 2048 x 2048 (Bayer)
Four data channels Blurring, Sub-sampling, g curve approximation per channel
Programmable Cropping frame size per channel
Up to four histograms per channel
Video Out
Supports RGB (5-6-5, 6-6-6, 8bit), Y:Cb:Cr 4:2:2 (8-8,8bit)
Output frame size – up to 4096 x 2048 Two layers (Image and Graphics)
Transparency - å-blending LUT for data layer generation
EyeQ2™ has the following interfaces:
A separate 32-bit low bandwidth Peripheral Bus (APB) is provided to connect all of the various peripherals such as the CAN Controllers
High connectivity
2 x CAN 2.0 ports
2 x UART ports
I2C slave/master port
32bit GPIO port
8 Timers
car interface connector
keypad-optional
car battery
host interface connector
host pc
EPM2
GPIO 2 x CAN
1000Mb
TCPIPSIM2
CAM
MOD
I/F
ICE + TRACE TOOLS
PDt/RRTJTAG
EyeQ2cameramodule
cameramodule
CON
LVDS
#1 balls fd14 and fd15 should have a weak pull-up#2 por_vdd ball should have an RC#3 I2C balls should have pull-up according the I2C spec#4 balls should be connectd to gnd#5 ball fd13 should be connected to weak pull-up for a crystal and a weak pull-down for an external clock
#6 An external resisitor of 121 Khom should be connected between the two balls#7 balls should not be connected to 1.8V unless port is not used. If the port is not used shoud be connected to ground in order to save leakage current
#8 ball tdbgint should have a week pull-down#9 fc3_n and fc1_n are used for SIM2
• • • • • •
•
•
•
•
• • •
• •
•
• • • •
• • • • •
EyeQ2™
Vision System on a Chip
Technology
EyeQ2™ Vision System on a Chip
EyeQ2, Mobileye's System-on-Chip (SoC) delivers a second generation solution for computationally intensive applications of real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems. The EyeQ2 reflects a new philosophy of vision based processing platforms, and includes an optimal combination for vision scalar and vector processing on a single die, based on Mobileye's algorithm knowledge.
EyeQ2 will be launched in 2009,start of production, involving a consolidated feature package of lanes, vehicles, pedestrian detection, and fusion. An engineering sample will be available in the first quarter of 2008. Mobileye EyeQ is manufactured by STMicroelectronics.
The chip architecture is designed to run a full-fledged application on a single chip, and is completely programmable to accommodate a wide range of visual processing applications beyond automotive specific applications.
EyeQ2 is manufactured using the leading STMicroelectronics CMOS 90nm-micron technology, operating at 332 MHz. To optimize cost performance, all peripheral interfaces are integrated into the SoC, including dual CAN Controllers; dual UART, I2C, Mobile DDR SDRAM controller, parallel I/O, dual video image data capture and video out units.
Mobileye’s SDK (System Development Kit) for EyeQ2 provides a comprehensive work environment for developers of EyeQ2-based applications. It is also suitable for inexperienced developers. The SDK is provided with Mobileye vision algorithm libraries.
The EyeQ2 architecture consists of two floating point, hyper-thread 64bit RISC 34KMIPS CPUs, five Vision Computing Engines (VCE), three Vector Microcode Processors (VMP), Denali 64bit Mobile DDR Controller, 128bit internal Sonics Interconnect, dual 16bit Video input and 18bit Video output controllers, 16 channels DMA and several peripherals. The MIPS34K CPU manages the five VCEs, three VMP and the DMA, the second MIPS34K CPU and the multi-channel DMA as well as the other peripherals. The five VCEs, three VMP and the MIPS34K CPU perform all the intensive
vision computations required by the applications such as tracking and pattern classification.
The Sonics Interconnect:
Vision Computing Engine (VCE) and Vector Microcode Machine (VMP): EyeQ2 has five VCEs and three VMPs optimized for
Expandability
16-bit Flash/SRAM Ctrl
64/32-bit Mobile DDR-SDRAM - fast and Robust external memories
• •
.
EyeQ2™
Vision System on a Chip
FeaturesBenefits:
•
•
•
•
•
Reduces the driver's load and increases driving safety
Low-cost — suitable for mass implementation
Compact size, single board solution
High reliability and availability
Performs a wide range of additional comfort functions
Mobileye
www.mobileye.comMobileye Technologies Limited. All rights reserved, 9/2007Mobi leye®, MOBILEYE AWS™, SeeQ® and EyeQ™ are trademarks of Mobileye Technologies Limited.Specifications are subject to change without notice.
Our Vision. Your Safety.
EyeQ2 ebug supports
In addition to the standard JTAG, the device supports high visibility by two debug ports: This enables to trace the CPUs internal activity as well as the internal Interconnect’s bus transactions. This allows the programmer to optimize the internal bandwidth and the 11 processors performance.
16bit Program & Data trace (PDtrace). Lossless / Stall-free tracing of MIPS two CPUs
16bit Request-Response Trace (RRT). Innovated Lossless and Stall-free internal buses bandwidth and latency.
EyeQ™ development platform EPM2
The following development platform enables:
Record EyeQ Image processing to the PC
Download video streams from the PC to EyeQ2
Download new code to EyeQ2 from the PC
Download Calibration to EyeQ2 from the PC
•
•
• • • •
EyeQ2™
Vision System on a Chip
The Interconnect:
The interconnect provides a high connectivity scheme needed for providing the required data bandwidth of the vision processing. The M Interconnect routes the 11 master ports to the four slave ports and enables concurrent operation of up to four 128bit OCP busses. If there is a bus contention on a slave port, the Interconnect decides on the winning master according to the priority scheme.
16 channel DMA:
The 16 channel DMA Controller is located on the Master Port. The DMA Controller is programmed by the MIPS34K CPU to support the captured video streams via the Video Interfaces block, drive the processed video via the video out interface and for on and off chip general data transactions.
Two Floating Point MIPS34K hyper threads RISC CPU
The VCE/VMP modules are:Classifier Engine - CEImage scaling & preprocessing unitsPattern classifier units
Tracker Engine-TrkImage warping and motion analysis unit
Pre-process, Window-PWImage Convolver and image pyramid unitsComputes vertical and& horizontal edge maps
Filter Engine-FFeatures based classifier unit
Disparity Finder Engine-dFPowerful stereo engineProgrammable search, 2 pixel/clock
Vector Microcode module -VMP:A generic vector processing unit without cacheVector Microcode machine
Very Long Instruction Word (VLIW)Each field is a Single Instruction Multi Data (SIMD)Each Instruction takes one clockPipeline is handled by the programmer
Program and Data memories are localNo cacheDeterministic accesses
Instruction example (dx):{ R0=Read0; Next0; R1=R0;(R2, R0)=COMB(R1, R0); R3=HSUB(R1, R2); Write1(R3); Next1; Cont(0) }
• • •
•
• •
•
• •
• •
• •
Main features are:
Memory to memory, peripheral to memory, and peripheral to peripheral transfers
Scatter or qather DMA is supported through the use of linked lists
64bit AHB bus width
VCE engine
Local Memoryfor input or results images
DMA Channels
Short queuefor 8 vision tasks/results
32 bit OCP Slave Port"commands"
64 bit OCP Master Port "images"
computing of major time-consuming image processing tasks. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. Ahigh-speed, 128bit width, 512Kbyte on-chip SRAM is located on this interconnect for fast image memory storage and retrieval.
Two MIPS34K hyper tread CPUs:
332 MHz operation
32KB Data and Instruction Caches
32KB and 8KB scratch pad memories
Four treads per Core
Interthread Unit for fast MIPS to MIPS communication
Floating Point Arithmetic Units
EyeQ2™ has two video in and one video out interfaces:
Video In
Supports a wide array of formats: Monochrome, Bayer, RGB, Y:Cb:Cr
Input frame size – up to 2048 x 2048 (Bayer)
Four data channels Blurring, Sub-sampling, g curve approximation per channel
Programmable Cropping frame size per channel
Up to four histograms per channel
Video Out
Supports RGB (5-6-5, 6-6-6, 8bit), Y:Cb:Cr 4:2:2 (8-8,8bit)
Output frame size – up to 4096 x 2048 Two layers (Image and Graphics)
Transparency - å-blending LUT for data layer generation
EyeQ2™ has the following interfaces:
A separate 32-bit low bandwidth Peripheral Bus (APB) is provided to connect all of the various peripherals such as the CAN Controllers
High connectivity
2 x CAN 2.0 ports
2 x UART ports
I2C slave/master port
32bit GPIO port
8 Timers
car interface connector
keypad-optional
car battery
host interface connector
host pc
EPM2
GPIO 2 x CAN
1000Mb
TCPIPSIM2
CAM
MOD
I/F
ICE + TRACE TOOLS
PDt/RRTJTAG
EyeQ2cameramodule
cameramodule
CON
LVDS
#1 balls fd14 and fd15 should have a weak pull-up#2 por_vdd ball should have an RC#3 I2C balls should have pull-up according the I2C spec#4 balls should be connectd to gnd#5 ball fd13 should be connected to weak pull-up for a crystal and a weak pull-down for an external clock
#6 An external resisitor of 121 Khom should be connected between the two balls#7 balls should not be connected to 1.8V unless port is not used. If the port is not used shoud be connected to ground in order to save leakage current
#8 ball tdbgint should have a week pull-down#9 fc3_n and fc1_n are used for SIM2
• • • • • •
•
•
•
•
• • •
• •
•
• • • •
• • • • •
EyeQ2™
Vision System on a Chip
Technology
EyeQ2™ Vision System on a Chip
EyeQ2, Mobileye's System-on-Chip (SoC) delivers a second generation solution for computationally intensive applications of real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems. The EyeQ2 reflects a new philosophy of vision based processing platforms, and includes an optimal combination for vision scalar and vector processing on a single die, based on Mobileye's algorithm knowledge.
EyeQ2 will be launched in 2009,start of production, involving a consolidated feature package of lanes, vehicles, pedestrian detection, and fusion. An engineering sample will be available in the first quarter of 2008. Mobileye EyeQ is manufactured by STMicroelectronics.
The chip architecture is designed to run a full-fledged application on a single chip, and is completely programmable to accommodate a wide range of visual processing applications beyond automotive specific applications.
EyeQ2 is manufactured using the leading STMicroelectronics CMOS 90nm-micron technology, operating at 332 MHz. To optimize cost performance, all peripheral interfaces are integrated into the SoC, including dual CAN Controllers; dual UART, I2C, Mobile DDR SDRAM controller, parallel I/O, dual video image data capture and video out units.
Mobileye’s SDK (System Development Kit) for EyeQ2 provides a comprehensive work environment for developers of EyeQ2-based applications. It is also suitable for inexperienced developers. The SDK is provided with Mobileye vision algorithm libraries.
The EyeQ2 architecture consists of two floating point, hyper-thread 64bit RISC 34KMIPS CPUs, five Vision Computing Engines (VCE), three Vector Microcode Processors (VMP), Denali 64bit Mobile DDR Controller, 128bit internal Sonics Interconnect, dual 16bit Video input and 18bit Video output controllers, 16 channels DMA and several peripherals. The MIPS34K CPU manages the five VCEs, three VMP and the DMA, the second MIPS34K CPU and the multi-channel DMA as well as the other peripherals. The five VCEs, three VMP and the MIPS34K CPU perform all the intensive
vision computations required by the applications such as tracking and pattern classification.
The Sonics Interconnect:
Vision Computing Engine (VCE) and Vector Microcode Machine (VMP): EyeQ2 has five VCEs and three VMPs optimized for
Expandability
16-bit Flash/SRAM Ctrl
64/32-bit Mobile DDR-SDRAM - fast and Robust external memories
• •
.
EyeQ2™
Vision System on a Chip
FeaturesBenefits:
•
•
•
•
•
Reduces the driver's load and increases driving safety
Low-cost — suitable for mass implementation
Compact size, single board solution
High reliability and availability
Performs a wide range of additional comfort functions
Mobileye
www.mobileye.comMobileye Technologies Limited. All rights reserved, 9/2007Mobi leye®, MOBILEYE AWS™, SeeQ® and EyeQ™ are trademarks of Mobileye Technologies Limited.Specifications are subject to change without notice.
Our Vision. Your Safety.
EyeQ2 ebug supports
In addition to the standard JTAG, the device supports high visibility by two debug ports: This enables to trace the CPUs internal activity as well as the internal Interconnect’s bus transactions. This allows the programmer to optimize the internal bandwidth and the 11 processors performance.
16bit Program & Data trace (PDtrace). Lossless / Stall-free tracing of MIPS two CPUs
16bit Request-Response Trace (RRT). Innovated Lossless and Stall-free internal buses bandwidth and latency.
EyeQ™ development platform EPM2
The following development platform enables:
Record EyeQ Image processing to the PC
Download video streams from the PC to EyeQ2
Download new code to EyeQ2 from the PC
Download Calibration to EyeQ2 from the PC
•
•
• • • •
EyeQ2™
Vision System on a Chip
The Interconnect:
The interconnect provides a high connectivity scheme needed for providing the required data bandwidth of the vision processing. The M Interconnect routes the 11 master ports to the four slave ports and enables concurrent operation of up to four 128bit OCP busses. If there is a bus contention on a slave port, the Interconnect decides on the winning master according to the priority scheme.
16 channel DMA:
The 16 channel DMA Controller is located on the Master Port. The DMA Controller is programmed by the MIPS34K CPU to support the captured video streams via the Video Interfaces block, drive the processed video via the video out interface and for on and off chip general data transactions.
Two Floating Point MIPS34K hyper threads RISC CPU
The VCE/VMP modules are:Classifier Engine - CEImage scaling & preprocessing unitsPattern classifier units
Tracker Engine-TrkImage warping and motion analysis unit
Pre-process, Window-PWImage Convolver and image pyramid unitsComputes vertical and& horizontal edge maps
Filter Engine-FFeatures based classifier unit
Disparity Finder Engine-dFPowerful stereo engineProgrammable search, 2 pixel/clock
Vector Microcode module -VMP:A generic vector processing unit without cacheVector Microcode machine
Very Long Instruction Word (VLIW)Each field is a Single Instruction Multi Data (SIMD)Each Instruction takes one clockPipeline is handled by the programmer
Program and Data memories are localNo cacheDeterministic accesses
Instruction example (dx):{ R0=Read0; Next0; R1=R0;(R2, R0)=COMB(R1, R0); R3=HSUB(R1, R2); Write1(R3); Next1; Cont(0) }
• • •
•
• •
•
• •
• •
• •
VCE engine
Local Memoryfor input or results images
DMA Channels
Short queuefor 8 vision tasks/results
32 bit OCP Slave Port"commands"
64 bit OCP Master Port "images"
computing of major time-consuming image processing tasks. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. Ahigh-speed, 128bit width, 512Kbyte on-chip SRAM is located on this interconnect for fast image memory storage and retrieval.
Two MIPS34K hyper tread CPUs:
332 MHz operation
32KB Data and Instruction Caches
32KB and 8KB scratch pad memories
Four treads per Core
Interthread Unit for fast MIPS to MIPS communication
Floating Point Arithmetic Units
#1 balls fd14 and fd15 should have a weak pull-up#2 por_vdd ball should have an RC#3 I2C balls should have pull-up according the I2C spec#4 balls should be connectd to gnd#5 ball fd13 should be connected to weak pull-up for a crystal and a weak pull-down for an external clock
#6 An external resisitor of 121 Khom should be connected between the two balls#7 balls should not be connected to 1.8V unless port is not used. If the port is not used shoud be connected to ground in order to save leakage current
#8 ball tdbgint should have a week pull-down#9 fc3_n and fc1_n are used for SIM2
• • • • • •
Technology
EyeQ2™ Vision System on a Chip
EyeQ2, Mobileye's System-on-Chip (SoC) delivers a second generation solution for computationally intensive applications of real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems. The EyeQ2 reflects a new philosophy of vision based processing platforms, and includes an optimal combination for vision scalar and vector processing on a single die, based on Mobileye's algorithm knowledge.
EyeQ2 will be launched in 2009,start of production, involving a consolidated feature package of lanes, vehicles, pedestrian detection, and fusion. An engineering sample will be available in the first quarter of 2008. Mobileye EyeQ is manufactured by STMicroelectronics.
The chip architecture is designed to run a full-fledged application on a single chip, and is completely programmable to accommodate a wide range of visual processing applications beyond automotive specific applications.
EyeQ2 is manufactured using the leading STMicroelectronics CMOS 90nm-micron technology, operating at 332 MHz. To optimize cost performance, all peripheral interfaces are integrated into the SoC, including dual CAN Controllers; dual UART, I2C, Mobile DDR SDRAM controller, parallel I/O, dual video image data capture and video out units.
Mobileye’s SDK (System Development Kit) for EyeQ2 provides a comprehensive work environment for developers of EyeQ2-based applications. It is also suitable for inexperienced developers. The SDK is provided with Mobileye vision algorithm libraries.
The EyeQ2 architecture consists of two floating point, hyper-thread 64bit RISC 34KMIPS CPUs, five Vision Computing Engines (VCE), three Vector Microcode Processors (VMP), Denali 64bit Mobile DDR Controller, 128bit internal Sonics Interconnect, dual 16bit Video input and 18bit Video output controllers, 16 channels DMA and several peripherals. The MIPS34K CPU manages the five VCEs, three VMP and the DMA, the second MIPS34K CPU and the multi-channel DMA as well as the other peripherals. The five VCEs, three VMP and the MIPS34K CPU perform all the intensive
vision computations required by the applications such as tracking and pattern classification.
The Sonics Interconnect:
Vision Computing Engine (VCE) and Vector Microcode Machine (VMP): EyeQ2 has five VCEs and three VMPs optimized for
Main features are:
Memory to memory, peripheral to memory, and peripheral to peripheral transfers
Scatter or qather DMA is supported through the use of linked lists
64bit AHB bus width
EyeQ2™ has two video in and one video out interfaces:
Video In
Supports a wide array of formats: Monochrome, Bayer, RGB, Y:Cb:Cr
Input frame size – up to 2048 x 2048 (Bayer)
Four data channels Blurring, Sub-sampling, g curve approximation per channel
Programmable Cropping frame size per channel
Up to four histograms per channel
Video Out
Supports RGB (5-6-5, 6-6-6, 8bit), Y:Cb:Cr 4:2:2 (8-8,8bit)
Output frame size – up to 4096 x 2048 Two layers (Image and Graphics)
Transparency - å-blending LUT for data layer generation
EyeQ2™ has the following interfaces:
A separate 32-bit low bandwidth Peripheral Bus (APB) is provided to connect all of the various peripherals such as the CAN Controllers
High connectivity
2 x CAN 2.0 ports
2 x UART ports
I2C slave/master port
32bit GPIO port
8 Timers
car interface connector
keypad-optional
car battery
host interface connector
host pc
EPM2
GPIO 2 x CAN
1000Mb
TCPIPSIM2
CAM
MOD
I/F
ICE + TRACE TOOLS
PDt/RRTJTAG
EyeQ2cameramodule
cameramodule
CON
LVDS
•
•
•
•
• • •
• •
•
• • • •
• • • • •
EyeQ2™
Vision System on a Chip
Expandability
16-bit Flash/SRAM Ctrl
64/32-bit Mobile DDR-SDRAM - fast and Robust external memories
• •
.
EyeQ2™
Vision System on a Chip
FeaturesBenefits:
•
•
•
•
•
Reduces the driver's load and increases driving safety
Low-cost — suitable for mass implementation
Compact size, single board solution
High reliability and availability
Performs a wide range of additional comfort functions
Mobileye
www.mobileye.comMobileye Technologies Limited. All rights reserved, 9/2007Mobi leye®, MOBILEYE AWS™, SeeQ® and EyeQ™ are trademarks of Mobileye Technologies Limited.Specifications are subject to change without notice.
Our Vision. Your Safety.
EyeQ2 ebug supports
In addition to the standard JTAG, the device supports high visibility by two debug ports: This enables to trace the CPUs internal activity as well as the internal Interconnect’s bus transactions. This allows the programmer to optimize the internal bandwidth and the 11 processors performance.
16bit Program & Data trace (PDtrace). Lossless / Stall-free tracing of MIPS two CPUs
16bit Request-Response Trace (RRT). Innovated Lossless and Stall-free internal buses bandwidth and latency.
EyeQ™ development platform EPM2
The following development platform enables:
Record EyeQ Image processing to the PC
Download video streams from the PC to EyeQ2
Download new code to EyeQ2 from the PC
Download Calibration to EyeQ2 from the PC
•
•
• • • •
EyeQ2™
Vision System on a Chip
The Interconnect:
The interconnect provides a high connectivity scheme needed for providing the required data bandwidth of the vision processing. The M Interconnect routes the 11 master ports to the four slave ports and enables concurrent operation of up to four 128bit OCP busses. If there is a bus contention on a slave port, the Interconnect decides on the winning master according to the priority scheme.
16 channel DMA:
The 16 channel DMA Controller is located on the Master Port. The DMA Controller is programmed by the MIPS34K CPU to support the captured video streams via the Video Interfaces block, drive the processed video via the video out interface and for on and off chip general data transactions.
Two Floating Point MIPS34K hyper threads RISC CPU
The VCE/VMP modules are:Classifier Engine - CEImage scaling & preprocessing unitsPattern classifier units
Tracker Engine-TrkImage warping and motion analysis unit
Pre-process, Window-PWImage Convolver and image pyramid unitsComputes vertical and& horizontal edge maps
Filter Engine-FFeatures based classifier unit
Disparity Finder Engine-dFPowerful stereo engineProgrammable search, 2 pixel/clock
Vector Microcode module -VMP:A generic vector processing unit without cacheVector Microcode machine
Very Long Instruction Word (VLIW)Each field is a Single Instruction Multi Data (SIMD)Each Instruction takes one clockPipeline is handled by the programmer
Program and Data memories are localNo cacheDeterministic accesses
Instruction example (dx):{ R0=Read0; Next0; R1=R0;(R2, R0)=COMB(R1, R0); R3=HSUB(R1, R2); Write1(R3); Next1; Cont(0) }
• • •
•
• •
•
• •
• •
• •
VCE engine
Local Memoryfor input or results images
DMA Channels
Short queuefor 8 vision tasks/results
32 bit OCP Slave Port"commands"
64 bit OCP Master Port "images"
computing of major time-consuming image processing tasks. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. All the VCEs work in parallel, retrieving their tasks from task queues (one per each VCE) by the on-block DMA channels. The VCEs and VMPs communicate over the high bandwidth interconnect block, via a common master port. The task queues are managed by the on-block DMA channels. Ahigh-speed, 128bit width, 512Kbyte on-chip SRAM is located on this interconnect for fast image memory storage and retrieval.
Two MIPS34K hyper tread CPUs:
332 MHz operation
32KB Data and Instruction Caches
32KB and 8KB scratch pad memories
Four treads per Core
Interthread Unit for fast MIPS to MIPS communication
Floating Point Arithmetic Units
#1 balls fd14 and fd15 should have a weak pull-up#2 por_vdd ball should have an RC#3 I2C balls should have pull-up according the I2C spec#4 balls should be connectd to gnd#5 ball fd13 should be connected to weak pull-up for a crystal and a weak pull-down for an external clock
#6 An external resisitor of 121 Khom should be connected between the two balls#7 balls should not be connected to 1.8V unless port is not used. If the port is not used shoud be connected to ground in order to save leakage current
#8 ball tdbgint should have a week pull-down#9 fc3_n and fc1_n are used for SIM2
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Technology
EyeQ2™ Vision System on a Chip
EyeQ2, Mobileye's System-on-Chip (SoC) delivers a second generation solution for computationally intensive applications of real-time visual recognition and scene interpretation and has cabin-grade automotive qualification for use in intelligent vehicle systems. The EyeQ2 reflects a new philosophy of vision based processing platforms, and includes an optimal combination for vision scalar and vector processing on a single die, based on Mobileye's algorithm knowledge.
EyeQ2 will be launched in 2009,start of production, involving a consolidated feature package of lanes, vehicles, pedestrian detection, and fusion. An engineering sample will be available in the first quarter of 2008. Mobileye EyeQ is manufactured by STMicroelectronics.
The chip architecture is designed to run a full-fledged application on a single chip, and is completely programmable to accommodate a wide range of visual processing applications beyond automotive specific applications.
EyeQ2 is manufactured using the leading STMicroelectronics CMOS 90nm-micron technology, operating at 332 MHz. To optimize cost performance, all peripheral interfaces are integrated into the SoC, including dual CAN Controllers; dual UART, I2C, Mobile DDR SDRAM controller, parallel I/O, dual video image data capture and video out units.
Mobileye’s SDK (System Development Kit) for EyeQ2 provides a comprehensive work environment for developers of EyeQ2-based applications. It is also suitable for inexperienced developers. The SDK is provided with Mobileye vision algorithm libraries.
The EyeQ2 architecture consists of two floating point, hyper-thread 64bit RISC 34KMIPS CPUs, five Vision Computing Engines (VCE), three Vector Microcode Processors (VMP), Denali 64bit Mobile DDR Controller, 128bit internal Sonics Interconnect, dual 16bit Video input and 18bit Video output controllers, 16 channels DMA and several peripherals. The MIPS34K CPU manages the five VCEs, three VMP and the DMA, the second MIPS34K CPU and the multi-channel DMA as well as the other peripherals. The five VCEs, three VMP and the MIPS34K CPU perform all the intensive
vision computations required by the applications such as tracking and pattern classification.
The Sonics Interconnect:
Vision Computing Engine (VCE) and Vector Microcode Machine (VMP): EyeQ2 has five VCEs and three VMPs optimized for
Main features are:
Memory to memory, peripheral to memory, and peripheral to peripheral transfers
Scatter or qather DMA is supported through the use of linked lists
64bit AHB bus width
EyeQ2™ has two video in and one video out interfaces:
Video In
Supports a wide array of formats: Monochrome, Bayer, RGB, Y:Cb:Cr
Input frame size – up to 2048 x 2048 (Bayer)
Four data channels Blurring, Sub-sampling, g curve approximation per channel
Programmable Cropping frame size per channel
Up to four histograms per channel
Video Out
Supports RGB (5-6-5, 6-6-6, 8bit), Y:Cb:Cr 4:2:2 (8-8,8bit)
Output frame size – up to 4096 x 2048 Two layers (Image and Graphics)
Transparency - å-blending LUT for data layer generation
EyeQ2™ has the following interfaces:
A separate 32-bit low bandwidth Peripheral Bus (APB) is provided to connect all of the various peripherals such as the CAN Controllers
High connectivity
2 x CAN 2.0 ports
2 x UART ports
I2C slave/master port
32bit GPIO port
8 Timers
car interface connector
keypad-optional
car battery
host interface connector
host pc
EPM2
GPIO 2 x CAN
1000Mb
TCPIPSIM2
CAM
MOD
I/F
ICE + TRACE TOOLS
PDt/RRTJTAG
EyeQ2cameramodule
cameramodule
CON
LVDS
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EyeQ2™
Vision System on a Chip
Expandability
16-bit Flash/SRAM Ctrl
64/32-bit Mobile DDR-SDRAM - fast and Robust external memories
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