ezdsp f28335 reference technical

eZdspTM F28335

2007 DSP Development Systems

ReferenceTechnical

eZdspTM F28335 Technical Reference

510195-0001 Rev. CNovember 2007

SPECTRUM DIGITAL, INC.12502 Exchange Dr., Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware, products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user, at his own expense, will be required to take any measures necessary to correct this interference.

TRADEMARKS

eZdsp is a trademark of Spectrum Digital, Inc.

Copyright © 2007 Spectrum Digital, Inc.

Contents

1 Introduction to the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides a description of the eZdspTM F28335, key features, and board outline.

1.0 Overview of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.1 Key Features of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.1 Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.1.2 Software Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 Functional Overview of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

2 Operation of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the eZdspTM F28335. Information is provided on the eZdsp’s various interfaces.

2.0 The eZdspTM F28335 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1 The eZdspTM F28335 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2 eZdspTM F28335 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.3 eZdspTM F28335 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.3 P4,P8,P7, I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.3.4 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.5 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.6 P10 Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.7 P11, CANA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.8 P12, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.9 J11, CANB 5 x 2 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.10 J12, SCI-B 5 x 2 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.11 J201, Embedded USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.12 Connector Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4 eZdspTM F28335 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.1 JP1, ADCREFIN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.2 JR2, XTPD Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.3 JR4, Connector P4, P8 Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.4.4 JR5, Connector P2, P10 Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.4.5 JR6, MUX GPIO22_24 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.4.6 JP7, CANA Termination Resistor Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.4.7 JP8, CANB Termination Resistor Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23

2.6 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.6.1 SW1, Boot Load Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.6.2 SW2, Processor Configuration Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.7 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26

A eZdspTM F28335 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the eZdspTM F28335

B eZdspTM F28335 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the eZdspTM F28335

List of Figures

Figure 1-1, Photo eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Figure 1-2, Block Diagram eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

Figure 2-1, eZdspTM F28335 PCB Outline (Top) . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Figure 2-2, eZdspTM F28335 PCB Outline (Bottom) . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 2-3, eZdspTM F28335 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Figure 2-4, P1 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Figure 2-5, Connector P2 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Figure 2-6, Connector P4/P8/P7 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Figure 2-7, Connector P5/P9 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Figure 2-8, Connector P6 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

Figure 2-9, eZdspTM F28335 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Figure 2-10, Connector P10 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Figure 2-11, P11, DB9 CANA Female Connector . . . . . . . . . . . . . . . . . . . . . . . 2-15 Figure 2-12, P12, DB9 RS-232 Female Connector . . . . . . . . . . . . . . . . . . . . . 2-16 Figure 2-13, J11 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Figure 2-14, J12 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Figure 2-15, Jumper JP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Figure 2-16, Jumper JR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Figure 2-17, Jumper JR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Figure 2-18, Jumper JR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Figure 2-19, Jumper JR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Figure 2-20, Jumper JP7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Figure 2-21, Jumper JP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Figure 2-22, SW1, Boot Load Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Figure 2-23, SW2, Processor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

Figure 2-24, eZdspTM F28335 Test Points (Bottom) . . . . . . . . . . . . . . . . . . . . . 2-26

List of Tables

Table 2-1, External Chip Select and Usages . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-2, eZdspTM F28335 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Table 2-3, P1, JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Table 2-4, P2, Expansion Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Table 2-5, P4, I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Table 2-6, P8, I/O Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Table 2-7, P7, I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Table 2-8, P5/P9, Analog Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Table 2-9, P10, Expansion Interface Connector . . . . . . . . . . . . . . . . . . . . . . . 2-14 Table 2-10, P11, CANA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Table 2-11, P12, P12, RS-232 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Table 2-12, J11, 5 x 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Table 2-13, J12, 5 x 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Table 2-14, J201, Embedded USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-15, eZdspTM F28335 Suggested Connector Part Numbers . . . . . . 2-19

Table 2-16, eZdspTM F28335 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Table 2-17, JP1, U29, Pin 2 to ADCREFIN Select . . . . . . . . . . . . . . . . . . . . . . 2-20 Table 2-18, JR2, XTPD Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Table 2-19, JR4, Connector P4, P8 Voltage Select . . . . . . . . . . . . . . . . . . . . . 2-21 Table 2-20, JR5, Connector P2, P10 Voltage Select . . . . . . . . . . . . . . . . . . . . 2-21 Table 2-21, JR6, MUX GPIO22 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Table 2-22, JP7, CANA Termination Resistor Select . . . . . . . . . . . . . . . . . . . . 2-22 Table 2-23, JP8, CANA Termination Resistor Select . . . . . . . . . . . . . . . . . . . . 2-23 Table 2-24, LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Table 2-25, SW1, Boot Load Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Table 2-26, SW2, Processor Configuration Switch . . . . . . . . . . . . . . . . . . . . . 2-25 Table 2-27, Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25

About This Manual

This document describes board level operations of the eZdspTM F28335 based on theTexas Instruments TMS320F28335 Digital Signal Controller (DSC).

The eZdspTM F28335 is a stand-alone module permitting engineers and softwaredevelopers evaluation of certain characteristics of the TMS320F28335 DSC todetermine processor applicability to design requirements. Evaluators can createsoftware to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The “eZdspTM F28335” will sometimes be referred to as the “eZdsp”.

“eZdsp” will include the socketed or unsocket version

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320F28335 Digital Signal Controllers Data Manual,literature #SPRS439

Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide,literature #SPRU430

Texas Instruments TMS320C28x Assembly Language Tools Users Guide, literature #SPRU513

Texas Instruments TMS320C28x Optimizing C/C++ Compiler User’s Guide,literature #SPRU514

Texas Instruments Code Composer Studio Getting Started Guide,literature #SPRU509

Table 1: Manual History

Revision History

A Production Release

B Updated Figures, Text, Schematics

C Updated Figures, Tables, Text

Table 2: Board History

PWBRevision

History

A Production Release

B Updated Silk-screen

1-1

Chapter 1

Introduction to the eZdspTM F28335

This chapter provides a description of the eZdspTM for theTMS320F28335 Digital Signal Controller, key features, and block diagramof the circuit board.

Topic Page

1.0 Overview of the eZdspTM F28335 1-21.1 Key Features of the eZdspTM F28335 1-31.1.1 Hardware Features 1-31.1.2 Software Features 1-31.2 Functional Overview of the eZdspTM F28335 1-4

Spectrum Digital, Inc

1-2 eZdspTM F28335 Technical Reference

1.0 Overview of the eZdspTM F28335

The eZdspTM F28335 is a stand-alone card--allowing developers to evaluate theTMS320F28335 digital signal controller (DSC) to determine if it meets their applicationrequirements. Furthermore, the module is an excellent platform to develop and runsoftware for the TMS320F28335 processor.

The eZdspTM F28335 is shipped with a TMS320F28335 DSC. The eZdspTM F28335allows full speed verification of F28335 code. Several expansion connectors areprovided for any necessary evaluation circuitry not provided on the as shippedconfiguration.

To simplify code development and shorten debugging time, a C2000 Code Composer

StudioTM driver is provided. In addition, an onboard JTAG connector providesinterface to emulators, with assembly language and ‘C’ high level language debug.

Figure 1-1, eZdsp F28335


1-3

1.1 Key Features of the eZdspTM F28335

1.1.1 Hardware Features

The eZdspTM F28335 has the following features:

• TMS320F28335 Digital Signal Controller

• 150 Mhz. operating speed

• On chip 32-bit floating point unit

• 68K bytes on-chip RAM

• 512K bytes on-chip Flash memory

• 256K bytes off-chip SRAM memory

• On chip 12 bit Analog to Digital (A/D) converter with 16 input channels

• 30 MHz. input clock

• On board RS-232 connector with line driver

• On board CAN 2.0 interface with line driver and connector

• Multiple Expansion Connectors (analog, I/O)

• On board embedded USB JTAG Controller

• 5-volt only operation with supplied AC adapter

• On board IEEE 1149.1 JTAG emulation connector

1.1.2 Software Features

• TI F28xx Code Composer StudioTM Integrated Development Environment, Version 3.3

• Texas Instruments’ Flash APIs to support the F28335

• Texas Instruments’ F28335 header files and example software



1.2 Functional Overview of the eZdspTM F28335

Figure 1-1 shows a block diagram of the basic configuration for the eZdspTM F28335.The major interfaces of the eZdsp are the JTAG interface, and expansion interface.

TMS320F28335

ANALOG TODIGITAL

CONVERTER USB

Figure 1-2, BLOCK DIAGRAM eZdspTM F28335

ANALOG

EXPANSION

I/O

EXPANSION

JTAGPORT/JTAGCONTROLLER

USB

EXTERNALJTAG

30 Mhz. XTAL1/OSCIN

128K x 16SRAM

XZCS7n

PORT

CAN-A

CAN-B

RS-232

SCI-B

CANA

CANB

SCIA

SCIB

2-1

Chapter 2

Operation of the eZdspTM F28335

This chapter describes the operation of the eZdspTM F28335, keyinterfaces and includes a circuit board outline.

Topic Page

2.0 The eZdspTM F28335 Operation 2-32.1 The eZdspTM F28335 Board 2-32.1.1 Power Connector 2-42.2 eZdspTM F28335 Memory 2-52.2.1 Memory Map 2-62.3 eZdspTM F28335 Connectors 2-72.3.1 P1, JTAG Interface 2-82.3.2 P2, Expansion Interface 2-92.3.3 P4/P8/P7, I/O Interface 2-102.3.4 P5/P9, Analog Interface 2-122.3.5 P6, Power Connector 2-132.3.6 P10, Expansion Interface 2-142.3.7 P11, CANA Connector 2-152.3.8 P12, RS-232 Connector 2-162.3.9 J11, CANB 5 x 2 Header 2-172.3.10 J12, SCIB 5 x 2 Header 2-182.3.11 J201, Embedded USB JTAG Interface 2-182.3.12 Connector Part Numbers 2-19



Topic Page

2.4 eZdspTM F28335 Jumpers 2-192.4.1 JP1, ADCREFIN Select 2-202.4.2 JR2, XTPD Voltage Select 2-202.4.3 JR4, Connector P4, P8 Voltage Select 2-212.4.4 JR5, Connector P2, P10 Voltage Select 2-212.4.5 JR6, MUX GPIO22_24 Select 2-222.4.6 JP7, CANA Termination Resistor Select 2-222.4.7 JP8, CANB Termination Resistor Select 2-232.5 LEDs 2-232.6 Switches 2-242.6.1 SW1, Boot Load Option Switch 2-242.6.2 SW2, Processor Configuration Switch 2-252.7 Test Points 2-26


2-3

2.0 The eZdspTM F28335 Operation

This chapter describes the eZdspTM F28335, key components, and operation.

Information on the eZdsp’s various interfaces is also included. The eZdspTM F28335consists of four major blocks of logic:

• Analog Interface Connector• I/O Interface Connector• On board Memory• JTAG Interface • Embedded USB JTAG Controller Interface

2.1 The eZdspTM F28335 Board

The eZdspTM F28335 is a 5.35 x 3.0 inch, multi-layered printed circuit board, poweredby an external 5-Volt only power supply. Figure 2-1 shows the layout of the top side ofthe F28335 eZdsp.

Figure 2-1, eZdspTM F28335 PCB Outline (Top)

SW1

SW2

P2

J12

P7

P8

P6

P5

P1

P4

J11

P12 P11

P10

J201

P9

DS2

DS1

DS201

JP1

JP8

JP7



Figure 2-2 shows the layout of the bottom side of the F28335 eZdsp.

2.1.1 Power Connector

The eZdspTM F28335 is powered by a +5 Volt only power supply, included with theunit. The power is supplied via connector P6. If expansion boards are connected to theeZdsp, a higher amperage power supply may be necessary.

Figure 2-2, eZdspTM F28335 PCB Outline (Bottom)

JR5

JR6

JR4

JR2


2-5

2.2 eZdspTM F28335 Memory

The eZdsp includes the following on-chip memory:

• 256K x 16 Flash• 8 blocks of 4K x 16 single access RAM (SARAM)• 2 blocks of 8K x 16 SARAM• 2 blocks of 1K x 16 SARAM

In addition 128K x 16 off-chip SRAM is provided. The processor on the eZdsp can beconfigured for boot-loader mode or non-boot-loader mode.

The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For largersoftware projects it is suggested to do a initial debug with on eZdsp F28335 modulewhich supports a total RAM environment. With careful attention to the I/O mapping inthe software the application code can easily be ported to the F28335.

The table below shows the external chip select signal and its use.

Table 1: External Chip Select and Usage

Chip Select Signal

Use

XZCS0n Expansion header

XZCS6n Expansion Header

XZCS7n External SRAM



2.2.1 Memory Map

The figure below shows the memory map configuration on the eZdspTM F28335.

Note: The on-chip flash memory has a security key which can prevent visibility whenenabled.

Figure 2-3, eZdspTM F28335 Memory Space


2-7

2.3 eZdspTM F28335 Connectors

The eZdspTM F28335 has fourteen connectors. The function of each connector isshown in the table below:

Table 2: eZdspTM F28335 Connectors

Connector Function

P1 JTAG Interface

P2 Expansion

P4/P8/P7 I/O Interface

P5/P9 Analog Interface

P6 Power Connector

P10 Expansion

P11 CAN-A

P12 SCI-A

J11 CAN-B

J12 SCI-B

J201 Embedded JTAG



2.3.1 P1, JTAG Interface

The eZdspTM F28335 is supplied with a 14-pin header interface, P1. This is thestandard interface used by JTAG emulators to interface to Texas Instruments DSPs.

The positions of the 14 pins on the P1 connector are shown in the diagram below asviewed from the top of the eZdsp.

The definition of P1, which has the JTAG signals is shown below.

Table 3: P1, JTAG Interface Connector

Pin # Signal Pin # Signal

1 XTMS 2 XTRST-

3 XTDI 4 GND

5 XTPD (+3.3/5V)

6 no pin

7 T_TDO 8 USBSEL

9 T_TCK RET 10 GND

11 XTCK 12 GND

13 T_EMU0 14 T_EMU1

Fig 2-4, P1 Pin Locations

P1

1

2

13

14

WARNING !The TMS320F28335 supports +3.3V Input/Output levelswhich are NOT +5V tolerant. Connecting the eZdsp toa system with +5V Input/Output levels will damage theTMS320F28335. If the eZdsp is connected to anothertarget then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.


2-9

2.3.2 P2, Expansion Interface

The positions of the 60 pins on the P2 connector are shown in the figure below.

The definition of P2, which has the I/O signal interface is shown below.

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JR5.

Table 4: P2, Expansion Interface Connector


1 +3.3V/+5V/NC * 2 +3.3/+5V/NC *3 GPIO79_XD0 4 GPIO78_XD15 GPIO77_XD2 6 GPIO76_XD3

7 GPIO75_XD4 8 GPIO74_XD59 GPIO73_XD6 10 GPIO72_XD711 GPIO71_XD8 12 GPIO70_XD9

13 GPIO69_XD10 14 GPIO68_XD1115 GPIO67_XD12 16 GPIO66_XD1317 GPIO65_XD14 18 GPIO64_XD15

19 GPIO40_XA0_XWE1n 20 GPIO41_XA121 GPIO42_XA2 22 GPIO43_XA323 GPIO44_XA4 24 GPIO45_XA5

25 GPIO46_XA6 26 GPIO47_XA727 GPIO80_XA8 28 GPIO81_XA929 GPIO82_XA10 30 GPIO83_XA11

31 GPIO84_XA12 32 GPIO85_XA1333 GPIO86_XA14 34 GPIO87_XA1535 GND 36 GND

37 GPIO36_SCIRXDA-XZCS0n 38 GPIO37_ECAP2_XZCS7n39 GPIO34_ECAP1_XREADY 40 B_GPIO28_SCIRXDA_XZCS6n41 GPIO35_SCIRXDA_XRNW 42 10K Pull-up

43 GPIO38_WE0n 44 XRDn45 +3.3V 46 No connect47 DSP_RSn 48 XCLKOUT

49 GND 50 GND51 GND 52 GND53 GPIO39_XA16 54 GPIO31_CANTXA_XA17

55 GPIO30_CANRXA_XA18 56 GPIO14_TZ3n_XHOLDn_SCITXB_MCLKXB57 GPIO15_XHOLDAn_SCIRXDB_MFSXB 58 GPIO29_SCITXDA_XA1959 No connect 60 No connect

Figure 2-5, Connector P2 Pin LocationsP2

1

2



2.3.3 P4/P8/P7, I/O Interface

The connectors P4, P8, and P7 present the I/O signals from the DSC. The layout ofthese connectors are shown below.

The pin definition of the P4 connector is shown in the table below.

Table 5: P4, I/O Connectors

Pin # Signal

1 +3.3V/+5V/NC *2 No connect

3 GPIO22_EQEP1S_MCLKRA_SCITXDB4 GPIO7_EPWM4B_MCLKRA_ECAP25 GPIO23_EQEP1_MFSXA_SCIRXDB

6 GPIO5_EPWM3B_MFSRA_ECAP17 GPIO20_EAEP1A_MXDA_CANTXB8 GPIO21_EQEP1B_MDRA_CANRXB

9 No connect10 GND11 GPIO3_EPWM2B_ECAP5_MCLKRB

12 GPIO1_EPWM1B/ECAP6/MFSRB13 No connect14 No connect

15 No connect16 No connect17 No connect

18 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB19 GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB20 GND

1 20

Figure 2-6, P4/P8/P7 Connectors

P4

P8

P7

11

2

39

40

20

10


2-11

The pin definition of the P8 connector is shown in the table below.

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JR4.

The P7 connector is supplied for backwards compatibility. Signals from otherconnectors can be wired to this connector to support existing user interfaces. The pindefinition of P7 connector is shown in the table below.

Table 6: P8, I/O Connectors


1 +3.3V/+5V/NC * 2 +3.3V/+5V/NC *

3 MUX_GPIO29_SCITXDA_XA19 4 MUX_GPIO28_SCIRXDA_XZCS6n

5 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB 6 GPIO20_EAEP1A_MXDA_CANTXB

7 GPIO21_EQEP18_MDRA_CANRXB 8 GPIO23_EQEP1_MFSXA_SCIRXDB

9 GPIO0_EPWM1A 10 GPIO1_EPWM1B/ECAP6/MFSRB

11 GPIO2_EPWM2A 12 GPIO3_EPWM2B_ECAP5_MCLKRB

13 GPIO4_EPWM3A 14 GPIO5_EPWM3B_MFSRA_ECAP1

15 GPIO27_ECAP4_EQEP2S_MFSXB 16 GPIO6_EPWMN4A_EPWMSYNCI/EPWMSYNCO

17 GPIO13_TZ2N_CANRXB_MDRB 18 GPIO34_ECAP1_XREADY

19 GND 20 GND

21 GPIO7_EPWM4B_MCLKRA_ECAP2 22 GPIO15TZ4n_XHOLDA_SCIRXDB_MFSXB

23 GPIO16_SPISIMOA_CANTXB_TZ5n 24 GPIO17_SPISOMIA_CANRXB_TZ6n

25 GPIO18_SPICLKA_SCITXDB_CANRXA 26 GPIO19_SPISTAn_SCIRXDB_CANTXA

27 _MUX_GPIO31_CANRXA_XA17 28 MUX_GPIO30_CANRXA_XA18

29 MUX_GPIO11_EPWM6B_SCIRXDB_ECAP4 30 MUX_GPIO8EPWM5A_CANTXB_ADCSOCA0nP3

31 MUX_GPIO9_EPWM5B_SCITXDB_ECAP3 32 MUX_GPIO10_EPWM6A_CANRXB_ADCASOCB0n

33 MUX_GPIO22 34 GPIO25_ECAP2_EPEQ2B_MDRB

35 GPIO26_ECAP3_EQEP21_MCLKXB 36 GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn

37 GPIO12_TZ1N_CANTXB_MDXB 38 GPIO33_SCLA_EPWNSYNCVO_ADCSOCBOn

39 GND 40 GND

Table 7: P7, I/O Connector


1 No connect 11 No connect

2 No connect 12 No connect3 No connect 13 No connect4 No connect 14 No connect

5 No connect 15 No connect6 No connect 16 No connect7 No connect 17 No connect

8 No connect 18 No connect9 No connect 19 No connect

10 No connect 20 GND



2.3.4 P5/P9, Analog Interface

The position of the 30 pins on the P5/P9 connectors are shown in the diagram belowas viewed from the top of the eZdsp.

The definition of P5/P9 signals are shown in the table below.

* Connect ADCLO to AGND or ADCLO of target system for proper ADC operation.

Table 8: P5/P9, Analog Interface Connector

P5 Pin # Signal P9 Pin # Signal P9 Pin # Signal

1 ADCINB0 1 GND 2 ADCINA0








9 ADCREFM 17 GND 18 ADCLO *

10 ADCREFP 19 GND 20 No connect

P9

Figure 2-7, Connector P5/P9 Pin Locations

1

202

19

ANALOG

10

P5

1


2-13

2.3.5 P6, Power Connector

Power (5 volts) is brought onto the eZdspTM F28335 via the P6 connector. Theconnector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. Theposition of the P6 connector is shown below.

The diagram of P6, which has the input power is shown below.

Figure 2-8, Connector P6 Location

PO

WE

R

P6

PC Board

P6+5V

Ground

Front ViewFigure 2-9, eZdspTM F28335 Power Connector



2.3.6 P10, Expansion Interface

The positions of the 60 pins on the P10 connector are shown in the figure below.

The definition of P10, which has the I/O signal interface is shown below.

Table 9: P10, Expansion Interface Connector


1 +3.3V/+5V/NC 2 +3.3V/+5V/NC3 GPIO63_SCITXDC_XD16 4 GPIO62_SCIRXDC_XD175 GPIO61_MFSRB_XD18 6 GPIO60_MCLKRB_XD19

7 GPIO59_MFSRA_XD20 8 GPIO58_MCLKRA_XD219 GPIO57_SPISTEAn_XD22 10 GPIO56_SPICLKA_XD2311 GPIO55_SPISOMIA_XD24 12 GPIO54_SPISIMOA_XD25

13 GPIO53EQEP1_XD26 14 GPIO52_EQEP1S_XD2715 GPIO51_EAEP1B_XD28 16 GPIO50_EQEP1A_XD2917 GPIO49_ECAP6_XD30 18 GPIO48_ECAP5_XD31

19 No connect 20 No Connect21 No connect 22 No Connect23 No connect 24 No Connect






55 No connect 56 No Connect57 No connect 58 No Connect59 GND 60 GND

Figure 2-10, Connector P10 Pin Locations

P10eZdsp TMS320F28335 EXPANSIONPin 2

Pin 1

Pin 60

Pin 59


2-15

2.3.7 P11, CANA Connector

The eZdsp F28335 has a 9 Pin female D-connector which brings out the CANAtransmit and receive signals. This CAN interface uses the SN65HVD235 CAN driver.The pin positions for the P11 connector as viewed from the edge of the printed circuitshown below.

The pin numbers and their corresponding signals are shown in the table below.

Table 10: P11, CANA Pinout

Pin # Signal Name

1 No Connect

2 CANLA

3 GND

4 No Connect

5 No Connect

6 No Connect

7 CANHA

8 No Connect

9 No Connect

Figure 2-11, P11, DB9 CANA Female Connector

6789

12345



2.3.8 P12, RS-232 Connector

The eZdsp F28335 has an RS-232 connector which brings out the SCIA transmit andreceive signals to be used as UART. This UART uses the MAX3238 RS-232 line driverand is routed to a male 9 pin D-connector, P12. The pin positions for the P10 connectoras viewed from the edge of the printed circuit board are shown below.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.

Table 11: P12, RS-232 Pinout

Pin # Signal Name Direction

1 No Connect

2 PCRXDA Out

3 PCTXDA In

4 No Connect

5 GND N/A

6 No Connect

7 No Connect

8 No Connect

9 No Connect

Figure 2-12, P12, DB9 RS-232 Female Connector

6789

12345


2-17

2.3.9 J11, CANB 5 x 2 Header

The CANB signals are routed through the SN65HVD235 CAN driver to a 5 x 2 doublerow header, J11. The pin numbers for J11 and their corresponding signals are shown inthe table below.

The location of the pins are shown in the figure below.

Table 12: J11, 5 x 2 Pinout

Pin # Signal Name Pin # Signal Name

1 No Connect 2 No Connect

3 CANLB 4 CANHB

5 GND 6 No Connect



Figure 2-13, J11 Pin Locations

J11 CAN-B

Pin 1

Pin 2

DSC Socket



2.3.10 J12, SCIB 5 x 2 Header

The SCIB signals are routed through the MAX3238 line driver to a 5 x 2 double rowheader, J10. The pin numbers for J12 and their corresponding signals are shown in thetable below.

The location of the pins are shown in the figure below.

2.3.11 J201, Embedded USB JTAG Interface

The USB connector J201 is used to connect to the host development system which isrunning the software development suite. The signals on this connector are shown in thetable below.

Table 13: J12, 5 x 2 Pinout

Pin # Signal Name Direction Pin # Signal Name Direction


3 PCRXDB Out 4 No Connect

5 PCTXDB In 6 No Connect


9 GND N/A 10 No Connect

Table 14: J201, Embedded USB JTAG Interface

Pin #Signal Name

1 USBVDD

2 D-

3 D+

4 NC

5 USBVSS

Figure 2-14, J12 Pin Locations

J12 SCI-B

Pin 1

Pin 2

DSP Socket


2-19

2.3.12 Connector Part Numbers

The table below shows the part numbers for connectors which can be used on the

eZdspTM F28335. Part numbers from other manufacturers may also be used.

*SSW or SSQ Series can be used

2.4 eZdspTM F28335 Jumpers

The eZdspTM F28335 has 7 jumpers available to the user which determine how

features on the eZdspTM F28335 are utilized. The table below lists the jumpers andtheir function. The following sections describe the use of each jumper.

Table 15: eZdspTM F28335 Suggested Connector Part Numbers

Connector Male Part Numbers Female Part Numbers

P1 SAMTEC TSW-1-10-07-G-T SAMTEC SSW-1-10-01-G-T

P2 SAMTEC TSW-1-20-07-G-T SAMTEC SSW-1-20-01-G-T

Table 16: eZdspTM F28335 Jumpers

Jumper # Size FunctionPosition As

Shipped From Factory

JP1 1 x 2 U29, Pin 2 to ADCREFIN Installed

JR2 1 x 3 +3.3/5V to XTPD +3.3 volts

JR4 1 x 3 +5/3.3V to P4, P8 Not populated

JR5 1 x 3 +5/3.3V to P2, P10 Not populated

JR6 1 x 3 MUX GPIO22_24 Select GPIO24

JP7 1 x 2 CANA Terminator Resistor Installed

JP8 1 x 2 CANB Terminator Resistor Installed



2.4.1 JP1, ADCREFIN Select

Jumper JP1 is used to connect the output of U29, REF3020 to ADCREFIN. When thejumper is shorted the +2.048 voltage level is routed to the ADCREFIN signal of theDSC. When the jumper is open the ADCREFIN floats.The positions are shown in thetable below.

* as shipped from factory

The layout of this jumper is shown in the figure below.

2.4.2 JR2, XTPD Voltage Select

Jumper JR2 is a surface mount jumper located on the bottom side of the board. Touse a configuration a zero ohm resistor should be used for shorting. This jumper isused to select either +3.3 or +5 volts to be touted to the XTPD pin on the external JTAGheader P1, pin 5. In configuration A, +5 volts is routed to XTPD. When configurationB is selected +3.3 volts is routed to XTPD. This is shown below.

* defaultThe layout of this jumper is shown in the figure below.

Table 17: JP1, U29, Pin 2 to ADCREFIN Select

Position Function

Shorted * Output of U29 (+2.048V) connected to ADCREFIN

Open Use internal reference for ADCREFIN

Table 18: JR2, XTPD Voltage Select

Configuration Function

A * +5 volts routed to XTPD

B +3.3 volts routed to XTPD

Installed/shortedJP1

Figure 2-15, Jumper JP1

Open

DSC

JP1

DSC

Configuration A Configuration B

Figure 2-16, Jumper JR2

JR2 JR2

+5V +3.3V

1 3 1 3


2-21

2.4.3 JR4, Connector P4, P8 Voltage Select

Jumper JR4 is a surface mount jumper located on the bottom side of the board. Touse a configuration a zero ohm resistor should be used for shorting. This jumper allowsthe user to bring +5 or +3.3 volts to connector P4, pin1, and connector P8, pins 1 and 2.When configuration A is used +5 volts is brought to the connectors. Configuration Broutes +3.3 volts to these connectors. These settings are shown below.


2.4.4 JR5, Connector P2, P10 Voltage Select

Jumper JR5 is a surface mount jumper located on the bottom side of the board. Touse a configuration a zero ohm resistor should be used for shorting. This jumper allowsthe user to bring +5 or +3.3 volts to connector P2, pin1 and 2, and connector P10,pins 1 and 2. When configuration A is used +5 volts is brought to the connectors. Configuration B routes +3.3 volts to these connectors. These settings are shown below.


Table 19: JR4, Connector P4, P8 Voltage Select


A +5 volts routed to P2, pins 1, P8, pins 1,2

B +3.3 volts routed to P2, pins 1, P8, pins 1,2

Table 20: JR5, Connector P2, P10 Voltage Select


A +5 volts routed to P2, pins 1,2, P10, pins 1,2

B +3.3 volts routed to P2, pins 1,2, P10, pins 1,2



+5 volts +3.3 voltsJR4JR41 3 1 3



+5 volts +3.3 voltsJR5

13

1

3 JR5



2.4.5 JR6, MUX GPIO22_24 Select

Jumper JR6 is a surface mount jumper located on the bottom side of the board. Touse a configuration a zero ohm resistor should be used for shorting. This jumper isused to route the signal GPIO22 or GPIO24 to connector P8, pin 33 (MUX GPIO22).In configuration A GPIO22 is selected. When configuration B is used GPIO24 isselected. These configurations are shown below.

* as shipped from factory


2.4.6 JP7, CANA Termination Resistor Select

Jumper JP7 is used to select the termination resistor on the CANA interface. Wheninstalled a termination resistor is placed between pins 2 and 7 of the connector P7. This jumper is installed at the factory. The positions are shown in the table below.


Table 21: JR6, MUX GPIO22 Select


A GPIO22 routed to MUX GPIO22_24

B * GPIO24 routed to MUX GPIO22_24

Table 22: JP7, CANA Termination Resistor Select


Installed/shorted Termination resistor installed

Open Termination resistor NOT resistor installed

Configuration A Configuration BFigure 2-19, Jumper JR6

GPIO22 GPIO24JR6JR6

13 1 3

Installed/shorted

JP7


Open

JP7


2-23

2.4.7 JP8, CANB Termination Resistor Select

Jumper JP8 is used to select the termination resistor on the CANB interface. Wheninstalled a termination resistor is placed between pins 3 and 4 of the connector J11. This jumper is installed at the factory. The positions are shown in the table below.


2.5 LEDs

The eZdspTM F28335 has three light-emitting diodes. DS1 indicates the presence of+5 volts and is normally ‘on’ when power is applied to the board. LED DS2 is undercontrol of the GPIO32 line from the processor. DS201 is connected to the embeddedUSB emulator and shows the status of the emulation link. These are shown in the tablebelow.

Table 23: JP8, CANB Termination Resistor Select


Installed/shorted Termination resistor installed

Open Termination resistor NOT resistor installed

Table 24: LEDs

LED # Color Controlling Signal

DS1 Green +5 Volts

DS2 Green GPIO32

DS201 Green Embedded emulation link status

Installed/shortedJP8


OpenJP8



2.6 Switches

The eZdspTM F28335 has two switches. SW1 is used to select the power on bootload options. SW2 is used to select the processor configuration.

2.6.1 SW1, Boot Load Option Switch

Switch SW1 is used to select the boot load option used by the F28335 processor onpower up. These selections are shown in the table below.

* As shipped from the factory.

The figure below shows the layout of SW1.

Table 25: SW1, Boot Load Option Switch

PINPosition 4

Boot-3XA15

Position 3Boot-2XA14



Boot Mode

1111 OFF OFF OFF OFF Jump to Flash

1110 OFF OFF OFF ON SCI-A boot

1101 OFF OFF ON OFF SPI-A boot *

1100 OFF OFF ON ON I2C-A boot

1011 OFF ON OFF OFF eCAN-A boot

1010 OFF ON OFF ON McBSP-A boot

1001 OFF ON ON OFF Jump to XINTX x16

1000 OFF ON ON ON Jump to XINTX x32

0111 ON OFF OFF OFF Jump to OTP

0110 ON OFF OFF ON Parallel GPIO I/O boot

0101 ON OFF ON OFF Parallel XINTF boot

0100 ON OFF ON ON Jump to SARAM

0011 ON ON OFF OFF Branch to check boot mode

0010 ON ON OFF ON Branch to Flash, skip ADC CAL

0001 ON ON ON OFF Branch to SARAM, skip ADC CAL

0000 ON ON ON ON Branch to SCI, skip ADC CAL

Figure 3-22, SW1, Boot Load Option Switch (default)

SW1 BOOT Raised NIBON Position1

23

4

ON


2-25

2.6.1 SW2, Processor Configuration Switch

Switch SW2 is used to select the processor configuration. The eZdspTM F28335supports 2 on board SCI ports and 2 on board CAN ports. These ports can be used onboard or routed to expansion connectors. Switch SW2 controls this configuration.These selections are shown in the table below.

* default

The figure below shows the layout of SW2.

Table 26: SW2, Processor Configuration Switch

Position State Value Function

1 OFF 1 Select GPIO28, GPIO29, GPIO30, GPIO31 as expansion

1 ON * 0 Select GPIO28, GPIO29, GPIO30, GPIO31 as on board SCI/CAN A

2 OFF 1 Disable MUX U22

2 ON * 0 Enable MUX U22

3 OFF 1 Select GPIO8, GPIO9, GPIO10, GPIO11 as expansion

3 ON * 0 Select GPIO8, GPIO9, GPIO10, GPIO11 as on board SCI/CAN B

4 OFF 1 Disable MUX U23

4 ON * 0 Enable MUX U23

5 OFF 1 Write protect I2C EEPROM

5 ON * 0 Enable Writes to I2C EEPROM

6 OFF 1 I2C EEPROM lowest address is 1

6 ON * 0 I2C EEPROM lowest address is 0

Figure 3-23, SW2, Processor Configuration Switch (default)

SW2 Raised NIBON Position

CONFIG

ON12

34

56



2.7 Test Points

The eZdspTM F28335 has fifteen test points. Their location on the bottom of the boardare shown in the figure below.

Figure 2-24, eZdspTM F28335 Test Points (Bottom)

TP4

TP2TP3

TP1


2-27

The signals each test point is tied to is listed in the table below.

Table 27: Test Points

Test Point Signal

TP1 AGND

TP2 XCLKOUT

TP3 U8(DSP) Pin 81, TEST1

TP4 U8(DSP) Pin 82, TEST2

A-1

Appendix A

eZdspTM F28335 Schematics

The schematics for the eZdspTM F28335 can be found on the CD-ROMthat accompanies this board. The schematics were drawn on ORCAD.

The schematics are correct for both the socketed and unsocketed version

of the eZdspTM.

Design Notes:

1. The TMS320F28335 X1/CLKIN pin is +1.8 volt input. The clock input is buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides +3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the schematics.

WARNING !The TMS320F28335 supports +3.3V Input/Output levelswhich are NOT +5V tolerant. Connecting the eZdsp toa system with +5V Input/Output levels will damage theTMS320F28335. If the eZdsp is connected to anothertarget then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.


A-2 eZdspTM F28335 Technical Reference

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SHEET01 - TITLE PAGE

SHEET02 - TMS320F28335 DSP

SHEET03 - DSP DECOUPLING CAPS

SHEET04 - BOOT SWITCHES,OSC

SHEET05 - MEMORY

SHEET06 - I/O MULTIPLEXING

SHEET07 - CAN, RS232

SHEET08 - EMIF EXPANSION

SHEET09 - I/O EXPANSION

SHEET10 - ANALOG EXPANSION

SHEET11 - JTAG

SHEET12 - POWER

SHEET13 - PLACEMENT TOP

SHEET14 - PLACEMENT BOTTOM

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XD

6X

D7

VD

D3

VF

LV

DD

IOV

DD

AGND

VD

DA

_3

V3

VD

DA

_1

V8

VD

DA

_1V

8

VD

DA

_3

V3

AGND

AD

CIN

A0

10A

DC

INA

110

AD

CIN

A2

10A

DC

INA

310

AD

CIN

A4

10A

DC

INA

510

AD

CIN

A6

10A

DC

INA

710

AD

CIN

B0

10A

DC

INB

110

AD

CIN

B2

10A

DC

INB

310

AD

CIN

B4

10A

DC

INB

510

AD

CIN

B6

10A

DC

INB

710

XR

Sn

11

C2

8_T

RS

Tn

11C

28_

TC

K1

1

C2

8_

TD

I1

1C

28_T

MS

11

XC

LK

OU

T8

C28

_T

DO

11

C2

8_E

MU

011

C2

8_E

MU

111

XC

LKIN

4

X14

X24

AD

CR

EF

M1

0

AD

CR

EF

P1

0

GP

IO5

8_M

CLK

RA

_XD

218

GP

IO59

_M

FS

RA

_X

D2

08 G

PIO

60_

MC

LKR

B_X

D19

8G

PIO

61_

MF

SR

B_

XD

18

8 GP

IO6

2_S

CIR

XD

C_

XD

17

8G

PIO

63_S

CIT

XD

C_

XD

168

GP

IO0_

EP

WM

1A9

GP

IO1

_E

PW

M1B

/EC

AP

6/M

FS

RB

9G

PIO

2_E

PW

M2A

9G

PIO

3_E

PW

M2

B_E

CA

P5_

MC

LKR

B9

GP

IO4_

EP

WM

3A9

GP

IO5

_EP

WM

3B

_M

FS

RA

_E

CA

P1

9

GP

IO7

_EP

WM

4B

_M

CL

KR

A_

EC

AP

29

GP

IO8

_EP

WM

5A_C

AN

TX

B_

AD

CS

OC

AO

nP3

6G

PIO

9_E

PW

M5

B_

SC

ITX

DB

_EC

AP

36

GP

IO10

_EP

WM

6A_

CA

NR

XB

_AD

CS

OC

BO

n6

GP

IO1

1_E

PW

M6B

_SC

IRX

DB

_E

CA

P4

6G

PIO

12_T

Z1n

_CA

NT

XB

_MD

XB

9 GP

IO13

_T

Z2

N_

CA

NR

XB

_M

DR

B9

GP

IO4

8_E

CA

P5

_XD

318

GP

IO4

9_E

CA

P6

_XD

308 G

PIO

50_E

QE

P1A

_XD

29

8G

PIO

51_

EA

EP

1B_X

D2

88

GP

IO52

_EQ

EP

1S_X

D2

78

GP

IO5

3_E

QE

P1_

XD

26

8 GP

IO54

_SP

ISIM

OA

_X

D2

58

GP

IO55

_SP

ISO

MIA

_X

D2

48

GP

IO5

6_S

PIC

LK

A_X

D2

38

GP

IO5

7_S

PIS

TE

An

_XD

22

8

AD

CR

EF

IN3

AD

CL

O1

0 GP

IO6

_EP

WM

4A

_E

PW

MS

YN

CI/

EP

WM

SY

NC

O9

GP

IO2

5_E

CA

P2

_EQ

EP

2B

_M

DR

B9G

PIO

17_

SP

ISO

MIA

_C

AN

RX

B_T

Z6

n9

GP

IO2

6_E

CA

P3

_EQ

EP

2I_M

CLK

XB

9

GP

IO1

8_S

PIC

LK

A_

SC

ITX

DB

_C

AN

RX

A9

GP

IO2

7_E

CA

P4

_EQ

EP

2S_M

FS

XB

9

GP

IO19

_S

PIS

TE

An

_SC

IRX

DB

_CA

NT

XA

9

GP

IO3

2_

SD

AA

_E

PW

MS

YN

CI_

AD

CS

OC

AO

n4

,5,9

GP

IO2

0_E

AE

P1A

_MD

XA

_CA

NT

XB

9

GP

IO3

3_

SC

LA

_E

PW

NS

YN

CO

_A

DC

SO

CB

On

5,9

GP

IO2

1_E

QE

P1

B_

MD

RA

_CA

NR

XB

9 GP

IO22

_E

QE

P1

S_M

CL

KR

A_

SC

ITX

DB

9G

PIO

23_

EQ

EP

1_M

FS

XA

_ SC

IRX

DB

9G

PIO

24_

EC

AP

1_E

QE

P2

A_M

DX

B9G

PIO

16

_SP

ISIM

OA

_C

AN

TX

B_T

Z5

n9

GP

IO1

4_T

Z3

n_X

HO

LD_S

CIT

XD

B_M

CLK

XB

8,9

GP

IO15

_TZ

4n_X

HO

LDA

_SC

IRX

DB

_MF

SX

B8

,9

GP

IO3

0_C

AN

RX

A_X

A1

86

,8G

PIO

31_C

AN

TX

A_X

A17

6,8

GP

IO28

_S

CIR

XD

A_X

ZC

S6n

6G

PIO

29_

SC

ITX

DA

_XA

196

,8

GP

IO3

4_

EC

AP

1_X

RE

AD

Y8

,9

XR

Dn

5,8

GP

IO35

_S

CIR

XD

A_

XR

NW

8

GP

IO71

_XD

85

,8G

PIO

70_X

D9

5,8

GP

IO69

_XD

105

,8G

PIO

68_X

D11

5,8

GP

IO67

_XD

125

,8G

PIO

66_X

D13

5,8

GP

IO65

_XD

145

,8G

PIO

64_X

D15

5,8

GP

IO79

_XD

05

,8G

PIO

78_X

D1

5,8

GP

IO77

_XD

25

,8G

PIO

76_X

D3

5,8

GP

IO75

_XD

45

,8G

PIO

74_X

D5

5,8

GP

IO73

_XD

65

,8G

PIO

72_X

D7

5,8

GP

IO40

_XA

0_X

WE

1n5

,8G

PIO

41_X

A1

5,8

GP

IO39

_XA

165

,8

GP

IO42

_XA

25

,8G

PIO

43_X

A3

5,8

GP

IO44

_XA

45

,8G

PIO

45_X

A5

5,8

GP

IO46

_XA

65

,8G

PIO

47_X

A7

5,8

GP

IO80

_XA

85

,8

GP

IO86

_XA

144

,5,8

GP

IO81

_XA

95

,8G

PIO

82_X

A10

5,8

GP

IO83

_XA

115

,8G

PIO

84_X

A12

4,5

,8G

PIO

85_X

A13

4,5

,8

GP

IO87

_XA

154

,5,8

GP

IO38

_WE

0n5

,8

GP

IO36

_SC

IRX

DA

_XZ

CS

0n8

GP

IO37

_EC

AP

2_X

ZC

S7n

5,8

B_G

PIO

28_

SC

IRX

DA

_XZ

CS

6n8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

21

4

B

TM

S3

20F

28

335

EzD

SP

TM

S3

20F

283

35

( 3.3V )

( 3.3V )

( 1.8V )

( 3.3V )

( 3.3V )

( 1.8V )

( 1.8V )

SIN

GLE

PO

INT

CO

NN

EC

TIO

N

C11 and C12 are 0805 Size

use biggest trace allowable

with no vias to connect

these to processor

TP

4T

ES

T P

OIN

T1

C1

22

.2u

F C

ER

AM

IC L

OW

ES

R

ADC

FLASH - 3.3V

VDD I/0 -3.3V

VDD

CORE - 1.8V-1.9V

1.8V

TMS320F28335 - 176 QFP

U8

TM

S3

20F

2833

5GF

GP

IO40

/XA

0/X

WE

1n15

1

GP

IO41

/XA

115

2

GP

IO42

/XA

215

3

GP

IO43

/XA

315

6

GP

IO44

/XA

415

7

GP

IO45

/XA

515

8

GP

IO46

/XA

616

1

GP

IO47

/XA

716

2

GP

IO80

/XA

816

3

GP

IO81

/XA

916

4

GP

IO82

/XA

1016

5

GP

IO83

/XA

1116

8

GP

IO84

/XA

1216

9

GP

IO85

/XA

1317

2

GP

IO86

/XA

1417

3

GP

IO87

/XA

1517

4

GP

IO39

/XA

1617

5

GP

IO31

/CA

NT

XA

/XA

1717

6

GP

IO30

/CA

NR

XA

/XA

181

GP

IO79

/XD

013

6

GP

IO78

/XD

113

5

GP

IO77

/XD

213

4

GP

IO76

/XD

313

3

GP

IO75

/XD

413

2

GP

IO74

/XD

513

1

GP

IO73

/XD

613

0

GP

IO72

/XD

712

9

GP

IO71

/XD

812

8

GP

IO70

/XD

912

7

GP

IO69

/XD

1012

4

GP

IO68

/XD

1112

3

GP

IO67

/XD

1212

2

GP

IO66

/XD

1311

9

GP

IO65

/XD

1411

6

GP

IO64

/XD

1511

5

GP

IO37

/EC

AP

2/X

ZC

S7n

150

GP

IO36

/SC

IRX

DA

/XZ

CS

0n14

5

GP

IO28

/SC

IRX

DA

/XZ

CS

6n14

1

GP

IO38

/XW

E0n

137

XR

Dn

149

GP

IO35

/SC

IRX

DA

/XR

nW14

8

GP

IO34

/EC

AP

1/X

RE

AD

Y14

2

XC

LKO

UT

138

GP

IO15

/TZ

4n/X

HO

LDA

n/S

CIR

XD

B/M

FS

XB

26G

PIO

14/T

Z3n

/XH

OLD

n/S

CIT

XD

B/M

CLK

XB

25

X1 104

X2 102

XR

Sn

80

TR

ST

n78

TC

K87

TM

S79

TD

I76

TD

O77

EM

U0

85

EM

U1

86

AD

CIN

A0

42

AD

CIN

A1

41

AD

CIN

A2

40

AD

CIN

A3

39

AD

CIN

A4

38

AD

CIN

A5

37

AD

CIN

A6

36

AD

CIN

A7

35

AD

CIN

B0

46

AD

CIN

B1

47

AD

CIN

B2

48

AD

CIN

B3

49

AD

CIN

B4

50

AD

CIN

B5

51

AD

CIN

B6

52

AD

CIN

B7

53

AD

CR

EF

P56

AD

CR

EF

M55

AD

CR

ES

EX

T57

AD

CLO

43A

DC

RE

FIN

54

GP

IO0/

EP

WM

1A5

GP

IO1/

EP

WM

1B/E

CA

P6/

MF

SR

B6

GP

IO2/

EP

WM

2A7

GP

IO3/

EP

WM

2B/E

CA

P5/

MC

LKR

B10

GP

IO4/

EP

WM

3A11

GP

IO5/

EP

WM

3B/M

FS

RA

/EC

AP

112

GP

IO6/

EP

WM

4A/E

PW

MS

YN

CI/E

PW

MS

YN

CO

13

GP

IO7/

EP

WM

4B/M

CLK

RA

/EC

AP

216

GP

IO8/

EP

WM

5A/C

AN

TX

B/A

DC

SO

CA

On

17

GP

IO9/

EP

WM

5B/S

CIT

XD

B/E

CA

P3

18

GP

IO10

/EP

WM

6A/C

AN

RX

B/A

DC

SO

CB

On

19

GP

IO11

/EP

WM

6B/S

CIR

XD

B/E

CA

P4

20

GP

IO12

/TZ

1n/C

AN

TX

B/M

DX

B21

GP

IO13

/TZ

2N/C

AN

RX

B/M

DR

B24

GP

IO16

/SP

ISIM

OA

/CA

NT

XB

/TZ

5n27

GP

IO17

/SP

ISO

MIA

/CA

NR

XB

/TZ

6n28

GP

IO18

/SP

ICLK

A/S

CIT

XD

B/C

AN

RX

A62

GP

IO19

/SP

IST

EA

n/S

CIR

XD

B/C

AN

TX

A63

GP

IO20

/EQ

EP

1A/M

DX

A/C

AN

TX

B64

GP

IO21

/EQ

EP

1B/M

DR

A/C

AN

RX

B65

GP

IO22

/EQ

EP

1S/M

CLK

XA

/SC

ITX

DB

66

GP

IO23

/EQ

EP

1/M

FS

XA

/SC

IRX

DB

67

GP

IO24

/EC

AP

1/E

QE

P2A

/MD

XB

68

GP

IO25

/EC

AP

2/E

QE

P2B

/MD

RB

69

GP

IO26

/EC

AP

3/E

QE

P2I

/MC

LKX

B72

GP

IO27

/EC

AP

4/E

QE

P2S

/MF

SX

B73

GP

IO33

/SC

LA/E

PW

MS

YN

CO

/AD

CS

OC

BO

n75

GP

IO59

/MF

SR

A/X

D20

110

GP

IO58

/MC

LKR

A/X

D21

100

GP

IO57

/SP

IST

EA

n/X

D22

99

GP

IO62

/SC

IRX

DC

/XD

1711

3

GP

IO52

/EQ

EP

1S/X

D27

94G

PIO

51/E

QE

P1B

/XD

2891

GP

IO48

/EC

AP

5/X

D31

88

GP

IO60

/MC

LKR

B/X

D19

111

GP

IO61

/MF

SR

B/X

D18

112

GP

IO56

/SP

ICLK

A/X

D23

98

GP

IO63

/SC

ITX

DC

/XD

1611

4

GP

IO53

/EQ

EP

1/X

D26

95

GP

IO54

/SP

ISIM

OA

/XD

2596

GP

IO55

/SP

ISO

MIA

/XD

2497

GP

IO50

/EQ

EP

1A/X

D29

90G

PIO

49/E

CA

P6/

XD

3089

VDD3VFL.184

VDD1A18 31

VDD2A18 59

VSS1AGND 32

VSS2AGND 58

VDDA2(A3V3) 34

VSSA2(AGND) 33

VDDAIO(A3V3).1 45

VSSAIO(AGND) 44

VSS.1 3

VSS.2 8

VSS.3 14

VSS.4 22

VSS.5 30

VSS.6 60

VSS.8 83

VSS.9 92

VSS.10 103

VSS.11 106

VSS.12 108

VSS.13 118

VSS.14 120

VSS.15 125

VSS.7 70

VDDIO(3V3).19

VDDIO(3V3).271

VDDIO(3V3).393

VDDIO(3V3).4107

VDDIO(3V3).5121

VDD(1V8).14

VDD(1V8).215

VDD(1V8).323

VDD(1V8).429

VDD(1V8).561

VDD(1V8).6101

VDD(1V8).8117

VDD(1V8).9126

VDD(1V8).10139

XCLKIN 105

VSS.16 140

VSS.17 144

VSS.18 147

VSS.19 155

VSS.19 160

VSS.20 166

VSS.21 171

VDDIO(3V3).6143

VDDIO(3V3).7159

VDDIO(3V3).8170

VDD(1V8).11146

VDD(1V8).12154

VDD(1V8).7109

(NC) TEST1 81(NC) TEST2 82

GP

IO29

/SC

ITX

DA

/XA

192

GP

IO32

/SD

AA

/EP

WM

SY

NC

I/AD

CS

OC

AO

n74

VDD(1V8).12167

R2

942

2.1

K

RN

2D

33

A4

B13

RN

2B

33

A2

B15

R8

33

RN

2E

33

A5

B12

RN

2A

33

A1

B16

RN

2F

33

A6

B11

RN

2C

33

A3

B14

TP2

TE

ST

PO

INT

1

TP

3T

ES

T P

OIN

T1

C1

12

.2u

F C

ER

AM

IC L

OW

ES

R



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VD

DA

_3V

3

VD

DA

_1V

8

AD

CR

EF

IN

VD

D

VD

DIO 1.9

V

3.3

V

VD

DA

_1

V8

VD

DA

_3

V3

VD

DA

_3

V3

AGND

AGND

AGND

AGND

AGND

AD

CR

EF

IN2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

31

4

B

TM

S3

20F

28

335

EzD

SP

DS

P D

eco

up

ling

Ca

pa

cito

rs

( 1.8V )

( 3.3V )

LOCATE NEAR DSP -- U8

These caps go with U8




Tie in one point on the Ground plane

C5

0.1

uF

C4

00

.1u

F

C3

7

0.0

01

uF

C8

0.1

uF

C5

8

0.1

uF

R2

50

12

C5

90.

1u

F

TP

1T

ES

T P

OIN

T1

C6

0.1

uF

+C

T6

22

uF

C56

0.0

01u

F

L4

BLM

21P

221S

N

C2

10

.1u

F

C20

0.1

uF

+C

T1

22u

F

C2

1u

F

C1

80

.1u

F+

CT

522

uF

C5

7

0.4

7u

F

C9

0.1

uFC

39

0.1

uF

L3

BLM

21P

221S

N

C1

90

.1u

F

C6

00

.1u

F

C3

1u

FC

38

0.1

uF

JP1

JMP

-2M

M

A1

B2

U2

9

RE

F3

020

IN1

OU

T2

GN

D3

C4

10

.1u

FC

610

.1u

F


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

XA

15X

A14

XA

13X

A12 3.3

V3

.3V

3.3V

3.3

V

XC

LK

IN2

X22

X12

GP

IO3

2_

SD

AA

_EP

WM

SY

NC

I_A

DC

SO

CA

On

2,5

,9

GP

IO8

6_X

A14

2,5

,8

GP

IO8

4_X

A12

2,5

,8

GP

IO8

7_X

A15

2,5

,8

GP

IO8

5_X

A13

2,5

,8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

41

4

B

TM

S3

20F

28

335

EzD

SP

Bo

ot

Sw

itch

es/

OS

C

SM

T/4P

IN D

IP

XF

WHEN CRYSTAL IS USED POPULATE C42 WITH 0 OHM RESISTOR

OFF

ON

OFF

ON

OFF

ON

OFF

OFF

OFF

PIN

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

BO

OT

-3B

OO

T-2

BO

OT

-1B

OO

T-0

XA

15

ON

XA

14X

A13

XA

12M

OD

E

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

ON

ON

ON

OFF

ON

WHEN OSCILLATOR IS USED POPULATE

R32 WITH 0 OHM RESISTOR

18 pF

18 pF

30MHz

NOT POPULATED

Jump to Flash

Parallel GPIO I/O boot

SCI-A boot

SPI-A boot

I2C-A boot

eCAN-A boot

Branch to SCI, skip ADC CAL

Branch to SARAM, skip ADC CAL

McBSP-A boot

Jump to OTP

Jump to XINTF x16

Jump to XINTF x32

Branch to Flash, skip ADC CAL

Branch to check boot mode

Jump to SARAM

Parallel XINTF boot

U1

2

SN

74A

HC

1G14

3

4

5

2 1

C2

7N

O-P

OP

R4

02

0KR

42

20K

R3

0N

O-P

OP

U1

1

30M

Hz

OF

Fn

1

GN

D2

VC

C4

CLK

3

R3

920

K

DS

2LT

ST

-C15

0GK

TG

RE

EN

2 1

C4

30

.1uF

C4

2N

O-P

OP

SW

1

SW

DIP

-4/S

M

1 2 3 4

8 7 6 5

R3

120

K

R3

20

R3

72

.2K

R1

52

.2K

R2

910

0

C62

0.1

uF

L1

BLM

21P

221S

N

C2

8N

O-P

OP

R3

62

.2K

R4

3

220

R4

12

.2K

Y2

NO

-PO

P

12



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

XD

4

XD

15

XD

1

XD

13

XD

3

XD

0

XD

12

XD

10

XD

7

XD

5

XD

2

XD

9X

D8

XD

6

XD

11

XD

14

SD

AA

SC

LA

I2C

_RO

M_

AD

D

3.3

V

3.3

V

3.3

V

3.3

V

XR

Dn

2,8

I2C

_R

OM

_AD

D6

I2C

_R

OM

_W

P6

GP

IO3

2_

SD

AA

_E

PW

MS

YN

CI_

AD

CS

OC

AO

n2

,4,9

GP

IO3

3_

SC

LA_

EP

WN

SY

NC

O_

AD

CS

OC

BO

n2

,9

GP

IO79

_XD

02

,8G

PIO

78_X

D1

2,8

GP

IO77

_XD

22

,8G

PIO

76_X

D3

2,8

GP

IO75

_XD

42

,8G

PIO

74_X

D5

2,8

GP

IO73

_XD

62

,8G

PIO

72_X

D7

2,8

GP

IO71

_XD

82

,8G

PIO

70_X

D9

2,8

GP

IO69

_XD

102

,8G

PIO

68_X

D11

2,8

GP

IO67

_XD

122

,8G

PIO

66_X

D13

2,8

GP

IO65

_XD

142

,8G

PIO

64_X

D15

2,8

GP

IO40

_XA

0_X

WE

1n2

,8G

PIO

41_X

A1

2,8

GP

IO39

_X

A16

2,8

GP

IO42

_XA

22

,8G

PIO

43_X

A3

2,8

GP

IO44

_XA

42

,8G

PIO

45_X

A5

2,8

GP

IO46

_XA

62

,8G

PIO

47_X

A7

2,8

GP

IO80

_XA

82

,8

GP

IO86

_X

A14

2,4

,8

GP

IO81

_XA

92

,8G

PIO

82_

XA

102

,8G

PIO

83_

XA

112

,8G

PIO

84_

XA

122

,4,8

GP

IO85

_X

A13

2,4

,8

GP

IO87

_X

A15

2,4

,8

GP

IO3

8_W

E0n

2,8

GP

IO37

_E

CA

P2_

XZ

CS

7n2

,8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5101

92-0

001

We

dn

esd

ay,

No

vem

be

r 07

, 2

007

51

4

B

TM

S3

20F

283

35 E

zDS

P

SR

AM

/SP

I E

EP

RO

M

ASRAM

64

Kx1

6,

128

Kx

16

an

d 2

56K

x 1

6C

om

pa

tible

DSP

R10

10K

R9

10K

U4

IS6

1LV

641

6-1

2T

A0

1

A1

2

A2

3

A3

4

A4

5

A5

18

A6

19

A7

20

A8

21

A9

22

A10

23

A11

24

A12

25

A13

26

A14

27

A15

42

A16

43

A17

44

D0

7

D1

8

D2

9

D3

10

D4

13

D5

14

D6

15

D7

16

D8

29

D9

30

D10

31

D11

32

D12

35

D13

36

D14

37

D15

38

CS

6

WE

17

OE

41

BH

E40

BLE

39

NC

28

VDD111

VDD233

VSS1 12

VSS2 34

C2

20

.1uF

R3

4.9

9KU

21 24W

C2

56

A0

1V

CC

8

VS

S4

NC

13

SC

L6

SD

A5

A1

2W

P7

R4

4.9

9K

C1

00

.1u

F


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3.3

V

3.3

V

3.3

V

UA

RT

_R

XD

B7

CA

N_

RX

B7

UA

RT

_R

XD

A7

CA

N_

RX

A7

UA

RT

_TX

DA

7

CA

N_T

XA

7

UA

RT

_TX

DB

7

CA

N_T

XB

7

MU

X_G

PIO

29_S

CIT

XD

A_X

A19

9

MU

X_G

PIO

28_

SC

IRX

DA

_XZ

CS

6n9

MU

X_G

PIO

31_C

AN

RX

A_X

A17

9

MU

X_G

PIO

30_C

AN

RX

A_X

A18

9

MU

X_G

PIO

9_E

PW

M5B

_SC

ITX

DB

_E

CA

P3

9

MU

X_G

PIO

11_

EP

WM

6B

_SC

IRX

DB

_EC

AP

49

MU

X_G

PIO

8_E

PW

M5A

_C

AN

TX

B_A

DC

SO

CA

OnP

39

MU

X_G

PIO

10_

EP

WM

6A

_CA

NR

XB

_AD

CS

OC

BO

n9

I2C

_R

OM

_WP

5

I2C

_R

OM

_A

DD

5

GP

IO8_

EP

WM

5A

_CA

NT

XB

_A

DC

SO

CA

OnP

32

GP

IO1

0_E

PW

M6A

_C

AN

RX

B_

AD

CS

OC

BO

n2

GP

IO11

_EP

WM

6B_

SC

IRX

DB

_EC

AP

42

GP

IO9_

EP

WM

5B_S

CIT

XD

B_E

CA

P3

2

GP

IO3

0_C

AN

RX

A_X

A1

82

,8

GP

IO31

_CA

NT

XA

_XA

172

,8GP

IO28

_SC

IRX

DA

_X

ZC

S6

n2

GP

IO2

9_S

CIT

XD

A_X

A1

92

,8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

61

4

B

TM

S3

20F

28

335

EzD

SP

I/O

MU

LT

IPLE

XIN

G

ON

OFF

Select GPIO28,GPIO29,GPIO30,GPIO31 as on board SCI/CAN A

Enable Mux U22

SW2-1

SW2-1

SW2-2

Select

GPIO28,GPIO29,GPIO30,GPIO31 as expansion

SW2-2

Disable Mux U22

Select GPIO8,GPIO9,GPIO10,GPIO11 as on board SCI/CAN B

Enable Mux U23

Disable Mux U23

Write Protect I2C EEPROM

Enable Writes to I2C EEPROM

I2C EEPROM lowest address is 0

I2C EEPROM lowest address is 1

Function

OFF

ON

OFF

ON

OFF

OFF

ON

ON

Select

GPIO8,GPIO9,GPIO10,GPIO11 as expansion

OFF

ON

SW2-3

SW2-3

SW2-4

SW2-4

SW2-5

SW2-5

SW2-6

SW2-6

Switch

Position

Value

1 1 1 1 1 1 000000

U2

2

SN

74

CB

TL

V3

257P

W

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

RN

3R

N1

0K

1234 5

678

U2

3

SN

74

CB

TL

V3

257P

W

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

C2

50

.1uF

SW

2

SW

DIP

-6/S

M

1 2 3 48 7

659101112

C2

60

.1u

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PC

RX

DA

PC

TX

DA

PC

RX

DB

PC

TX

DB

CA

NH

B

CA

NH

A

CA

NL

A

CA

NL

B

3.3

V

3.3

V

3.3

V

3.3

V

3.3

V

UA

RT

_T

XD

A6

UA

RT

_T

XD

B6

CA

N_

TX

A6

CA

N_T

XB

6

UA

RT

_R

XD

A6

UA

RT

_R

XD

B6

CA

N_R

XA

6

CA

N_

RX

B6

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-0

001

Wed

ne

sda

y, N

ove

mb

er

07,

20

07

71

4

B

TM

S3

20F

2833

5 E

zDS

P

RS

23

2/C

AN

SCI-A

1

2

3

4

5

6

7

8

9

10

1

6

2

7

3

8

4

9

5

IDC

DSUB-F

1

2

3

4

5

6

7

8

9

10

1

6

2

7

3

8

4

9

5

IDC

DSUB-F

C2

40

.1uF

C1

70

.1u

F

JP7

JMP

-2M

M

A1

B2C

13

0.1

uF

P11

DB

9F

594837261

10 11

J11

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

R2

312

0

RN

10

RN

10K

1234 5

678

U2 S

N6

5H

VD

235VC

C3

CA

NH

7

CA

NL

6

GN

D2

AB

5

TX

D1

RX

D4

RS

8

U3 S

N6

5H

VD

235

VC

C3

CA

NH

7

CA

NL

6

GN

D2

AB

5

TX

D1

RX

D4

RS

8

R2

412

0

J12

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

JP8

JMP

-2M

M

A1

B2

RN

9R

N1

0K

1234 5

678

C1

60

.1u

F

P12

DB

9F

594837261

10 11

C1

40

.1u

F

U1

MA

X32

38C

PW

DIN

124

DIN

223

DIN

322

RO

UT

121

RO

UT

220

RO

UT

318

DO

UT

15

DO

UT

26

DO

UT

37

RIN

18

RIN

29

RIN

311

FO

RC

EO

N13

FO

RC

EO

FF

n14

C1+

28

C1-

25

C2+

1

C2-

3

V+

27V

-4

GN

D2

RO

UT

1B16

INV

ALI

Dn

15

DIN

419

DIN

517

DO

UT

410

DO

UT

512

VC

C26

C2

30

.1u

F

C15

0.1

uF


A-9

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DS

P_

RS

n

GP

IO79

_X

D0

GP

IO77

_X

D2

GP

IO75

_X

D4

GP

IO73

_X

D6

GP

IO71

_X

D8

GP

IO69

_X

D10

GP

IO67

_X

D12

GP

IO65

_X

D14

GP

IO78

_XD

1G

PIO

76_X

D3

GP

IO74

_XD

5G

PIO

72_X

D7

GP

IO70

_XD

9G

PIO

68_X

D11

GP

IO66

_XD

13G

PIO

64_X

D15

XA

16

XC

LK

OU

T

+5V

3.3

V

3.3

V3

.3V

XR

Dn

2,5

DS

P_

RS

n11

XC

LK

OU

T2

GP

IO4

8_E

CA

P5_

XD

312

GP

IO4

9_E

CA

P6_

XD

302

GP

IO50

_EQ

EP

1A_X

D2

92

GP

IO5

1_E

AE

P1B

_XD

282

GP

IO52

_EQ

EP

1S_X

D2

72

GP

IO5

3_E

QE

P1_

XD

262

GP

IO5

4_S

PIS

IMO

A_X

D25

2G

PIO

55_

SP

ISO

MIA

_X

D24

2G

PIO

56_S

PIC

LKA

_XD

232

GP

IO5

7_S

PIS

TE

An_

XD

222

GP

IO5

8_M

CLK

RA

_XD

212

GP

IO5

9_M

FS

RA

_X

D20

2G

PIO

60_

MC

LKR

B_X

D19

2G

PIO

61_

MF

SR

B_

XD

182

GP

IO6

2_S

CIR

XD

C_X

D17

2G

PIO

63_

SC

ITX

DC

_XD

162

GP

IO3

0_C

AN

RX

A_X

A18

2,6

GP

IO3

1_C

AN

TX

A_X

A1

72

,6

GP

IO29

_SC

ITX

DA

_X

A19

2,6

GP

IO14

_TZ

3n_X

HO

LD_S

CIT

XD

B_M

CLK

XB

2,9

GP

IO1

5_T

Z4

n_X

HO

LD

A_S

CIR

XD

B_M

FS

XB

2,9

GP

IO79

_XD

02

,5G

PIO

78_X

D1

2,5

GP

IO77

_XD

22

,5G

PIO

76_X

D3

2,5

GP

IO75

_XD

42

,5G

PIO

74_X

D5

2,5

GP

IO73

_XD

62

,5G

PIO

72_X

D7

2,5

GP

IO71

_XD

82

,5G

PIO

70_X

D9

2,5

GP

IO69

_XD

102

,5G

PIO

68_X

D11

2,5

GP

IO67

_XD

122

,5G

PIO

66_X

D13

2,5

GP

IO65

_XD

142

,5G

PIO

64_X

D15

2,5

GP

IO35

_SC

IRX

DA

_XR

NW

2

GP

IO40

_X

A0_

XW

E1n

2,5

GP

IO4

1_X

A1

2,5

GP

IO42

_XA

22

,5G

PIO

43_

XA

32

,5G

PIO

44_X

A4

2,5

GP

IO4

5_X

A5

2,5

GP

IO46

_XA

62

,5G

PIO

47_

XA

72

,5G

PIO

80_X

A8

2,5

GP

IO8

6_X

A14

2,4

,5

GP

IO8

1_X

A9

2,5

GP

IO8

2_X

A10

2,5

GP

IO8

3_X

A11

2,5

GP

IO8

4_X

A12

2,4

,5G

PIO

85_

XA

132

,4,5

GP

IO8

7_X

A15

2,4

,5

GP

IO3

9_X

A16

2,5

GP

IO38

_WE

0n2

,5

GP

IO36

_SC

IRX

DA

_XZ

CS

0n2

GP

IO3

4_

EC

AP

1_X

RE

AD

Y2

,9G

PIO

37_

EC

AP

2_X

ZC

S7n

2,5

B_

GP

IO2

8_S

CIR

XD

A_

XZ

CS

6n

2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

81

4

B

TM

S3

20F

28

335

EzD

SP

EM

IF E

XP

AN

SIO

N C

ON

NE

CT

OR

S

Mak

e a

sold

er c

onne

ctio

n on

JR

5 to

the

app

ropr

iate

pow

er s

uppl

y.N

ote

JR4

also

can

pow

er d

omai

nsso

this

jum

per

shou

ld b

e se

t acc

ordi

ngly

.

TM

S32

0F28

335

supp

orts

3.3

Vin

put/

outp

ut le

vels

whi

ch a

re N

OT

5V t

oler

ant.

Con

nect

ing

the

eZds

p to

a s

yste

m w

ith

5Vin

put/

outp

ut le

vels

will

dam

age

the

TM

S32

0F28

335.

If

the

eZd

spis

con

nect

ed t

o an

othe

r ta

rge

tth

en t

he e

Zds

p m

ust

be p

ower

edup

fir

st a

nd p

ower

ed d

own

last

to

prev

ent

latc

hup

cond

itio

ns.

Tie

off

unus

ed F

24xx

com

patib

le s

igna

ls.

XA18

XA17

XA19

P2

NO

-PO

P

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

R5

10K

P10

NO

-PO

P

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

JR5

NO

-PO

P

A1

B 2

C3



8 8

7 7

6 6

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MU

X_G

PIO

22

+5V

3.3

V

GP

IO0_

EP

WM

1A2

GP

IO1_

EP

WM

1B

/EC

AP

6/M

FS

RB

2G

PIO

2_E

PW

M2A

2G

PIO

3_E

PW

M2

B_E

CA

P5_

MC

LKR

B2

GP

IO4_

EP

WM

3A2

GP

IO5

_EP

WM

3B_M

FS

RA

_E

CA

P1

2G

PIO

6_E

PW

M4

A_

EP

WM

SY

NC

I/E

PW

MS

YN

CO

2

GP

IO7

_EP

WM

4B

_M

CL

KR

A_

EC

AP

22

GP

IO12

_TZ

1n_C

AN

TX

B_M

DX

B2G

PIO

13_

TZ

2N

_C

AN

RX

B_

MD

RB

2

GP

IO7_

EP

WM

4B_

MC

LK

RA

_E

CA

P2

2

GP

IO5

_EP

WM

3B_

MF

SR

A_E

CA

P1

2 GP

IO3_

EP

WM

2B_E

CA

P5_

MC

LKR

B2

GP

IO1

_E

PW

M1B

/EC

AP

6/M

FS

RB

2G

PIO

17_S

PIS

OM

IA_C

AN

RX

B_T

Z6

n2

GP

IO1

6_S

PIS

IMO

A_

CA

NT

XB

_TZ

5n

2 GP

IO1

8_S

PIC

LK

A_

SC

ITX

DB

_C

AN

RX

A2

GP

IO1

9_S

PIS

TE

An

_SC

IRX

DB

_CA

NT

XA

2

GP

IO20

_EA

EP

1A_M

DX

A_C

AN

TX

B2

GP

IO2

3_E

QE

P1_

MF

SX

A_S

CIR

XD

B2

GP

IO2

5_E

CA

P2

_EQ

EP

2B

_MD

RB

2G

PIO

26_

EC

AP

3_E

QE

P2I

_MC

LKX

B2

GP

IO2

7_E

CA

P4

_EQ

EP

2S_M

FS

XB

2

GP

IO24

_EC

AP

1_E

QE

P2A

_MD

XB

2

GP

IO32

_S

DA

A_

EP

WM

SY

NC

I_A

DC

SO

CA

On

2,4

,5G

PIO

33

_S

CL

A_

EP

WN

SY

NC

O_

AD

CS

OC

BO

n2

,5

GP

IO22

_E

QE

P1S

_MC

LKR

A_S

CIT

XD

B2 G

PIO

22

_EQ

EP

1S_

MC

LK

RA

_SC

ITX

DB

2

GP

IO23

_E

QE

P1

_MF

SX

A_S

CIR

XD

B2

GP

IO2

1_E

QE

P1

B_

MD

RA

_CA

NR

XB

2

GP

IO2

1_E

QE

P1B

_M

DR

A_

CA

NR

XB

2G

PIO

20_E

AE

P1

A_M

DX

A_

CA

NT

XB

2

GP

IO14

_T

Z3

n_X

HO

LD_

SC

ITX

DB

_MC

LKX

B2

,8G

PIO

15_T

Z4

n_X

HO

LDA

_SC

IRX

DB

_MF

SX

B2

,8

GP

IO34

_E

CA

P1

_XR

EA

DY

2,8

MU

X_

GP

IO29

_SC

ITX

DA

_XA

196

MU

X_

GP

IO2

8_S

CIR

XD

A_X

ZC

S6n

6

MU

X_G

PIO

31_C

AN

RX

A_X

A17

6M

UX

_GP

IO30

_CA

NR

XA

_XA

186

GP

IO1

4_T

Z3

n_X

HO

LD

_SC

ITX

DB

_M

CLK

XB

2,8

MU

X_G

PIO

9_E

PW

M5B

_SC

ITX

DB

_EC

AP

36M

UX

_G

PIO

11_

EP

WM

6B

_SC

IRX

DB

_EC

AP

46

MU

X_

GP

IO8

_EP

WM

5A_

CA

NT

XB

_AD

CS

OC

AO

nP

36

MU

X_

GP

IO1

0_E

PW

M6

A_C

AN

RX

B_

AD

CS

OC

BO

n6

GP

IO1

5_T

Z4n

_X

HO

LDA

_S

CIR

XD

B_M

FS

XB

2,8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5101

92-0

001

We

dn

esd

ay,

No

vem

be

r 07

, 2

007

91

4

B

TM

S3

20F

283

35 E

zDS

P

I/O

EX

PA

NS

ION

CO

NN

EC

TO

RS

TM

S32

0F28

335

supp

orts

3.3

Vin

put/

outp

ut le

vels

whi

ch a

re N

OT

5V t

oler

ant.

Con

nect

ing

the

eZds

p to

a s

yste

m w

ith

5Vin

put/

outp

ut le

vels

will

dam

age

the

TM

S32

0F2

8335

. If

the

eZ

dsp

is c

onne

cted

to

anot

her

targ

etth

en t

he e

Zds

p m

ust

be p

ower

edup

fir

st a

nd p

ower

ed d

own

last

to

prev

ent

latc

hup

cond

itio

ns.

Mak

e a

sold

er c

onne

ctio

n on

JR

4 to

the

app

ropr

iate

pow

er s

uppl

y.N

ote

JR5

also

can

pow

er d

omai

nsso

this

jum

per

shou

ld b

e se

t acc

ordi

ngly

.

JR4

NO

-PO

P

A1

B 2

C3

P7 1

1

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

JR6

JUM

PE

R3

_SM

T

A1 B2

C 3

P4

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

P8

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040


A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AGND

AGND

AD

CIN

A0

2A

DC

INA

12

AD

CIN

A2

2A

DC

INA

32

AD

CIN

A4

2A

DC

INA

52

AD

CIN

B0

2A

DC

INB

12

AD

CIN

B2

2A

DC

INB

32

AD

CIN

B4

2A

DC

INB

52

AD

CIN

B6

2A

DC

INB

72

AD

CR

EF

M2

AD

CR

EF

P2

AD

CIN

A6

2A

DC

INA

72

AD

CL

O2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

101

4

B

TM

S3

20F

28

335

EzD

SP

Ana

log

Exp

ansi

on

Con

nect

AD

CLO

to A

GN

D o

rto

AD

CLO

of t

arge

t sys

tem

for p

rope

r A

DC

ope

ratio

n.

PLACE R6 AS CLOSE TO DSP AS POSSIBLE

P5

11

22

33

44

55

66

77

88

99

1010

R1

0

P9

11

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

R6

0



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_T

CK

_RE

TT

_TD

OT

_EM

U0

T_E

MU

1G

ND

T_T

RS

Tn

T_T

MS

T_

TD

I

T_

TC

K

XD

S_

4.1V

XT

RS

Tn

XTM

S

XT

DI

XT

CK

US

BS

EL

XTP

D

+5V

3.3

V

3.3

V

3.3

V

3.3

V

3.3

V

3.3

V

+5V 3

.3V

+5V

PO

NR

Sn

IN12

C28

_TR

ST

n2

C2

8_T

MS

2

C2

8_

TD

I2

C28

_TC

K2

C28

_TD

O2

C2

8_E

MU

02

C2

8_E

MU

12

XR

Sn

2D

SP

_R

Sn

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

111

4

B

TM

S3

20F

28

335

EzD

SP

EM

UL

AT

ION

IN

TE

RF

AC

E

XR

Sn

is

log

ica

l AN

D o

f P

ON

RS

nIN

and

emu

lato

r co

ntr

olle

d r

ese

t.

Po

we

r o

n d

efa

ult

is P

ON

Rn

IN c

on

tro

ls X

RS

n.

USBSEL - HIGH, SELECT USB EMULATION

USBSEL - LOW, SELECT XDS EMULATION

Locate near DSP TCK

pin

Lo

cate

R7

,R5

4,

C7

0 a

t th

e D

SP

XR

Sn

pin

for

be

st E

MI/

ES

D n

ois

e im

mu

nit

y.

IF U13 IS INSTALLED THEN

REMOVE R49 AND R48.

To/from expansion header

JR2

JUM

PE

R3_

SM

T

A1 B2

C 3

U1

9

SN

74C

BT

3257

PW

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

R5

410

0

R1

1

10K

US

B1

Em

bedd

ed_

US

B

GN

D

3.3V

T_T

CK

_RE

TT

_TC

K

T_T

MS

T_T

DI

T_T

DO

T_E

MU

0T

_EM

U1

T_T

RS

Tn

DS

P_R

S_O

UT

_OD

n

RE

SE

T_I

Nn

5V

R8

0

1.5

K

R1

4

10K

R1

833

R2

010

0

R1

933

R7

1.5

K

C7

02

2nF

D2

LM

404

0DC

IM3-

4.1

21

3

C4

22

pF

R1

7

10K

R1

610

K

P1

HE

AD

ER

7X

211

22

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

R1

2

10K

R2

2

10K

U2

6

SN

74LV

C1G

321 2

4

5 3

R1

3

10K

C8

00

.1u

F


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PO

NR

Sn

IN

1.8

VO

Nn

VD

D1

.9V

VD

DIO

VD

D3

VF

L

3.3

V

3.3

V

+5V

PO

NR

Sn

IN

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

121

4

B

TM

S3

20F

28

335

EzD

SP

PO

WE

R S

UP

PL

IES

+5V Max

16.9

K 1

.848

V15

.0K

1.7

73V

13.7

K 1

.722

V

TIE

TP

S7

67D

30

1 P

OW

ER

PA

D T

O G

ND

PL

AN

E (

TI-

SLM

A00

2)

18.2

K 1.

899V

+C

T2

47

uF

+C

T3

22u

F

C7

0.1

uF

C6

3

0.1

uF

R4

53

0.1

K,

1%

R4

60

P6

RA

SM

712

CE

NT

ER

SH

UN

TS

LEE

VE

DS

1LT

ST

-C15

0GK

TG

RE

EN

2 1

C6

6

0.1

uF

+C

T4

22

uF

U9

TP

S76

7D30

1

1IN

A5

1IN

B6

1EN

4

1GN

D3

2IN

A11

2IN

B12

2EN

10

2GN

D9

NC

11

NC

22

NC

37

NC

48

NC

513

NC

614

NC

1215

NC

1116

NC

1020

NC

921

NC

826

NC

727

1RE

SE

T28

1OU

TA

23

1OU

TB

24

1FB

/SE

NS

E25

2RE

SE

T22

2OU

TA

17

2OU

TB

18

2SE

NS

E19

THERMAL_PAD 29

R3

5N

O-P

OP

R4

422

0

1 2

C6

5

0.1

uF

C1

1u

F

R5

30

R5

20

R2 10K

J2 NO

-PO

P1

C64

0.1

uF

R3

31

8.2

K,

1%



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dnes

day,

Nov

embe

r 0

7, 2

007

131

4

B

TM

S3

20F

28

335

EzD

SP

PLA

CE

ME

NT

TO

P

RN202

L207

USB,

90-OHM, KEEP OUT

01

23

45

5.5

INCHES

1

3INCHES

0

P6

U9

P8

P4

P7

11 121 12

P5

P9

1 2P1

P2

P10

11 22

U210

D208

D209

U203

J204

U202

J205

1 2

A1

A14

RN201

U8

1

U207

P12

P11

12

21J12

J11

U4

SW1

44

88

132

U19

JP7

JP8

1

SW2

U21

ANALOG KEEP OUT AREA

U12

DS2

DS1

DS201


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5101

92-

000

1

We

dn

esd

ay,

No

vem

be

r 0

7,

20

07

141

4

B

TM

S3

20F

28

335

EzD

SP

PLA

CE

ME

NT

BO

TT

OM

U205

INCHES

0

JR2

JP7

JP8

P8

P4

P7

11 121 12

P12

P11

P5

P9

12

21J12

J11

1 2P1

01

23

45

5.5

INCHES

1

P2

P10

3

11 22

PLACEMENT ON BOTTOM IS LOOKING THROUGH THE BOARD

ANALOG KEEP OUT AREA

U11

Y2

JR5

JR4

JR6

U2

U3

U1

U26

B-1

Appendix B

eZdspTM F28335 MechanicaI Information

This appendix contains the mechanical information about the socketed and

unsocketed versions of the eZdspTM F28335


B-2 eZdspTM F28335 Technical Reference

Th

is d

raw

ing

is n

ot

to s

cale


B-3


B-4 eZdspTM F28335 Technical Reference

Printed in U.S.A., November 2007510195-0001 Rev. C