ezvga640 video controller datasheet

Rev A 11/2009

FEATURES Straightforward host interface consisting of 8 data and 5 addressable control lines.

Dedicated video memory address and data lines minimize the usage of other system buses.

Ideal for embedded microcontroller and microprocessor systems.

Screen resolution of 640 by 480.

Independent red, green, and blue color output lines allow for 256 different colors.

Auto-incrementing X & Y position registers allow for quick screen reads and writes.

Single write and read operations.

Independent color write and read registers.

Operates from a single clock source.

Fast host pixel write and read times.

Sync and blanking signals automatically done on-board.

All video memory read and writes automatically synchronized on-board.

Requires only a single 512K x 8 10nS SRAM memory for operation.

Single 3.3V Supply with 5V tolerant inputs.

Reno, NV 89521 TEL: (775) 852-7430 FAX: (775) 852-7430 WEB: www.multilabs.net

ezVGA640 VIDEO CONTROLLER

ezV

GA

64

0 V

IDE

O C

ON

TR

OL

LE

R

GENERAL DESCRIPTION The ezVGA640 Video Controller is designed for color video graphics applications that require display on VGA compatible monitors and displays. It provides all the circuitry needed to control the video memory and generate screen resolutions of 640 by 480 with 256 colors (8-bit pixel depth) while offering a straightforward host interface making it ideal for embedded microcontroller and microprocessor designs where cost effective video generation is required.

ezVGA640 PIN CONFIGURATION

76

51

26

1

ezVGA640

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

R / W NC

CLOCK

D7

VCC

D6

NC

D5

D4

D3

D2

D1

D0

VA0

VA0

VA1

VA1

VA2

NC

VA2

GND

VA3

VA3

NC

VA4

VC

C

VA

4

VD

0

VA

17

VD

2

GN

D

VD

3

VW

E

NC

VA

18

VA

18

VA

17

VC

C

VD

1

VA

16

VA

16

VA

15

NC

GN

D

NC

NC

NC

NC

VA

15

VD

7

VCC

VD6

VD5

VD4

VA14

VA14

VCC

VA13

VA13

VA12

VA12

GND

VA11

VA11

VA10

VA10

VA5

VA5

GND

VA6

VA6

VA7

NC

VA7

GND

VA

8

VA

8

VA

9

VA

9

NC

B0

B1

NC

GN

D

G0

G1

G2

VC

C

R0

R1

R2

VS

HS

A0

A1

A2

CE

VC

C

CE

GN

D

Copyright © Multilabs – 2009 All rights reserved

THIS PAGE LEFT BLANK INTENTIONALLY


SECTION 1

OPERATION

About the ezVGA640 Video Controller

Operational Description

Display Control Operations

Power Supply Requirement


ABOUT THE ezVGA640 VIDEO CONTROLLER

The ezVGA640 Video Controller is a cost effective and straightforward way to implement VGA color video in any application. It generates all necessary video, control, and synchronization signals and also controls the storage and retrieval of display data in the external video memory. The interface between the ezVGA640 and the VGA display device requires a minimum of components making it an effective solution for video generation. The interface between the ezVGA640 and the host is done via 8 data and 5 addressable control lines. Having addressable control lines also allows the ezVGA640 to share a common system data bus with other devices if required. The host creates texts and graphics by writing individual pixels to the screen. The screen pixel color data is stored in an external video memory which serves as the video frame buffer. This memory is automatically controlled by the ezVGA640 and is invisible to the host. This leaves the controller/processor free to run the host application while the ezVGA640 controls the aspects of video generation. Screen refreshing, sync signals, blanking signals, and video memory management are all handled automatically by the ezVGA640. Besides writing pixels the host can also read any pixel on the screen and also control the X and Y position registers that determine the pixel position. During reading or writing of a pixel there is the option of having the X and Y position registers automatically increment afterwards. This allows the host to perform fast writes and reads of the entire screen.

OPERATIONAL DESCRIPTION

Figure 1 shows a block diagram of the ezVGA640 Video Controller.

Figure 1

When first powered up all registers are cleared to zero. During continuous operation the Horizontal Dot Counter and Vertical Line Counter keep track of which pixel to load and display on the screen. The addresses generated by these two counters are sent through the Output Buffer to the external video

CE CE A2 A1 A0 R / W

Horizontal Dot Counter

Vertical Line Counter

X Position Register

Y Position Register

Ou

tpu

t Bu

ffers

10

9

10

9

VA18 - 0

HS

Green Red Blue

B0

B1

G0

G2

R0

R2

Re

ad

Co

lor

Re

gis

ter

Write

Co

lor

Re

gis

ter

VD7 - 0

8

8

3 3 2 H

ost I/O

Inte

rface

Circ

uit

D7 - 0

Control Signals

8

VWE Clock Bus

Clo

ck

VS

G1

R1


memory. The pixel color data then appears on the VD data bus which is latched into the Red, Green, and Blue output color registers. The Horizontal Dot Counter and Vertical Line Counter registers are also responsible for generation of the horizontal and vertical sync and blanking signals to keep all of the frames synchronized and the red, green, and blue color registers cleared during certain times. All of this is clocked via the Clock input. The data that appears on the R2, R1, R0, G2, G1, G0, B1, and B0 pins via the Red, Green, Blue output color registers is the pixel color. Red and green are each 3-bits in length and blue is 2-bits. This is known as a 'True Color' configuration. Since the human eye is more sensitive to red and green they provide more color information. A simple resistive ladder digital-to-analog converter can be used to generate the analog voltage signal needed for the VGA display device. Refer to the reference design later in this document for more information on this circuit. The host interface is via the data and addressable control lines on the left-hand side of the block diagram. There are two chip enable (CE) pins, one active low and one active high. The active low pin is designated with a line over it. These pins must be at the correct logic level before the ezVGA640 can be controlled. If not properly selected no data can be written to or read from the ezVGA640 and the data lines will remain in a high-impedance input state. The enable lines can be used however needed. If the ezVGA640 is to be constantly selected then they can be tied off to the proper logic level. If part of a system that uses a common data bus they can be used to ensure that the ezVGA640 is only selected when needed. If only one enable line is needed then the other can be tied off to the proper logic level while the other is used to control when the ezVGA640 is enabled. The 3 address lines (A2 – A0) are used to select what operation to perform. The R/W (Read/Write) pin controls the bi-directional data flow of the ezVGA640. With this pin logic low the data pins are in high-impedance input mode. If the pin is logic high then the data pins will be driven as outputs when a read operation is selected. If any operation other than a pixel read is selected than the data pins will remain in a high-impedance state even with the R/W pin logic high. The host interface is asynchronous to the internal operation of the ezVGA640. Data can be passed to and from the ezVGA640 at any time. The X and Y Position Registers are where the host stores the pixel position to be written to or read from. These registers can be automatically increment each time a pixel read or write command is completed such that the X position register is incremented and if the end of the line is reached the X position register is reset back to 0 and the Y position register is incremented. Should the Y position register be on the last line when it is incremented it will also automatically reset to 0. This is called progressive incrementing. This allows for fast whole screen reads and writes. When a pixel read or write is executed the address in the X Position and Y Position Registers is passed through the Output Buffers to the external video memory. If the instruction is a write the VWE (Video Write Enable) pin will go low to place the external video memory in write mode. The data in the Write Color Register will appear on the VD pins to be latched into the external video memory. For a read instruction the data from the external video memory is latched into the Read Color Register. The ezVGA640 is clocked from a single clock source. There is no internal oscillator drive circuitry so a LVTTL level clock source must be provided. The main clock is 25.175MHz and it is fed into the Clock pin.

DISPLAY CONTROL OPERATIONS The ezVGA640 can perform 8 different operations. The operation to be performed is selected by the 3 address lines (A2 – A0) as shown in the following table.


A2 A1 A0 OPERATION

0 0 0 Load X position register low byte

0 0 1 Load X position register high byte

0 1 0 Load Y position register low byte

0 1 1 Load Y position register high byte

1 0 0 Write pixel without auto-incrementing X & Y position registers

1 0 1 Read pixel without auto-incrementing X & Y position registers

1 1 0 Write pixel and auto-increment X & Y position registers

1 1 1 Read pixel and auto-increment X & Y position registers

For each operation it is assumed the ezVGA640 is properly selected. Refer to the timing diagrams for proper data and address timing when writing to and reading data from the ezVGA640. Load X Position Register Low Byte Operation: With the ezVGA640 addressed for this operation the data on the data bus (D7 – D0) will be written to bits 7 through 0 respectively of the 10-bit X position register when the R/W pin is brought logic low and then brought back to logic high. Bits 9 and 8 are not changed. The allowed values of the X position register are 0 to 639 for a total of 640 horizontal pixels.

Figure 2

Load X Position Register High Byte Operation: With the ezVGA640 addressed for this operation the data on the data bus (D1 – D0) will be written to bits 9 through 8 respectively of the 10-bit X position register when the R/W pin is brought logic low and then brought back to logic high. Bits 7 through 0 are not changed. The allowed values of the X position register are 0 to 639 for a total of 640 horizontal pixels.

Figure 3

Load Y Position Register Low Byte Operation: With the ezVGA640 addressed for this operation the data on the data bus (D7 – D0) will be written to bits 7 through 0 respectively of the 9-bit Y position register when the R/W pin is brought logic low and then brought back to logic high. Bit 8 is not changed. The allowed values of the Y position register are 0 to 479 for a total of 480 vertical lines.

D1

D0

--

--

--

--

--

--

--

--

X8

X9

X Position Register

D7

D6

D5

D4

D3

D2

D1

D0

X7

X6

X5

X4

X3

X2

X1

X0

--

--

X Position Register


Figure 4

Load Y Position Register High Byte Operation: With the ezVGA640 addressed for this operation the data on the data bus (D0) will be written to bit 8 of the 9-bit Y position register when the R/W pin is brought logic low and then brought back to logic high. Bits 7 through 0 are not changed. The allowed values of the Y position register are 0 to 479 for a total of 480 vertical lines.

Figure 5

Write Pixel Without Auto-Incrementing X & Y Position Registers Operation: With the ezVGA640 addressed for this operation the data (pixel color) on the data bus (D7 – D0) will be written to the video memory. The position of the pixel is taken from the X and Y position registers. To execute the write the R/W pin is brought logic low and then brought back to logic high.

Figure 6

Read Pixel Without Auto-Incrementing X & Y Position Registers Operation: With the ezVGA640 addressed for this operation the data bus (D7 – D0) will output data (pixel color) from the video memory. The position of the pixel is taken from the X and Y position registers. This operation is automatically executed when properly addressed and the R/W line is logic high.

D7

D6

D5

D4

D3

D2

D1

D0

B1

B0

G2

G1

G0

R2

R1

R0

Read Color Register

D7

D6

D5

D4

D3

D2

D1

D0

B1

B0

G2

G1

G0

R2

R1

R0

Write Color Register

D0

--

--

--

--

--

--

--

--

Y8

Y Position Register

D7

D6

D5

D4

D3

D2

D1

D0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

--

Y Position Register


Figure 7 Write Pixel and Auto-Increment X & Y Position Registers Operation: With the ezVGA640 addressed for this operation the data (pixel color) on the data bus (D7 – D0) will be written to the video memory. The position of the pixel is taken from the X and Y position registers. To execute the write the R/W pin is brought logic low and then brought back to logic high. After this the position registers are automatically incremented as previously explained.

Figure 8

Read Pixel and Auto-Increment X & Y Position Registers Operation: With the ezVGA640 addressed for this operation the data bus (D7 – D0) will output data (pixel color) from the video memory. The position of the pixel is taken from the X and Y position registers. This operation is automatically executed when properly addressed and the R/W line is logic high. To signal the end of the operation the address must be changed or the ezVGA640 de-selected. After this the position registers are automatically incremented as previously explained.

Figure 9

POWER SUPPLY REQUIREMENTS All VCC power inputs should be provided with individual bypass capacitors placed as closed to the power pins as possible. These capacitors should have a low internal inductance, low equivalent series resistance, and good frequency characteristics. All of the GND pins should be connected to a low-impedance ground plane for best performance. The ezVGA640 can create high-speed switching signal noise. A good low-impedance ground source is necessary to minimize noise and ground bounce. All ground connections in the final design should be connected to the same low-impedance ground plane for best operation.

D7

D6

D5

D4

D3

D2

D1

D0

B1

B0

G2

G1

G0

R2

R1

R0

Read Color Register

D7

D6

D5

D4

D3

D2

D1

D0

B1

B0

G2

G1

G0

R2

R1

R0

Write Color Register


SECTION 2

CONNECTIONS AND TIMING

Pin Descriptions

Timing Diagrams


VA0

76

51 26

1

ezVGA640

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

NC

CLOCK

D7

VCC

D6

NC

D5

D4

D3

D2

D1

D0

VA0

VA1

VA1

VA2

NC

VA2

GND

VA3

VA3

NC

VA4

VC

C

VA

4

VD

0

VA

17

VD

2

GN

D

VD

3

VW

E

NC

VA

18

VA

18

VA

17

VC

C

VD

1

VA

16

VA

16

VA

15

NC

GN

D

NC

NC

NC

NC

VA

15

VD

7

VCC

VD6

VD5

VD4

VA14

VA14

VCC

VA13

VA13

VA12

VA12

GND

VA11

VA11

VA10

VA10

VA5

VA5

GND

VA6

VA6

VA7

NC

VA7

GND

VA

8

VA

8

VA

9

VA

9

NC

B0

B1

NC

GN

D

G0

G1

G2

VC

C

R0

R1

R2

VS

HS

A0

A1

A2

CE

VC

C

CE

GN

D

R/W

PIN DESCRIPTIONS

Figure 10 The ezVGA640 is provided in a 100-pin TQFP package. The following is a table of each pin’s description:

PIN NAME PIN NUMBER FUNCTION

VA0 14 15

Address A0 of the external video memory. These two pins must be tied together for proper operation.

VA1 16 17


VA2 18 20


VA3 22 23


VA4 25 27


VA5 67 68


VA6 70 Address A6 of the external video memory. These two pins must be



71 tied together for proper operation.

VA7 72 74


VA8 76 77


VA9 78 79


VA10 65 66


VA11 63 64


VA12 60 61


VA13 58 59


VA14 55 56


VA15 42 49


VA16 40 41


VA17 37 39


VA18 35 36


VD0 28 External video memory data bit 0.








VWE 33 Write enable line of the external video memory.

NC 2 7 19 24 34 43 45 46 47 48 73 80 83

No connection.

VCC 5 26 38 51 57 88

+3.3V Power supply.



98

GND 21 31 44 62 69 75 84 100

Power supply common return ground.

CLOCK 3 25.175MHz LVTTL Level clock input. Minimum ±100ppm and 45%/55% duty cycle or better.

CE 99 Chip enable active high input.

CE 97 Chip enable active low input.

A0 94 Address line 0.



R/W 1 Read/write input. Low keeps the data line in high-impedance state for writes to the ezVGA640. High turns on the output drivers while enabled and addressed for a pixel read.

D0 4 Data bus bit 0.








HS 93 Negative horizontal sync signal. Goes to pin 13 of a standard DB15HD VGA connector.

VS 92 Negative vertical sync signal. Goes to pin 14 of a standard DB15HD VGA connector.

R0 89 Low-bit of red color. Refer to reference schematic for a simple digital-to-analog circuit.

R1 90 Middle-bit of red color. Refer to reference schematic for a simple digital-to-analog circuit.

R2 91 High-bit of red color. Refer to reference schematic for a simple digital-to-analog circuit.

G0 85 Low-bit of green color. Refer to reference schematic for a simple digital-to-analog circuit.

G1 86 Middle-bit of green color. Refer to reference schematic for a simple digital-to-analog circuit.

G2 87 High-bit of green color. Refer to reference schematic for a simple digital-to-analog circuit.

B0 81 Low-bit of blue color. Refer to reference schematic for a simple digital-to-analog circuit.

B1 82 High-bit of blue color. Refer to reference schematic for a simple digital-to-analog circuit.


CE

CE

R/W

A2 – A0

1

4

3

ADDRESS VALID

D7 – D0 DATA VALID

2

TIMING DIAGRAMS X Position Register and Y Position Register Writes:

Figure 11

NUMBER ITEM SYMBOL MIN TYP MAX UNIT

1 Address and data setup time TADS 0 nS

2 Data stable before R/W rising edge TDSRW 13 nS

3 R/W hold time TRWH 13 nS

4 Address and data hold time TADH 8 nS

NOTES 1. To avoid writing to the incorrect register the address should be made stable before or at the

same time as the R/W line is brought low.


CE

CE

R/W

A2 – A0

1

4

3

ADDRESS VALID

D7 – D0 DATA VALID

2

Pixel Write:

Figure 12


1 Address and data setup time TADS 0 nS

2 Data stable before R/W rising edge TDSRW 9 nS

3 R/W hold time TRWH 40 nS

4 Address and data hold time TADH 8 nS

NOTES 1. To avoid writing to the incorrect register the address should be made stable before or at the

same time as the R/W line is brought low. 2. After the rising edge of R/W a wait time of a minimum of 92nS must be observed before

performing another operation.


CE

CE

R/W

A2 – A0

1

ADDRESS VALID

D7 – D0 DATA VALID HI-Z HI-Z INVALID DATA

2 3

4

Pixel Read:

Figure 13


1 Time till output is active after valid address TOVA 11 nS

2 Time till data is valid after valid address TVDVA 44 nS

3 Address hold time after valid data (see notes) TAHVD -- -- -- --

4 Time till high-z after invalid address THZIA 11 nS

NOTE

1. Hold time is dependant on the amount of time the host needs to sample the data after it is valid. Once sampled the address may be changed or the ezVGA640 deselected.

2. After completion of the read operation a wait time of a minimum of 53nS must be observed before performing another operation.


SECTION 3

APPLICATION

Sample Application

Electrical Characteristics


SAMPLE APPLICATION Figure 14 on the next page shows the schematic for the ezVGA640 demo board. The ezVGA640 (U1) is the center of this design. Starting with its power supply all VCC power inputs should be provided with individual bypass capacitors placed a closed to the pins as possible. These capacitors should have a low internal inductance and good frequency characteristics. All of the GND pins should be connected to a low-impedance ground plane for best performance. The ezVGA640, along with the video memory, creates a lot of high-speed switching signals. A good low-impedance ground source is necessary to minimize noise and ground bounce. All ground connections in the design should be connected to the same low-impedance ground plane for best operation. As is evident from the schematic the majority of the pins of the ezVGA640 are dedicated to the external video memory. Here the video memory is designated U2. The ezVGA640 has been tested with a Cypress CY7C1049DV33-10ZSXI 10nS 512K x 8 Asynchronous Fast SRAM. The ezVGA640 is also compatible with this memory's pin-outs. However, any memory that is equivalent or better can be used. For example, ISSI has a memory with the same characteristics and pin-outs. The part type number is IS61WV5128BLL-10TLI. There are two points to be made about the memory. The first is the access time speed. A minimum of 10nS is needed to meet the timing requirements of the ezVGA640. Secondly, the ezVGA640 pin-outs are positioned to interface to this memory easily as is shown with the PCB layout figures. However, this is a center power design that is common in the industry and is used by other manufacturers. Any memory pin layout will work but be sure to observe the length of the traces. All traces connecting the ezVGA640 with the video memory should be as short as possible with minimal impedance and preferably no vias. The video memory should be as close to the ezVGA640 as possible and provided with its own bypass capacitors as shown in the schematic. The schematic shows that the ezVGA640 has two sets of memory address line outputs. These must be tied together for proper operation. The memory is wired so that it is constantly selected. Only the Write Enable line is used by the ezVGA640, all other lines are grounded for constant selection. Power traces should be wide enough or have enough cross-section to handle several hundred milliamps of current. Just like the ground plane, any power traces or power plane should be as low in impedance as possible, the wider the traces the better. The ezVGA640 is clocked from a 25.175MHz clock source, designated as Y1. The ezVGA640 does not have any internal oscillation drive circuitry so a LVTTL level clock oscillator must be provided. This clock oscillator should be crystal based and it is recommended that a minimum of ±100ppm stability should be specified with a duty cycle of 45%/55% or better. The clock does not require an enable line as shown in the schematic since operation is continuous. However, if one is provided it should be tied off to the proper logic level. The clock source should be provided with a dedicated bypass capacitor as well. The ezVGA640 has eight digital color output lines, 3 for red, 3 for green, and 2 for blue. This allows for a total of 256 color combinations. These pins need to be changed to an analog signal before being sent to the display. Each of the three color inputs (red, green, and blue) of a VGA compatible display requires a signal between 0 and 0.7 volts; 0 being no intensity and 0.7 being full intensity. The reference design shows a simple cost-effective resistive ladder digital-to-analog converter that works very well for this application. Of course any digital-to-analog converter with a full-scale output voltage of 0.7 volts will work. Note that the resistors of each ladder are all 1% parts. This will keep all three of the color output levels as close as possible with minimal variation. The output of the amplifier is an emitter-follower and is set to give a 0 to 0.7 volt output when loaded by a 75 ohm load impedance. These analog color voltages are feed into a standard female high-density 15-pin DB style connector common to all VGA compatible devices. This connector is also fed with the horizontal and vertical sync signals from the ezVGA640. Refer to the figures later for proper connection.


Figure 14


Connector J2 on the schematic shows five pins that are used for connecting to the VGA device. They are R (Red), G (Green), B (Blue), HS (Horizontal Sync), and VS (Vertical Sync). Figure 15 below, and the accompanying table, shows how these pins are connected to a female high-density 15-pin DB style connector. All of the grounds (pins 5, 6, 7, 8, and 10) may be tied together.

Figure 15

PIN TYPE NOTE

1 Red Red video (0V – 0.7V into 75Ω).

2 Green Green video (0V – 0.7V into 75Ω).

3 Blue Blue video (0V – 0.7V into 75Ω).

4 NC

5 GND Common.

6 RGND Common for red video.

7 GGND Common for green video.

8 BGND Common for blue video.

9 NC

10 SGND Common for sync signals.

11 NC

12 NC

13 HSYNC Horizontal sync.

14 VSYNC Vertical sync.

15 NC

The following three diagrams show the layout for the demo board PCB. These can be used as a reference to aid in your own circuit design.


Top Layer With Overlay:

Figure 16


Top Layer Without Overlay:

Figure 17


Bottom Layer:

Figure 18


ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings:

SYMBOL DESCRIPTION VALUE UNITS

VCC Supply voltage relative to GND –0.5 to 4.0 V

VIN Input voltage relative to GND –0.5 to 5.5 V

VTS Voltage applied to 3-state output –0.5 to 5.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TJ Junction temperature +150 °C

Recommended Operation Conditions:

SYMBOL PARAMETER MIN MAX UNITS

VCC Supply voltage for logic, input, and output buffers 3.0 3.6 V

VIL Low-level input voltage 0 0.8 V

VIH High-level input voltage 2.0 5.5 V

VO Output voltage 0 VCC V

DC Characteristic Over Recommended Operating Conditions:

SYMBOL PARAMETER MIN MAX UNITS

VOH Output high voltage (see Figure 19 for output voltage versus current) 2.4 VCC V

VOL Output low voltage 0 0.4 V

IIL Input leakage current - ±10 µA

IIH I/O High-z leakage current (VIN= GND or VCC) - ±10 µA

IIH I/O High-z leakage current (GND < VIN < VCC) - ±50 µA

CIN I/O Capacitance - 10 pF

ICC Operating supply current Typ 70 mA

NOTE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions are not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.


Voltage Out Vs. Current

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3

Voltage

Cu

rren

t

Figure 19


APPENDICES


APPENDIX A COLORS This is a color swatch of all the available colors. Colors are approximate. Actual colors will depend on the display devices settings such as color temp, brightness, contrast, and other color adjustment controls. Color variance is also subject to component tolerances of the digital to analog conversion circuitry.

Figure 20

Colors 0 - 15

Colors 16 - 31

Colors 32 - 47

Colors 48 - 63

Colors 64 - 79

Colors 80 - 95

Colors 96 - 111

Colors 112 - 127

Colors 128 - 143

Colors 144 - 159

Colors 160 - 175

Colors 176 - 191

Colors 192 - 207

Colors 208 - 223

Colors 224 - 239

Colors 240 - 255


LIMITED WARRANTY Multilabs warrants to the original consumer purchaser of this product that, for a period of 90 days from the date of purchase, this product will be free from defects in material and workmanship and will perform in substantial conformity to the description of the product in this Owner's Manual. This warranty shall not apply to defects or errors caused by misuse or neglect. If the product is found to be defective in material or workmanship or if the product does not perform as warranted above during the warranty period, Multilabs will repair it, replace it, or refund the purchase price. The repair, replacement, or refund that is provided for above shall be the full extent of Multilabs's liability with respect to this product. For repair or replacement during the warranty period, contact Multilabs customer service by email at [email protected] to receive a return authorization number and return instructions. LIMITATIONS THE ABOVE WARRANTY IS IN LIEU OF AND MULTILABS DISCLAIMS ALL OTHER WARRANTIES, WHETHER ORAL OR WRITTEN, EXPRESS OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. ANY IMPLIED WARRANTY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, WHICH MAY NOT BE DISCLAIMED OR SUPPLANTED AS PROVIDED ABOVE SHALL BE LIMITED TO THE 90 DAYS OF THE EXPRESS WARRANTY ABOVE. NO OTHER REPRESENTATION OR CLAIM OF ANY NATURE BY ANY PERSON SHALL BE BINDING UPON MULTILABS OR MODIFY THE TERMS OF THE ABOVE WARRANTY AND DISCLAIMER. IN NO EVENT SHALL MULTILABS BE LIABLE FOR SPECIAL, INCIDENTAL, CONSEQUENTIAL OR OTHER DAMAGES RESULTING FROM THE POSSESSION OR USE OF THIS PRODUCT, INCLUDING WITHOUT LIMITATION DAMAGE TO PROPERTY AND, TO THE EXTENT PERMITTED BY LAW, PERSONAL INJURY, EVEN IF MULTILABS KNEW OR SHOULD HAVE KNOWN OF THE POSSIBILITY OF SUCH DAMAGES. Some states do not allow limitations on how long an implied warranty lasts and/or the exclusion or limitation of damages, in which case the above limitations and/or exclusions may not apply to you. You may also have other legal rights, which may vary from state to state.

ezvga640 video controller datasheet

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