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Fabrication and Characterization of Sub-100 nm Carbon Nanotube Vias

Changjian Zhou1, Anshul Vyas2, Patrick Wilhite2, Phillip Wang3, Mansun Chan1,

and Cary Y. Yang2 1Hong Kong University of Science and Technology, Hong Kong

2Santa Clara University, Santa Clara, CA, USA 3Applied Materials Inc. Santa Clara, CA, USA

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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New interconnect materials needed Current copper interconnect suffers

from electromigration at current density ~ 1 MA/cm2

Increase of resistivity due to width-dependent scattering

Source: ITRS 2011

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Nanocarbons

The first transistor

Intel CPU ~2000

~1960

~1947

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Nanocarbons as Interconnect Materials Physical properties of CNT: High current carrying capability > 107 A/cm2 (Cu ~ 106 A/cm2) Electromigration resistant High mobility and ballistic transport (6.45 KΩ/shell) Low resistance High thermal conductivity ~3000 W/K.m (Cu ~ 400 W/K.m)

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Objective and Approach Objective: To determine electrical characteristics of CNT on-chip via

interconnects as a potential replacement for Cu.

CNT Via Interconnect Analysis for Advanced Nodes

CNT array Dielectric fill

CNT array Dielectric fill

Sub-1000 nm vias Sub-150 nm Vias Individual CNTs

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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Fabrication of Sub-1000 nm Vias

Deposit oxide and ground metal

Deposit oxide Deposit metal for pads

Patterning Vias Photoresist removal Via pad separation

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Fabrication of Sub-1000 nm Vias

Ni Electroplating CNT Growth

500 nm 500 nm

Dielectric Deposition and Polishing

SEM image after CNT growth SEM image after polishing

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Fabrication of Sub-150 nm Vias

Top-view and cross-sectional SEM image of 60 nm vias for CNT growth

S i

S iO 2C ra -S i/L T O

P R N i

(a ) V ia p a tte rn in g (b ) D ry e tc h in g a n d P R re m o v a l

(c ) C a ta ly s t d e p o s it io n a n d p o lis h in g

S i S i

wh

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Fabrication of Sub-150 nm Vias

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Fabrication of Sub-150 nm Vias Estimation of CNT areal density in via, DCNT

90 nm CNT via

~2.2×1011/cm2 ~1.7×1011/cm2

60 nm CNT via

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Fabrication for Individual CNT Probing

CNT grown on Ti/Si

After final polish

Si

Ti 80 nm

Growth

Si

Ti 80 nm

Epoxy encapsulation

Si

Ti 80 nm

After polish

2 µm

25 µm

1 µm

After encapsulation & partial polish

100 nm

200 nm

300 nm

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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Measurement setup for Single CNT Via

Pt Si

probe probe

I + -

V

CNT array inside via

2 µm

In situ nanoprobing inside SEM Sub-1000nm CNT via

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Measurement setup for Single CNT Via In situ nanoprobing inside SEM Sub-150nm CNT via

Tip radius ≤ 50nm

Probing a single CNT Via

+

V

Cr SiO2

Si

I + -

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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103 kΩ

1.4 kΩ

Electrical Characteristics of Sub-1000 nm Vias

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Electrical Characteristics of Sub-1000 nm Vias

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05

10152025303540

5 - 10 10 -15

15 -20

20 -25

25 -30

30 -35

35 -40

40 -45

45 -50

50-55 55-60 60-65 65-70 70-75

CN

T co

unt

CNT diameter (nm)

CNT diameter distribution

0.4um via

0.5um via

0.6um via

0.7um via

0.8um via

1 um via

CNT diameter distribution in Sub-1000 nm Vias

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1

10

100

1000

10000

0 200 400 600 800 1000 1200

Via

Resi

stan

ce/L

engt

h (Ω

/μm

)

Via width (nm)

Measured

Extrapolated

2.88 kΩ at 30 nm

Projected resistance from Sub-1000 nm Vias

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Electrical Characteristics of a 60 nm Via

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R = 21 kΩ R = 567 Ω

Before Current Stressing After Current Stressing

W-probe enlarges during probing

High-current annealing (~3.5 mA) improves probe contact

Electrical Characteristics of Single CNT

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Electrical Characteristics of Single CNT

Diameter of probed samples: ~50 nm

Ni/Ti

RC

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Further Consideration Metal-CNT Contact

Side Contact

End Contact

Chemical bonding at end contact – Saturated C-bonds – Conduction modes of graphitic

structure is unaffected – Interface with concentric walls

Van der Waals bonding at side contact – Larger interfacial separation – C-bonds remain unsaturated,

inhibiting conduction – Interface with outermost wall only

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Side and End Contacts

R ~ 700 Ω

Wang et al., Adv. Mater. 22, 5350 (2010)

R ~ 10 kΩ

(a)

(b)

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• I-V nonlinearity reduced by stress current • Interfacial gap remains large • Contact resistance ~ few kΩ

Contact improvement Joule Heating

Kitsuki et al, APL 92, 173110 (2008) Yamada et al, JAP 107, 044304 (2010)

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• Resistance with W-deposited contacts reduced significantly and independent of stress current

• Contact resistance minimized

Contact improvement Deposited Tungsten

Kitsuki et al, APL 92, 173110 (2008) Saito et al, APL 93, 102108 (2008)

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Total resistance reduced from 300 kΩ to 116 Ω

Kim et al, IEEE Trans Nanotech. 11, 1223 (2012)

EBID-C deposition at edges

Contact improvement EBID-C + Joule Heating

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Outline

Introduction CNT Via Test Structure Electrical Characterization Results and Discussion Summary

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CNT vias down to 60 nm width fabricated and characterized – Linear I-V characteristics for vias and individual CNTs – “Best” projected resistance for 30 nm CNT via ~ 5 x W via

resistance Ongoing efforts to decrease CNT diameter and increase CNT

packing density to reduce via resistance Additional contact engineering needed to reduce overall

resistance Further considerations on contact resistance reduction with

CNT growth process improvements

Summary

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Thank You…

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