fan-out solutions solutions: today, tomorrow ... rdl & copper pillar bump (3d only) chip attach...
TRANSCRIPT
1
Fan-Out Solutions:
Today, Tomorrow … the Future
Ron HuemoellerCorporate Vice President, WW RnD & Technology Strategy
2
In the Beginning eWLB
3
Fan Out Packaging Emerges
• Introduction of Fan Out (eWLB)
– Marketed as package replacement for fcCSP
– Limited in application and use at initial stages – 54M units shipped in ’09
– 284M units shipped in 2015… far short of earlier predictions at that time
Fan Out market struggled
4
Today (2016)
5
2016 Has Become the Year of Fan Out
• Expected ~ 2 billion packages to ship this year
– So what changed?
6
Mobile Market: Space & Performance
• The need for more space and performance are key triggers
• Traditional Fan Out
– More space for larger battery
• Thinner and smaller than fcCSP
– Convergence of WLCSP to Fan Out
• Same BGA pin out on advanced nodes
to address die shrink
• Advanced Fan Out
– InFO
– Performance!
• Electrical, power, thermal
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WLFO Traditional Applications and Drivers
• Main applications
– Mobility
• CODEC
• RF Switch/Transceiver
• PMIC
– Automotive
• RF radar
• Connectivity
• Primary drivers
– Form factor reduction
– Fine feature size (advanced photo lithography)
– Multi-die and 3D capability
– Strong electrical performance (mmW capable)
CODEC
RF Transceiver
MCU
PMIC
NFC
8
Advanced Fan Out Value Proposition
• Reduced Z-height & form factor
• Enhanced signal integrity
• Superior impedance matching
• Optimized power distribution
• Improved thermal performance/junction temperature
• Ability to address multi-die heterogeneous integration (SiP)
9
Simplified Wafer Level Process FlowAdvanced Fan Out – Chips Last/RDL First
RDL & Copper Pillar
Bump (3D Only)
Chip Attach & UF
Carrier
Wafer Mold
Carrier
Top Side Routing
For Memory Interface
Carrier Remove
Carrier
RDL for Memory Interface
40 µm Pitch
< 0.30 mm
Total Height
POP Pillars
200 µm Pitch
SWIFT™
10
Tomorrow
11
Fan-Out WLP Market Projections
284
2,001
3,481
5,113
5,8316,240
0
1,000
2,000
3,000
4,000
5,000
6,000
7,000
2015 2016 2017 2018 2019 2020
MillionsofPackages
©2016TechSearchInternational,Inc.
• Device types driving HVM
include RF transceiver
and switch, PMIC,
CODEC, automotive
radar, connectivity (IoT)
modules, Apple's
application processors
made by TSMC and
application processors
from other companies in
future
• Future memory for top
PoP
• Many multi-die products in
future
12
Fan Out Market 2017
• Traditional Fan Out gaining momentum
– Large activity in mobile market
– RFIC, PMIC, CODEC
Courtesy of TechSearch International, Inc.
Product Body Size Total Units (M)
RFIC 3 mm
See TechSearch
CODEC 4 mm
PMIC 6 mm
Other mixed
Totals .
13
Projected Wafer Demand for FO-WLP (300mm equivalents)
528
1,345
2,929
6,261
8,669
9,292
0
1,000
2,000
3,000
4,000
5,000
6,000
7,000
8,000
9,000
10,000
2015 2016 2017 2018 2019 2020
Thousandsof300mm-Equivalent
ReconstitutedW
afers
©2016TechSearchInternational,Inc.
• Device types driving HVM
include RF transceiver
and switch, PMIC,
CODEC, automotive
radar, connectivity (IoT)
modules, application
processors
• Assumes 80 µm die street
• Assumes high-yield
process of 99%
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Process
Emergence of Advanced Fan OutSWIFTTM
Cycle time & yield
Flexibility &
scalability
Performance
RDL first
Chip attach last
Package variants –
3D, SiP etc.
Multi-die, passives
Flexible thickness
Shorter cycle time
RDL wafer pre-build
Known good RDL wafer
Thermal
Electrical
Reliable
15
Advanced Fan Out Comparison
Key AttributesFan Out
SWIFT™
fcCSP
Exp Die PoP
fcCSP
Fan-in PoPSWIFT™ Benefits
Package
Thickness0.453 mm 0.47 mm 0.660 mm
4% reduction
31% reduction
Layer Count 3 or 4 3 5
Construction
3 layers on bottom +
1 layer on top
(if fan in)
3 layer substrate
on bottom
3 layer substrate
on bottom +
2 layer substrate
on top
Same as exposed die
Fewer layers
Electrical
Reduced signal width
allows flexibility in
routing/impedance
control
Predetermined
location at edge of
package
Fixed signal widths
and difficulty in
impedance control
Flexibility, reduced
trace length, reduced
DC resistance & AC
loss
Interposer
Interconnect to
Package Edge
50 µm 200 µm 200 µm 75% Reduction
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DDR4: Signal Integrity Comparison
Key AttributesFan Out
SWIFT™
fcCSP
Exp Die PoPSWIFT™ Benefits
Eye Diagram
DDR4 @ 6 Gbps
Eye Amplitude 548 mV 451 mV 3.0x Improvement
Eye Height 481 mV 339 mV 1.4x Improvement
Eye Width 164 ps 158 ps 4.0x Improvement
Pk-Pk Jitter 3.7 ps 9.8 ps 2.2x Improvement
Rise/Fall Time 64 ps 75 ps 1.2x Improvement
17
DDR4: Signal Integrity Comparison
Key AttributesFan Out
SWIFT™
fcCSP
Fan-In PoPSWIFT™ Benefits
Eye Diagram
DDR4 @ 6 Gbps
Eye Amplitude 638 mV 444 mV 5.0x Improvement
Eye Height 551 mV 318 mV 5.0x Improvement
Eye Width 159 ps 145 ps 3.0x Improvement
Pk-Pk Jitter 7.9 ps 14.1 ps 1.8x Improvement
Rise/Fall Time 63 ps 75 ps 1.2x Improvement
18
SerDes: Signal Integrity Comparison
Key Attributes SWIFT™ fcCSP
Exposed Die PoPSWIFT™ Benefits
Eye Diagram
PCIe3 @ 8 Gbps
Eye Amplitude 998 mV 995 mV 4.0x Improvement
Eye Height 954 mV 882 mV 3.0x Improvement
Eye Width 125 ps 124.5 ps 0.5x Improvement
Pk-Pk Jitter .01 ps .07 ps 6.0x Improvement
Rise/Fall Time 29 ps 32 ps 1.4x Improvement
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SerDes: Signal Integrity Comparison
Key Attributes SWIFT™ fcCSP
Exposed Die PoPSWIFT™ Benefits
Eye Diagram
PCIe3 @ 16
Gbps
Eye Amplitude 995mV 993 mV 2.0x Improvement
Eye Height 826 mV 604 mV 2.3x Improvement
Eye Width 55 ps 50 ps 5.0x Improvement
Pk-Pk Jitter 2.9 ps 4.8 ps 1.8x Improvement
Rise/Fall Time 19 ps 31 ps 1.5x Improvement
20
SerDes: Signal Integrity Comparison
Key Attributes SWIFT™ fcCSP
Fan-In PoP (MEP)SWIFT™ Benefits
Eye Diagram
PCIe3 @ 8 Gbps
Eye Amplitude 1098 mV 1001 mV 5.0x Improvement
Eye Height 934 mV 906 mV 3.3x Improvement
Eye Width 122 ps 118 ps 4.0x Improvement
Pk-Pk Jitter 2.5 ps 6.25 ps 2.5x Improvement
Rise/Fall Time 36 ps 42 ps 1.4x Improvement
21
SerDes: Signal Integrity Comparison
Key Attributes SWIFT™ fcCSP
Fan-In PoP (MEP)SWIFT™ Benefits
Eye Diagram
PCIe4 @ 16
Gbps
Eye Amplitude 1009 mV 1007 mV 0.1x Improvement
Eye Height 799 mV 361 mV 9.0x Improvement
Eye Width 55 ps 53.9 ps 1.0x Improvement
Pk-Pk Jitter 7.8 ps 7.8 ps equivalent
Rise/Fall Time 26 ps 41 ps 1.4x Improvement
22
Power Integrity: Lower PDN Impedance
• PDN Impedance: Improved by 11% vs FC PoP (at 250 MHz)
– SWIFT™: Substrate eliminated resulting in reduced pad-BGA wiring length
– Low PDN Impedance → High power integrity
FC PoP
PCB PCB
SWIFT™FC PoP
SWIFT™
89%
Impedance
Reduction
250.0
MH
z
23
Noise: Signal Integrity Comparison
Insertion Loss
SWIFT’s controlled impedance has a
wideband low pass filter effect –
essential for PCIe and Ethernet
applications
Cross-talk
Improved by
6 dB @ 2 GHz
Return Loss
Improved by
6 dB @ 2 GHz
24
SWIFT™ vs FC PoP Thermal SimulationSteady State Analysis
79.6
100.6
76.4
95.6
60
70
80
90
100
110
JEDEC Mobile phone
℃
Max die temperature (3W dissipation)
FI-PoP SWIFT
15.6
21.6
14.7
20.2
10
15
20
25
JEDEC Mobile phone
℃/W
Theta JA
FI-PoP SWIFT
Max Temp C
(3W)FC PoP SWIFT Delta
Delta
%
JEDEC 79.6 76.4 -3.2 -4%
Mobile Phone 100.6 95.6 -5.0 -5%
Theta JA
C/WFC PoP SWIFT Delta
Delta
%
JEDEC 15.6 14.7 -0.9 -6%
Mobile Phone 21.6 20.2 -1.4 -6%
25
20
40
60
80
100
120
140
0 10 20 30 40 50 60
Te
mpera
ture
, ℃
Time, sec
JEDEC
FI-PoP SWIFT
20
40
60
80
100
120
140
0 10 20 30 40 50 60
Te
mpera
ture
, ℃
Time, sec
Mobile Phone
FI-PoP SWIFT
• Time to reach the allowable max die temperature when a 9 watt duty cycle is applied
• The assumed allowable max die temperature is 105C
• SWIFT extends the time to reach 105C by approximately 9 and 16 seconds as compared to
conventional substrate FC PoP
JEDECMobile
Phone
fcPoP 19.5 sec 20.5 sec
SWIFT 28.2 sec 36.8 sec
Gain
8.7 sec 16.3 sec
45% 80%
9 seconds 16 seconds
Time for die temp to reach 105C
(9W power dissipation)
SWIFT™ vs FC PoP Thermal SimulationTransient Analysis
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Advanced Fan Out
• SWIFTTM and InFO
– Mobility
• Apps-Processor
• Baseband (Logic + Memory)
• Power Management
• Display Driver (SiP)
• Drives Performance
– Reduced form factor
– Enhanced signal integrity
– Superior impedance matching
– Optimized power distribution
– Improved thermal performance
27
The Future
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Future: Traditional Fan Out … which direction?Relative Cost Comparison
fcCSP
Fan Out [1ML]
Higher $
Lower $WLCSP
Die Size+
0.00 mm
(WLCSP)
Die Size+
0.50 mm
fcCSP
Fan Out [1ML]
Die Size+
0.25 mm
Die Size+
1.00 mm
Die Size+
1.50 mm
Die Size+
3.00 mm
As package to die ratio
increases, there is more
disparity between Fan Out and
low cost fcCSP
Die Size+
2.00 mm
Die Size+
2.50 mm
Approximate
price parity
29
Future: Advanced Fan Out Package RoadmapAll About Performance
Available 2016 2017 2018
Single Die PoP• 3D tall Cu interconnect
• Land side cap
Multi-Die PoP• 3D tall Cu
interconnect
• Land side cap
• Fan-in RDL
Wafer Level SiP• Active and passive
components
• Sputtered EMI shield
SWIFT™ on Substrate• Split logic
• 3D Interconnect
• Land-side cap
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Summary
• Fan out packaging addresses needs from very small, low I/O devices
all the way up to large die, high end processors
• Fan out enables the most complex SiP solutions, such as mobile RF
front-end or MEMS technologies, with package form factor reduction
• Traditional fan-out will continue to be pressured by lower cost
substrate technologies
• Advanced fan out is uniquely suited:
– to improve product performance
– to handle multiple die from different functional blocks
(analog, mixed-signal, digital)
– to enable very small form factors
