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Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A Seyed Nematollah Ahmadian, Seyed Ghassem Miremadi Behavioral Modeling and Simulation (BMAS) Conf. September 2010 Sharif University of Technology Department of Computer Engineering Dependable System Lab [DSL] 1

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Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A. Sharif University of Technology Department of Computer Engineering Dependable System Lab [DSL] . Seyed ‌ Nematollah Ahmadian , Seyed Ghassem Miremadi Behavioral Modeling and Simulation (BMAS) Conf. - PowerPoint PPT Presentation

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Page 1: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Seyed‌‌Nematollah‌Ahmadian,‌Seyed‌Ghassem‌Miremadi

Behavioral‌Modeling‌and‌Simulation‌(BMAS)‌Conf.September‌2010

Sharif‌University‌of‌TechnologyDepartment‌of‌Computer‌Engineering

Dependable‌System‌Lab‌[DSL]‌‌

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Page 2: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Outline

Dependability Mixed‌Signal‌Flow Behavioral‌Fault‌Modeling Fault‌Models

Single‌Event‌Transient‌/‌Upset‌(SET/SEU) Power‌Line‌Disturbance‌(PLD) Electro‌Magnetic‌Interference‌(EMI)

Results

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Page 3: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Dependability‌and‌Reliability

Dependability‌and‌Reliability Not‌just‌words!

An‌effective‌technique‌for‌the‌experimental‌dependability‌evaluation

We‌propose‌a‌simulation-based‌fault‌injection‌method‌in‌mixed-signal‌environment.

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Page 4: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Previous‌Fault‌Injection‌Tools

Level‌of‌abstraction

HDL Circuit HDL CircuitDoes not include enough details For accurate modeling

Too slow, too old. cannot include verification method like

testbenches, etc.

solution:Mixed-signal fault injection

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Page 5: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Flow

Fault‌injection‌and‌simulation‌is‌performed‌in‌Mixed-Signal‌environment Performance/Accuracy‌tradeoff

More‌accurate‌than‌RTL‌simulationFaster‌than‌SPICE‌simulation

Fault‌injection‌on‌SoCs‌with‌analog‌coresPLLs,‌DLLs,‌SRAMs,‌…

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Page 6: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Flow

SPICE‌simulation‌near‌the‌fault‌site: accurate‌fault‌simulation

HDL‌Simulation‌(elsewhere) Motive:‌Most‌of‌the‌fault‌manifest‌themselves‌as‌and‌error‌

outside‌the‌fault‌site‌ HDL‌simulation‌provides‌enough‌accuracy‌to‌continue‌simulation.

Original‌testbenches/verification‌scripts‌are‌intact Faster‌simulation.‌Can‌compensate‌for‌the‌SPICE‌simulation‌

penalty.

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Page 7: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Fault‌Modeling

We‌develop‌fault‌models‌in‌behavioral‌modeling‌languages‌(such‌as‌Verilog-A) Easy‌modeling Reduce‌development‌time Accurate‌simulations Access‌to‌internal‌nodes/‌structure‌of‌transistor/electrical‌element

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Page 8: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Tool-chain‌architecture

Mixed-signal‌three-level‌of‌abstraction

Faults‌are‌embedded‌inside‌Verilog-A‌model. Resulted‌fault‌models‌are‌inserted‌to‌Circuit‌as‌an‌external‌component

Design Under Test Unit Under TestConverted to SPICE

Replaced device modelWith

Fault Injection

Unit under test

FaultyCell/

device

HDL level Circuit Level Gate Level

Verilog/VHDLModelSim 6.5 SE

SPICE netlistSynopsys hsim

Verilog-A modelSynopsys hsim

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Page 9: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Fault‌models

Behavioral‌fault‌modeling Single‌Event‌Transients/Upset‌‌(SET/SEU) Electro‌-Magnetic‌Interference‌(EMI) Power‌‌Line‌Disturbance‌(PLD)

Our‌flow‌supports‌other‌fault‌models‌as‌well.

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Page 10: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

SET‌Fault‌Modeling

Cause:‌hitting‌a‌high-power‌particle‌into‌transistors‌diffusion‌area.

Effect:‌transient‌current‌spike‌on‌diffusion,‌single‌event‌transient‌and‌upset.

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Page 11: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Electro-Magnetic‌Interference‌Modeling

EM‌or‌RF‌induced‌interference‌

Modeled‌as‌a‌Continues-wave‌RFI‌superimposed‌on‌specific‌nodes. Input Clock …

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Page 12: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Power‌Line‌Disturbance‌Modeling

Common‌PLDs: Power‌supply‌noise Overshoot,‌Undershoot

Ground‌Bouncing

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Page 13: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Flow:‌Initialization/Injection

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Page 14: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Flow:‌Simulation/Evaluation

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Page 15: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Experimental‌Setup

We‌used‌the‌following‌3rd‌party‌tools‌and‌IPs: HDL‌Simulator:‌ModelSim‌6.5‌SE Spice‌Simulator:‌Synopsys‌HSIM‌2008.09 Process:‌TSMC‌0.25μm

Our‌fault‌characteristics: SET:‌‌‌Q=10pc,‌with‌TO=TB=10ns‌,‌Random‌injection,‌Two‌exponential‌model

EMI:‌‌100‌MHz‌CW‌RF‌signal,‌Vpeak=‌0.5V‌,‌100ns‌pulse‌envelope,‌Random‌injection

PLD:‌‌100ns‌‌duration,‌Voltage‌shortage‌(from‌‌2.5V‌‌to‌‌0V‌)‌on‌VDD‌line,‌Random‌injection‌

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Page 16: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Results‌of‌System‌Failures

Counter FSM ALU SRAM UART AVERAGE0

10

20

30

40

50

60

70

80

90

100

PLDEMISET

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Page 17: Fault Injection in Mixed-Signal Environment Using Behavioral Fault Modeling in Verilog-A

Thank‌you!

Questions?

Thank‌you‌for‌your‌attention.

17


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