fd-soi: ecosystem and ip design

Amir Bar-Niv

IP Group, Group Director, Product Marketing

FD-SOI Symposium

February 27, 2015

San Francisco, California

FD-SOI: Ecosystem and IP Design

2 © 2015 Cadence Design Systems, Inc. All rights reserved.

The Race to Advance Nodes

• Moore’s Law continues more Features and Speed

• Increased effort to keep up with Moore's Law

Moore’s Law (1965)

2014 Apple iPhone 5sDimensions: 4.87 inches x 2.31 inches

Weight: 3.95 ounces

Processor speed: 1.3GHz, dual-core

Memory: 64GB

Display: Multi-Touch 1136 x 640

Price: $99

1966 Apollo Guidance Computer Dimensions: 24 x 12.5 x 6.5 inches

Weight: 70 pounds

Processor speed: 1 MHz

Memory: 2,048 words

Display: Seven-segment numeric

Price: $150,000 (est.)

1974

6000

1984

1000

1994

600

2004

90

2014

14

Process Node [nm]


SoC Design ChallengesBigger, More Complex, more IP

SoCs are Increasing in System

Design ComplexitySource: IBS Report, Aug. 2014

0

20

40

60

80

100

120

140

65nm 45/40nm 32/38nm 22/20nm 16/14nm

Growing Number of IP Blocks in an SoC

Other Specialty Interfaces Processors


The Advanced Node Decision Choices or Challenges?

Bulk vs. FinFet vs. FD-SOI

What is the right choice?


• Cost– FD-SOI assumed to be 10% cheaper

per die

• Power consumption – Extended battery life for IoT / consumer

– Lower thermal dissipation for Networking

• Reliability– Good reliability for Automotive

FD-SOI BenefitsCadence’ customer perspective

Low

High

High

Perf

orm

ance

Leakage

Servers

GamesSwitches, Routers,

Storage

Base stations

Digital TV

Medical

Cameras,

Mobile Graphics,

GPS

Source: IBM Corporation, 2007


Partnerships with Ecosystem Leaders

Cadence System Design SolutionComplete Support for the FD SOI Ecosystem

Mobile Consumer Cloud

Datacenter

Auto Medical

CHIP(Core EDA)

Design and implementation

IP/SoC verification

On-chip protocol IP

Dataplane unit IP

Software drivers

SYSTEM

INTEGRATION

System analysis

Hardware-Software verification

System-level IP protocols

Software applications

Software development

PACKAGE and

BOARD

PCB design

Package design

PCB and package analysis

Chip-to-chip protocol IP


Ecosystem Investment

ECOSYSTEM

Power. Performance. Area

Mobility

Cloud

Internet of things

It is critical to invest in advanced process technologies and work

closely to integrate tools and IP with foundries to bring

advanced processes to our customers

Tools IP


• Established Design Flows– Over 3 years of experience in FDSOI design

– Close development of IP, EDA tools and flows

– Support of Cadence tools and flows

• Engineering Team Experienced in FD-SOI – Analog design and layout engineers

– Digital designers

– Digital place and route engineers

• Silicon Success in FD-SOI IP– Working with lead customers

– Leading edge IP: DDR4 2667 silicon

– Multiple DDR4/DDR3 Combo PHY’s

Cadence FD-SOI Tools and IP Expertise


• 28 FD-SOI Technology– ST Technology

– Licensed by Samsung

• 28FD-SOI, 14FD-SOI, 14FF-SOI– Existing Solutions from Cadence

– Previous engagements with ST and IBM

• ST FD-SOI enablement has been provided from ST to Samsung

• IP developed for 28FD-SOI is available

Cadence FD-SOI Tools Expertise

ST 28nm

FD-SOI

ST 14nm

FD-SOI

IBM

14nm

FF-SOI

Encounter® Digital Impl. Sys. (EDI)

Encounter RTL Compiler/RTL

Compiler Advanced Physical

Quantus™ QRC Extraction Solution

Tempus™ solution

Voltus™ solution

Physical Verification System (PVS)

DFM/Litho Physical Analyzer (LPA)

DFM/Litho Electrical Analyzer (LEA)

DFM/Chemical-mechanical

planarization (CMP)

Virtuoso® simulation technology

Virtuoso MMS

Supported

In Progress*

Not planned*NOTE: for yellow and red items, please discuss with Cadence on how to proceed.

Foundry support may be negotiable, or Cadence may be able to support directly.

* This roadmap is provided for informational purposes only and does not represent a commitment to deliver any of the features or functionality discussed in the materials.


Cadence IP PortfolioBroad and growing solution for your next SoC

Interfaces Controllers and PHYs

EthernetUSB PCIe®Display

AnalogMemory Controllers and PHYs

Analog Mixed Signal

MIPI

M-PHY Gear1/2/3

D-PHY 1.1

CSI-2/DSI

SoundWire/

SLIMbus

DigRF v4

UniPro 1.6

Specialty Memory

HMC SR PHY

Wide I/O

PCIe 4.0

PCIe 3.0

PCIe 2/1

PCIe 4.0 PHY

PCIe 2/1 PHY

M-PCIe™

PCIe 3.0 PHY

USB 3.0/2.0/1.1 PHY

USB 3.0/2.0/1.1

Device

USB 3.0/2.0 Host

USB 3.0 SSIC

USB 2.0 HSIC

USB 3.0/2.0 OTG

HDCP 2.2

DRAM

DDR4

DDR3

DDR1/2

LPDDR1/2

DDR/LPDDR3/4

Combo PHY

Storage

eMMC

Toggle 1/2

SD/SDIO

UFS 2.0

ONFi 1/2/3LPDDR4

LPDDR3

SATA PHY

Gen 1,2,3 3.1

ONFi 4

HBM

USB 3.1 Host

USB 3.1 Device

USB 3.1 PHY

HDMI 1.4/2.0

MHL 3.x

DP 1.2/eDP 1.4

10/100M MAC

10/40G MAC

1G PHY

10/100 PHY

SGMII/QSGMII

PHY

XAUI/RXAUI PHY

10G-KR PHY

25/50/100G MAC

GPON, EPON PHY

1/2.5G MAC

10Gbps Multi-

protocol SerDes

320MHz 12bit

ADC

PLL/DLL

6Gbps Multi-

protocol SerDes

VT Monitors

16Gbps Multi-

protocol SerDes

3.2GHz 7bit

ADC/DAC


Cadence Design IP Latest AchievementsAdvanced technology with proven results

First tape-out of PCIe 4.0 in FinFET

First PCI Express 2.0 / 3.0 Compliance for TSMC 16FF+

First 28FD SOI DDR4 test chip silicon proven

First 16FF DDR4 silicon proven and in production

FinFet USB in high volume production

First 28nm Low Power PCIe 3.0 w/L1 SerDes

First WiGig (802.11ad) ADC/DAC in 28nm


DDR IP Leads the way in FD-SOIDDR4 Market Trends

• 50% bandwidth over DDR3, 20% less energy than DDR3

• Optimized for cloud platforms, high capacity (3D stacking, LRDIMM)

• CDNS wins@ many of ARM based micro server designs

• 2016 expected for DDR4 to be dominant memory extending to other segments

Source: IHS


• 28 FD-SOI PHY 2667Mbps– Support for DDR4 & DDR3

• High Performance– Target 2400Mbps, achieve 2667Mbps– 32 bit interface – 2 DIMM slots

– DIMM rated at 2400Mbps

– Cadence DDR 4 controller

– DDR4/3 combination IO

• First silicon operating @ 1600Mb/s in 24 hours

• Full BIST pass at 2667Mbps

Cadence DDR4 PHY IPAn Example of FD-SOI IP


• Halo/End Cap Cell– Aggressive end cap rule must be applied

on all macros

– Complex to implement, tool support

• Substrate Tap Handling– Different and counter intuitive compared to

non FDSOI (bulk)

• STA Signoff– Data derate factor

– Clock derate is reasonable

– Aging corner timing closure

– AOCV

28 FD-SOI IP Design Complexity and Challenges


DDR FD-SOI HighlightsDDR4/DDR3-2667, in silicon

• Low power digital DLL (half of Analog DLL)

• Power down modes (Deep/light sleep mode). Data Retention support

Low Power and Area

• Multi band power architecture (Analog, Logic, Clock, Delay line, IO)

• High resolution and low power digital DLL; Low noise IO

Noise Tolerance / Low Jitter

• High speed PLL & DLL (2.6GHz PLL / ~10 ps granularity DLL)

• De-skew architecture (per bit DQs,CAs, per rank, PHY Independent)

High Speed

• Accurate Delay line test; High-speed loopback test for I/O

• IEEE1500 test protocol; DRAM BIST

Testability


Complete DDR IP Solution in FD-SOIIntegrated PHY and Controller IP

Extremely Flexible

Most things in the controller are configurable or resizable to match your exact system

needs. If a feature is not needed, it is entirely removed from the RTL, scripts, and docs.

ExternalMemory

LPDDR1LPDDR2LP2NVMLPDDR3LPDDR4

DDR1DDR2DDR3DDR4

Wide-IO

Combos

PHY

DFI

Low Power

Data Management Unit

Arbitration

Unit

Round Robin

Weighted Round Robin

Priority Bandwidth

System

Port(s)

Port 0

Port 1

…

Port N

Tuning

Registers

CommandQueue

Look Ahead Optimization

PlacementEngine

ExecutionUnit

RAS DIMMBIST

Controller


• New Architecture– Based on the knowledge and methods

developed for advance node designs

• Time to Integrate– One PHY to integrate and support

• Time to Market– One PHY to bring up and characterize

– Firmware re-use for multiple links

• Protocol Versatility – One design for multiple applications

– Minimized power and logic with advanced TX and clocking architecture

Advantage of Multi-Protocol PHYTime, Flexibility and Cost

Multi-Protocol PCS

PLL

Ring Osc

Bias

Frac-N

Lane

TX/RX

DFT

LPBK

Lane

TX/RX

DFT

LPBK

Lane

TX/RX

DFT

LPBK

Lane

TX/RX

DFT

LPBK

PIPE RMMI Others…

True Multi-Protocol per lane !

• IP Cost– Single IP for multi-use

– System and software optimization

– Calibration circuit shared across multiple macros

reducing ext pins/components

"Cadence, Encounter, Quantus, Tempus, Voltus, Virtuoso, and the Cadence logo are trademarks of

Cadence Design Systems, Inc. All other trademarks and logos are the property of their respective holders."

Cadence Confidential.

Summary

FD-SOI starts to get momentum (ST, Samsung). Low power is the main benefit.

Lowlight: Uncertainty and bare-wafer cost

Highlight: Ecosystems is growing

Cadence offers a complete solution for FD-SOI System Integration, based on advance tools and IP cores

© 2014 Cadence Design Systems, Inc. All rights reserved.

Thank You !

Cadence, Encounter, Quantus, Tempus, Voltus, Virtuoso, and the Cadence logo are trademarks of Cadence Design Systems, Inc. All other trademarks and logos are the property of their respective holders.

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