the fd-soi technology for very high-speed and energy ... · pdf filethe fd-soi technology for...

The FD-SOI technology for very

high-speed and energy efficient SoCs

Giorgio Cesana

STMicroelectronics

FD-SOI Technology

2

July 2014 The FD-SOI technology for very high-speed and energy efficient SoCs

Bulk Transistor Reaching Limits at 20nm

Heavily Doped Wells High variability due to dopant fluctuation

Longer minimum gate length (less speed, less density)

Severe layout effects (wells proximity)

Gate

Gate oxide stack

Source Drain

Complex channel architecture High cost process flow (yield, cycle time, capex)

Source of variability (multiple steps)

Source of leakages currents

Limited body bias capability Weak process compensation

Low process/design co-optimization

The FD-SOI technology for very high-speed and energy efficient SoCs

FD-SOI = 2D

FinFET = 3D

gate

Thin Silicon film

gate

drain

source

heig

ht

Thin Silicon film

Depleted devices deliver improved

electrostatic control and device scalability

July 2014

3

UTBB FD-SOI, A Long R&D Success Story

1991, LETI. SmartCut patent

1992, Creation of SOITEC

1997, CNET. Silicon On Nothing Fabrication of thin BOX on ordinary

Bulk wafers within the CMOS process

1999, ST & LETI

Fabrication of SON silicon

2000, SON (Silicon On Nothing): an

innovative process for advanced CMOS

IEEE, TED, Nov. 2000 Prized with the Rappaport Award for the

best IEEE EDS paper of year 2000

2009. FD-SOI on Thin BOX Thin BOX (Buried OXide) wafers

available from Soitec

2000-2012. ST & LETI Module development

& device understanding

2012. 28nm UTBB FD-SOI

Available for production


4

28FDSOI Transistor Summary 5

Shorter

Gate Length

DIBL lowering

VT lowering

Forward/Reverse

Body Bias

Hybrid

Devices

integration


Efficient FD-SOI Transistors

• FD-SOI enables better transistor electrostatics

• Enabling faster operation at low voltage, leading to better energy efficiency

• Improving transistor behavior, especially at low supply,

enabling ultra-low-voltage operation

• Reducing transistor variability sources

• FD-SOI has a shorter channel length

• 28nm FD-SOI is in reality a 24nm technology!

• FD-SOI has lower leakage current

• Lower channel leakage current

• Carriers efficiently confined from source to drain

• Thicker gate dielectrics, leading to lower

gate leakage

• Enabling ultra low power SRAM memories

• Leakage current is less sensitive to temperature with FD-SOI

6


FD-SOI The best technology choice

7

Superior and flexible technology

Enhanced design options

Gives your SOC

competitive advantages

• FD-SOI transistors are faster, cooler, simpler

• Outstanding power efficiency across all use cases

• Efficiency at all levels: CPU, logic, Memories, Analog

• Manufacturing infrastructure and process reuse

• Improved reliability

• Very large operating range for the same design

• Back-biasing as a flexible and powerful optimization

• Ultra-wide range DVFS

• Enhanced efficiency of multi-core processing

• Easier design than FinFET

• Costs: chip-level and/or system-level

(e.g. cost of cooling)

• Thermal power dissipation (TDP)

• Extended battery life

• Computing Power / Speed / Reactivity

• Reliability

• Time-to-Market


Forward Body Biasing (FBB)

• An extremely powerful and flexible concept in FD-SOI to :

• Boost performance

• Optimize passive and dynamic power consumption

• Cancel out process variations and extract

optimal behavior from all parts

• Comparatively easy to implement – if you’ve ever done DVFS you’ll

have no difficulty with Body Biasing

8

0 1.3V

A very reasonable effort for extremely worthwhile benefits


FD-SOI: Efficiency at all levels 9

CPU, GPU and logic

FBB dynamic modulation to get

the best total power

Best dynamic power /leakage

tradeoff

Memories

Memory bit cells in FD-SOI

have much less leakage

compared to Bulk

Analog & High-speed

FD-SOI analog performance far

beyond Bulk one

Better figure of merit than

FinFET for high-speed IPs

Extended body

bias range

Lower channel leakage Lower gate leakage

Fully depleted

channel

Better transistor electrostatics


FD-SOI Energy Efficiency


28nm FD-SOI Best in class efficiency 11

20%

40%

60%

80%

100%

120%

140%

0% 20% 40% 60% 80% 100% 120% 140%

Speed (relative DMIPS)

En

erg

y e

ffic

ien

cy

(re

lative

DM

IPS

/mW

)

@ low Vdd @ highVdd (overdrive)


FD-SOI: The FBB advantage

• What is Body Biasing?

• A voltage is applied to the substrate (or body).

• When voltage is positive, it is called

Forward Body Biasing, or FBB

• Why FBB is much more efficient in FD-SOI?

• The Insulator layer (UTTB) prevents the parasitic

effects that normally appear during the body biasing

• This allows much wider range of biasing compared to Bulk

• FBB can be modulated dynamically during the transistor

operation and the transitions are transparent to the SW

• FBB benefits

• Performance boost

• Reduce power consumption at a given performance requirement

• Process compensation reducing the margins to be taken at design

• Easy to implement: seamless inclusion in the EDA flow

0 1.3V

0 0.3V

FD-SOI

Bulk


12

FBB for performance boost

• FBB provides performance boost when voltage can’t be increased

• Limited impact on dynamic power, no impact on voltage drops

More efficient performance increase than turning the voltage

• Impact on leakage at high temperature

Back into 28G range but leakage can be turned off anytime by removing FBB

0.6V

1.1V

Frequency

Total Power

1.1V FBB

FBB

FBB = more performance


13

FBB improves power efficiency

• FBB improve the power efficiency at a given frequency

• Limited impact on leakage, slightly higher than without FBB

• Drastically decrease dynamic power

0.6V

0.9V

FBB

Frequency

Total Power

0.8V

0.9V

FBB = less power


14

Process Compensation

by Forward Body Bias


15

0.1

1

10

100

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7

Leakag

e P

ow

er

@ 1

.0V

/125C

(m

W)

Frequency @ 0.8V/WC_temp (GHz)

SS

TT

FF

Performance Corner Spread w/o Body Bias 16


Lmin

+4nm

+10nm

+16nm

• Frequency and leakage corner spreads depend on PVT and channel

length

FF TT

SS

0.1

1

10

100

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7

Leakag

e P

ow

er

@ 1

.0V

/125C

(m

W)


SS

TT

FF

WC

Worst Case Performances w/o Body Bias 17


Lmin

+4nm

+10nm

+16nm

• For each gate length, the worst case performance trend (WC) is built

using the slowest case (SS) and the leakiest case (FF)

• This is what used for ASIC sign-off

FF TT

SS WC

FF

FBB-based Process Compensation: Principle

• SLVT doesn’t allow RBB FBB must be applied on typical to allow

“pseudo-RBB” for Fast parts (leakage containment)

• Higher FBB is applied to accelerate Slow parts

18


Typical FBB

FF SS

TT TT

SS

FBB

(to accelerate Slow parts) FBB

(to reduce leakage

on Fast parts)

Frequency gain

on Slow parts

Fast parts leakage

unchanged

1

10

100

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7

Leakag

e P

ow

er

@ 1

.0V

/125C

(m

W)


SS FBB 500mV

TT FBB 250mV

FF 0FBB

WC

Process Compensation Through FBB 19


Lmin

+4nm

+10nm

+16nm

• Process Compensation through FBB allows

• Masking SS-FF process spread

• Recovering +17% speed in 28nm FD-SOI, at no dynamic power expense

(as it would happen if using AVS)

WC

+17%

Process Compensation Benefits The case of a Cortex M4

• ARM Cortex-M4

• 50kgates, 5k FF

• Target frequency: 700MHz @ WC/0.8V

• Two implementations comparison

• Standard methodology, full process spread sign-off

• Process compensation by FBB

• SS corner is compensated by 600mV FBB

20

ARM Cortex-M4 FDSOI28

Standard Proc. Comp. Diff/ %

Area (µm²) 81’407 61’035 -25%

Total Power @ Vmax, 125C, RCmax

REF 0.55x -45%

Leakage (mA) @ Vmax, 125C

REF 0.49x -51% 0

10

20

30

40

50

PB0 PB4 PB10 PB16K

gate

s

Multi-Channel Length Repartition

STD

ProcComp


FD-SOI Technology for Fast

CPU/GPU

21


Demonstrated Reduced Design Effort for Full 28nm SoC Porting

• Same design flow as for 32/28nm LP

• Same tools used

• Same design cycle time

• True concurrent engineering

• FDSOI product received before bulk version

22

• Direct mapping of IPs + ECO

• Script based

• Faster than rerunning synthesis

• Floorplan reuse

CPU

Dual Cortex A9

+40% in speed

> 3X at low V

GPU

SGX544 MP1

+20% at nom V

Power reduction

HD camera

IP

+30% in speed

LPDDR2

533Mhz

-15% in power

PLLs

Up to 4.6GHz

-15% in power


FD-SOI allowing Ultra-Wide DVFS

• FD-SOI allows the widest Vdd range

for voltage scaling

• Still guaranteeing top notch speeds

at very low operating voltage

• >5x when compared to 28LP technology

• >35% when compared to 28G technologies

• DVFS energy efficiency optimization

is further extended thanks to body bias

• Allowing to balance and optimize the static

and dynamic power consumption components

23

1 GHz at 0.61V

2.3 GHz at 1.0V

3.0 GHz at 1.34V

300 MHz at 0.5V

CPU freq. (GHz)

CPU supply (V)

3

2

1

0.5 0.6 0.8 0.9 1.0 1.1 1.2 1.3 1.4 0.7

Real measurements of continuous DVFS

in the range 0.5V – 1.4V

Performed on a very large number of

ICs, showing extremely good reliability of

the DVFS in this range


Dual Cortex A9 subsystem architecture

Soc supply

Vana

AXI FIFO AXI FIFO

misc i/f misc i/f

ls

ctrl regs

AXI

SCU/L2 cache logic

cache memories periphery

L2 cache + L2 tag memories array

CPU Core #0 logic

CPU Core #1 logic

6T ram arrays

L1 ram periph

6T ram arrays

L1 ram periph

body biased region under Varm

vbbn/ vbbp

Body-Bias generator

DVFS ctrl

Process Monitors

Varm

on-die decap

Vmem

clamp

on/off switch

on/off switch

power switch

power switch

power switch

PLL

D.Jacquet et al., VLSI Symposium 2013 July 2014 The FD-SOI technology for very high-speed and energy efficient SoCs

24

Body-Bias voltage generation 25

• How to generate programmable body voltages ?

gnds grid

PW

P

W

NM

O

S

PM

O

S

D-N

W

P-S

UB

NW

vdds grid

FBB : positive V 0V

t

FBB : negative V 0V

t

DAC

0 -1.3V

Neg.

Charge Pump

1V8

GND

-1V8

DAC

0 1.3V


Fully digital testing of the BBgen

• The BBgen is generating 2 independent voltages

• For the Nmos [0 to 1.3V] & Pmos [-1.3V to 0V] bodies

• With a resolution of 100 mV

• The embedded process monitors allow a full digital test of the BBGen in production test

• No need for body nodes external access

• Full access via a digital interface

Body Bias Gen

vbbn

vbbp

Process monitor

Process monitor

Process monitor frequency (MHz)

Volt

age (

V)

Slide 26

Tester digital interface


26

Only few mV

1ms

Fast dynamic body-bias management

• Low Zout amplifiers allow ms settling time of the body nodes

• E.g. 3 body domains connected to the same generator

• Each body domain can be activated

• In less than 1ms

• Activating any body domain does not disturb the voltage of the others

The FD-SOI technology for very high-speed and energy efficient SoCs July 2014

BB Domain#2 voltage

BB Domain#1 voltage

BB Domain#0 voltage

Slide 27 D.Jacquet et al., VLSI Symposium 2013

27

Cortex A9 Power vs. Performances

• LVT only block (multi-channel: Lmin to +16nm)

• Measurements done on board at room temperature

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0

50

100

150

200

250

300

350

400

450

500

ARM 0.8GHz ARM 1.2GHz ARM 1.5GHz ARM 1.85GHz ARM 2.0GHz ARM 2.3GHz

To

tal

Po

we

r (m

W)

A9 Single Dhrystone power consumption

28nm-bulk Pow

28nm-FD-SOI Pow

28nm-FD-SOI FBB Pow

Gain

Gain FBB


28

Cortex A9 Benchmark

28nm Silicon Results 29


• VMIN for a given frequency (1.85GHz) • Vmin search is an EWS metric for Fmax

• The metric allows a one-to-one benchmark between 28FD and 28LP performances

28LP Corner

28FD Corner Lot

(slow corner wafers)

Cortex A9 Benchmark

Process Compensation through FBB 30

• Applying FBB 600mV enable reaching the target VMIN perfs • SLOW Population brought in TT-FF range

28LP Corner

28FD TYP and FF Corner wafers with 0V FBB

28FD Slow Corner wafers with 600mV FBB


Cooler Demo 31


FD-SOI Technology for Ultra

Low Power / Voltage applications


ULV Gains Confirmed in 28 FD-SOI

• Intrinsic FD-SOI advantage for ULV

• Electrostatic control enhancement

speed at low voltage

• Undoped homogeneous channel

Reduced variability

Lower minimum usable supply voltage

• Specific design solutions

to leverage FDSOI outstanding

performance at ULV

• Higher ION for clock tree

• FBB for improved energy efficiency

and delay

33

Ultra-Low Voltage through technology and

design boosts

BULK

BULK ULV

BULK ULV

Optimized

FD-SOI ULV

optimized

Standard

design voltage

scaling

ULV design.

Logic, Memories, Flow

FD-SOI

Technology

boost

ULV

optimization

Frequency efficiency reliable

En

erg

y


ULV Si Evidences at 28nm

• 2 BCH decoders: 28FD vs. 28LP

• 252b frame error-decoder

• Both adopting ULV specific design

• FD-SOI boost at ULV

• Ultra-wide DVFS

• From 1 to 700 MHz for 0.35-1.00V

• Higher frequency at given energy

• x1.3 to x4

• Energy saver at given frequency

• -25% to -50%

• Yielding at lower voltages

• FD-SOI at 100% yield already at 0.35V

• 100mV lower than 28LP

34

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1 10 100 1000

Ene

rgy

(nJ)

Frequency (MHz)

BULK

FDSOI

0.35V

Freq. x4

1V

Freq. x1.3

Energy

-50%

en

erg

y

0%

25%

50%

75%

100%

0.35V 0.40V 0.45V

BULK

FDSOIY

ield

, 3

0°C

, 1

MH

z


DSP architecture

Bit

Exte

nsio

n

Shift

Reg.

32bit VLIW DSP core - V/F domain

Control

Address

Gen.

Data

SRAM

Address

Gen.

Regis

ter

Arr

ay

2R

ea

d-1

Write

Port

s 6

4x3

2b

Mux

Comp/Select 3

2b

Multip

lier

Adde

r

40

b

Mux Bit T

runc

Prog

SRAM

MAC

Serial

Interface

Variability

Power

Control (CVP) PLL

Input/Output

RAM

2x1Kx32

CODA TMFLT-R

Cordics

+

Divider

Shift

Reg.

Bit

Exte

nsio

n

TMFLT-

S

TMFLT-

S

TMFLT-

S

TMFLT-

S

TMFLT-

S

TMFLT-

S

© 2014 IEEE - International Solid-State Circuits Conference 27.1 : A 460MHz@397mV – [email protected] 32bit VLIW DSP Embedding FMAX Tracking


35

Chip Micrograph

Technology UTBB FDSOI

28 nm

Transistors LVT

Lmin=24nm

Core area 1 mm²

DSP

benchmark FFT 1024

VDD range 0.397V-1.3V

VBB range 0V/±2V



36

DSP speed performance measured results

460MHz@397mV

• FBB up to +2V and FMAX tracking : – ↗ frequency up to 460MHz at minimum voltage

0

500

1000

1500

2000

2500

3000

300 400 500 600 700 800 900 1000 1100 1200 1300

Fre

quency (

MH

z)

VDD voltage (mV)

Boost 0mV

Boost 500mV

Boost 1000mV

Boost 1500mV

Boost 2000mV

FBB 0V

FBB 0.5V

FBB 1.0V

FBB 1.5V

FBB 2.0V

1GHz@570mV

[email protected]



37

DSP energy performance measured results

0

50

100

150

200

250

300

350

400

450

300 500 700 900 1100 1300 1500 1700 1900 2100 2300 2500

Frequency (MHz)

Boost 0mV

Boost 500mV

Boost 1000mV

Boost 1500mV

Boost 2000mV

62pJ/cycle @ 460MHz

FBB 0V

FBB 0.5V

FBB 1.0V

FBB 1.5V

FBB 2.0V

• For a fixed voltage supply : – Lowest energy at 460MHz

– Power consumption : 370mW at 1V

En

erg

y/c

ycle

(p

J/c

ycle

)



38

Comparison with State of the Art WVR

MIT, TI, 28nm, ISCC 2011

MIT, TI, 28nm, ISSCC 2011

MIT, TI, 28nm, ISSCC 2011

INTEL, 32nm, ISSCC 2012

INTEL, 32nm, ISCC 2012

INTEL, 22nm, ISCC 2012

NXP, IMEC, 32nm, ISSCC

2011

CSEM (100µW/MHz)

TI (200µW/MHz)

TI, CEVA, 40nm TI, 40nm

22nm, INTEL, ISSCC

1

10

100

1000

0 0.2 0.4 0.6 0.8 1 1.2 1.4

3000 3000

Fre

qu

ency (

MH

z)

This work

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Supply Voltage (V)



39

Thank You!

40


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