fee electronics progress

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FEE Electronics progress •Mezzanine manufacture progress •FEE64 testing and VHDL progress •Test mezzanine. •Trial mechanical assembly 10th November 2009

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FEE Electronics progress. Mezzanine manufacture progress FEE64 testing and VHDL progress Test mezzanine. Trial mechanical assembly. Mezzanine manufacture Progress. PCB design sent to manufacturer Order for assembly placed and parts purchase started. - PowerPoint PPT Presentation

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Page 1: FEE Electronics progress

FEE Electronics progress•Mezzanine manufacture progress•FEE64 testing and VHDL progress•Test mezzanine.•Trial mechanical assembly

10th November 2009

Page 2: FEE Electronics progress

Mezzanine manufacture Progress

10th November 2009

• PCB design sent to manufacturer• Order for assembly placed and parts

purchase started.• PCB manufacture error requires

restarting the build.• Expect PCB this week.• Assembler planning sequence broken

– hard to predict delivery until pcb arrives.

• Two of the failed pcbs delivered to use for mechanical checks.

• ERNI connector mounted – pcb too large – manufacturer will change by 1mm overall

• Plan to send one pcb to wirebond engineers.

Page 3: FEE Electronics progress

FEE64 testing and VHDL progress

• Assembled boards delivered.• Power supplies tested and found to be working OK after a couple of wire mods.• FPGA programmed through JTAG port.• Two misplaced devices removed and re-fitted• Flash memory programmed and used to program the FPGA.

10th November 2009

Page 4: FEE Electronics progress

FEE64 testing and VHDL progress• 128MB SDRAM operating successfully• Gbit ethernet functions at 10/100/1000 Mbits/s• Linux loaded over the network after the core loaded by JTAG.

Loading from Flash memory not functioning yet.• Some ethernet problems solved by damping capacitor.• Ethernet rate tests => 10MB/sec

10th November 2009

Started testing the multiplex readout ADC.First results using MIDAS and TCL scripts.100mV input via the test mezzanine.VHDL for timestamped ASIC driven operation in progress.

Page 5: FEE Electronics progress

FEE64 testing and VHDL progress

Test system

10th November 2009

Test mezzanine

Power supplies ( +30v , -5v)

DC source

Page 6: FEE Electronics progress

Clock distribution• Schematics for four way clock distribution box entered.• Pcb layout to proceed after VHDL for acquisition complete.• Designed for manufacture locally.

10th November 2009

FEE64 (sync master)

FEE64

FEE64

FEE64

Clock box

200Mhz clock and SYNC distribution

Master SYNC to clock box

Page 7: FEE Electronics progress

Test mezzanine

• Two assembled boards delivered 4th November.• In use in T9 to exercise the multiplex readout ADC.

10th November 2009

Page 8: FEE Electronics progress

Trial mechanical assemblyPlastic versions of the FEE mechanics created by a ‘Z’ printer.

Two FEE64 cards and two mezzanine scrap boards assembled.

Some alterations to the spacer required.

10th November 2009