feedforward operational amplifier

Basem Soufi Copy Right (c) 1

High Speed, High Gain Operational High Speed, High Gain Operational High Speed, High Gain Operational High Speed, High Gain Operational

Amplifier ResearchAmplifier ResearchAmplifier ResearchAmplifier Research

Basem SoufiBasem SoufiBasem SoufiBasem Soufi

Iowa State UniversityIowa State UniversityIowa State UniversityIowa State University

[email protected]@[email protected]@iastate.edu

1/7/2005 1Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Research Interest Research Interest Research Interest Research Interest Next Stage

VinVin

SUB-SUB-ADC

DAC

Amplifier Settling The Classical Pipeline Stage has My Amplifier Settling

Time (Bandwidth)

Amplifier Settling

Pipeline Stage has many different performance

My

personal

research Amplifier Settling Accuracy (Gain)

Slew Rate

performance limitations. Amplifier Design is the main challenge when

research

specific

interest at

Performance LimitationsCapacitor Mismatch

Slew Ratechallenge when designing for low power, low voltage,

interest at

Iowa State

UniversityCapacitor Mismatch

Offset

power, low voltage, high speed and resolution

2Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005


Feed forward Architecture to Bypass Feed forward Architecture to Bypass Feed forward Architecture to Bypass Feed forward Architecture to Bypass

Parasitic Poles.Parasitic Poles.Parasitic Poles.Parasitic Poles.

Last Update 10/5/2005Last Update 10/5/2005Last Update 10/5/2005Last Update 10/5/2005


The Opamp ProblemThe Opamp ProblemThe Opamp ProblemThe Opamp Problem

�� The operational amplifier problem is a very The operational amplifier problem is a very The operational amplifier problem is a very The operational amplifier problem is a very

matured analog problem. matured analog problem.

�� Researching the literature, found no architecture Researching the literature, found no architecture

can solve all the problems at once.can solve all the problems at once.can solve all the problems at once.can solve all the problems at once.

�� Key amplifier characteristics are to haveKey amplifier characteristics are to have highhigh--�� Key amplifier characteristics are to haveKey amplifier characteristics are to have highhigh--

gain, highgain, high--bandwidth, high bandwidth, high GBW/Power GBW/Power ratio, ratio, gain, highgain, high--bandwidth, high bandwidth, high GBW/Power GBW/Power ratio, ratio,

high output signal swing, and fast settling step high output signal swing, and fast settling step high output signal swing, and fast settling step high output signal swing, and fast settling step

response.response.



Bad Assumption in Multistage Bad Assumption in Multistage Bad Assumption in Multistage Bad Assumption in Multistage

Opamp DesignOpamp DesignOpamp DesignOpamp Design

�� When designing multiWhen designing multi--stage amplifiers, most stage amplifiers, most �� When designing multiWhen designing multi--stage amplifiers, most stage amplifiers, most

authors, even with feedauthors, even with feed--forward architectures, forward architectures, authors, even with feedauthors, even with feed--forward architectures, forward architectures,

assumeassume that the internal parasitic poles are located that the internal parasitic poles are located

at a very high speed and can be ignored for at a very high speed and can be ignored for

design purposes.design purposes.design purposes.design purposes.

�� This is a very bad assumption when you need to This is a very bad assumption when you need to �� This is a very bad assumption when you need to This is a very bad assumption when you need to

build amplifiers with operational frequencies build amplifiers with operational frequencies build amplifiers with operational frequencies build amplifiers with operational frequencies

near those ignored poles.near those ignored poles.near those ignored poles.near those ignored poles.


Frequency Segregation Structure Frequency Segregation Structure -- Intuitive Intuitive

Idea DevelopmentIdea DevelopmentIdea DevelopmentIdea Development

• By passing internal

parasitic poles of earlier

stages that are not stages that are not

needed at high

frequencies.In phase

signals frequencies.

• A1 has the highest DC

gain and lowest power

signals

gain and lowest power

consumption A3 has the

highest speed and most of highest speed and most of

the power consumption

• GB and Slew-Rate are • GB and Slew-Rate are

mostly determent by

A3…that’s good news! A3…that’s good news!

(90% of power in A3!)

• If A3 is simple CS amp, Smaller feature size is actually good for this architecture (Better • If A3 is simple CS amp,

then, GBW/POWER is

of single stage and “rail-

Smaller feature size is actually good for this architecture (Better

GBW/Power ratio), while maintaining high DC gain and

going well beyond the speed of internal parasitic poles.


of single stage and “rail-

to-rail” output swing.

going well beyond the speed of internal parasitic poles.


TwoTwo--Stage implementation and modeling Stage implementation and modeling

without parasiticswithout parasiticswithout parasiticswithout parasiticsCircuit Issues: [1]

In phase (LHP

Zero) Circuit Issues: [1]

1) Positive feedback through Cf

Zero)

2) Negative capacitance at the input

3) Pole-Zero doublet (process variations)3) Pole-Zero doublet (process variations)

Solving issues 1&2:

Add a buffer. This will consume power.

Several design strategies and circuit

techniques can be used. Will use Ideal techniques can be used. Will use Ideal

Buffers for now.

Open Loop poles and zero (ignoring Rs=Ideal Buffer

Z = −gm1/Cf GB = Cf/(C1 + Cf)*gm2/CII

Open Loop poles and zero (ignoring Rs=Ideal Buffer

Added):

Z = −gm1/Cf

P1 = −go1/CI (CI=C1+Cf)

P2 = −go2/CII (CII=C2+CL)

GB = Cf/(C1 + Cf)*gm2/CII


P2 = −go2/CII (CII=C2+CL)

Want P2=Z

Open Loop Model Frequency ResponseOpen Loop Model Frequency Response

First Order Overall Frequency Response with perfect zero-pole with perfect zero-pole cancellation

Pole-Zero Pole-Zero cancellation

90 Degrees Flat Phase Response90 Degrees Flat Phase Response

Two stage model ac simulation when no parasitics

poles are included. Used ideal vccs, resistors, caps,

and a buffer to simulate the model.


and a buffer to simulate the model.


Model Step ResponseModel Step Response

Two Stage model simulation when no parasitics poles included. Used ideal vccs, resistors, caps, feedback

network and a buffer to simulate the model.


network and a buffer to simulate the model.

Tuning the PoleTuning the Pole--Zero Mismatch with process Zero Mismatch with process

variations. variations. Case with no parasitic polesCase with no parasitic poles. . variations. variations. Case with no parasitic polesCase with no parasitic poles. . -45° phase shift occurs at the pole.-45° phase shift occurs at the pole.

+45° phase shift occurs at the zero.

Idea!

Detect the respective frequencies of 45° Detect the respective frequencies of

the phase shifts of the zero and

pole, and tune one of them to

45°

overlap the other.

The principle of pole-zero The principle of pole-zero

mismatch correction is NOT new.

[2]

When we have the closed loop poles widely separated, then the best settling time is achieved When we have the closed loop poles widely separated, then the best settling time is achieved

when we have 100% pole-zero cancellation. For widely separated poles, the maximum allowable

overlap mismatch that results in a system that settles at least as fast as one without a mismatch overlap mismatch that results in a system that settles at least as fast as one without a mismatch

is in the order of the settling accuracy requirement. So, for 0.001% settling accuracy, we need

0.001% tuning accuracy [3], this fact makes tuning very difficult if one desires very fast settling


0.001% tuning accuracy [3], this fact makes tuning very difficult if one desires very fast settling

requirement.


ClosedClosed--loop dominant pole movement with different feedback loop dominant pole movement with different feedback

factors when perfect zerofactors when perfect zero--pole cancellation occurs.pole cancellation occurs.factors when perfect zerofactors when perfect zero--pole cancellation occurs.pole cancellation occurs.

Model simulation with no parasitic pole in the first stage Model simulation with no parasitic pole in the first stage

Accurate second stage Accurate second stage pole and zero cancellation

Dominant pole movementDominant pole movement

Feedback factor = 1Feedback factor = 0Feedback factor = 0

Dominant pole rolls to higher frequencies as the feedback factor increases, identical to a first-order closed loop response. This occurs with accurate pole-zero cancellation.


loop response. This occurs with accurate pole-zero cancellation.

Ideal two stage model with no parasitics in the first stage.Ideal two stage model with no parasitics in the first stage.

Poles movement with different feedback factors when the zero Poles movement with different feedback factors when the zero Poles movement with different feedback factors when the zero Poles movement with different feedback factors when the zero

is is fasterfaster than the second stage pole.than the second stage pole.is is fasterfaster than the second stage pole.than the second stage pole.

Zooming in

Second Stage Dominant Pole

First Stage Dominant Pole

Z

Dominant Pole

First stage and second stage pole come together and form a complex conjugate pair at low feedback

factor values (close to 1/(second stage open loop gain)), then, the pole of the second stage come

back close to the zero and the first stage travels to higher frequencies.


back close to the zero and the first stage travels to higher frequencies.


Ideal two stage model with no parasitics.Ideal two stage model with no parasitics.Ideal two stage model with no parasitics.Ideal two stage model with no parasitics.

Poles movement with different feedback factors when the zero Poles movement with different feedback factors when the zero

is is slowerslower than the second stage pole.than the second stage pole.is is slowerslower than the second stage pole.than the second stage pole.

Zooming in

Second Stage Dominant Pole Z

First Stage Dominant Pole

First stage pole come closer to the zero and gets partially cancelled and forms a dipole. While the

second stage travels to higher frequencies.


So, what does this tell us?So, what does this tell us?So, what does this tell us?So, what does this tell us?

�� The relative position of the zero in respect to The relative position of the zero in respect to �� The relative position of the zero in respect to The relative position of the zero in respect to

open loop poles has drastic effects on the open loop poles has drastic effects on the open loop poles has drastic effects on the open loop poles has drastic effects on the

behavior of the closed loop poles.behavior of the closed loop poles.

�� It is an interesting caseIt is an interesting case--study to see how fast the study to see how fast the

system settles relative to a twosystem settles relative to a two--pole system and pole system and system settles relative to a twosystem settles relative to a two--pole system and pole system and

how sensitive to process variations the system is how sensitive to process variations the system is how sensitive to process variations the system is how sensitive to process variations the system is

when we have when we have small closed loop factorsmall closed loop factor, or more , or more when we have when we have small closed loop factorsmall closed loop factor, or more , or more

specifically, when we have complex conjugate specifically, when we have complex conjugate

pair and a zero. pair and a zero. pair and a zero. pair and a zero.



Studying the circuit with parasitic Studying the circuit with parasitic Studying the circuit with parasitic Studying the circuit with parasitic

poles in the first stage.poles in the first stage.poles in the first stage.poles in the first stage.


Modeling the two stage amplifier Modeling the two stage amplifier

with a parasitic pole in the first stage.with a parasitic pole in the first stage.with a parasitic pole in the first stage.with a parasitic pole in the first stage.

Feed-Forward CapCap

Cascode First Stage Ideal Buffer

Second Stage Model

Cascode First Stage Model

Vout

Vin

Vout

Deriving the transfer function Vout/Vin we see a three pole, two zero system. If there are more parasitic Deriving the transfer function Vout/Vin we see a three pole, two zero system. If there are more parasitic capacitances in the first stage getting by-passed by the capacitor, then an additional zero will appear. The case of one parasitic pole in the first stage is chosen to simplify the analysis.



Some simulations to prove the concept of bySome simulations to prove the concept of by--

passing parasitic polespassing parasitic polespassing parasitic polespassing parasitic poles

Overall Stage Gain

Without

Feed-

First Stage Gain

Overall Stage Gain

forward By-

Pass Path.Second Stage Phase

Second Stage Gain

First Stage Phase

A nasty Parasitic pole


Parasitic Pole ByParasitic Pole By--Passed!Passed!Parasitic Pole ByParasitic Pole By--Passed!Passed!

Near First Order

Transfer Curve.

With Feed-

Forward By-Transfer Curve.

Pass Path.

The main Zero-Pole

cancellationcancellation



Movement of the poles in the closed loop Movement of the poles in the closed loop

configuration when the model has a parasitic configuration when the model has a parasitic configuration when the model has a parasitic configuration when the model has a parasitic

pole in the first stagepole in the first stagepole in the first stagepole in the first stageIn all the following figures, Green is the dominant pole of the first stage, red is the

dominant pole of the second stage, and blue is the parasitic pole of the first stage. We can dominant pole of the second stage, and blue is the parasitic pole of the first stage. We can

see the additional zero in the transfer function due to by-passing the parasitic pole. We can

also observe that the parasitic pole always travels to much higher frequencies.also observe that the parasitic pole always travels to much higher frequencies.

When the dominant Zero When the dominant Zero When the dominant Zero When the dominant Zero

is after the pole of the

second stage.

When the dominant Zero

is before second stage

pole.

When the dominant Zero

accurately cancels the

second stage pole.


Tuning FactsTuning Facts

�� Tuning poles and zeros in FF opamps is Tuning poles and zeros in FF opamps is NOTNOT new [2]!new [2]!

�� When having a parasitic pole, the pole location of the second When having a parasitic pole, the pole location of the second stage and the dominant zero, are not located at stage and the dominant zero, are not located at --45 and +45 45 and +45

�� When having a parasitic pole, the pole location of the second When having a parasitic pole, the pole location of the second stage and the dominant zero, are not located at stage and the dominant zero, are not located at --45 and +45 45 and +45 phase shifts respectively as the case when we had an ideal first phase shifts respectively as the case when we had an ideal first order first stage amplifier. This makes the tuning the amplifier in order first stage amplifier. This makes the tuning the amplifier in phase shifts respectively as the case when we had an ideal first phase shifts respectively as the case when we had an ideal first order first stage amplifier. This makes the tuning the amplifier in order first stage amplifier. This makes the tuning the amplifier in the open loop phase domain harder if not impossible.the open loop phase domain harder if not impossible.

�� However, sweeping the FF capacitor in simulation over a certain However, sweeping the FF capacitor in simulation over a certain �� However, sweeping the FF capacitor in simulation over a certain However, sweeping the FF capacitor in simulation over a certain range, will guarantee a pole zero cancellation. Such tuning is range, will guarantee a pole zero cancellation. Such tuning is illustrated next.illustrated next.illustrated next.illustrated next.

�� When changing the FF capacitor, will also change the GB of the When changing the FF capacitor, will also change the GB of the �� When changing the FF capacitor, will also change the GB of the When changing the FF capacitor, will also change the GB of the amplifier, however, fine tuning change in the feedforward amplifier, however, fine tuning change in the feedforward capacitor changes the GB negligibly.capacitor changes the GB negligibly.capacitor changes the GB negligibly.capacitor changes the GB negligibly.



Simulation to prove the tuning concept Simulation to prove the tuning concept

by linear sweeping of the FF capacitorby linear sweeping of the FF capacitorby linear sweeping of the FF capacitorby linear sweeping of the FF capacitor

500fF

700fF Feedback 700fF Feedback

factor is 0.5

500fF500fF1pF

This is a three pole,

two zero system.two zero system.

Zero movement with FF capacitance sweeping, and fine tuning the dominant zero

location by sweeping a varactor at the parasitic node will be shown next.


Zeros movement with FF capacitor sweeping.Zeros movement with FF capacitor sweeping.Zeros movement with FF capacitor sweeping.Zeros movement with FF capacitor sweeping.

Dominant zero movement.

Non-Dominant zero

movement.movement.



Fine tuning the dominant zero by sweeping a Fine tuning the dominant zero by sweeping a Fine tuning the dominant zero by sweeping a Fine tuning the dominant zero by sweeping a

varactorvaractor added at the parasitic added at the parasitic nodenode

Fine tuning

the dominant

zero by

Large sensitivity of Non-

Dominant zero & its movement

zero by

sweeping a

varactor at the

parasitic node.Dominant zero & its movement

while incrementing the parasitic

capacitance

parasitic node.


Tuning Ideas.Tuning Ideas.Tuning Ideas.Tuning Ideas.�� We can have a spectrum based tuning. Since it is We can have a spectrum based tuning. Since it is �� We can have a spectrum based tuning. Since it is We can have a spectrum based tuning. Since it is

a differential circuit, the amplifier can be a differential circuit, the amplifier can be configured in a closed loop SC amplifier. The configured in a closed loop SC amplifier. The configured in a closed loop SC amplifier. The configured in a closed loop SC amplifier. The thirdthird--order harmonic distortion can be detected order harmonic distortion can be detected thirdthird--order harmonic distortion can be detected order harmonic distortion can be detected and the capacitor can be swept to minimize it.and the capacitor can be swept to minimize it.and the capacitor can be swept to minimize it.and the capacitor can be swept to minimize it.

�� In ADC design, calibration algorithms can be In ADC design, calibration algorithms can be used to tune the amplifier for less integral nonused to tune the amplifier for less integral non--used to tune the amplifier for less integral nonused to tune the amplifier for less integral non--linearity. Since in two stage Amplifier there is linearity. Since in two stage Amplifier there is linearity. Since in two stage Amplifier there is linearity. Since in two stage Amplifier there is only one zeroonly one zero--pole cancellation taking place, the pole cancellation taking place, the only one zeroonly one zero--pole cancellation taking place, the pole cancellation taking place, the search algorithm for the optimal tune can be search algorithm for the optimal tune can be done with smalldone with small complexitycomplexity..done with smalldone with small complexitycomplexity..



Solving the Positive FeedbackSolving the Positive FeedbackSolving the Positive FeedbackSolving the Positive Feedback

�� Adding a buffer in the forward path to block the Adding a buffer in the forward path to block the �� Adding a buffer in the forward path to block the Adding a buffer in the forward path to block the

positive feedback will compromise the positive feedback will compromise the positive feedback will compromise the positive feedback will compromise the

performance of the operational amplifier.performance of the operational amplifier.

�� Creating a negative feedback to cancel the Creating a negative feedback to cancel the

positive feedback should in principle mitigate positive feedback should in principle mitigate positive feedback should in principle mitigate positive feedback should in principle mitigate

the positive feedback effect.the positive feedback effect.the positive feedback effect.the positive feedback effect.

�� Matching between the canceling paths becomes Matching between the canceling paths becomes �� Matching between the canceling paths becomes Matching between the canceling paths becomes

an issuean issuean issuean issue


Solving the Positive FeedbackSolving the Positive Feedback--Solving the Positive FeedbackSolving the Positive Feedback--

continue continue continue continue Passive Paths provide bidirectional connectivity.

No power consumption by the path. No No power consumption by the path. No

speed/power tradeoff.

Buffered forward path adds a pole to the system

with speed limitation and added power

consumption. However, the positive feedback is consumption. However, the positive feedback is

solved.

-1-1

Cancellation of the positive feedback with a

negative feedback eliminates the pole in the negative feedback eliminates the pole in the

feedforward path and provides a much more

attractive speed/power tradeoff.


attractive speed/power tradeoff.


Final Circuit SchematicFinal Circuit SchematicFinal Circuit SchematicFinal Circuit Schematic

The final circuit contains a feedforward path whose positive feedback path is cancelled with a buffered The final circuit contains a feedforward path whose positive feedback path is cancelled with a buffered negative feedback.

The canceling feedback paths should match well. This means the buffer should be as close to -1 as The canceling feedback paths should match well. This means the buffer should be as close to -1 as possible while having the capacitors matched as well.

Since the opamp A1 already has a finite input capacitance, there is a room for mismatch in the Since the opamp A1 already has a finite input capacitance, there is a room for mismatch in the cancellation method

The bandwidths of the buffer of the canceling negative feedback needs not to be any larger than the The bandwidths of the buffer of the canceling negative feedback needs not to be any larger than the bandwidth of A1.


Comparison Comparison -- 11Comparison Comparison -- 11

�� The circuit in [5] provides, and to a certain degree, The circuit in [5] provides, and to a certain degree, �� The circuit in [5] provides, and to a certain degree, The circuit in [5] provides, and to a certain degree,

polepole--zero tracking with process variations. However, zero tracking with process variations. However,

the feedforward path consumes a lot of power for a the feedforward path consumes a lot of power for a

certain bandwidth as the designer in [5] says: “certain bandwidth as the designer in [5] says: “The main certain bandwidth as the designer in [5] says: “certain bandwidth as the designer in [5] says: “The main

restriction here is that the nondominant pole of the restriction here is that the nondominant pole of the

feedforward and second stage must be placed after the

overall unity-gain bandwidth of the amplifier in order to overall unity-gain bandwidth of the amplifier in order to

minimize phase degradation.” The feedforward path of minimize phase degradation.” The feedforward path of

[5] consumes 71% of total power!!!



ComparisonComparison--22ComparisonComparison--22

�� The circuits presented in [4] and [5] reduce the The circuits presented in [4] and [5] reduce the �� The circuits presented in [4] and [5] reduce the The circuits presented in [4] and [5] reduce the

output impedance of amplifier making it very output impedance of amplifier making it very output impedance of amplifier making it very output impedance of amplifier making it very

difficult to maintain the DC characteristic of the difficult to maintain the DC characteristic of the

amplifier.amplifier.

To reTo re--iterate, the active feedforward scheme iterate, the active feedforward scheme �� To reTo re--iterate, the active feedforward scheme iterate, the active feedforward scheme

consumes a lot of power, degrades the phase, consumes a lot of power, degrades the phase, consumes a lot of power, degrades the phase, consumes a lot of power, degrades the phase,

and reduces the output impedance.and reduces the output impedance.and reduces the output impedance.and reduces the output impedance.


ComparisonComparison--33ComparisonComparison--33

�� The presented circuit provides High Gain, High The presented circuit provides High Gain, High �� The presented circuit provides High Gain, High The presented circuit provides High Gain, High Bandwidth, without sacrificing much power in the Bandwidth, without sacrificing much power in the feedforwardfeedforward bandwidth.bandwidth.feedforwardfeedforward bandwidth.bandwidth.

�� If step response is very critical, poleIf step response is very critical, pole--zero calibration zero calibration �� If step response is very critical, poleIf step response is very critical, pole--zero calibration zero calibration should take should take place. If the amplifier is used in pipeline place. If the amplifier is used in pipeline ADC, tuning can be done via detecting the lowest ADC, tuning can be done via detecting the lowest ADC, tuning can be done via detecting the lowest ADC, tuning can be done via detecting the lowest linearity errors of the outputs during the calibration linearity errors of the outputs during the calibration linearity errors of the outputs during the calibration linearity errors of the outputs during the calibration process.process.

�� A hybrid between this FF technique and the regular A hybrid between this FF technique and the regular �� A hybrid between this FF technique and the regular A hybrid between this FF technique and the regular miller compensation can be developed to provide a miller compensation can be developed to provide a miller compensation can be developed to provide a miller compensation can be developed to provide a highest possible efficiency for an operational amplifier.highest possible efficiency for an operational amplifier.



Design Example for Capacitive Two Design Example for Capacitive Two

stage Feedforward Amplifierstage Feedforward AmplifierCascode Cascade example in

stage Feedforward Amplifierstage Feedforward AmplifierCascode Cascade example in

TSMC CMOS 0.18µm:

8.8GHz, 75dB, ~75mA, 8.8GHz, 75dB, ~75mA,

87°PM, 500fF on each end.


Openloop performance of the first stage separately.Openloop performance of the first stage separately.

Total open loop phase shift Total open loop phase shift

due to first stage Cascode

when the parasitic by-pass is when the parasitic by-pass is

not employed.



ReferencesReferencesReferencesReferences

[1] “[1] “1.2 V mixed analog/digital circuits using 0.3 µm CMOS LSI technology”1.2 V mixed analog/digital circuits using 0.3 µm CMOS LSI technology”Matsuura, T.; Yano, K.; Hiraki, M.; Sasaki, Y.; Miyamoto, M.; Ishii, T.; Nagai, R.; Nishida, T.; Matsuura, T.; Yano, K.; Hiraki, M.; Sasaki, Y.; Miyamoto, M.; Ishii, T.; Nagai, R.; Nishida, T.; Matsuura, T.; Yano, K.; Hiraki, M.; Sasaki, Y.; Miyamoto, M.; Ishii, T.; Nagai, R.; Nishida, T.; Matsuura, T.; Yano, K.; Hiraki, M.; Sasaki, Y.; Miyamoto, M.; Ishii, T.; Nagai, R.; Nishida, T.; Seki, K.; Imaizumi, E.; Anbo, T.; Sumi, N.; Rikino, K.;Seki, K.; Imaizumi, E.; Anbo, T.; Sumi, N.; Rikino, K.;SolidSolid--State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International 16International 16--18 Feb. 1994 Page(s):250 18 Feb. 1994 Page(s):250 -- 251 251 International 16International 16--18 Feb. 1994 Page(s):250 18 Feb. 1994 Page(s):250 -- 251 251

[2] “[2] “Technique to eliminate slowTechnique to eliminate slow--settling components that appear due to dipoles”settling components that appear due to dipoles”

Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on Volume 1,44th IEEE 2001 Midwest Symposium on Volume 1, 1414--17 Aug. 2001 Page(s):74 17 Aug. 2001 Page(s):74 -- 77 vol.1 77 vol.1 44th IEEE 2001 Midwest Symposium on Volume 1,44th IEEE 2001 Midwest Symposium on Volume 1, 1414--17 Aug. 2001 Page(s):74 17 Aug. 2001 Page(s):74 -- 77 vol.1 77 vol.1

[3] “[3] “Relationship between amplifier settling time and poleRelationship between amplifier settling time and pole--zero placements for secondzero placements for second--order order systems”systems”Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2000. Proceedings of the 43rd IEEE Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2000. Proceedings of the 43rd IEEE systems”systems”Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2000. Proceedings of the 43rd IEEE Schlarmann, M.E.; Geiger, R.L.; Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on Volume 1,Midwest Symposium on Volume 1, 88--11 Aug. 2000 Page(s):54 11 Aug. 2000 Page(s):54 -- 59 vol.1 59 vol.1

[4] “[4] “A new multipath amplifier design technique for enhancing gain without sacrificing A new multipath amplifier design technique for enhancing gain without sacrificing bandwidth”bandwidth”

[4] “[4] “A new multipath amplifier design technique for enhancing gain without sacrificing A new multipath amplifier design technique for enhancing gain without sacrificing bandwidth”bandwidth”Schlarmann, M.E.; Lee, E.K.F.; Geiger, R.L.; Circuits and Systems, 1999. ISCAS '99. Proceedings Schlarmann, M.E.; Lee, E.K.F.; Geiger, R.L.; Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume 2,of the 1999 IEEE International Symposium on Volume 2, 30 May30 May--2 June 1999 Page(s):610 2 June 1999 Page(s):610 -- 615 615 vol.2 vol.2 vol.2 vol.2

[5] “[5] “A robust feedforward compensation scheme for multistage operational transconductance A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors” amplifiers with no Miller capacitors” Thandri, B.K.; SilvaThandri, B.K.; Silva--Martinez, J.; SolidMartinez, J.; Solid--State Circuits, State Circuits, IEEE Journal of Volume 38,IEEE Journal of Volume 38, Issue 2,Issue 2, Feb. 2003 Page(s):237 Feb. 2003 Page(s):237 –– 243243IEEE Journal of Volume 38,IEEE Journal of Volume 38, Issue 2,Issue 2, Feb. 2003 Page(s):237 Feb. 2003 Page(s):237 –– 243243


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