FEP ITWG ITRS Summer Public Conference 2012, SF 1

Front End ProcessesITRS 2012 Summer Public Conference

12 July 20122012 Summer Meeting FEP ITWG ContributorsJ. BarnettM. WaldenC. HobbsM. GoldsteinM. AlessandriR. JammyM. WatanabeP. MajhiY. Le TiecC. GottschalkTom LiiW. Y. LohDarryl Peters

FEP ITWG ITRS Summer Public Conference 2012, SF 2

2012 ITRS FEP Sub-TWG Leadership

• HP MPU ASIC (Table FEP 2)– Wei-Yip Loh (US)

• LOP (FEP 3)– Wei-Yip Loh (US)

• LSTP (FEP 4)– Wei-Yip Loh (US)

• DRAM (FEP 5)– Ho Jin Cho (KR)

• Floating Gate Flash (FEP 6)– Mauro Alessandri (EU)

• Charge Trapping Flash (FEP 7)– Mauro Alessandri (EU)

• PCM (FEP 8)– Mauro Alessandri (EU)

• FeRAM (FEP 9)– Yukinobu Hikosaka (JP)

• Starting Materials (FEP 10)– Mike Walden (US)

– Mike Goldstein (US)

• Surface Preparation (FEP 11)– Joel Barnett (US)

• Therm/Thin Films/Doping (FEP 12)– Wei-Yip Loh (US)

• Etch (FEP 13)– Tom Lii (US)

• CMP (FEP 14)– Darryl Peters (US)

FEP ITWG ITRS Summer Public Conference 2012, SF 3

Next Generation Metal Gate/High k stacks

New High Mobility Channel Materials

New Memory Materials Phase Change Memory

FDSOI+ III/V and Ge

High µAlternative

Channel Mat’ls

3D Devices - Formation, Doping, Stress

New Structures and Materials for Transistors and Memory

Advanced Memory

FEP ITWG ITRS Summer Public Conference 2012, SF 4

New Materials impact CD Metrology

wavelength

Next Generation High k stacks

Resolving New Materials and Processes• What is the correlation between electrical properties & materials structure? • How can interfaces be engineered?

Hill

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X. Zhao and D. Vanderbilt, Phys. Rev. B., 233106 (2002)

Theoretically determined k values

monoclinic cubic tetragonal

k (HfO2)* 16 29 70

k (ZrO2)† 20 37 47

high-k higher-k

FEP ITWG ITRS Summer Public Conference 2012, SF 5

FEP Difficult ChallengesNear Term

• Strain Engineering - continued effective use for increasing device performance - application to FDSOI and Multi-gate technologies

• Achieving DRAM cell capacitance with dimensional scaling - finding robust dielectric with dielectric constant of ~60 - finding electrode material with high work function

• Achieving clean surfaces free of killer defects - with no pattern damage - with very low material loss (<0.1 A)

• High-k/Metal Gate - introduction to full scale manufacturing for HP, LOP, and LSTP

• Application to advanced structures and materials - scaling equivalent oxide thickness (EOT) below 0.8nm while

maintaining electrical performance• 450mm wafers - production level quantity

FEP ITWG ITRS Summer Public Conference 2012, SF 6

FEP Difficult ChallengesLong Term

• Continued scaling of HP multigate device in all aspects: EOT, junctions, mobility enhancement, new channel materials, parasitic series resistance, contact silicidation.

• Lowering required DRAM capacitance by 4F2 cell scheme or like, while continuing to address materials challenges

• Continued achievement of clean surfaces while eliminating material loss and surface damage and sub-critical dimension particle defects

• Continued EOT scaling below 0.7 nm with appropriate metal gates

• Continued charge retention with dimensional scaling and introduction of new non-charged based NVM technologies

FEP ITWG ITRS Summer Public Conference 2012, SF 7

2012 Logic Update

• Provide to Metrology new requirements– USJ, 3D and new channel materials– Establish criteria for deciding how new technology's

will be incorporated as tables

• Continue to interact with PIDS– Vdd and FDSOI pull-in– n-III-V and p-Ge table entries

FEP ITWG ITRS Summer Public Conference 2012, SF 8

• Continue to monitor industry activities related to 450mm development and assess impact on the Starting Materials table entries

• Treated edge roll-off in chapter text for 2011; continue to assess adding metrics (model development dependent) in future updates

• Address wafer flatness colorization issues

• Continue to review progress relative to FinFET (SOI-based) adoption and revisit SOI starting layer thickness table entries, as appropriate

2012 Starting Materials Update

FEP ITWG ITRS Summer Public Conference 2012, SF 9

2012/2013 Surface Prep Update

• Critical particle size driver. ½ DRAM ½ Pitch is current driver but flash is smaller

• Modifying specification for AFM measurement of roughness to reflect decreased critical area size

• Address the difficult aspects of measuring low-k value due to damage/failure

• Address ESH aspects of III-V cleans (generation of phosphine, arsine gases)

• Include anti-stiction drying for pattern collapse in Potential Solutions table (typically a MEMS issue)

FEP ITWG ITRS Summer Public Conference 2012, SF 10

2012 Etch Update• Gate CD variation updates

– With grid design rule widely used at gate layer, through pitch Lgate variation item is removed from total gate CD variation calculation

– Replacement gate high-K last dummy gate stack removal induced Lgate variation was added into total gate CD variation calculation

– Advanced gate etch chamber clean helped to improve wafer to wafer and lot to lot Lgate variations

– Gate LWR performance is marginal from 2012 Year of Production 2012 2013 2014 2015 2016 2017 2018

MPU Printed Gate Length (nm) 31 28 25 22 19.8 17.7 15.7

MPU Physical Gate Length (nm) 22 20 18 17 15.3 14.0 12.8

Trench width at top (nm) [A] 38.4 32.4 28.8 25.2 22.6 20.2 18.0

Trench sidewall angle (degrees) [B} >88.2 >88.2 >88.5 >88.7 >88.8 >88.9 >89.0

Gate etch bias (nm) [C] 9.4 7.9 6.6 5.4 4.5 3.7 2.9

Lgate 3s variation (nm) [D] 2.65 2.42 2.21 2.02 1.84 1.68 1.53

Lgate line width roughness 3s (nm) [E] 2.1 1.91 1.74 1.6 1.45 1.33 1.21

Across chip Lgate variation 3s (nm) [F] 0.91 0.84 0.77 0.7 0.64 0.58 0.53

Across wafer Lgate variation 3s (nm) [G] 0.91 0.84 0.77 0.7 0.64 0.58 0.53

Wafer to wafer within lot Lgate 3s (nm) 0.55 0.5 0.46 0.41 0.38 0.35 0.32

Lot to lot Lgate 3s (nm) 0.55 0.5 0.46 0.41 0.38 0.35 0.32Dummy Gate Stack Removal Induced Lgate Variation 3s (nm) [H] 0.59 0.55 0.50 0.45 0.42 0.37 0.35Minimum measurable gate dielectric remaining (post gate etch clean) [I] >0 >0 >0 >0 >0 >0 >0

Profile control (side wall angle) [J] 90 90 90 90 90 90 90

LWR becomes largest portion of gate CD variation. High power plasma UV resist treatment is a potential LWR improvement method

FEP ITWG ITRS Summer Public Conference 2012, SF 11

2012 CMP Update

• Address Replacement Metal Gate (RMG)– Obtained metrics from end users for RMG (Poly-

open Process and metal polish) – Revise RMG table. – Add text for RMG post-CMP cleans – Revise challenges.

FEP ITWG ITRS Summer Public Conference 2012, SF 12

• For Logic: – Provide to Metrology new requirements for USJ, 3D and new channel materials– Continue to interact with PIDS on Vdd and FDSOI pull-in, discuss table entries

for n-III-V and p-Ge – Work with PIDS to Monitor and Update MPU and Leading Edge Logic

technology trends, and establish criteria for deciding how new technology's will be incorporated as tables

• For Etch:– Lgate variation addressed – LWR becomes largest portion of gate CD variation

• For Starting Materials:– Continuing to monitor industry activities related to 450mm development and

assess impact on the Starting Materials table entries– Address SOI-based FinFET adoption and revisit SOI starting layer thickness

table entries• For Surface Prep:

– Revisit critical metals , ½ DRAM ½ Pitch critical particle size, AFM measurement of roughness, pattern collapse potential solutions

– Highlight ESH aspects of III-V cleans (generation of phosphine, arsine gases)

FEP 2012 Summer 1-page Update

FEP ITWG ITRS Summer Public Conference 2012, SF 13

The FEP Story

• High-κ metal gate in high-volume manufacturing What’s next?

• FinFET introduced sooner than expected• FDSOI making significant progress – expect

introduction in 2013• III-V high-mobility channels in research –

2018 introduction

• New structures/materials = New Challenges