i:\litho\013\roadmap info\itrs 07-11 1 lithography itwg report for itrs 2000 conference december 6,...

$: I:\litho\013\Roadmap info\ITRS 07-11 1 Lithography ITWG Report for ITRS 2000 Conference December 6, 2000 Hsinchu, Taiwan$
i:\litho\013\Roadmap info\ITRS 07-11 1

Lithography ITWG Reportfor

ITRS 2000 Conference

December 6, 2000Hsinchu, Taiwan


Lithography ITWG Report

OUTLINE

• Major Changes from 1999

• Key Concerns

• Lithography Requirements

• Potential Solutions

• Key Challenges

• Summary


Major Lithography Changes from 1999 ITRS• Technology Node Timing accelerated 1-2 years

– 130nm in 2001– 100nm in 2003 90nm in 2004

• MPU half-pitch accelerated one additional year.... now lags DRAM half-pitch by only one year

• MPU gate length (in resist) set at 70% of DRAM half-pitch …. more aggressive than ORTC

• MPU physical gate length (post-etch) leads MPU gate length (in resist) by one year

• New DRAM chip sizes allow smaller minimum field size and 5X option for advanced optical tools

• MEF drives much tighter optical mask requirements• Changes supported by 3 of 5 regions


ITRS Roadmap Acceleration (2000)95 97 99

1994

1997

1998 & 1999

Min

imu

m F

eatu

re S

ize

(nm

)

500

350

250

180

130

100

70

50

35

2595 97 99 02 05 08 11 14

02 05 08 11 14

Proposed 2000 ITRS Update - 7/21/00

Work-in-Progress - Not for Publication

Half Pitch(IRC Proposals 7/11/00)

(post-etch)(IRC Proposals 7/11/00)

MPU Gate Length(printed in resist)


Key Concerns for 2000 ITRS Update

1) Review of technology node timing

2) SOC definition

3) ROI study (model)

4) SOC and MPU chip sizes

5) Technical issues- Scanner reduction ratio

- Mask (MEF)

- Defect

6) New devices - requirements, etc.


2000 ITRS Technology Node Timing• Roadmap timing continues to be one of the major concerns

for Lithography ITWG• Discussed extensively by all 5 regions at April and July

ITWG meetings. Industry surveys conducted in Japan and USA.

• Consensus was not reached at July ITRS workshop• Three proposals made since July meeting:

#1 – IRC ORTC Revision 1 ke, 7/28/00

#2 – USA Lithography TWG, 9/1/00

#3 – Japan Lithography TWG, 9/28/00

• Two regions voted for proposal #2, one for proposal #3, and two abstained

• Lithography Requirements are based on proposal #2


2000 ITRS Chip & Field Size

• High performance (HP) MPU drove minimum field size in 1999 Roadmap (>800mm2 at 50nm node)

• Chip Size Study Group (CSSG) reviewed models and current chips in this market segment

– Recommended changing model to cut on-chip cache in half (1M in 1999 and doubling every 2 years)

HP MPU chip size at 35nm node is now ~ 600mm2

– MPU designs can be very flexible, will be driven by economics, and should not be used to drive scanner field sizes

• CSSG also recommended that scanner field sizes should be driven by DRAM . . . 2 production chips/field


2000 ITRS Chip & Field Size

• FEP ITWG studied issues with DRAM model, ‘a’ factor is too aggressive

– Analyzed tradeoffs of chip size growth rates, density increase rates, ‘a’ factor, and scanner field sizes (800mm2 @ 4X, and 572mm2 @ 5X on 6-inch glass)

– Final results show that 2 production chips can be contained in 572mm2 field size

• IRC agreed with FEP ITWG and CSSG recommendations and included in ORTC

• Lithography TWG recommends staying at 6-inch glass for now and studying productivity benefits of 7-inch glass in the future


Scanner Reduction Ratio (SRR)

• ITWG recommends following issues be addressed at May 8, 2000 SRR Workshop organized by ISMT

1) What is the timing? Node, year, wavelength?

2) Comprehensive cost analysis

- Impact of throughput reduction

- Impact on mask industry; what real benefit do they get?

- Does it help accelerate the Roadmap?

3) Complications of 4X, 5X/6X on leading edge mask making?

4) Do all scanner suppliers have to agree? What if they don’t?

5) Impact on NGL? Must they follow? Especially EPL?


Scanner Reduction Ratio (SRR) WorkshopMay 8, 2000

• The 62 attendees represented a broad cross-section of the industry

• Voting restricted to one response per company represented– One exception is allowed; “captive mask manufacturers” are

asked to vote separately from their respective wafer lines

Chip Manufacturers

Mask Manufacturers


Mask Availability by Magnification

• Participants believed that the 70nm node mask availability could be improved by 2+ years if magnification increased above 4X


Optical Reticle Size Choice - 157nm

• Stay at 6”– Minimal support for

larger reticles– More support for 7”

than 9”

• Introduce 157nm with 5X

• Secondary choice mixed– 6X has more votes

than 4X

100nm Node - 157nm

0

5

10

15

20

25

30

4X 6" 5X 6" 6X 6" 5X 7" 6X 7" 5X 9" 6X 9" No 2ndChoice

70nm Node - 157nm

0

5

10

15

20

25

30

4X 6" 5X 6" 6X 6" 5X 7" 6X 7" 5X 9" 6X 9" No 2ndChoice


Recommendations of Tool Suppliers(157nm Technology, Updated 11/9/00)

Primary Secondary

• ASML 5X 6” ---

• Canon 5X 6” ---

• Nikon 4X 6” (5X 6”) *

• SVGL 4X 6” ---

* However: If reticle accuracy can not be satisfied in the future, Nikon

accepts changing to 5X for 157nm under the conditions of….

Accepting lower throughput.

Firmly standardizing optical reduction ratio.

Accepting difficulties in mix & match between 4X & 5X.


Does NGL need to follow the magnification ratio of the optical tools?


SRR Workshop (5/8/00) Summary

• The majority choice for 157nm & 70nm node:

– Mask magnification 5X

– Slit height 22mm

– Substrate 6-inch

• Recommend adding 5X as an option at 100nm & 70nm nodes for optical tools


• Mask Error Factor (MEF) is the relation between changes in the pattern found on the mask and the corresponding pattern on the wafer:

where M is the scanner reduction ratio

• Ideally MEF = 1.0. In practice, process variables can significantly increase the MEF as the image fidelity of the scanner deteriorates.

• Proposals organized through ISMT Optical Extensions & MASC groups in June meetings

Mask Error Factor (MEF) and Specifications

CD wafer

(CD reticle) / MMEF =


Mask Error Factor (MEF) and Specifications

• ISMT contracted with IMEC to study MEF (modeling vs. experimental)

• Results show MEF increases very rapidly at duty ratio below 1:1.5; alternating PSM technology does NOT solve this issue

• Mask specifications for dense lines must be much tighter (The 1999 relaxation was shown to be unwarranted)

• Recommend same CD uniformity specification for alternating PSM as for binary mask; requires more study in 2001

MEF as a Function of Pitch for 100 nm LinesSensitivity to Focus

Alternating Phase-Shift Mask, =193 nm, NA=0.55, =0.3

Duty Ratio

0 1 2 3 4 5 6 7 8 9 10

ME

F

0

1

2

3

4

No Bias: Best Focus No Bias: +/- 0.2 mm Out of Focus Optimum Bias: Best FocusOptimum Bias: +/- 0.2 m Out of Focus

CMG, 3-Feb-2000

Target MEF Spec=0.8

MEF As A Function of Pitch for 100nm Lines

18


Lithography Requirements• Exposure Tools - Table 39

– Continuous improvements in 248nm tools and processes have demonstrated solutions for DRAM and MPU down to 150nm half pitch, including CD control of 10nm

– MFS for development has been demonstrated down to 70nm with 193nm + PSM– CD control solutions are being pursued down to 6nm by engineering analysis of

error sources (mask, process, tool)

• Resists - Table 40– Resist thickness solutions now exist down to 0.33 - 0.44 um– PEB solutions exist at 3nm / ºC with 248nm resists– Resist sensitivity solutions exist for all resists except 157nm; solutions are being

pursued at MIT/LL and suppliers for 157nm at 5-10 mJ/cm2

• Masks - Table 41– Based on development of 50KeV e-beam writers, solutions now exist for mask

minimum image size and OPC feature size to 200nm, image placement to 27nm, CD uniformity to 15nm, and linearity to 20nm

– CD uniformity for dense lines with alternating PSM must be much tighter due to better understanding of MEF


First Year of IC Production 1999 2001 2004 2007 2010 2013

Dense Lines (nm) (DRAM half pitch)

180 130 90 65 45 33

Isolated Lines (nm) (gate length, printed in resist)

140 90 60 45 32 23

Isolated Lines (nm) (gate length, post-etch)

120 80 55 40 28 20

Gate CD Control (nm) (3 sigma post-etch)

12 8 6 4 3 2

Overlay (nm) (mean + 3 sigma)

65 45 31 26 18 13

Minimum Field Area (mm2) (2 production DRAM chips/field)

262 254 304 366 512 478

Mask Blank Size (mm) (square) 152 152 152 152 152 152 (diameter) 200 200 200 Mask CD Uniformity (nm) (3 sigma, isolated lines, 4X)

16 10 7 7 5 4

Mask Image Placement (nm) (3 sigma, multi-point, 4X)

39 27 19 15 11 8

Lithography Requirements - Overview

Solution Exists Solution Being Pursued No Known Solution

Proposed 2000 ITRS Update - 10/14/00

Work-in-Progress - Not for Publication

Lithography Exposure Tool Potential Solutions

21Proposed 2000 ITRS Update - 10/14/00 - Work-in-Progress - Not for Publication

Research Required Development Underway Qualification/Pre-Production

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the technology solution.

First Year of IC Production 2001 20041999 2010 2013 2007

248nm

248nm + PSM193nm

193nm + PSM157nmEPLXRLIPL

NarrowOptions

157nm + PSMEPLEUVIPLXRLEBDW

NarrowOptions

EUVEPLIPLEBDW

Note: Production level exposure tools should be available one year before first IC shipment.

Te

chn

olo

gy

Op

tion

s a

t T

ech

no

log

y N

od

es

(DR

AM

Ha

lf P

itch

, n

m)

180

130

90

65

45

33

DRAM Half Pitch(Dense Lines)

NarrowOptions

NarrowOptions

EUVEPLIPLEBDWINNOVATIVE TECHNOLOGY


Key Challenges for Lithography in ITRS 2000 Update

• Impact of the technology node acceleration on lithography exposure technology and mask making capability.

• Gate CD control and overlay improvements.

• Ever tightening mask requirements, especially CD uniformity and image placement.

• Return on investment (ROI) for lithography suppliers, especially for single node solutions below 90nm.


0

100

200

300

400

500

600

700

800

900

1000

'92 '94 '96 '98 '00 '02 '04 '06 '08

Lithography R&D Funding

$M

EUV (70nm/2007)

EPL (70nm/2006)

157 (100nm/2004)193 (130nm/2001)

248

Optics Applications

Advanced Lithography R&D

USA ONLY (1 regional solution, 2-year cycle, 2 NGL solutions)


Cost of Ownership• Consider two comparison cases

– 157nm and EPL (Scalpel) at the 70nm node– EUV and EPL (Scalpel) at the 50nm node– Compare both at mask usage's of 500 and 5000 wpm– ISMT Dec.’99 - Rev. 4 assumptions (e.g. 25 x 25, 3rd yr,

etc.)

• Analyze Cost of Ownership as a function of tool and mask cost “Mark-Up’s”

NODE Technology Exp. Tool

Throughput (wph)

Tool Base Cost*

Blank Cum. Yield

Mask Cum. Yield

Mask Base Cost*

70nm 157nm 39 $ 9.2 M 70.0% 72.3 % $ 16,500(1)

70nm EPL 22 $ 5.1 M 76.0% 69.2 % $ 11,600(2)

50nm EPL 17 $ 5.8 M 76.0% 69.2 % $ 13,200(2)

50nm EUV 56 $ 11.5 M 29.0% 68.2 % $ 25,000(3)

*Tool and mask “Base Cost” values are from ISMT Dec. ’99 CoO analysis Without margin markups (1) 157nm mask cost is for 90/270 alternating PSM (2) EPL use ISMT Dec. ’99 “Pellicle-less Tax” adjustment; added $2,200/mask + shared mask inspection equipment. (3) EUV use ISMT Dec. ’99 “Pellicle-less Tax” adjustment; added $1,600/mask + shared mask inspection equipment


Cost of Ownership @ 70nm Node

0

50

100

150

200

250

300

350

0 1 2 3 4 5 6

Cost Markup "X" (markup factor to both exposure tool and mask)

Co

st

of

Ow

ne

rsh

ip (

$/G

WL

E)

157nm - 5000 wpm

157nm - 500 wpm

EPL - 500 wpm

EPL - 5000 wpm


Cost of Ownership @ 50nm Node

0

50

100

150

200

250

300

350

0 1 2 3 4 5 6

Cost Markup "X" (markup factor to both exposure tool and mask)

Co

st o

f O

wn

ersh

ip (

$/G

WL

E)

EPL - 500 wpm

EPL - 5000 wpm

EUV - 500 wpm

EUV - 5000 wpm


Cost Conclusions

• Total R&D spending for one regional solution could approach one billion dollars in 2002 alone

– Almost 2X previous spending rates

– Finding both the funds and the necessary talented people may be biggest challenge of all

• Roadmap acceleration exacerbates business situation . . . fewer tools, more improvements over shorter time

• To make sufficient ROI suppliers may have to increase mark-up

• Increased tool and mask costs will drive up CoO at all mask usage levels


Lithography ITWG Report – 2000 Update Summary

• Technology Node Timing accelerated 1-2 years– 130nm in 2001 90nm in 2004

– Not a consensus decision

Puts major strain on entire lithography infrastructure

• New DRAM and MPU chip sizes allow smaller minimum field size and 5X option for advanced optical tools with 6-inch reticles

• Optical mask requirements for dense lines must be much tighter, based on latest MEF data

• Cost control and ROI continue to be major concerns for acceleration at 90nm – 45nm nodes


Acknowledgements

We would like to express our most sincere gratitude and appreciation for the outstanding support and cooperation from the ITWG participants.

Europe Paolo CanestrariJan-Willem Gemmink

Japan Hiroshi OhtsukaMasaru Sasago

Korea Ki Ho BaikJoo-Tae Moon

Taiwan Y.C. KuAnthony Yen

USA George GombaGil Shelden

Lithography ITWG Report

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