final project design simple cpu
DESCRIPTION
Final project design Simple CPU. The basic flow for CPU. Register. 做資料的存取. 32. 32. Instr. Memory. PC. operation. i_addr. i_data. 做資料的存取. Data Memory. The Memory modules. clk. 32. 32. Instr. Memory. Always i_dataTRANSCRIPT
Final project designSimple CPU
NCKU EE CAD
ASIC Lab 2Jou, Jer Min, NCKU
Instr.Memory i_datai_addr
3232
PC operation
DataMemory
Register
The basic flow for CPU
做資料的存取
做資料的存取
NCKU EE CAD
ASIC Lab 3Jou, Jer Min, NCKU
Instr.Memory
i_datai_addr
clk
DataMemory
d_dataoutd_datain
d_addr
clk
d_rw
3232
32
3232
When d_rw = 0 : read : d_dataout <= Mem[d_addr]
When d_rw = 1 : write : Mem[d_addr]<=d_datain
Always i_data <= Mem[i_addr]
The Memory modules
NCKU EE CAD
ASIC Lab 4Jou, Jer Min, NCKU
The hierarchy of our design
i_addr i_data
Instruction Memory
d_rw d_addr
Data Memory
d_datain d_dataout
pc inst dmem_rw
d_addr
d_datain d_dataout
FINAL
32 32 32 32 321
Design this block
NCKU EE CAD
ASIC Lab 5Jou, Jer Min, NCKU
MIPS 指令格式
NCKU EE CAD
ASIC Lab 6Jou, Jer Min, NCKU
Instruction Set Architecture (1/3)
NCKU EE CAD
ASIC Lab 7Jou, Jer Min, NCKU
Instruction Set Architecture (2/3)
NCKU EE CAD
ASIC Lab 8Jou, Jer Min, NCKU
Instruction Set Architecture (3/3)
類別 指令 例子 意義 說明J J J 25 go to 25 無條件跳躍:跳到目的位址J JAL JAL 25 go to 25
$ra = PC+1
無條件跳躍:用在程序呼叫,儲存返回位址
PC 0
1
2
3
::
::
addrInstr.
Memory
32 bits
Instr. 0
Instr. 1
Instr. 2
Instr. 3PC = PC + 1
$ra = return address
這裡我們令 $R31 當 $ra來使用
NCKU EE CAD
ASIC Lab 9Jou, Jer Min, NCKU
MIPS 運算碼
格式 指令 Opcode Function codeR SLL 6’b000000 6’b000000R SRL 6’b000000 6’b000010R SRA 6’b000000 6’b000011R JR 6’b000000 6’b001000R ADD 6’b000000 6’b100000R SUB 6’b000000 6’b100010R AND 6’b000000 6’b100100R OR 6’b000000 6’b100101R XOR 6’b000000 6’b100110R SLT 6’b000000 6’b101010
格式 指令 OpcodeI BEQ 6’b000100I BNE 6’b000101I ADDI 6’b001000I SUBI 6’b001001I SLTI 6’b001010I ANDI 6’b001100I ORI 6’b001101I LW 6’b100011I SW 6’b101011J J 6’b000010J JAL 6’b000011
NCKU EE CAD
ASIC Lab 10Jou, Jer Min, NCKU
繳交資料繳交日期: 6/30 p.m. 12:00 以前繳交資料:
一份書面報告 (word 檔 ) 簡易說明程式內容及執行結果。 組員工作分配。
程式檔案 Verilog 檔
檔名請命名成” groupXX.v”, XX 是組別號碼。 Top module 請命名成 FINAL 。
繳交方式:與繳交 lab 作業方式相同,上傳至 ftp
其他:若有 CPU 規格或上傳作業之問題,可寄信或到實驗室找助教
NCKU EE CAD
ASIC Lab 11Jou, Jer Min, NCKU
1 addi $r1,$r0,32---r1=r0+32 2 subi $r2,$r1,5----r2=r1-5 3 slti $r3,$r0,32---()r3=1 4 lw $r4,1($r0)-----r4=DMEM[1+0] 5 sw $r1,0($r0)-----DMEM[0+0]=r1 6 add $r5,$r1,$r2---r5=r1+r2 7 slt $r6,$r0,$r1---r6=1 8 sll $r7,$r1,1-----r7=r1<<1 9 j 13--------------pc=52 10 beq $r7,$r7,1-----pc=48 11 jr $r31-----------pc=60 12 bne $r1,$r0,-2----pc=44 13 addi $r8,$r0,8----r8=r0+8 14 jal 10-----------pc=40,r31=15*4 15 srl $r9,$r1,2-----r9=r1>>2 16 sra $r10,$r1,2----r10=r1>>2 17 sub $r11,$r1,$r2--r11=r1-r2 18 and $r12,$r2,$r4--r12=r2&r4 19 or $r13,$r2,$r4---r13=r2 | r4 20 xor $r14,$r2,$r4--r14=r2 ^ r4 21 andi $r15,$r2,22--r15=r2 & 22 22 ori $r16,$r2,22---r16=r2 | 22
Addr. data Addr. data
0 0 16 0
1 0 17 0
2 0 18 0
3 0 19 0
4 0 20 0
5 0 21 0
6 0 22 0
7 0 23 0
8 0 24 0
9 0 25 0
10 0 26 0
11 0 27 0
12 0 28 0
13 0 29 0
14 0 30 0
15 0 31 0
32
27
1
DATA MEMORY ADDR data
0 5
1 6
6
32
57
1
64
8
60
8
8
5
3
63
60
18
31
NCKU EE CAD
ASIC Lab 12Jou, Jer Min, NCKU
001000_00000_00001_00000_00000_100000 //addi $r1,$r0,32---r1=32
001001_00001_00010_00000_00000_000101 //subi $r2,$r1,5----r2=27
001010_00000_00011_00000_00000_100001 //slti $r3,$r0,32---r3=1
100011_00000_00100_00000_00000_000001 //lw $r4,1($r0)-----r4=DMEM[1]
101011_00000_00001_00000_00000_000000 //sw $r1,0($r0)-----DMEM[0]=r1
000000_00001_00010_00101_00000_100000 //add $r5,$r1,$r2---r5=r1+r2
NCKU EE CAD
ASIC Lab 13Jou, Jer Min, NCKU
000000_00000_00001_00110_00000_101010 //slt $r6,$r0,$r1---r6=1
000000_00001_00000_00111_00001_000000 //sll $r7,$r1,1-----r7=64
000010_00000_00000_00000_00000_001101 //j 13--------------pc=52
000100_01001_01001_00000_00000_000001 //beq $r7,$r7,1-----pc=48
000000_00000_00000_00000_00000_001000 //jr $r31-----------pc=60
000101_00000_00001_11111_11111_111110 //bne $r1,$r0,-2----pc=44
NCKU EE CAD
ASIC Lab 14Jou, Jer Min, NCKU
001000_00000_01000_00000_00000_001000 //addi $r8,$r0,8----r8=8
000011_00000_00000_00000_00000_001010 //jal 10------------pc=40,r31=60
000000_00001_00000_01001_00010_000010 //srl $r9,$r1,2-----r9=8
000000_00001_00000_01010_00010_000011 //sra $r10,$r1,2----r10=8
000000_00001_00010_01011_00010_100010 //sub $r11,$r1,$r2--r11=5
000000_00010_00100_01100_00000_100100 //and $r12,$r2,$r4--r12=3
NCKU EE CAD
ASIC Lab 15Jou, Jer Min, NCKU
000000_00010_00100_01101_00000_100101 //or $r13,$r2,$r4---r13=63
000000_00010_00100_01110_00000_100110 //xor $r14,$r2,$r4--r14=60
001100_00010_01111_00000_00000_010110 //andi $r15,$r2,22--r15=18
001101_00010_10000_00000_00000_010110 //ori $r16,$r2,22---r16=31