Author : Masanori Bando and H. Jonathan ChaoAuthor : Masanori Bando and H. Jonathan Chao

Publisher : INFOCOM, 2010Publisher : INFOCOM, 2010

Presenter : Jo-Ning YuPresenter : Jo-Ning Yu

Date : 2011/02/16Date : 2011/02/16

Introduction

FlashTrie Prefix-Compressed Trie HashTune Membership Query Module

Lookup operation

Architecture

Update

Performance evaluation

2

Outline

Tree Bitmap have been used in today’s high-end routers.

However, their large data structure often requires multiple external memory accesses for each route lookup.

In this paper, we propose a new IP route lookup architecture called FlashTrie that overcomes the shortcomings of the multibit-trie based approach.

We also develop a new data structure called Prefix-Compressed Trie that reduces the size of a bitmap by more than 80%.

We use a hash-based membership query to limit off-chip memory accesses per lookup to one and to balance memory utilization among the memory modules.

3

Introduction

overview

4

FlashTrie Architecture

Construction of the PC-Trie has two rules:1. All sibling nodes must be filled with NHI if at least one

node in the node set contains NHI.2. The parents node set can be deleted if two child node

sets exist.

5Prefix-Compressed Trie

(PC-Trie)

The main difference between Tree Bitmap and our data structure is that a bit in the Tree Bitmap represents only one node, while a bit represents more than one node in PC-Trie.

6Prefix-Compressed Trie

(PC-Trie)

Advantage Tree Bitmap, the internal bitmap : 2stride+1−1 bits. PC-Trie n, 2(s+1−log(n))−1 bits, s is the stride size (in bits).

For example, a PC-Trie 8 and 8-bit stride (n = 8, s = 8) : Tree Bitmap = 28+1−1 = 29−1 = 511 bits PC-Trie = 2(8+1−log(8))−1 = 2(9−3)−1 = 26−1 = 63 bits

Drawback NHI may need to be duplicated as the figure shows. However, the number of memory slots needed for the

NHI table is reduced. Because the size of a NHI is so small that multiple NHI

can be stored into a single memory slot.

7Prefix-Compressed Trie

(PC-Trie)

The hash table has two different entries:1. no-collision : Least-Significant Bit of the hash table entry is set to

“0”.2. collision : Least-Significant Bit of the hash table entry is set to

“1”. The collided items are stored in Black Sheep (BS)

memory.

8

Membership Query Module

1. no-collision : If the Verify Bits are matched with the input IP address,

then the Verify Bits plus the hash result becomes the PC-Trie address for the input IP address.

2. collision : We have multiple on-chip BS memory modules that are

accessed in parallel to void access one BS memory multiple times.

Based on simulation results, in the worst case IPv4 : five BS memory modules are needed. IPv6 : seven BS memory modules are needed.

9

Membership Query Module

10

Membership Query Module

We use HashTune as the hash function because it

has a compact data structure and better memory utilization.

Advantages:1. Key distribution is more uniform over the entire

hash table.2. The size of Verify Bits can be reduced.

11

HashTune

The entire hash table is segmented into multiple small hash tables called groups and all groups have the same number of bins.

Each group is allowed to select a different hash function from the pool of hash functions.

The selected hash function ID is stored in a Hash ID Table, which is also stored in on-chip memory and used for query operations.

12

HashTune

Each group is assigned an ID called Group ID and the ID is selected from LSBs of root nodes in each sub-trie.

For example : Resolving 17 bits input and choosing 8 LSBs as the group

ID gives us the remaining 9 bits to be stored as Verify Bits. As a result, the Verify Bit size and on-chip memory

requirements are reduced.

13

HashTune

IPv4 Prefix Distribution from 2002 to 2009. Sources from the RouteViews project , Oregon, USA.

14

Prefix Distribution

We select three levels based on the prefix distribution of figure.

They are IPv4/16 (16 Most-Significant Bits of an IPv4 address), IPv4/17 (MSB 17 bits to 24 bits), and IPv4/25 (MSB 25 bits to 32 bits).

IPv6 Prefix Distribution. Sources from the RouteViews project , Oregon, USA and

expected future IPv6 routing tables.

15

Prefix Distribution

The number of routes increases every 8 bits, and we can observe major prefix lengths in that 8-bit region (e.g., /32, /40, and /48).

Thus, we also select stride size 8 for IPv6.

The input 32-bit IPv4 address is categorized in

IPv4/16, IPv4/17, and IPv4/25. IPv4/16 is resolved using Direct Lookup (on-chip),

and IPv4/17 and IPv4/25 are resolved using the Membership Query (on-chip) and PC-Trie (off-chip).

16

Lookup Operation

FlashTrie Architecture for IPv4

17

Architecture

Suppose “100,” is the input to this PC-Trie

The contents of the bitmap is “1,” which means NHI exists for the input “100”.

Since the LSB of the input is “0”, E is selected as the final NHI.

For PC-Trien, more than one (log2(n)) bit from the LSB of the input destination IP address is used to find the final NHI.

18

Performance Evaluation

279, 117 routes 279, 117 routes

stride size = 8 bits

19

Performance Evaluation

Memory Requirements On-Chip Memory:1. Direct Lookup for up to /16.2. Hash table for membership queries.3. Hash ID table (storing a hash ID for each group).4. Black Sheep memories for collided items in the hash

table.

Memory Requirements Off-Chip Memory:1. PC-Trie

sub-trie size : (stride size = 8 bits) Tree Bitmap = 1063 bits (internal bitmap + external

bitmap + pointers) PC-Trie8 = 83 bits (PC-Trie bitmap + pointer)

20

Performance Evaluation

Memory Requirements Off-Chip Memory:2. NHI

21

Performance Evaluation

Memory Requirements It is evident from the result that the reduction in bitmap size

is more than 80% (for higher compression degree of PC-Trie).

22

Performance Evaluation

Lookup Speed and Timing Analysis

23

Performance Evaluation