Status of FTK: toward the TDR

1FTK Status future developments

b e b bm tetthbbmFTKGruppo 1, incontro con I referees, Luglio 8 2013 Paola Giannetti for the FTK collaborationOUTLINEsblocco SJ Conditons: TDR MOU - chip design

PERFORMANCES in the TDR

Italian role in FTK

Sblocco SJ: 222 keuro perordine di AMchip06 2

Conditions to be satisfied: (1) solid Italian collaboration, (2) adeguate coverage of costs, (3) design of Amchip done.Italian Group is growing fast (FTE: 11,90 in 2012, 18,1 in 2014)FTK TDR with simplified, but very interesting physics case - printed version: https://cds.cern.ch/record/1552953?ln=enIn the TDR: Solid collaboration has been defined with sharing of responsibilities and costsFor Amchip design see later in the talkThe team & cost sharing 3

Possible extra costsPossible extraJoined recently, after the 2010 reviewAMCHIP statusMiniAsic just received - ongoing tests at Milan

Design of AMchip05 (LPNHE-MI-LNF-PI-) advanced Submission during summer if IP core (SerDes) is working correctly

Design of AMchip06 expected for spring 2014

AMchip04(1) AM chip04: TMSC 65 nm with Variable Resolutioncustom cell to reduce pattern size & consumption 8k patterns in 14 mm^2.

5DOI:10.1109/ANIMMA.2011.6172856

MI-LNF-PI-LPNHE

Even IF power consumption is as expected Core Power Consumption has to be decreased because of increase due toSerialized I/O6

IF final Chip power < 2W& AUX power < 75 WThis is ~ the limit for (a) Standard PS availability (b) cooling ~ 1.2 kW on the back

COOLING TESTS IN PAVIA (A. Lanza)~ 4500 W 4.5 kW in front crate

We are confident we can cool ~ 5 kWNext Steps:Turn on the chiller to cool the airUse last-version of Wiener fans to see if improved power gives better resultsClose the Wiener fans on the sides.Turn on two old AMBoards (or 3) and see if they work correctlyLast: try the final boards and final chips in the crateTESTS reported here WITH CDF FANs9

AMchip05 design 10Changes in LOGIC (LPNHE):SERDES I/O @ 16 bits (2 DC)(AMchip04 was 15 bits 3 DC. Internally it's always 18 bits with configurable DC)Two pattern inputs one pattern output (merge of pattern streams)1-layer match threshold (other thresholds: never, 8, 7, 6, always)double width mode (4 bus - 32 bit)optional continuous readout mode(AMchip04 was event based only)Change for implementation of designMajority inside pattern becomes full custom (MILAN)New Low Power full custom cell for pattern (LNF)

New features wrt AMchip04Milan11

The Low Voltage/very Low Power Cell expectations:promisingBut very large uncertainty

AMchip Review July 8 - 2013LNF12Conclusion for the SJAMchip06 design is not ready (expected to be ready spring 2014) but it is like AMchip05, only larger, and:Complex order ~500 keuros, involves 6 funding agencies! To be prepared in advance, money must be ready months before the submission.AMchip05 in advanced status, all the relevant features are thereMiniasic tests will allow to check the status of IP cores before AMchip05 submissionWe will care about not submitting AMchip06 if the IP core will not work in the miniasic.

If the order of AMchip05 is delayed by Monday review to end of September, we can wait September for the SJ release.Tau Physics case: one example from the TDR13

Fcore>0,75ET>15 GeVStandard Level-2: calorimeters cuts to lower the rate before performing trackingFTK Selection with no calorimeter action before14

leading PT track in ROi (Ri in figure)Rsig = 0,1 & Riso=0,3 around leading track; 1 (1-prong) or 2-3 (3-prong) tracks in Rsig;Count tracks in Riso.RISORIRSIGJet axisResults15

Tau EFFICIENCYTau Pt spectrum from light HRejection of fake tauOther arguments in the FTK TDR 3.2.1 Lepton Isolation3.2.2 b-jet tagging3.2.3 Primary Vertex Finding

To be added to TDAQ TDR in September association Jet-primary vertex (fraction track energy coming from prim. VertexTrack correction to MET16Project organization-Italian responsibilities 17

The team and task sharingThe Italian role today 18

In addition to Amchip design..19Rewriting FTK_IM clustering firmware - testing new protototypes

Designing boards for Miniasic, AMchip05, AMchip06.

AMBSLP

miniLamb X miniasic

LambSLP X AMchip05, 06PISA - CERN PRIELE inside IAPP

Design Frascati + WasedaFirst tests @ Waseda FTK_IM prototype compatible with DF via FMC connector. Problem with power generator solved (changed component) Output to DF tested up to 400 MHz (design) for some lines. New requirement from DF: more lines at 400MHz being tested. A. Annovi - March 13th, 2013

High S/Nlow S/NA new Variable Resolution Associative Memory for High Energy PhysicsATL-UPGRADE-PROC-2011-004

doi:10.1109/ANIMMA.2011.61728561 layer

AMchip0421

HW limits satisfied with variable resolutionNot USA responsabilitiescost sharing 2014 -2017 22ITALIA core 2013: = 220 keuro AMchip06ITALIA core 2014: 135 (FTK_IM)+ 30 (AMBSLP) + 120 (tests parzialmente SJ)= 285 keuroITALIA core 2015: 80 (AMBSLP)+200 wafers = 280 keuroITALIS core 2016-2017: = 390 keuro AMBSLP + qualche spesa piccola non-core

ConclusionsComplex orders for Amchip object of SJ releaseThere is good progress on all of the hardware components.Nice results for the physics case. FTK collaboration is growing in particular Italy

Italian group has an important role (see backup)Share of costs is defined extra costs already appears, but new funding agencies can provide more than what in TDR tableItalian Core costs ~flat, still in evolution23

BACKUP24ITALIAN ResponsibilitiesProject Manager - M. Shochet (Chicago)Deputy Project Manager - P. Giannetti (Pisa)

Task

FTK_IM - M. Beretta (Frascati) AMBoard - M. Piendibene (Pisa) LAMB P. Giannetti (Pisa) AMBoard and LAMB firmware - D. Magalotti (Perugia) AM chip - A. Stabile (Milan), F. Crescioli (Paris)

System Integration Tests & board integration in the Vertical Slice - M. Piendibene (Pisa) DAQ integration: Vertical Slice/Demonstrator - A. Annovi (LNF) Rack integration: p. supplies, cooling, & safety - A. Lanza (Pavia) Interface to level-2 - J. Zhang (Argonne), A. Negri (Pavia), A. Annovi (LNF) FTK simulation - G. Volpi (LNF) 25TALKS to Italians 2012-1326

2 PRINs + 1 FIRB @ second selection + 2 FP7 People projects ongoingSTd Power Supply - Tot ~5320 W 5V: AUX expected need ~75 W 15 A/AUX 15 A*16 = 240 A + some spare current for VME requested 260-270 A- ~ 1350 W; Wiener proposal: 3 modules 115 A each for a total of 345 A

14 V: AMchip core; goal~128 W9.2 A/AMB9.2 A *16 = 147 A-2048W Wiener proposal: 4 modules @15 V 550 W each for a total of 2200 W @14 V 184 A 2200 W

48 V: for SerDes and fanouts: ~120 W2,5 A/AMB 2,5 A *16 = 40 A 1920 WWiener proposal: 3 modules 13.5 A each for a total of 40.5 ARACK OPTIONS

CAEN IDEA1 single PSFor 2 cratesIn the middle

CAENHow to fit 3 crates - Too long cables? PS in the middle?

Green ~cable lengthassuming Bins have Connection tools on top& PS output on top & bottomUNCERTAINTIES on made IPOTHESISWill AMCHIP core consumption be < 2 W /128 kpatterns ??

Will AUX / SSB board consumption be ~ 75 W ??

Which fan we will choose? 2 Unit fan or 1 Unit fan ??

Which power supplies we will use? Wiener 6 Units PS, one per crateCAEN 9-10 Units PS, one for 2 crates.

On 3 and 4 + eventual need of extra crates will influence the cost

Proposal: lets use what we have for 2015 as much as possible, lets buy new stuff when uncertainties above are clarified.RACK will be defined at that moment.(8) The AM system schedule30

Installation of the first 8 PUs expected at the beginning of 201531

40-60oUnit fan: air mixed before crateBut 1 unit distance between wheel and crate