fujitsu carmine eval...digital rgb input cable 2 1 1 22 d d c c b b a a 1 2 i2c 1 7 7 5 video input...
TRANSCRIPT
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_RESET#
VI0_RGB[2..0]
VI0_EXT_SYNC[1..0] VI0_EXT_SYNC[1..0]
RESET#2
VI0_RGB[2..0]
VO_CTRL[1..0]
I2C[1..0]
CONFIG[7..5]
CONFIG[7..5]
VO_CTRL[1..0]
CONFIG[4..0]
VO0_SYNC4VO0_GVVO0_GV
VO0_CLK[4..0]
VO0_SYNC_EXT[2..0]
RESET#2
CM_VI0_SYNC[3..0]
I2C[1..0]
RESET#2
VO1_SYNC[4..0]
CM_VI1_656_D[7..0]
VO1_SYNC_EXT[2..0]
VO0_RGB[23..0]
RESET#[2..0]
VO0_SYNC[4..0]
CM_VI0_RGB[17..0] VO1_CLK[4..0]
VO1_RGB[23..0]
CM_VI1_CLK
Title
Size Document Number Rev
Date: Sheet o f
30100-001 PA11
Fujitsu Carmine Evaluation Board
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A3
1 15Monday, November 21, 2005
Top Top
Revision: PA11
Top#3
Carmine Evaluation Board
#7
#2Reference ID: 100
Hierarchy Part References
Carmine Evaluation Board
+---#1 Carmine Eval Top ¦ +---#2 Power 1xx +---#3 Video Input +---#4 RGB Input 2xx +---#5 YUV Input 3xx +---#6 Vin Selector 4xx +---#7 Video Output +---#8 RGB Output 5xx +---#9 DVI Output 6xx +---#10 LVDS Output 7xx +---#11 Carmine Subsystem +---#12 Carmine 8xx +---#13 Carmine Power 8xx +---#14 PCI 8xx +---#15 DRAM 9xx
Power &Config
#11
VideoInput Output
Video
Device Function
I2C Address Map
U200 AD9883 RGB input ADC 0x98 0x99U300 SAA7113 composite video in #0 0x48 0x49U301 SAA7113 composite video in #1 0x4a 0x4bU400 XC2C128* video input selector 0x60 0x61U600 SIL164 DVI transmitter #0 0x70 0x71U601 SIL164 DVI transmitter #1 0x72 0x73
* I2C address of video input selector depends on CPLD implementation
ReadWrite
VO0_RGB[23..0]
VO1_RGB[23..0]
VO1_SYNC[4..0]
VO0_SYNC[4..0]
VI0_RGB[2..0]
VO_CTRL[1..0]
VI0_EXT_SYNC[1..0]
RESET#2
VO0_CLK[4..0]
VO1_CLK[4..0]
I2C[1..0]
PCI_RESET# RESET#[2..0]
CONFIG[4..0]CONFIG[7..5]
CM_VI0_RGB[17..0]
CM_VI1_656_D[7..0]
CM_VI0_SYNC[3..0]
CM_VI1_CLK
I2C[1..0]
CONFIG[7..5]
RESET#2
VI0_RGB[2..0]
VI0_EXT_SYNC[1..0]
VO1_SYNC_EXT[2..0]
VO0_SYNC_EXT[2..0]
VO_CTRL[1..0]
VO0_GV
Carmine Subsystem
CM_VI0_RGB[17..0]
CM_VI1_656_D[7..0] VO1_RGB[23..0]
RESET#[2..0]PCI_RESET#
VO0_SYNC[4..0]
VO1_SYNC[4..0]
VO0_RGB[23..0]
CONFIG[4..0]
CM_VI1_CLK
CM_VI0_SYNC[3..0]
I2C[1..0]
VO1_SYNC_EXT[2..0]
VO0_SYNC_EXT[2..0]
VO0_CLK[4..0]
VO1_CLK[4..0]
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RESET#2
PG_VCC12
CO
NFI
G3
CLK
SE
L0
CO
NFI
G0
JTA
G_T
RS
T#
CO
NFI
G2
CA
RM
INE
_MO
DE
1C
ON
FIG
1C
AR
MIN
E_M
OD
E0
CO
NFI
G5
VI_
MO
DE
0C
ON
FIG
6V
I_M
OD
E1
CO
NFI
G7
VO
UT0
_RG
B_S
EL
CONFIG[7..5]
CONFIG[4..0]
CO
NFI
G4
CLK
SE
L1
PG_VCC12
PG_VCC12#
PG_VCC12
PG_VCC12#
RESET#0
PCI_RESET#
RESET#1
RESET#2
RESET#1
RESET#0
RESET#[2..0]
RESET#0RESET#1RESET#2
PG_VCC25
PG_VCC25
CONFIG[4..0]
CONFIG[7..5]
PCI_RESET#
RESET#[2..0]
VCC50VCC33VCC_PCI33 VCC25VCC_PCI33VCC25
VCC_PCI33
VCC_PCI33
VCC18VCC25
VCC33
VCC_PCI33
VCC_PCI33
VCC_PCI33 VCC25VCC12
VCC33
VCC33 VCC_PCI33VCC33
VCC50
VT_DRAM
VCC_PCI33 VCC25
VCC_PCI33
VCC12
Title
Size Document Number R ev
Date: Sheet o f
30100-002 PA11
Fujitsu Carmine Evaluation Board: Power
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
2 15Monday, November 21, 2005
PCB label:3.3V
PCB label:5.0V
PCB label:2.5V
PCB label:RESET
PCB label:PG 1.2V
switch #no function default
DIP Switch Settings
1 JTAG TRST# on2 Carmine MODE0 pin off3 Carmine MODE1 pin off4 Carmine CLKSEL 0 pin off5 Carmine CLKSEL 1 pin on6 Video in Mode 0 off7 Video in Mode 1 off8 Video out #0 RGB select on
DDR SDRAM Supply
Carmine Core Supply
Video Input Selector CPLD Supply
Carmine 3.3V switch
Place C128 - C132 directly tothe corresponding U103 pins!
NP
DDR SDRAM Termination
PCB label:Carmine Reset
100uC145
10kR130
D102TLMC3100
21kR119
100uC102
1n
C142
10nC146
R106680R
309kR100
4k7R128
110kR109
392kR108
100nC129
10uC125
LTC1763
U102
LTC1763CS8
Out 1
SENSE/ADJ 2
GND1 3
BYP 4SHDN5
GND26
GND37
IN8
100p
C117
7447785001L100
U100
LTC3412EFE
PVIN216
SVIN1
SYNC/MODE6
RT5
ITH3SGND1 8
PGND1 12
PGOOD 2
SW1 10
VFB4
SG
ND
217
SW2 11SW3 14SW4 15
PGND2 13
PVIN19
RUN/SS7
10kR111
1n
C107
R104150R
SI3443
T100
SI3443DV
D11
D22
G3 S 4
D3 5
D4 6
22uC105
7447785001L103
100p
C140
22uC114
100nC101
+ C122100u100n
C124
R105470R
U106
LTC3413EFE
PVIN216
SVIN1
SYNC/MODE6
RT5
ITH3SGND1 8
PGND1 12
PGOOD 2
SW1 10
VFB4
SG
ND
217
SW2 11SW3 14SW4 15
PGND2 13
PVIN19
RUN/SS7
100u
C137
100uC144
71k5
R125
1n
C115
309kR113
1k5R120
7447785001L102
U101
LTC3412EFE
PVIN216
SVIN1
SYNC/MODE6
RT5
ITH3SGND1 8
PGND1 12
PGOOD 2
SW1 10
VFB4
SG
ND
217
SW2 11SW3 14SW4 15
PGND2 13
PVIN19
RUN/SS7
D100TLMT3100
D104TLMC3100
10kR118
100nC123
1n
C116
1k91R124
110kR116
100uC111
22pC100
100u
C136
100nC128
100nC133
100nC104
10u
C120
TLC7733
U104
TLC7733ID
CONTROL1
RESIN2
CT3
GND4
VDD 8
SENSE 7
RESET 6
RESET# 5
2n2
C139
1k5R121
1k5
R126
100nC113
2k94R129
100p
C108
T101MGSF1N02LT1
1n
C138
10nC130
100uC103
15kR107
100n
C141
100nC132
D101TLMC3100
D103TLMC3100
10n
C119
100nC143
4M7
R112
93k1R115
15kR114
28kR123
1nC134
100nC110
100n
C135
100n
C121
SW100MHS-08
R101390R
5k11R132
100nC126
100uC112
LTC2900
U103
LTC2900-1IMS
V31
V12
CRT3
RST#4
VREF 8
VPG 7
GND 6PBR#5
V4 9
V2 10
309kR131
10kR127
SW101B3S1000
1 4
2 3
75k
R117
100nC131
1n
C106
100n
C118
1k87
R122
22pC109
75k
R110
R103309k
100nC127
R102470R
TLC7733
U105
TLC7733ID
CONTROL1
RESIN2
CT3
GND4
VDD 8
SENSE 7
RESET 6
RESET# 5
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RESET#2
VI0_656_CLK
VI1_656_CLK
VI0_656_D[7..0]
VI1_656_D[7..0]
CM_VI0_SYNC[3..0]
I2C[1..0]
CM_VI1_CLK
CM_VI0_RGB[17..0]
CM_VI1_656_D[7..0]
RESET#2
VI0_RGB[2..0]
VO_CTRL[1..0]
VI0_RGB_D[17..0]
CONFIG[7..5]
I2C[1..0]
VI0_EXT_SYNC[1..0]
VI0_RGB_CLK
VO1_SYNC_EXT[2..0]
VO0_SYNC_EXT[2..0]
VI0_RGB_CLK
VI0_RGB_D[17..0]
VI0_RGB_SYNC[1..0]
VO0_GV
VI2_656_CLK
VI2_656_D[7..0]
VI2_656_SYNC[1..0]
VI2_656_SYNC[1..0]
VI0_FID
VI0_FID
VI0_RGB_SYNC[1..0]
VI_CTRL0
RG
BA
N_I
N_D
IS#
RESET#2
I2C[1..0]
CM_VI0_RGB[17..0]
CM_VI0_SYNC[3..0]
CM_VI1_CLK
CM_VI1_656_D[7..0]
CONFIG[7..5]
VI0_RGB[2..0]
VO_CTRL[1..0]
VI0_EXT_SYNC[1..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
VO0_GV
Title
Size Document Number Rev
Date: Sheet o f
30101-003 PA11
Fujitsu Carmine Evaluation Board: Video Input
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A3
3 15Monday, November 21, 2005
Reference ID: 300#5
Reference ID: 200#4
Input
Input
RGB
YUV
Video InputSelector
#6 Reference ID: 400
VI0_656_CLK
VI1_656_CLK
VI0_656_D[7..0]
VI1_656_D[7..0]
CM_VI1_656_D[7..0]
CM_VI1_CLK
I2C[1..0]
RESET#2
CM_VI0_SYNC[3..0]
CM_VI0_RGB[17..0]
CONFIG[7..5]
VI0_RGB_D[17..0]
VO_CTRL[1..0]
VI0_RGB_CLK
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
VO0_GV
VI2_656_CLK
VI2_656_D[7..0]
VI2_656_SYNC[1..0]
VI2_656_SYNC[1..0] VI0_FID
VI0_RGB_SYNC[1..0]
VI_CTRL0
VI0_RGB_SYNC[1..0]
VI0_RGB_D[17..0]
VI0_RGB[2..0]
I2C[1..0]
VI0_RGB_CLK
VI0_EXT_SYNC[1..0]
VI_CTRL0
RGBAN_IN_DIS#
RESET#2
I2C[1..0]
VI0_656_CLK
VI1_656_CLK
VI0_656_D[7..0]
VI1_656_D[7..0]
VI0_RGB_D[17..0]
VI0_RGB_SYNC[1..0]
VI0_RGB_CLK
VI2_656_CLK
VI2_656_D[7..0]
VI2_656_SYNC[1..0]
VI0_FID
RGBAN_IN_DIS#
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VI0_RGB_CLK
VI0_RGB[2..0]
VI0
_RG
B0
VI0
_RE
DV
I0_R
GB
1V
I0_G
RE
EN
VI0
_RG
B2
VI0
_BLU
E
VI0_EXT_HS
VI0_EXT_VS
I2C_SCLI2C_SDA
I2C[1..0]
I2C0 I2C_SCLI2C1 I2C_SDA
VI0_RGB_D0VI0_RGB_D2VI0_RGB_D4VI0_RGB_D6VI0_RGB_D8VI0_RGB_D10VI0_RGB_D12VI0_RGB_D14VI0_RGB_D16
VI0_RGB_D1VI0_RGB_D3VI0_RGB_D5VI0_RGB_D7VI0_RGB_D9VI0_RGB_D11VI0_RGB_D13VI0_RGB_D15VI0_RGB_D17
VI0_VSYNC
VI0_RGB_CLKRGBAN_IN_DIS#VI0_HSYNC
VI_CTRL0
VI0_RGB_SYNC1VI0_VSYNCVI0_RGB_SYNC0VI0_HSYNC
VI0_RGB_SYNC[1..0]RGBAN_IN_DIS#
VI0_VSYNCVI0_HSYNC
VI0_B0VI0_B1VI0_B2VI0_B3VI0_B4VI0_B5
VI0_G0VI0_G1VI0_G2VI0_G3VI0_G4VI0_G5VI0_R0VI0_R1VI0_R2VI0_R3VI0_R4VI0_R5
VI0_RGB_D2VI0_B2VI0_RGB_D3VI0_B3
VI0_RGB_D1VI0_B1
VI0_RGB_D12VI0_R0VI0_RGB_D13VI0_R1
VI0_RGB_D6VI0_G0
VI0_RGB_D4VI0_B4
VI0_RGB_D14VI0_R2
VI0_RGB_D10VI0_G4
VI0_RGB_D5VI0_B5
VI0_RGB_D0VI0_B0
VI0_RGB_D15VI0_R3
VI0_RGB_D11VI0_G5
VI0_RGB_D[17..0]
VI0_RGB_D8VI0_G2VI0_RGB_D7VI0_G1
VI0_RGB_D9VI0_G3
VI0_RGB_D16VI0_R4VI0_RGB_D17VI0_R5
VI0_EXT_SYNC1VI0_EXT_VSVI0_EXT_SYNC0VI0_EXT_HS
VI0_EXT_SYNC[1..0]
RGBAN_IN_DIS#
VI0_RGB_CLK
VI0_RGB[2..0]
I2C[1..0]
VI_CTRL0
VI0_RGB_SYNC[1..0]
VI0_RGB_D[17..0]
VI0_EXT_SYNC[1..0]
RGBAN_IN_DIS#
VCC33
GND_RGBI
GND_RGBI
VCC33VCC33
GND_RGBI GND_RGBI
GND_RGBI
GND_RGBI
GND_RGBI GND_RGBI
VCC_PLL_ADC
VCC_PLL_ADC
VCC33
VCC33
GND_RGBI
GND_RGBI
VCC50
VCC33
Title
Size Document Number R ev
Date: Sheet o f
30101-004 PA11
Fujitsu Carmine Evaluation Board: Video Input: RGB
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
4 15Monday, November 21, 2005
Place filter networks directlyto U200 power pins!
NP
I2C addressesof ADV9883read: 0x99,write: 0x98
Place RN200 - RN204, R207 directlyto the corresponding U200 pins!Consider ADV9883 layout rules!
Short traces, no vias for all analog signals!
Place filter network directlyto U201 power pins!
RG
B d
igit
al in
put
RG
B a
nalo
g
in
put
Digital RGB input cablemust tie pin 22 and 24 together in order to avoiddigital RGB input busconflict with ADC!
R20010k
R202 0R
R203 0R
1nC204
X200
FTSH-105-01-L-DV
12345678910
10uC203
100nC205
47nC212
82nC223
R201 0R
RN203
33Rx4
1234 5
678
1nC200
33pC219
BLM18PG600SN1
L201
100nC220
10uC210
10uC207
R204 75R
C225100n
100nC202
BLM18PG600SN1
L200
X201
FTSH-112-01-L-DV-ES
1 23 45 67 89 10
11 1213 1415 1617 1819 202123 24
22
10uC217
BLM18PG600SN1L204
R207 33R
47nC213
8n2C224
RN202
33Rx4
1234 5
678
R205 0R
1nC215
47nC211
100nC222
33pC218
R206 75R
100nC209
ADV9883Video ADC
RGB
inSy
nc in
I2C
Ref
GND Sync
out
Blu
e ou
tR
ed o
utG
reen
out
Analog supplyDigital supply PLL supply
U200
AD9883ABSTZ-RL140
VD
D1
11V
DD
222
VD
D3
23V
DD
469
VD
D5
78V
DD
679
VD
139
VD
242
VD
345
VD
446
VD
551
VD
652
VD
759
VD
862
PV
D1
26P
VD
227
PV
D3
34P
VD
435
GN
D1
1G
ND
210
GN
D3
20G
ND
421
GN
D5
24G
ND
625
GN
D7
28G
ND
832
GN
D9
36G
ND
1040
GN
D11
41G
ND
1244
GN
D13
47G
ND
1450
GN
D15
53G
ND
1660
GN
D17
61G
ND
1863
GN
D19
68G
ND
2080
RAIN54
GAIN48
BAIN43
SOGIN49
HSYNC30
VSYNC31
CLAMP38
COAST29
RDO0 77RDO1 76RDO2 75RDO3 74RDO4 73RDO5 72RDO6 71RDO7 70
GDO0 9GDO1 8GDO2 7GDO3 6GDO4 5GDO5 4GDO6 3GDO7 2
BDO0 19BDO1 18BDO2 17BDO3 16BDO4 15BDO5 14BDO6 13BDO7 12
SOGOUT 65HSOUT 66VSOUT 64DTACK 67
SDA57SCL56
A055
REF_BYP58
MIDSCV37
FILT33
100nC206
C227100n
R212 2k7
R210 0R
47nC214
100nC216
100nC201
BLM18PG600SN1L205
RN201
33Rx4
1234 5
678
FSAV430
U201
FSAV430MTC
S 1
1B2 3
1A 4
2B1 5
2B2 6
2A 7
1B1 2
GND 83A9
VCC16
4B213
OE15
4B114
4A12
3B210
3B111
R209 75R
BLM18PG600SN1L203
R208 0R
RN200
33Rx4
1234 5
678
1nC208
RN204
33Rx4
1234 5
678
L206
BLM18PG600SN1
C22610u
33pC221
U202
FST16211MTDX
1A121A231A341A451A561A67
VC
C17
GN
D8
GN
D19
GN
D38
GN
D49
1A791A810 1B8 46
1B7 471B6 481B5 501B4 511B3 521B2 531B1 54
2OE551OE156
2B1 412B2 402B3 392B4 37
2A1152A2162A3182A420
1A9111A10121A11131A1214
1B9 451B10 441B11 431B12 42
2A5212A6222A7232A8242A9252A10262A11272A1228
2B5 362B6 352B7 342B8 332B9 32
2B10 312B11 302B12 29
NC 1
R211 0R
R213
4k7
BLM18PG600SN1
L202
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RESET#2
SAA7113_CLK0
VI0_656_CLK
I2C[1..0]
I2C0 I2C_SCL
I2C1 I2C_SDAAVIN0_12
AVIN0_11
AVIN0_21
AVIN0_22
I2C0 I2C_SCL
I2C1 I2C_SDA
VI1_656_D0VI1_656_D1VI1_656_D2
AVIN1_21
AVIN1_22
SAA7113_CLK1
AVIN1_11
AVIN1_12
VI1_656_D[7..0]
VI1_656_CLK
VI0_656_D2
VI1_656_D6VI1_656_D7
VI1_656_D5
VI0_656_D1
VI0_656_D5VI0_656_D4
VI0_656_D7VI0_656_D6
VI0_656_D3
VI0_656_D0
VI0_656_D[7..0]
VI1_656_D4
VI1_656_D3
SAA7113_CLK0
SAA7113_CLK1
VI0_RGB_CLK
VI0_RGB_SYNC[1..0]
VI0_RGB_SYNC1 VI0_VSYNCVI0_RGB_SYNC0 VI0_HSYNC
RESET#2
VI0_RGB_D3 VI0_B3VI0_RGB_D4 VI0_B4
VI0_RGB_D8 VI0_G2
VI0_RGB_D1 VI0_B1
VI0_RGB_D11 VI0_G5
VI0_RGB_D14 VI0_R2
VI0_RGB_D12 VI0_R0VI0_RGB_D0 VI0_B0
VI0_RGB_D10 VI0_G4
VI0_RGB_D17 VI0_R5
VI0_RGB_D[17..0]
VI0_RGB_D5 VI0_B5
VI0_RGB_D9 VI0_G3
VI0_RGB_D2 VI0_B2
VI0_RGB_D7 VI0_G1
VI0_RGB_D15 VI0_R3
VI0_RGB_D6 VI0_G0
VI0_RGB_D13 VI0_R1
VI0_RGB_D16 VI0_R4
VI2_656_D[7..0]
VI2_656_D0VI2_656_D1VI2_656_D2VI2_656_D3VI2_656_D4VI2_656_D5VI2_656_D6VI2_656_D7VI2_656_CLKVI2_656_HSYNC
VI2_656_VSYNC
RESET#2
VI0_HSYNC
AVIN0_12AVIN0_11AVIN0_22
VI2_656_CLK
VI2_656_SYNC[1..0]
VI2_656_SYNC0VI2_656_HSYNCVI2_656_SYNC1VI2_656_VSYNC
AVIN1_12AVIN1_11
AVIN0_21
AVIN1_22AVIN1_21
VI2_656_D0
VI2_656_D2VI2_656_D3VI2_656_D4VI2_656_D5
VI2_656_D7VI2_656_D6
VI2_656_D1
VI0_VSYNC
VI0_RGB_CLK
VI0_B2VI0_B3VI0_B4VI0_B5
VI0_B0VI0_B1
VI0_G2VI0_G3VI0_G4VI0_G5
VI0_G0VI0_G1
VI0_R2VI0_R3
VI0_R5VI0_R4
VI0_R0VI0_R1
I2C_SCL
I2C_SDA
VI0_FID
VI0_FID
RGBAN_IN_DIS#
VI0_656_CLK
VI0_656_D[7..0]
RESET#2
I2C[1..0]
VI1_656_CLK
VI1_656_D[7..0]
VI0_RGB_CLK
VI0_RGB_SYNC[1..0]
VI0_RGB_D[17..0]
VI2_656_D[7..0]
VI2_656_CLK
VI2_656_SYNC[1..0]
VI0_FID
RGBAN_IN_DIS#
VCC33
VCC33
VCC33
VCC33
VCC33 VCC33
GND_CV
GND_CV
GND_CV
GND_CV
GND_CV GND_CV
GND_CVGND_CV
GND_CV GND_CV
GND_CVGND_CV
GND_CV
GND_CV
GND_CV
GND_CV
GND_CV
GND_CV
Title
Size Document Number R ev
Date: Sheet o f
30101-005 PA11
Fujitsu Carmine Evaluation Board: Video Input: YUV
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
5 15Monday, November 21, 2005
PCB Layout: refer to layout guideand SAA7113 application note!
Place capacitors directlyto digital power pins!
Place filter networkdirectly to VDDAx andVSSAx power pins!
I2C addresses of SAA7113 #0read: 0x49, write: 0x48
Place RN300, RN301 andR304 directly to thecorresponding U300 pins!
I2C addresses of SAA7113 #1read: 0x4b, write: 0x4a
Place RN302, RN303 andR314 directly to thecorresponding U301 pins!
Place capacitors directlyto digital power pins!
Place filter networkdirectly to VDDAx andVSSAx power pins!
Place R320, R322directly to Y300 pin 3!
Keep SAA7113 clock signalsas short as possible!
Pads
Keep analog videosignals short, no vias!
Com
posi
tevi
deo
inpu
t
RN303
33Rx4
1234 5
678
47nC308
47nC315
10uC320
L302
BLM18PG600SN1
18RR300
47nC304
100nC309
47nC301
4k7
R318
100nC324
R322 33R
100nC318
18RR317
100nC319
33RR304
10uC307
18RR312
18RR315
18RR302
10uC325
18RR310
56RR301
BLM18PG600SN1L300
100nC311
100nC310
47nC314
33RR314
C328100n
18RR308
100nC323
Video in 1
Video in 2
Bound ary S can
I 2C
V ideo out
C lock
I O
SAA7113H
U301
AI11 4AI1D 5AI12 7
AOUT 9
AI21 43AI2D 44AI22 1
AGND 6
VSSA1 2VSSA2 41
VDDA1 3VDDA2 42
TDI 38TCK 37TMS 39
TRST 8TDO 36
VD
DD
E1
18V
DD
DI
29V
DD
DA
33V
DD
DE
234
VS
SD
E1
16V
SS
DI
28V
SS
DA
30V
SS
DE
235
RTS
026
RTS
127
RTC
025
VD
DA
010
VS
SA
011
CE
40VPO022VPO121VPO220VPO319VPO415VPO514VPO613VPO712
XTALI32
LLC17
SCL24
SDA23
XTAL31
C3271u L303
BLM18PG600SN1
18RR305
RN302
33Rx4
1234 5
678
10uC312
56RR319
X302
FTSH-110-01-L-DV-ES
123456
121314151617181920
7891011
56RR313
56RR316
BLM18PG600SN1L301
56RR303
56RR311
47nC300
100nC322
100nC306
56RR309
X300
FTSH-108-01-L-DV
1 23 45 67 89 10
11 1213 1415 16
56RR306
47nC321
C326100n
0RR323
4k7
R321
100nC305
47nC303
RN301
33Rx4
1234 5
678
R320 33R
47nC316
47nC317
47nC302
47nC313
X301
9632S-45-B-T
123456789
101112131415161718192021222324252627282930313233343536373839404142434445
5152
OSC
Y300
SG8002 CA PC 24.576
OE 1
GND 2OUT3
VCC4
RN300
33Rx4
1234 5
678
Video in 1
Video in 2
Bound ary S can
I 2C
V ideo out
C lock
I O
SAA7113H
U300
AI11 4AI1D 5AI12 7
AOUT 9
AI21 43AI2D 44AI22 1
AGND 6
VSSA1 2VSSA2 41
VDDA1 3VDDA2 42
TDI 38TCK 37TMS 39
TRST 8TDO 36
VD
DD
E1
18V
DD
DI
29V
DD
DA
33V
DD
DE
234
VS
SD
E1
16V
SS
DI
28V
SS
DA
30V
SS
DE
235
RTS
026
RTS
127
RTC
025
VD
DA
010
VS
SA
011
CE
40
VPO022VPO121VPO220VPO319VPO415VPO514VPO613VPO712
XTALI32
LLC17
SCL24
SDA23
XTAL31
4k7R307
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CM_VI0_SYNC[3..0]
CM_VI0_RGB[17..0]
CM_VI1_656_D[7..0]
VO_CTRL[1..0]
CM_VI0_SYNC2CM_VI0_VSCM_VI0_SYNC3CM_VI0_FID
CPLD_VI1_656_D7 CM_VI1_656_D7
I2C[1..0]
CONFIG[7..5]
VI0_RGB_CLK
VI0_RGB_SYNC[1..0]
VI0_RGB_SYNC1 VI0_VSYNCVI0_RGB_SYNC0 VI0_HSYNC
VI0_RGB_D[17..0]
VI0_RGB_D12 VI0_R0VI0_RGB_D13 VI0_R1VI0_RGB_D14 VI0_R2
VI0_RGB_D17 VI0_R5
VI0_RGB_D15 VI0_R3VI0_RGB_D16 VI0_R4
VI0_RGB_D3 VI0_B3
VI0_RGB_D0 VI0_B0
VI0_RGB_D2 VI0_B2VI0_RGB_D1 VI0_B1
VI0_RGB_D5 VI0_B5VI0_RGB_D4 VI0_B4
VI0_RGB_D9 VI0_G3
VI0_RGB_D6 VI0_G0
VI0_RGB_D8 VI0_G2VI0_RGB_D7 VI0_G1
VI0_RGB_D11 VI0_G5VI0_RGB_D10 VI0_G4
VI1_656_D1VI1_656_D0
VI1_656_D3VI1_656_D2
VI1_656_D5VI1_656_D4
VI1_656_D7VI1_656_D6
VI0_656_D[7..0]
VI1_656_D[7..0]
VI0_656_D6VI0_656_D7
VI0_656_D4VI0_656_D5
VI0_656_D2VI0_656_D3
VI0_656_D0VI0_656_D1
VO_CTRL0VO_CTRL1
VO1_SYNC_EXT[2..0]VO1_EXT_CLK VO1_SYNC_EXT0
VO1_SYNC_EXT1VO1_EXT_HSYNCVO1_EXT_VSYNC VO1_SYNC_EXT2
VO0_SYNC_EXT1VO0_EXT_HSYNC
VO0_SYNC_EXT[2..0]
VO0_SYNC_EXT2VO0_EXT_VSYNC
VO0_SYNC_EXT0VO0_EXT_CLK
I2C0I2C_SCLI2C1I2C_SDA
CONFIG5CONFIG6
VO_CTRL1VO_CTRL0
VO0_GV
VI2_656_CLK
VI2_656_D0
VI2_656_D[7..0]
VI2_656_D6VI2_656_D7
VI2_656_D4VI2_656_D5
VI2_656_D2VI2_656_D3
VI2_656_D0VI2_656_D1
VI2_656_D1
VI2_656_D2VI2_656_D3
VI2_656_D6
VI2_656_D7
VI2_656_D4VI2_656_D5
VI0_656_CLK
VI1_656_CLK
VI2_656_SYNC[1..0]
VI2_656_VSYNCVI2_656_SYNC1VI2_656_HSYNCVI2_656_SYNC0
VI2_656_VSYNCVI2_656_HSYNC
CM_VI0_SYNC0CM_VI0_CLKCM_VI0_SYNC1CM_VI0_HS
CM_VI0_RGB16CM_VI0_R4CM_VI0_RGB17CM_VI0_R5
CM_VI0_RGB14CM_VI0_R2CM_VI0_RGB15CM_VI0_R3
CM_VI0_RGB12CM_VI0_R0CM_VI0_RGB13CM_VI0_R1
CM_VI0_RGB11CM_VI0_G5
CM_VI0_RGB8CM_VI0_G2CM_VI0_RGB9CM_VI0_G3CM_VI0_RGB10CM_VI0_G4
CM_VI0_RGB7CM_VI0_G1
CM_VI0_RGB4CM_VI0_B4CM_VI0_RGB5CM_VI0_B5CM_VI0_RGB6CM_VI0_G0
CM_VI0_RGB3CM_VI0_B3
CM_VI0_RGB0CM_VI0_B0CM_VI0_RGB1CM_VI0_B1CM_VI0_RGB2CM_VI0_B2
CM_VI1_656_D7CPLD_VI1_656_D7
CM_VI1_656_D4CM_VI1_656_D5CM_VI1_656_D6
CM_VI1_656_D3
CM_VI1_656_D0CM_VI1_656_D1CM_VI1_656_D2
CM_VI1_CLKVI0_FID
VI_CTRL0
CONFIG7
CONFIG7
RESET#2
CM_VI0_RGB[17..0]
CM_VI0_SYNC[3..0]
CM_VI1_CLK
CM_VI1_656_D[7..0]
VO_CTRL[1..0]
I2C[1..0]
RESET#2
CONFIG[7..5]
VI0_RGB_CLK
VI0_656_CLK
VI1_656_CLK
VI0_RGB_D[17..0]
VI0_RGB_SYNC[1..0]
VI1_656_D[7..0]
VI0_656_D[7..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
VI_CTRL0
VO0_GV
VI2_656_CLK
VI2_656_D[7..0]
VI2_656_SYNC[1..0]
VI0_FID
VCC33VCC18 VCC33
VCC33
VCC33
VCC33
VCC33
Title
Size Document Number R ev
Date: Sheet o f
30101-006 PA11
Fujitsu Carmine Evaluation Board: Video Input: Selector
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
6 15Monday, November 21, 2005
Place capacitors directlyto U400 power pins!
1nC400
100nC407
RN401
33Rx4
1234 5
678
RN404
33Rx4
1234 5
678
100nC404
Xilinx CPLDCoolRunner II -TQ144
Configuration, no connects
Power
1
2
4
3
8
7
6
5
U400
XC2C128-7TQ144
GN
D10
123
GN
D6
89G
ND
790
GN
D8
99G
ND
910
8
VC
CIO
2_1
109
VC
CIO
1_4
93V
CC
IO1_
373
VC
CIO
1_2
55V
CC
IO1_
127
VC
C3
84V
CC
237
VC
C1
1
FB1_216FB1_315FB1_414FB1_513FB1_612FB1_1111FB1_1210FB1_139FB1_147FB1_156FB1_165
FB2_119FB2_221FB2_322FB2_423
TDI
63TM
S65
TCK
67TD
O12
2
VC
CIO
2_2
127
VC
CIO
2_3
141
VC
CA
UX
8
GN
D5
72
GN
D3
47G
ND
236
GN
D1
29
GN
D4
62
FB1_117
FB2_524FB2_625FB2_1126FB2_1228FB2_1330FB2_1432FB2_1535FB2_1638
FB3_13FB3_24FB3_32FB3_4143FB3_5140FB3_6138
FB3_11134FB3_12133FB3_13132FB3_14131FB3_15130FB3_16129
FB3_7136
FB4_139FB4_240FB4_341FB4_443FB4_545FB4_649FB4_750FB4_1151FB4_1252FB4_1353FB4_1454FB4_1556FB4_1657
FB8_1 77FB8_2 76FB8_3 74FB8_4 71FB8_5 70FB8_6 69
FB8_11 68FB8_12 64FB8_13 61FB8_14 60FB8_15 59FB8_16 58
FB7_1 112FB7_2 113FB7_3 115FB7_4 116FB7_5 117FB7_6 118FB7_7 119
FB7_11 120FB7_12 121FB7_13 124FB7_14 125FB7_15 126FB7_16 128
FB5_1 94FB5_2 95FB5_3 96FB5_4 97FB5_5 98FB5_6 100FB5_7 101
FB5_11 102FB5_12 103FB5_13 104FB5_14 105FB5_15 110FB5_16 111
FB6_1 92FB6_2 91FB6_3 88FB6_4 87FB6_5 86FB6_6 85
FB6_11 83FB6_12 82FB6_13 81FB6_14 80FB6_15 79FB6_16 78
GN
D11
144
NC
118
NC
220
NC
331
NC
433
NC
534
NC
642
NC
744
NC
846
NC
948
NC
1066
NC
1175
NC
1210
6N
C13
107
NC
1411
4N
C15
135
NC
1613
7N
C17
139
NC
1814
2
R403 33R
RN407
33Rx4
1234 5
678
R404 33R
RN400
33Rx4
1234 5
678
RN4094k7x4
1 2 3 45678
RN403
33Rx4
1234 5
678
R400 4k7
10uC406
100nC409
100nC401
RN408
33Rx4
1234 5
678
1nC403
RN406
33Rx4
1234 5
678
X400
TSM-106-01-L-SH-A
123456
10uC408
R4014k7
RN402
33Rx4
1234 5
678
RN405
33Rx4
1234 5
678
100nC405
10uC402
R402
4k7
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VO_CTRL[1..0]
VI0_EXT_SYNC[1..0]
VI0_RGB[2..0]
VO0_RGB[23..0]
VO1_RGB[23..0]
VO1_RGBAN[2..0]
VO0_RGBAN[2..0]
RESET#2
VO0_RGB[23..0]
VO1_RGB[23..0]
RESET#2
VO0_CLK3
VO1_CLK3
VO1_SYNC[4..0]
VO0_SYNC0VO0_SYNC1VO0_SYNC2
VO1_SYNC0VO1_SYNC1VO1_SYNC2
VO0_SYNC[4..0]
VO1_SYNC[2..0]
VO0_SYNC[2..0]
VO0_CLK[4..0]
VO_CTRL0
VO_CTRL0
VO0_CLK[2..0]
VO1_CLK0
VO1_CLK2
VO0_CLK3
VO1_CLK[4..0]
VO0_CLK2
VO1_CLK1
VO0_CLK0VO0_CLK1
VO1_CLK[2..0]
VO1_CLK3
I2C[1..0]
VO0_SYNC0VO0_SYNC1VO0_SYNC2VO0_SYNC3
VO1_SYNC0VO1_SYNC1VO1_SYNC2VO1_SYNC3
VO1_SYNC[3..0]
VO0_SYNC[3..0]
VO0_CLK4
VO1_CLK4
RESET#2
VO0_RGB[23..0]
VO1_RGB[23..0]VO1_CLK4
VO0_CLK4
I2C[1..0]
VI0_RGB[2..0]
VO_CTRL[1..0]
VI0_EXT_SYNC[1..0]
VO0_RGB[23..0]
VO1_RGB[23..0]
RESET#2
VO0_SYNC[4..0]
VO1_SYNC[4..0]
VO0_CLK[4..0]
VO1_CLK[4..0]
Title
Size Document Number Rev
Date: Sheet o f
30100-007 PA11
Fujitsu Carmine Evaluation Board: Video Output
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A3
7 15Monday, November 21, 2005
#8 LVDS Output
DVI Output
RGB Output
Reference ID: 500
#9 Reference ID: 600
Reference ID: 700#10
VO0_RGBAN[2..0]
VO1_RGBAN[2..0]
VO_CTRL[1..0]
RESET#2
VO1_RGB[23..0]
VO0_RGB[23..0]
VI0_RGB[2..0] VO0_SYNC[4..0]
VO1_SYNC[4..0]
VO0_CLK[2..0]
VO1_CLK[2..0]
I2C[1..0]
VO0_SYNC[3..0]
VO1_SYNC[3..0]
VO0_CLK4
VO1_CLK4
RESET#2
VO0_RGB[23..0]
VO1_RGB[23..0]
VO0_RGBAN[2..0]
VO1_RGBAN[2..0]
VI0_EXT_SYNC[1..0]
I2C[1..0]
VO0_RGB[23..0]
VO1_RGB[23..0]
RESET#2
VO0_SYNC[2..0]
VO1_SYNC[2..0]
VO1_CLK3
VO0_CLK3
VO_CTRL0
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DAC0_R
DAC0_G
DAC0_B
VO0_RGB[23..0]
VO0_RGB0 VO0_B0VO0_RGB1 VO0_B1VO0_RGB2 VO0_B2VO0_RGB3 VO0_B3VO0_RGB4 VO0_B4VO0_RGB5 VO0_B5VO0_RGB6 VO0_B6VO0_RGB7 VO0_B7
VO0_RGB8 VO0_G0VO0_RGB9 VO0_G1VO0_RGB10 VO0_G2VO0_RGB11 VO0_G3VO0_RGB12 VO0_G4VO0_RGB13 VO0_G5VO0_RGB14 VO0_G6VO0_RGB15 VO0_G7
VO0_RGB16 VO0_R0VO0_RGB17 VO0_R1VO0_RGB18 VO0_R2VO0_RGB19 VO0_R3VO0_RGB20 VO0_R4VO0_RGB21 VO0_R5VO0_RGB22 VO0_R6VO0_RGB23 VO0_R7
VO0_CSYNC
VO1_RGB0 VO1_B0VO1_RGB1 VO1_B1VO1_RGB2 VO1_B2VO1_RGB3 VO1_B3VO1_RGB4 VO1_B4VO1_RGB5 VO1_B5VO1_RGB6 VO1_B6VO1_RGB7 VO1_B7
VO1_RGB8 VO1_G0VO1_RGB9 VO1_G1VO1_RGB10 VO1_G2VO1_RGB11 VO1_G3VO1_RGB12 VO1_G4VO1_RGB13 VO1_G5VO1_RGB14 VO1_G6VO1_RGB15 VO1_G7
VO1_RGB16 VO1_R0VO1_RGB17 VO1_R1VO1_RGB18 VO1_R2VO1_RGB19 VO1_R3VO1_RGB20 VO1_R4VO1_RGB21 VO1_R5VO1_RGB22 VO1_R6VO1_RGB23 VO1_R7
VO1_RGBAN2
VO1_RGBAN1
VO1_RGBAN0
VO1_RGB[23..0]VO1_RGB[23..0]
VO1_CSYNC
VO_CTRL[1..0]
VO_CTRL0
VO_CTRL1DAC0_B
DAC0_G
DAC0_R
VI0_RGB[2..0]
VI0_RGB0 VI0_BLUE
VI0_RGB1 VI0_GREEN
VI0_RGB2 VI0_RED
VO0_RGBAN0
VO0_RGBAN1
VO0_RGBAN2
VO1_RGBAN[2..0]
VO0_RGBAN[2..0]
VO0_RGBAN0VO0_BLUEVO0_RGBAN1VO0_GREENVO0_RGBAN2VO0_RED
VO1_RGBAN0VO1_BLUEVO1_RGBAN1VO1_GREENVO1_RGBAN2VO1_RED
VO0_CLK[2..0]
VO0_CLK0VO0_CLK1
VO1_CLK[2..0]
VO1_CLK0VO1_CLK1
VO0_CLK0 VO1_CLK0
VO0_SYNC[4..0]
VO
0_SY
NC
0V
O0_H
SY
NC
VO
0_SY
NC
1V
O0_V
SY
NC
VO
0_SY
NC
2V
O0_D
EV
O0_S
YN
C3
VO
0_CS
YN
CV
O0_S
YN
C4
VO
0_GV
VO1_SYNC[4..0]
VO
1_SY
NC
0V
O1_H
SY
NC
VO
1_SY
NC
1V
O1_V
SY
NC
VO
1_SY
NC
2V
O1_D
EV
O1_S
YN
C3
VO
1_CS
YN
CV
O1_S
YN
C4
VO
1_GV
VO0_B1VO0_B3VO0_B5VO0_B7VO0_G1VO0_G3VO0_G5VO0_G7
VO0_R1VO0_R3VO0_R5VO0_R7VO0_VSYNCVO0_CSYNCVO0_CLK1I2C_SDA
VO0_B0VO0_B2VO0_B4VO0_B6VO0_G0VO0_G2VO0_G4VO0_G6
VO0_R0VO0_R2VO0_R4VO0_R6VO0_HSYNCVO0_DEVO0_GVI2C_SCL
VO1_B1VO1_B3VO1_B5VO1_B7VO1_G1VO1_G3VO1_G5VO1_G7
VO1_R1VO1_R3VO1_R5VO1_R7VO1_VSYNCVO1_CSYNCVO1_CLK1I2C_SDA
VO1_B0VO1_B2VO1_B4VO1_B6VO1_G0VO1_G2VO1_G4VO1_G6
VO1_R0VO1_R2VO1_R4VO1_R6VO1_HSYNCVO1_DEVO1_GVI2C_SCL
I2C[1..0]
I2C0 I2C_SCLI2C1 I2C_SDA
VO1_CLK2
VO0_CLK2
RESET#2
VO1_R0VO1_R1VO1_R2VO1_R3VO1_R4VO1_R5VO1_R6VO1_R7
VO1_G0VO1_G1VO1_G2VO1_G3VO1_G4VO1_G5VO1_G6VO1_G7
VO1_B0VO1_B1VO1_B2VO1_B3VO1_B4VO1_B5VO1_B6VO1_B7
VO1_CLK2
VO1_GV
VO0_R0VO0_R1VO0_R2VO0_R3VO0_R4VO0_R5VO0_R6VO0_R7
VO0_G0VO0_G1VO0_G2VO0_G3VO0_G4VO0_G5VO0_G6VO0_G7
VO0_B0VO0_B1VO0_B2VO0_B3VO0_B4VO0_B5VO0_B6VO0_B7
VO0_CLK2
VO0_GV
RESET#2 RESET#2
VO0_VSYNCVO0_HSYNCVO0_CSYNCVO0_DE
VO1_VSYNCVO1_HSYNCVO1_CSYNCVO1_DE
VO_CTRL[1..0]
VO0_RGB[23..0]
VO0_CLK[2..0]
VO1_RGB[23..0]
VI0_RGB[2..0]
VO0_RGBAN[2..0]
VO1_RGBAN[2..0]
VO1_CLK[2..0]
VO0_SYNC[4..0]
VO1_SYNC[4..0]
I2C[1..0]
RESET#2
GND_RGBO
GND_RGBO
GND_RGBO
GND_RGBO
VCC33GND_RGBO
GND_RGBO
GND_RGBO
VCC33
GND_RGBO
VCC33
VCC33
VCC33
VCC33 VCC33
Title
Size Document Number R ev
Date: Sheet o f
30100-008 PA11
Fujitsu Carmine Evaluation Board: Video Output: RGB Output
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
8 15Monday, November 21, 2005
Place filter network directlyto U500 power pins!
NP
NP
Place filter network directlyto U501 power pins!
NP
NP
Consider ADV7125 layout rules!
RG
B d
igit
al o
utpu
t #0
RG
B d
igit
al o
utpu
t #1
PadsPads
100nC515
10kR515
BLM18PG600SN1L501
68RR508
75RR500
10uC514
100nC516
75RR502
0RR516
100nC510
10uC519
0RR517
0RR518
X500
FTSH-120-01-L-DV-ES
1 23 45 67 89 10
11 1213 1415 1617 1819 202123 24
22
2527 2829 3031 3233 3435 3637 3839 40
26
470RR509
BLM18PG600SN1L500
L502
BLM18PG600SN1
68RR506
100nC512
100nC506
X501
FTSH-120-01-L-DV-ES
1 23 45 67 89 10
11 1213 1415 1617 1819 202123 24
22
2527 2829 3031 3233 3435 3637 3839 40
26
100nC502
X503
9632S-40-B-T
123456789
10111213141516171819202122232425262728293031323334353637383940
4142
100nC508
100nC513
100nC511
10kR511
100nC518
75RR504
BLM18PG600SN1L503
10kR514
10uC504
470RR507
ADV7125Video DAC
U500
ADV7125JSTZ240
B016B117B218B319B420B521B622B723
G03G14G25G36G47G58G69G710
R041R142R243R344R445R546R647R748
SYNC#12BLANK11CLOCK24
PSAVE#38
IOR 34
IOG 32
IOB 28
IOR# 33
IOG# 31
IOB# 27
VC
C13
VC
C29
VC
C30
GN
D1
GN
D2
GN
D14
GN
D15
GN
D25
GN
D26
GN
D39
GN
D40
RSET 37
COMP 35
VREF 36
10kR510
X502
9632S-40-B-T
123456789
10111213141516171819202122232425262728293031323334353637383940
4142
100nC509
1nC507
10uC517
75RR505
1nC503
100nC505
0RR513
100nC501
75RR503
75RR501
FSAV433
U502
FSAV433
1B11
1B33
GND14
2B15
2B26
2B37
1B22
GND28
3B19
GND5 16
3A 13
2A 15
GND4 14
GND3 12
3B210 3B3 11
1A 17
S2 18
S1 19
VCC 20
0RR512
10uC500
ADV7125Video DAC
U501
ADV7125JSTZ240
B016B117B218B319B420B521B622B723
G03G14G25G36G47G58G69G710
R041R142R243R344R445R546R647R748
SYNC#12BLANK11CLOCK24
PSAVE#38
IOR 34
IOG 32
IOB 28
IOR# 33
IOG# 31
IOB# 27
VC
C13
VC
C29
VC
C30
GN
D1
GN
D2
GN
D14
GN
D15
GN
D25
GN
D26
GN
D39
GN
D40
RSET 37
COMP 35
VREF 36
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C_SDAI2C_SCL
DVI0_PLLVCC
VO0_TX2MVO0_TX2P
VO0_TX1MVO0_TX1P
VO0_TX0MVO0_TX0P
VO0_TXCPVO0_TXCM
DVI0_PLLVCC
VO0_
TX1M
VO0_
TX0P
VO0_
TXC
M
VO0_
TX0M
VO0_
TX2M
VO0_
TX2P
VO0_
TXC
P
VO0_
TX1P
DVI0_HTPLG
DVI0_DKEN
DVI0_CTL1
DVI0_ISEL
DVI0_CTL3
DVI0_HTPLGDVI0_PD
DVI1_PDDVI1_ISEL
DVI0_CTL2
RESET#2
DVI0_CTL1
DVI0_CTL2
DVI0_CTL3
VO0_CLK3
VO0_R7VO0_R6VO0_R5
VO0_R3VO0_R2VO0_R1VO0_R0VO0_G7VO0_G6VO0_G5VO0_G4
VO0_R4
VO
0_B
0V
O0_
B1
VO
0_B
2V
O0_
B3
VO
0_B
4V
O0_
B5
VO
0_B
7V
O0_
G0
VO
0_G
1V
O0_
G2
VO
0_G
3
VO
0_B
6
VO0_SYNC[2..0]
VO0_VSYNCVO0_HSYNC
VO0_DE
VO0_SYNC2 VO0_DEVO0_SYNC1 VO0_VSYNCVO0_SYNC0 VO0_HSYNC
VO0_RGB[23..0]
VO
0_C
LK3
VO
0_RG
B0
VO
0_B0
VO
0_RG
B1
VO
0_B1
VO
0_RG
B2
VO
0_B2
VO
0_RG
B3
VO
0_B3
VO
0_RG
B4
VO
0_B4
VO
0_RG
B5
VO
0_B5
VO
0_RG
B6
VO
0_B6
VO
0_RG
B7
VO
0_B7
VO
0_RG
B8
VO
0_G0
VO
0_RG
B9
VO
0_G1
VO
0_RG
B10
VO
0_G2
VO
0_RG
B11
VO
0_G3
VO
0_RG
B12
VO
0_G4
VO
0_RG
B13
VO
0_G5
VO
0_RG
B14
VO
0_G6
VO
0_RG
B15
VO
0_G7
VO
0_RG
B16
VO
0_R0
VO
0_RG
B17
VO
0_R1
VO
0_RG
B18
VO
0_R2
VO
0_RG
B19
VO
0_R3
VO
0_RG
B20
VO
0_R4
VO
0_RG
B21
VO
0_R5
VO
0_RG
B22
VO
0_R6
VO
0_RG
B23
VO
0_R7
DVI1_DKEN
DVI1_CTL3DVI1_CTL2DVI1_CTL1
DVI1_PD
DVI1_ISEL
VO1_REDVO1_GREENVO1_BLUE
VO1_CLK3
VO1_TX2MVO1_TX2P
VO1_VSYNCVO1_TX1MVO1_TX1P
VO1_TX0MVO1_TX0P
VO1_TXCPVO1_TXCM
VO1_HSYNC
RESET#2
VO1_G4
DVI1_PLLVCC
DVI1_CTL1
DVI1_CTL2
DVI1_CTL3
VO1_SYNC2 VO1_DEVO1_SYNC1 VO1_VSYNCVO1_SYNC0 VO1_HSYNC
I2C_SDAI2C_SCL
DVI1_HTPLG
VO
1_C
LK3
VO1_SYNC[2..0]
VO1_VSYNC
DVI1_PLLVCC
VO1_
TXC
M
VO1_
TX0P
VO1_
TX0M
VO1_
TXC
P
VO1_
TX1M
VO1_
TX2M
VO1_
TX1P
VO1_
TX2P
VO1_HSYNC
VO1_DE
DVI1_HTPLG
VO1_G5VO1_G6VO1_G7VO1_R0VO1_R1VO1_R2VO1_R3VO1_R4VO1_R5VO1_R6VO1_R7
VO
1_B
0V
O1_
B1
VO
1_B
2V
O1_
B3
VO
1_B
4V
O1_
B5
VO
1_B
6V
O1_
B7
VO
1_G
0V
O1_
G1
VO
1_G
2V
O1_
G3
VO
1_RG
B14
VO
1_G6
VO
1_RG
B15
VO
1_G7
VO
1_RG
B23
VO
1_R7
VO
1_RG
B19
VO
1_R3
VO
1_RG
B3
VO
1_B3
VO
1_RG
B20
VO
1_R4
VO
1_RG
B12
VO
1_G4
VO
1_RG
B9
VO
1_G1
VO1_RGB[23..0]
VO
1_RG
B17
VO
1_R1
VO
1_RG
B5
VO
1_B5
VO
1_RG
B16
VO
1_R0
VO
1_RG
B10
VO
1_G2
VO
1_RG
B1
VO
1_B1
VO
1_RG
B13
VO
1_G5
VO
1_RG
B21
VO
1_R5
VO
1_RG
B4
VO
1_B4
VO
1_RG
B11
VO
1_G3
VO
1_RG
B0
VO
1_B0
VO
1_RG
B7
VO
1_B7
VO
1_RG
B8
VO
1_G0
VO
1_RG
B2
VO
1_B2
VO
1_RG
B22
VO
1_R6
VO
1_RG
B6
VO
1_B6
VO
1_RG
B18
VO
1_R2
VO0_REDVO0_GREENVO0_BLUE
VO0_RGBAN1 VO0_GREENVO0_RGBAN0 VO0_BLUE
VO0_RGBAN[2..0]
VO0_RGBAN2 VO0_RED
VO1_RGBAN1 VO1_GREENVO1_RGBAN2 VO1_RED
VO1_RGBAN0 VO1_BLUE
VO1_RGBAN[2..0]
VO_CTRL0
VO_CTRL0
VO0_VSYNC
VI0_EXT_VS
VO_CTRL0
VO0_HSYNC
VI0_EXT_HS
VI0_EXT_VSVI0_EXT_SYNC1
VI0_EXT_SYNC[1..0]
I2C[1..0]
I2C0 I2C_SCLI2C1 I2C_SDA
VI0_EXT_HSVI0_EXT_SYNC0
RESET#2
VO0_RGB[23..0]
VO0_CLK3
VO0_SYNC[2..0]
VO1_SYNC[2..0]
VO1_RGB[23..0]
VO1_CLK3
VO0_RGBAN[2..0]
VO1_RGBAN[2..0]
VO_CTRL0
VI0_EXT_SYNC[1..0]
I2C[1..0]
VCC33
VCC33
VCC50
GND_DVI
VCC33
GND_DVI
GND_DVI
VCC33
GND_DVIVCC33
VCC33
VCC33
GND_DVI
VCC50
GND_DVI
VCC33
GND_DVI
VCC33
VCC33
VCC50
Title
Size Document Number R ev
Date: Sheet o f
30100-009 PA11
Fujitsu Carmine Evaluation Board: Video Output: DVI Output
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
9 15Monday, November 21, 2005
NP
Place filter network directlyto U600 power pins!
Place filter network directlyto U601 power pins!
Place filter network directlyto U600 power pins!
Place filter network directlyto U601 power pins!
Place capacitors directlyto U600 power pins!
Place capacitors directlyto U601 power pins!
Consider SIL164 PCBlayout application note!
Consider SIL164 PCBlayout application note!
I2C addresses of SIL164 #0read: 0x71, write: 0x70
I2C addresses of SIL164 #1read: 0x73, write: 0x72
NP
NP
BLM18PG600SN1L615
100nC628
0RR617
10uC634
BLM18PG600SN1L611
33pC631
BLM18PG600SN1L605
33pC614
100nC609
BLM18PG600SN1L613
10uC624
510RR608
33pC611
1nC608
0RR609
SIL 164 PanelLinkTransmitter
U601
SiI164CT64
VCC11DE2VREF3HSYNC4VSYNC5CTL3/A3/DK36CTL2/A2/DK27CTL1/A1/DK18EDGE/HTPLG9PD10MSEN11VCC212ISEL/RST13DESL/SDA14BSEL/SCL15GND116
PG
ND
17P
VC
C1
18E
XT_
SW
ING
19A
GN
D1
20TX
C-
21TX
C+
22A
VC
C1
23TX
0-24
TX0+
25A
GN
D2
26TX
1-27
TX1+
28A
VC
C2
29TX
2-30
TX2+
31A
GN
D3
32
VCC3 33RESEVED 34
DKEN 35D23 36D22 37D21 38D20 39D19 40D18 41D17 42D16 43D15 44D14 45D13 46D12 47
GND2 48P
VC
C2
49D
1150
D10
51D
952
D8
53D
754
D6
55ID
CK
-56
IDC
K+
57D
558
D4
59D
360
D2
61D
162
D0
63G
ND
364
0RR612
4k7x4RN600
12345
678
100nC616
100nC601
D600BZX84C3V32
2
11
33
100nC604
BLM18PG600SN1L608
SIL 164 PanelLinkTransmitter
U600
SiI164CT64
VCC11DE2VREF3HSYNC4VSYNC5CTL3/A3/DK36CTL2/A2/DK27CTL1/A1/DK18EDGE/HTPLG9PD10MSEN11VCC212ISEL/RST13DESL/SDA14BSEL/SCL15GND116
PG
ND
17P
VC
C1
18E
XT_
SW
ING
19A
GN
D1
20TX
C-
21TX
C+
22A
VC
C1
23TX
0-24
TX0+
25A
GN
D2
26TX
1-27
TX1+
28A
VC
C2
29TX
2-30
TX2+
31A
GN
D3
32
VCC3 33RESEVED 34
DKEN 35D23 36D22 37D21 38D20 39D19 40D18 41D17 42D16 43D15 44D14 45D13 46D12 47
GND2 48
PV
CC
249
D11
50D
1051
D9
52D
853
D7
54D
655
IDC
K-
56ID
CK
+57
D5
58D
459
D3
60D
261
D1
62D
063
GN
D3
64
0RR616
220RR611
0RR602
10uC629
33pC630
BLM18PG600SN1L606
BLM18PG600SN1L609
100nC636
0RR615
1nC
618
BLM18PG600SN1L602
390RR610
4k7x4RN601
12345
678 BLM18PG600SN1
L603
510RR618
BLM18PG600SN1L600
33pC606
390RR600
DVIS029T-002BSX601
123456789
1011121314151617181920212223
C1C2C3C4
C5A
24
C5B
30 31
NC7SB3257
U603
NC7SB3257P6
B11
GND2
B03 A 4
VCC 5
S 6
4k7x4RN602
12345
678
NC7SB3257
U602
NC7SB3257P6
B11
GND2
B03 A 4
VCC 5
S 6
0RR619
BLM18PG600SN1L614
10uC600
33pC633
10uC615
100nC621
100nC626
0RR607
1nC622
BLM18PG600SN1L607
33pC613
100nC635
0RR614
0RR605
10uC610
100nC619
BLM18PG600SN1L601
1nC
637
10kR613 BLM18PG600SN1
L612
100nC603
L616
BLM18PG600SN1
10uC620
0RR606
220RR601
10kR603
33pC625
100nC623
DVIS029T-002BSX600
123456789
1011121314151617181920212223
C1C2C3C4
C5A
24
C5B
30 31
33pC632
D601BZX84C3V32
2
11
33
10uC605
BLM18PG600SN1L604
1nC602
100nC607
33pC612
100nC617
BLM18PG600SN1L610
1nC627
0RR604
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDS_DIS#VO0_CLK4
VO
1_RG
B1
VO
1_B1
VO
1_RG
B2
VO
1_B2
VO
1_RG
B3
VO
1_B3
VO
1_RG
B5
VO
1_B5
VO
1_RG
B6
VO
1_B6
VO
1_RG
B4
VO
1_B4
VO
1_RG
B7
VO
1_B7
VO
1_RG
B9
VO
1_G1
VO
1_RG
B10
VO
1_G2
VO
1_RG
B11
VO
1_G3
VO
1_RG
B8
VO
1_G0
VO
1_RG
B14
VO
1_G6
VO
1_RG
B13
VO
1_G5
VO
1_RG
B15
VO
1_G7
VO
1_RG
B19
VO
1_R3
VO
1_RG
B17
VO
1_R1
VO
1_RG
B18
VO
1_R2
VO
1_RG
B23
VO
1_R7
VO
1_RG
B16
VO
1_R0
VO
1_RG
B21
VO
1_R5
VO
1_RG
B22
VO
1_R6
VO
1_RG
B20
VO
1_R4
VO
1_RG
B12
VO
1_G4
VO1_RGB[23..0]
VO
1_RG
B0
VO
1_B0
VO1_SYNC[3..0]
VO
1_SY
NC
0V
O1_H
SY
NC
VO
1_SY
NC
1V
O1_V
SY
NC
VO
1_SY
NC
2V
O1_D
EV
O1_S
YN
C3
VO
1_CS
YN
C
VO0_CLK4
VO1_CLK4
VO0_DE
VO0_LVDS_3PVO0_LVDS_3MVO0_LVDS_CPVO0_LVDS_CMVO0_LVDS_2PVO0_LVDS_2M
VO0_LVDS_1PVO0_LVDS_1MVO0_LVDS_0PVO0_LVDS_0M
VO0_R6VO0_R0VO0_R1
VO0_R2VO0_R3VO0_R4
VO0_R7VO0_R5VO0_G0
VO0_G1VO0_G2VO0_G6
VO0_G7VO0_G3VO0_G4
VO0_G5
VO0_B6
VO0_B7VO0_B1VO0_B2
VO0_B3VO0_B4VO0_B5
VO0_HSYNCVO0_VSYNC
LVDS_DIS#VO1_CLK4VO1_DE
VO1_LVDS_3PVO1_LVDS_3MVO1_LVDS_CPVO1_LVDS_CM
VO1_LVDS_2M
VO1_LVDS_1PVO1_LVDS_1MVO1_LVDS_0PVO1_LVDS_0M
VO1_R6VO1_R0VO1_R1
VO1_R2VO1_R3VO1_R4
VO1_R7VO1_R5VO1_G0
VO1_G1VO1_G2VO1_G6
VO1_G7VO1_G3VO1_G4
VO1_G5VO1_B0VO1_B6
VO1_B7VO1_B1VO1_B2
VO1_B3VO1_B4VO1_B5
VO1_HSYNCVO1_VSYNC
VO1_LVDS_2P
VO0_LVDS_0M VO0_LVDS_0PVO0_LVDS_1M VO0_LVDS_1PVO0_LVDS_2M VO0_LVDS_2P
VO0_LVDS_CPVO0_LVDS_3P
VO0_LVDS_CMVO0_LVDS_3M
VO1_LVDS_0M VO1_LVDS_0PVO1_LVDS_1M VO1_LVDS_1PVO1_LVDS_2M VO1_LVDS_2P
VO1_LVDS_CPVO1_LVDS_3P
VO1_LVDS_CMVO1_LVDS_3M
RESET#2 LVDS_DIS#
VO
0_RG
B16
VO
0_R0
VO
0_RG
B4
VO
0_B4
VO
0_SY
NC
0V
O0_H
SY
NC
VO
0_RG
B9
VO
0_G1
VO
0_RG
B2
VO
0_B2
VO
0_RG
B23
VO
0_R7
VO0_RGB[23..0]
VO
0_RG
B7
VO
0_B7
VO
0_RG
B13
VO
0_G5
VO
0_RG
B21
VO
0_R5
VO
0_SY
NC
2V
O0_D
E
VO
0_RG
B18
VO
0_R2
VO0_B0
VO
0_RG
B0
VO
0_B0
VO
0_RG
B19
VO
0_R3
VO
0_RG
B1
VO
0_B1
VO
0_SY
NC
3V
O0_C
SY
NC
VO
0_RG
B5
VO
0_B5
VO
0_RG
B14
VO
0_G6
VO
0_RG
B10
VO
0_G2
VO
0_SY
NC
1V
O0_V
SY
NC
VO
0_RG
B12
VO
0_G4
VO
0_RG
B8
VO
0_G0
VO
0_RG
B22
VO
0_R6
VO
0_RG
B20
VO
0_R4
VO0_SYNC[3..0]
VO
0_RG
B3
VO
0_B3
VO
0_RG
B6
VO
0_B6
VO
0_RG
B15
VO
0_G7
VO
0_RG
B17
VO
0_R1
VO
0_RG
B11
VO
0_G3
VO0_CSYNC
VO1_CSYNC
VO0_RGB[23..0]
VO1_RGB[23..0]
VO0_SYNC[3..0]
VO1_SYNC[3..0]
VO0_CLK4
VO1_CLK4
RESET#2
VCC33
VCC33
VCC33
GND_LVDS
GND_LVDS
VCC33
VCC33
GND_LVDS
VCC33
GND_LVDS
VCC33
GND_LVDS
VCC33
VCC33
Title
Size Document Number R ev
Date: Sheet o f
30100-010 PA11
Fujitsu Carmine Evaluation Board: Video Output: LVDS Output
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A2
10 15Monday, November 21, 2005
Place filter directlyto PLL power pins!
Place capacitors directlyto digital power pins!
Place capacitors directlyto LVDS power pins!
Place capacitors directlyto LVDS power pins!
Place filter directlyto PLL power pins!
Place capacitors directlyto digital power pins!
NP
NP
BLM18PG600SN1L702
100nC703
100nC721
1nC700
R702 0R
100nC710
100nC712
10uC719
R701
0R
BLM18PG600SN1L700
10uC708
10uC715
100nC720
R704 0R
10uC713
R70010k
1nC716
R7030R
100nC709
1nC705
R7050R
100nC714
DS90CR285
TransmitterChannel Link
U700
DS90CR285MTD
TXIN52VCC11
TXIN63TXIN74GND15TXIN86TXIN97TXIN108VCC29TXIN1110TXIN1211TXIN1312GND213TXIN1414TXIN1515TXIN1616VCC317TXIN1718TXIN1819TXIN1920GND321TXIN2022TXIN2123TXIN2224TXIN2325VCC426TXIN2427TXIN2528 GND4 29
TXIN26 30TXCLKIN 31
PWRDWN 32PLLGND1 33
PLLVCC 34PLLGND2 35
LVDSGND1 36TXOUT3_P 37TXOUT3_M 38
TXCLKOUT_P 39TXCLKOUT_M 40
TXOUT2_P 41TXOUT2_M 42LVDSGND2 43
TXOUT0_P 47TXOUT1_M 46TXOUT1_P 45LVDSVCC 44
TXOUT0_M 48LVDSGND3 49
TXIN27 50TXIN0 51TXIN1 52GND5 53TXIN2 54TXIN3 55TXIN4 56
100nC718
100nC701
10uC704
DS90CR285
TransmitterChannel Link
U701
DS90CR285MTD
TXIN52VCC11
TXIN63TXIN74GND15TXIN86TXIN97TXIN108VCC29TXIN1110TXIN1211TXIN1312GND213TXIN1414TXIN1515TXIN1616VCC317TXIN1718TXIN1819TXIN1920GND321TXIN2022TXIN2123TXIN2224TXIN2325VCC426TXIN2427TXIN2528 GND4 29
TXIN26 30TXCLKIN 31
PWRDWN 32PLLGND1 33
PLLVCC 34PLLGND2 35
LVDSGND1 36TXOUT3_P 37TXOUT3_M 38
TXCLKOUT_P 39TXCLKOUT_M 40
TXOUT2_P 41TXOUT2_M 42LVDSGND2 43
TXOUT0_P 47TXOUT1_M 46TXOUT1_P 45LVDSVCC 44
TXOUT0_M 48LVDSGND3 49
TXIN27 50TXIN0 51TXIN1 52GND5 53TXIN2 54TXIN3 55TXIN4 56
X700
FTSH-108-01-L-DV
1 23 45 67 89 10
11 1213 1415 16
100nC707
100nC717
L701
BLM18PG600SN1
1nC711
X701
FTSH-108-01-L-DV
1 23 45 67 89 10
11 1213 1415 16
10uC702
100nC706
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_RESET#
VO0_SYNC[4..0]
RESET#[2..0]
JTAG[4..0]
CM_VI0_SYNC[3..0]
PCI33_CTRL[14..0]
CM_VI1_656_D[7..0]
I2C[1..0]
CM_VI1_CLK
VO1_SYNC_EXT[2..0]
CONFIG[4..0]
VO0_SYNC_EXT[2..0]
VO1_RGB[23..0]
VO1_SYNC[4..0]
PCI33_AD[31..0]
VO0_RGB[23..0]CM_VI0_RGB[17..0]
VO0_CLK[4..0]
VO1_CLK[4..0]
SD_D[63..0]
SD_AD[15..0]
SD_DQS[7..0]
SD_CTRL[12..0]
SD_DQM[7..0]
VO0_SYNC_EXT[2..0]
PCI_RESET#
CM_VI1_656_D[7..0]
VO0_RGB[23..0]
I2C[1..0]
CM_VI1_CLK
CM_VI0_RGB[17..0]
VO1_RGB[23..0]
CM_VI0_SYNC[3..0]
RESET#[2..0]
CONFIG[4..0]
VO1_SYNC_EXT[2..0]
VO0_CLK[4..0]
VO1_CLK[4..0]
VO0_SYNC[4..0]
VO1_SYNC[4..0]
Title
Size Document Number Rev
Date: Sheet o f
30100-011 PA11
Fujitsu Carmine Evaluation Board: Carmine Subsystem
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A3
11 15Monday, November 21, 2005
#13
#12
Vide
o in
put
PCI
CarminePower
DDRSDRAM
I2C
, con
fig,
rese
t
Reference ID: 8xx, 9xx
Reference ID: 8xx #14 #15Reference ID: 9xxReference ID: 8xx
DD
R S
DR
AM
Exte
rnal
Sy
ncVi
deo
out
SD_DQM[7..0]
SD_D[63..0]
SD_AD[15..0]
SD_CTRL[12..0]
SD_DQS[7..0]
Carmine
SD_AD[15..0]
SD_D[63..0]
SD_DQM[7..0]
SD_CTRL[12..0]
SD_DQS[7..0]
PCI33_AD[31..0]
PCI33_CTRL[14..0]
RESET#[2..0]
I2C[1..0]
JTAG[4..0]
VO1_RGB[23..0]
VO0_RGB[23..0]
VO1_SYNC[4..0]
VO0_SYNC[4..0]
CONFIG[4..0]
CM_VI1_656_D[7..0]
CM_VI1_CLK
CM_VI0_RGB[17..0]
CM_VI0_SYNC[3..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
VO1_CLK[4..0]
VO0_CLK[4..0]
PCI
PCI_RESET#
PCI33_AD[31..0]
PCI33_CTRL[14..0]
JTAG[4..0]
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PC
I33_
AD
4
PC
I33_
AD
6
PC
I33_
TRD
Y#
PC
I33_
CT
RL2
PC
I33_
IRD
Y#
PC
I33_
CT
RL3
PC
I33_
AD
19
PC
I33_
AD
30
PC
I33_
AD
9
PC
I33_
PE
RR
#P
CI3
3_C
TR
L7
PC
I33_
AD
31
PC
I33_
AD
0
PC
I33_
AD
7P
CI3
3_A
D8
PC
I33_
AD
10
PC
I33_
AD
27
PC
I33_
CLK
PC
I33_
CT
RL0
PC
I33_
AD
15
PC
I33_
AD
18P
CI3
3_A
D17
RE
SE
T#1
PC
I33_
AD
24
PC
I33_
AD
29
PC
I33_
INT#
PC
I33_
CT
RL1
4
PC
I33_
AD
16
PC
I33_
FRA
ME
#P
CI3
3_C
TR
L1
PC
I33_
AD
25
PC
I33_
AD
12
PC
I33_
AD
2
PC
I33_
AD
21
PC
I33_
DE
VS
EL#
PC
I33_
CT
RL5
PC
I33_
AD
11
PC
I33_
IDS
EL
PC
I33_
CT
RL9
PC
I33_
C/B
E#1
PC
I33_
CT
RL1
1
PC
I33_
AD
3
PC
I33_
AD
1
PC
I33_
C/B
E#0
PC
I33_
CT
RL1
0
PC
I33_
AD
20
PC
I33_
AD
14
PC
I33_
AD
5
PC
I33_
PA
RP
CI3
3_C
TR
L6
PC
I33_
SE
RR
#P
CI3
3_C
TR
L8
PC
I33_
AD
28
PC
I33_
STO
P#
PC
I33_
CT
RL4
PC
I33_
AD
26
PC
I33_
AD
22
PC
I33_
AD
13
PC
I33_
AD
23
PC
I33_
C/B
E#3
PC
I33_
CT
RL1
3P
CI3
3_C
/BE
#2P
CI3
3_C
TR
L12
PCI33_AD[31..0]
PCI33_CTRL[14..0]
RE
SE
T#0
MD
Q0
MD
Q1
MD
Q2
MD
Q3
MD
Q4
MD
Q5
MD
Q6
MD
Q7
MD
Q8
MD
Q9
MD
Q10
MD
Q11
MD
Q12
MD
Q13
MD
Q14
MD
Q15
MD
Q16
MD
Q17
MD
Q18
MD
Q19
MD
Q20
MD
Q21
MD
Q22
MD
Q23
MD
Q24
MD
Q25
MD
Q26
MD
Q27
MD
Q28
MD
Q29
MD
Q30
MD
Q31
MD
Q32
MD
Q33
MD
Q34
MD
Q35
MD
Q36
MD
Q37
MD
Q38
MD
Q39
MD
Q40
MD
Q41
MD
Q42
MD
Q43
MD
Q44
MD
Q45
MD
Q46
MD
Q47
MD
Q48
MD
Q49
MD
Q50
MD
Q51
MD
Q52
MD
Q53
MD
Q54
MD
Q55
MD
Q56
MD
Q57
MD
Q58
MD
Q59
MD
Q60
MD
Q61
MD
Q62
MD
Q63
MD
QS
0M
DQ
S1
MD
QS
2M
DQ
S3
MD
QS
4M
DQ
S5
MD
QS
6M
DQ
S7
MB
A1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA
10M
A11
MA
12M
A13
RE
SE
T#2
CK
E_S
TAR
T
SD
_VR
EF0
SD
_VR
EF1
SD
_VR
EF2
MD
M4
MD
M5
MD
M6
MD
M7
MC
K_0
MC
K_1
XM
CK_
0X
MC
K_1
LOO
P_0
LOO
P_1
LOO
PI_
1
MR
AS
MC
AS
MW
EM
CK
EM
CS
MB
A0
MD
M0
MD
M1
MD
M2
MD
M3
MD
Q62
SD
_D62
MD
Q59
SD
_D59
MD
Q58
SD
_D58
MD
Q56
SD
_D56
SD
_DQ
S6
MD
QS
6M
DM
6S
D_D
QM
6
MD
Q54
SD
_D54
MD
Q51
SD
_D51
SD
_DQ
M4
MD
M4
MD
Q47
SD
_D47
MD
Q46
SD
_D46
MD
Q44
SD
_D44
MD
Q39
SD
_D39
MD
Q37
SD
_D37
MD
Q34
SD
_D34
MD
Q33
SD
_D33
MD
Q28
SD
_D28
MD
Q26
SD
_D26
SD
_DQ
M3
MD
M3
MD
Q24
SD
_D24
MD
Q20
SD
_D20
MD
Q19
SD
_D19
MD
Q18
SD
_D18
MD
Q12
SD
_D12
MD
Q11
SD
_D11
MD
Q9
SD
_D9
MD
Q8
SD
_D8
MD
QS
1S
D_D
QS
1
MA
10M
BA
1M
BA
0M
A13
MA
12M
A11
MA9
MA8
MA7
MA6
MA5
MA4
SD
_DQ
M7
SD
_DQ
M6
SD
_DQ
M4
MD
Q41
SD
_D41
MD
Q40
SD
_D40
MD
QS
5S
D_D
QS
5M
DM
5S
D_D
QM
5
SD
_DQ
M1
SD
_DQ
M3
SD
_DQ
M0
SD
_DQ
M2
MD
M2
SD
_DQ
S7
MD
QS
7S
D_D
QS
6
SD
_DQ
S5
SD
_DQ
S4
MD
Q48
SD
_D48
MD
Q49
SD
_D49
SD
_DQ
S2
SD
_DQ
S3
SD
_DQ
S1
MD
QS
0S
D_D
QS
0M
DQ
7S
D_D
7
SD_DQM[7..0]
SD_DQS[7..0]
CM
_VO
0_V
SY
NC
CM
_V
O0_
CS
YN
CC
M_V
O0_
DE
CM
_VO
0_G
V
VO
0_D
CLK
IC
M_
VO
0_H
SY
NC
CM
_VO
1_B
4C
M_V
O1_
B5
CM
_VO
1_B
6C
M_V
O1_
B7
CM
_VO
1_B
0C
M_V
O1_
B1
CM
_VO
1_B
2C
M_V
O1_
B3
I2C
_SD
AI2
C_S
CL
CLK
SE
L1C
LKS
EL0 CLKSEL0
CLKSEL1
CARMINE_CLK_EN
CM
_VI1
_656
_D4
CM
_VI1
_656
_D5
CM
_VI1
_656
_D6
CM
_VI1
_656
_D7
CM
_VI1
_656
_D0
CM
_VI1
_656
_D1
CM
_VI1
_656
_D2
CM
_VI1
_656
_D3
CM
_VI1
_CLK
CM
_VI0
_CLK
CA
RM
INE
_MO
DE
1C
AR
MIN
E_M
OD
E0
JTA
G_T
RS
T#
JTA
G_T
DI
JTA
G_T
MS
JTA
G_T
CK
JTA
G_T
DO
JTAG_TDIJTAG_TMSJTAG_TCK
I2C_SDAI2C_SCLCKE_STARTCARMINE_CLK_EN
CM
_VO
1_R
4C
M_V
O1_
R5
CM
_VO
1_R
6C
M_V
O1_
R7
CM
_VO
1_R
1C
M_V
O1_
R2
CM
_VO
1_R
3
CM
_VO
1_R
0
CM
_VO
1_G
4C
M_V
O1_
G5
CM
_VO
1_G
6C
M_V
O1_
G7
CM
_VO
1_G
1C
M_V
O1_
G2
CM
_VO
1_G
3
CM
_VO
1_G
0
CM
_VO
0_B
4C
M_V
O0_
B5
CM
_VO
0_B
6C
M_V
O0_
B7
CM
_VO
0_B
1C
M_V
O0_
B2
CM
_VO
0_B
3
CM
_VO
0_B
0
CM
_VO
0_G
4C
M_V
O0_
G5
CM
_VO
0_G
6C
M_V
O0_
G7
CM
_VO
0_G
1C
M_V
O0_
G2
CM
_VO
0_G
3
CM
_VO
0_G
0
CM
_VO
0_R
4C
M_V
O0_
R5
CM
_VO
0_R
6C
M_V
O0_
R7
CM
_VO
0_R
1C
M_V
O0_
R2
CM
_VO
0_R
3
CM
_VO
0_R
0
CM
_VO
1_V
SY
NC
CM
_V
O1_
CS
YN
CC
M_V
O1_
DE
CM
_VO
1_G
V
VO
1_D
CLK
IC
M_
VO
1_H
SY
NC
VO0_SYNC[4..0]
CM
_V
O0_
HS
YN
C
VO
0_R
GB
10V
O0_
G2
VO
0_R
GB
15V
O0_
G7
VO
0_R
GB
2V
O0_
B2
VO
0_R
GB
3V
O0_
B3
VO
0_R
GB
4V
O0_
B4
VO
0_R
GB
5V
O0_
B5
VO
0_S
YN
C3
VO
0_C
SY
NC
VO
0_S
YN
C2
VO
0_D
E
VO
0_R
GB
8V
O0_
G0
VO
0_R
GB
9V
O0_
G1
VO
0_R
GB
11V
O0_
G3
VO
0_R
GB
12V
O0_
G4
VO
0_R
GB
13V
O0_
G5
VO
0_R
GB
14V
O0_
G6
VO
0_R
GB
0V
O0_
B0
VO
0_R
GB
1V
O0_
B1
VO
0_R
GB
16V
O0_
R0
VO
0_R
GB
17V
O0_
R1
VO
0_R
GB
20V
O0_
R4
VO
0_R
GB
21V
O0_
R5
VO
0_R
GB
18V
O0_
R2
VO
0_R
GB
19V
O0_
R3
VO
0_R
GB
22V
O0_
R6
VO
0_R
GB
23V
O0_
R7
VO
1_B
4V
O1_
RG
B4
VO
1_B
5V
O1_
RG
B5
VO
1_C
SY
NC
VO
1_S
YN
C3
VO
1_D
EV
O1
_SY
NC
2
VO
1_G
4V
O1_
RG
B12
VO
1_G
5V
O1_
RG
B13
VO
1_B
0V
O1_
RG
B0
VO
1_B
3V
O1_
RG
B3
VO
1_G
6V
O1_
RG
B14
VO
1_G
7V
O1_
RG
B15
VO
1_B
1V
O1_
RG
B1
VO
1_B
2V
O1_
RG
B2
VO
1_R
4V
O1_
RG
B20
VO
1_R
5V
O1_
RG
B21
VO
1_G
0V
O1_
RG
B8
VO
1_G
1V
O1_
RG
B9
VO
1_R
0V
O1_
RG
B16
VO
1_R
1V
O1_
RG
B17
VO
1_R
2V
O1_
RG
B18
VO
1_R
3V
O1_
RG
B19
VO
1_R
6V
O1_
RG
B22
VO
1_R
7V
O1_
RG
B23
VO
1_G
2V
O1_
RG
B10
VO
1_G
3V
O1_
RG
B11
VO0_RGB[23..0]
CM
_VO
0_G
2C
M_V
O0_
G7
CM
_VO
0_B
2C
M_V
O0_
B3
CM
_VO
0_B
4C
M_V
O0_
B5
CM
_V
O0_
CS
YN
CC
M_V
O0_
DE
CM
_VO
0_G
0C
M_V
O0_
G1
CM
_VO
0_G
3C
M_V
O0_
G4
CM
_VO
0_G
5C
M_V
O0_
G6
CM
_VO
0_B
0C
M_V
O0_
B1
CM
_VO
0_R
0C
M_V
O0_
R1
CM
_VO
0_R
4C
M_V
O0_
R5
CM
_VO
0_R
2C
M_V
O0_
R3
CM
_VO
0_R
6C
M_V
O0_
R7
CM
_VO
1_G
7C
M_V
O1_
B1
CM
_VO
1_B
2
CM
_VO
1_B
4C
M_V
O1_
B5
CM
_V
O1_
CS
YN
CC
M_V
O1_
DE
CM
_VO
1_G
4C
M_V
O1_
G5
CM
_VO
1_B
0C
M_V
O1_
B3
CM
_VO
1_G
6
CM
_VO
1_R
7C
M_V
O1_
G2
CM
_VO
1_G
3
CM
_VO
1_R
4C
M_V
O1_
R5
CM
_VO
1_G
0C
M_V
O1_
G1
CM
_VO
1_R
0C
M_V
O1_
R1
CM
_VO
1_R
2C
M_V
O1_
R3
CM
_VO
1_R
6
I2C[1..0]
I2C0 I2C_SCLI2C1 I2C_SDA
CONFIG[4..0]
RESET#[2..0]
RESET#0RESET#1RESET#2
MC
K_0
XM
CK_
0
MC
K_1
XM
CK_
1
MC
SM
RA
SM
CA
SM
WE
MC
KE
JTAG3 JTAG_TMS
JTAG1 JTAG_TDO
CONFIG2 CARMINE_MODE1
CONFIG4 CLKSEL1
JTAG4 JTAG_TCK
JTAG_TRST#
CONFIG0 JTAG_TRST#
JTAG2 JTAG_TDI
JTAG0 JTAG_TRST#
CONFIG1 CARMINE_MODE0
CONFIG3 CLKSEL0
JTAG[4..0]
CM_VI1_656_D[7..0]
CM
_VI1
_656
_D0
CM
_VI1
_656
_D1
CM
_VI1
_656
_D2
CM
_VI1
_656
_D3
CM
_VI1
_656
_D4
CM
_VI1
_656
_D5
CM
_VI1
_656
_D6
CM
_VI1
_656
_D7
CM_VI1_CLK
CM
_VI0
_RG
B0
CM
_VI0
_B0
CM
_VI0
_RG
B1
CM
_VI0
_B1
CM
_VI0
_RG
B2
CM
_VI0
_B2
CM
_VI0
_RG
B3
CM
_VI0
_B3
CM
_VI0
_RG
B4
CM
_VI0
_B4
CM
_VI0
_RG
B5
CM
_VI0
_B5
CM
_VI0
_RG
B6
CM
_VI0
_G0
CM
_VI0
_RG
B7
CM
_VI0
_G1
CM
_VI0
_RG
B8
CM
_VI0
_G2
CM
_VI0
_RG
B9
CM
_VI0
_G3
CM
_VI0
_RG
B10
CM
_VI0
_G4
CM
_VI0
_RG
B11
CM
_VI0
_G5
CM
_VI0
_RG
B12
CM
_VI0
_R0
CM
_VI0
_RG
B13
CM
_VI0
_R1
CM
_VI0
_RG
B14
CM
_VI0
_R2
CM
_VI0
_RG
B15
CM
_VI0
_R3
CM
_VI0
_RG
B16
CM
_VI0
_R4
CM
_VI0
_RG
B17
CM
_VI0
_R5
CM
_VI0
_SY
NC
0C
M_V
I0_C
LKC
M_V
I0_S
YN
C1
CM
_VI0
_HS
CM
_VI0
_SY
NC
2C
M_V
I0_V
SC
M_V
I0_S
YN
C3
CM
_VI0
_FID
CM_VI0_SYNC[3..0]
CM_VI0_RGB[17..0]
VO0_SYNC_EXT[2..0]
VO
1_S
YN
C_E
XT2
VO
1_E
XT_
VS
YN
C
VO1_SYNC_EXT[2..0]
VO
1_S
YN
C_E
XT1
VO
1_E
XT_
HS
YN
CV
O1_
SY
NC
_EX
T0V
O1_
DC
LKI
VO
0_S
YN
C_E
XT0
VO
0_D
CLK
IV
O0_
SY
NC
_EX
T1V
O0_
EX
T_H
SY
NC
VO
0_S
YN
C_E
XT2
VO
0_E
XT_
VS
YN
C
VO0_EXT_HSYNC
VO0_EXT_VSYNC
VO1_EXT_HSYNC
VO1_EXT_VSYNC
CM_VO0_HSYNC
CM_VO0_VSYNC
CM_VO1_HSYNC
CM_VO1_VSYNC
VO1_SYNC[4..0]
CM
_VO
1_B
7C
M_V
O1_
B6
CM
_VO
1_G
V
CM
_VO
0_G
V
VO
1_S
YN
C3
VO
1_S
YN
C2
VO
1_S
YN
C0
VO
1_H
SY
NC
VO
1_S
YN
C4
VO
1_G
V
VO
1_S
YN
C1
VO
1_V
SY
NC
VO
0_S
YN
C4
VO
0_G
V
VO
0_S
YN
C3
VO
0_S
YN
C2
VO
0_H
SY
NC
VO
0_S
YN
C0
VO
0_V
SY
NC
VO
0_S
YN
C1CM_VO1_DCLKO CM_VO0_DCLKO
CM_VO0_DCLKO
VO0_CLK[4..0]
VO0_CLK4
VO0_CLK1
VO0_CLK3
VO0_CLK0
CM_VO1_DCLKO
VO1_CLK[4..0]
VO1_CLK0
VO1_CLK1
VO1_CLK2
VO1_CLK3
VO1_CLK4
VO0_CLK2
CM
_VI0
_B5
CM
_VI0
_B1
CM
_VI0
_B2
CM
_VI0
_B3
CM
_VI0
_B4
CM
_VI0
_B0
CM
_VI0
_G4
CM
_VI0
_G5
CM
_VI0
_G0
CM
_VI0
_G1
CM
_VI0
_G2
CM
_VI0
_G3
CM
_VI0
_R3
CM
_VI0
_R5
CM
_VI0
_R4
CM
_VI0
_R0
CM
_VI0
_R1
CM
_VI0
_R2
CM
_VI0
_FID
CM
_VI0
_HS
CM
_VI0
_VS
SD_VREF3SD_VREF2
SD_VREF0 SD_VREF1
SD
_DQ
S2
MD
QS
2
SD
_DQ
M7
MD
M7
SD
_DQ
M0
MD
M0
CARMINE_MODE0CARMINE_MODE1
VO
1_B
6V
O1_
B7
CM
_VO
0_V
SY
NC
VO
0_B
7V
O0_
B6
CM
_VO
0_B
7C
M_V
O0_
B6
VO
0_R
GB
7V
O0_
B7
VO
0_R
GB
6V
O0_
B6
CM
_VO
1_V
SY
NC
CM
_V
O1_
HS
YN
C
VO
1_R
GB
7V
O1_
B7
VO
1_R
GB
6V
O1_
B6
VO1_RGB[23..0]
SD
_D30
MD
Q30
SD
_DQ
M1
MD
M1
SD
_D14
MD
Q14
SD
_D23
MD
Q23
SD
_D61
MD
Q61
SD
_D32
MD
Q32
SD
_D2
MD
Q2
SD
_D6
SD
_D7
SD
_D5
MD
Q5
SD
_D3
MD
Q3
SD
_D43
MD
Q43
SD
_D36
MD
Q36
SD
_D21
MD
Q21
SD
_D15
MD
Q15
SD
_D17
MD
Q17
SD
_D41
SD_D[63..0]
SD
_D13
MD
Q13
SD
_D27
MD
Q27
SD
_D60
MD
Q60
SD
_D63
MD
Q63
SD
_D48
SD
_D31
SD
_D49
SD
_D35
MD
Q35
SD
_D25
MD
Q25
SD
_D30
SD
_D16
MD
Q16
SD
_D40
SD
_D10
MD
Q10
SD
_AD
14
SD
_AD
6
SD_AD[15..0]
SD
_AD
8
MA3
SD
_AD
13
SD
_AD
5
SD
_AD
15
SD
_AD
11
SD
_AD
1
SD
_AD
7
SD
_AD
4
SD
_AD
2
SD
_AD
9
SD
_AD
12
SD
_AD
10
SD
_AD
0M
A0
SD
_AD
3M
A2M
A1
SD
_D57
MD
Q57
SD
_D55
MD
Q55
SD
_D50
MD
Q50
SD
_D52
MD
Q52
SD
_D53
MD
Q53
SD
_DQ
S4
MD
QS
4
SD
_D42
MD
Q42
SD
_D45
MD
Q45
SD
_D38
MD
Q38
SD
_D29
MD
Q29
SD
_DQ
S3
MD
QS
3
SD
_D22
MD
Q22
SD
_D4
MD
Q4
SD
_D0
MD
Q0
SD
_D1
MD
Q1
SD
_D6
MD
Q6
SD
_D31
MD
Q31
SD
_CTR
L2D
CK
1
SD
_CTR
L12
LOO
PI_
1D
LOO
PI_
1
SD
_CTR
L0D
CK
0
SD
_CTR
L8D
CA
S#
SD
_CTR
L10
LOO
PI_
0D
LOO
PI_
0
SD
_CTR
L4D
CS
#0
SD
_CTR
L11
DLO
OP
O_1
LOO
P_1
SD
_CTR
L6D
WE
#
SD
_CTR
L3D
CK
1#
LOO
PI_
0
SD
_CTR
L1D
CK
0#
SD
_CTR
L7D
RA
S#
SD_CTRL[12..0]
DC
KE
SD
_CTR
L5
SD
_CTR
L9D
LOO
PO
_0LO
OP
_0
SD
_VR
EF3
PCI33_AD[31..0]
PCI33_CTRL[14..0]
SD_D[63..0]
SD_AD[15..0]
SD_DQM[7..0]
SD_DQS[7..0]
JTAG[4..0]
VO0_RGB[23..0]
VO1_RGB[23..0]
I2C[1..0]
CONFIG[4..0]
RESET#[2..0]
SD_CTRL[12..0]CM_VI0_SYNC[3..0]
CM_VI0_RGB[17..0]
CM_VI1_CLK
CM_VI1_656_D[7..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
VO0_SYNC[4..0]
VO1_SYNC[4..0]
VO1_CLK[4..0]
VO0_CLK[4..0]
VCC33
VCC33
VCC25
VCC33
VCC33
VCC25
VCC25 VCC25
VT_DRAM
VT_DRAM
Title
Size Document Number R ev
Date: Sheet o f
30100-012 PA11
Fujitsu Carmine Evaluation Board: Carmine Subsystem: Carmine
© mycable GmbHBoeker Stieg 43D-24613 AukrugGermanywww.mycable.de
A1
12 15Monday, November 21, 2005
Place all DDR damping resistorsaccording to Carmine design guide!
Consider DDR SDRAM layoutrules from Carmine design guide!
PCI_CTRL0 CLKPCI_CTRL1 FRAME#PCI_CTRL2 TRDY#PCI_CTRL3 IRDY#PCI_CTRL4 STOP#PCI_CTRL5 DEVSEL#PCI_CTRL6 PARPCI_CTRL7 PERR#PCI_CTRL8 SERR#PCI_CTRL9 IDSELPCI_CTRL10 C/BE0#PCI_CTRL11 C/BE1#PCI_CTRL12 C/BE2#PCI_CTRL13 C/BE3#PCI_CTRL14 INT#
PCI Signal Assignment
Place R820 directlyto Y800 pin 3!
Place R815 directlyto U800 pin D7!
Kee
p C
arm
ine
cloc
k si
gnal
as s
hort
as
poss
ible
!
NP
Plac
e al
l DD
R V
ref n
etw
orks
dire
ctly
to th
e co
rres
pond
ing
Car
min
e pi
ns!
Place R823 - R826 close to thecorresponding Carmine pins!
Place R829 - R833 close to thecorresponding U801 pins!
Place R827, R828 directly to thecorresponding Carmine pins!
Place R834 - R837 close to thecorresponding U802 pins! NP
NPClock skew adjustment
Clock skew adjustment
NPNP
NP NP
R836 33R
R81
90R
C804
100n
RN827
4k7x4
1234 5
678
RN
835
33R
x4
1 2 3 45678
R829 33R
R8011k5
C826100n
R86
00R
R80
60R
R826 0R
C82810u
L800
BLM18PG600SN1
R834 33R
C822
100n
C801
100n
RN
829
33R
x4
1 2 3 45678
RN
800
0Rx4
1 2 3 45678
R86
10R
R838 33R
R81
80R
C83110p
RN
830
33R
x4
1 2 3 45678
C829100n
R82833R
R8141k5
R8001k5
R81
60R
RN
832
33R
x4
1 2 3 45678
R82733R
C810
100n
PCI-InterfaceMemory-Interface
Carmine Graphics Processor
Video-Out 1Video-Capture InterfaceI2CCLOCKTEST Video-Out 0
U800AMB86297
AD
00C
11A
D01
B11
AD
02A
11A
D03
C12
AD
04B
12A
D05
A12
AD
06C
13A
D07
B13
AD
08C
14A
D09
B14
AD
10A
14A
D11
C15
AD
12B
15A
D13
A15
AD
14C
16A
D15
B16
AD
16C
19A
D17
B19
AD
18A
19A
D19
C20
AD
20B
20A
D21
A20
AD
22C
21A
D23
B21
AD
24A
21A
D25
C22
AD
26B
22A
D27
A22
AD
28C
23A
D29
B23
AD
30A
23A
D31
B24
CB
E0
A13
CB
E1
D15
CB
E2
D22
CB
E3
A24
PA
RD
16FR
AM
ED
19TR
DY
C18
IRD
YB
18S
TOP
C17
DE
VS
EL
D18
IDS
EL
B10
PE
RR
D17
SE
RR
A16
PC
LKA
18X
RS
TC
8X
INT
D11
MD
Q0
M26
MD
Q1
M25
MD
Q2
N26
MD
Q3
N25
MD
Q4
P26
MD
Q5
P25
MD
Q6
R26
MD
Q7
R25
MD
Q8
H25
MD
Q9
H26
MD
Q10
G25
MD
Q11
G26
MD
Q12
F25
MD
Q13
F26
MD
Q14
E25
MD
Q15
E26
MD
Q16
G24
MD
Q17
G23
MD
Q18
H24
MD
Q19
H23
MD
Q20
J24
MD
Q21
J23
MD
Q22
K24
MD
Q23
K23
MD
Q24
U23
MD
Q25
U24
MD
Q26
T23
MD
Q27
T24
MD
Q28
R23
MD
Q29
R24
MD
Q30
P23
MD
Q31
P24
MD
Q32
AF7
MD
Q33
AE
7M
DQ
34A
F8M
DQ
35A
E8
MD
Q36
AF9
MD
Q37
AE
9M
DQ
38A
F10
MD
Q39
AE
10M
DQ
40A
E17
MD
Q41
AF1
7M
DQ
42A
E16
MD
Q43
AF1
6M
DQ
44A
E15
MD
Q45
AF1
5M
DQ
46A
E14
MD
Q47
AF1
4M
DQ
48A
D12
MD
Q49
AC
12M
DQ
50A
D13
MD
Q51
AC
13M
DQ
52A
D14
MD
Q53
AC
14M
DQ
54A
D15
MD
Q55
AC
15M
DQ
56A
C8
MD
Q57
AD
8M
DQ
58A
C7
MD
Q59
AD
7M
DQ
60A
C6
MD
Q61
AD
6M
DQ
62A
C5
MD
Q63
AD
5
MD
QS
0T2
6M
DQ
S1
J26
MD
QS
2L2
4M
DQ
S3
V24
MD
QS
4A
F11
MD
QS
5A
F18
MD
QS
6A
D16
MD
QS
7A
D9
MD
M0
T25
MD
M1
J25
MD
M2
L23
MD
M3
V23
MD
M4
AE
11M
DM
5A
E18
MD
M6
AC
16M
DM
7A
C9
MC
K_0
AB
26M
CK
_1A
F22
XM
CK
_0A
A26
XM
CK
_1A
F21
LOO
P_0
Y26
LOO
P_1
AF2
0
LOO
PI_
0W
26LO
OP
I_1
AF1
9
MR
AS
AD
20M
CA
SA
C19
MW
EA
D19
MC
KE
Y24
MC
SA
C20
MB
A0
AD
21M
BA
1A
C21
MA
0A
C22
MA
1A
E23
MA
2A
D23
MA
3A
E24
MA
4A
C24
MA
5A
C25
MA
6A
B23
MA
7A
B24
MA
8A
A23
MA
9A
A24
MA
10A
D22
MA
11Y
23M
A12
W23
MA
13W
24
DLL
_RS
TC
26C
KE
_STA
RT
C25
VR
EF0
AA
10V
RE
F1A
A17
VR
EF2
U21
VR
EF3
K21
SD
AD
26S
CL
D25
CLK
A8
PLL
RE
SE
TA
10C
LKS
EL0
D10
CLK
SE
L1C
10
TCK