functional vs. structural • definition and types • path ...fglima/projeto/aula5t.pdf · •...
TRANSCRIPT
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Lecture 5 – Test Pattern Generation
• Functional vs. Structural• Definition and Types• Path sensitization method• ATPG for Sequential
Circuits
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Functional vs. Structural ATPG
Functional ATPG • generate complete set of tests for circuit input-output combinations• 129 inputs, 65 outputs:2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912patterns
• Using 1 GHz ATE, would take 2.15 x 1022 years
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Sum and Carry Circuits
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• Structural test:– No redundant adder hardware, 64 bit slices– Each with 27 faults (using fault equivalence)– At most 64 x 27 = 1728 faults (tests)– Takes 0.000001728 s on 1 GHz ATE
• Designer gives small set of functional tests –augment with structural tests to boost coverage to 98+ %
Functional vs. Structural (Cont’d)
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Definition of Automatic Test-Pattern Generator
• Operations on digital hardware:– Inject fault into circuit modeled in computer– Use various ways to activate and propagate fault effect through
hardware to circuit output– Output flips from expected to faulty signal
• Test generation cost– fault-dependent or not
• Quality of generated test– fault coverage (fault simulation)
• Test application cost– test time, memory requirements
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TG Types
• Exhaustive– cheap generation, high FC, expensive application
• Fault-Oriented (deterministic)– expensive generation, possibly high FC, cheaper
application
• Random (pseudo-random)– cheap generation, low FC, + - expensive application
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Exhaustive Algorithm
• For n-input circuit, generate all 2n input patterns
• Unfeasible, unless circuit is partitioned into cones of logic, with 15 inputs– Perform exhaustive ATPG for each cone– Misses faults that require specific activation
patterns for multiple cones to be tested
≤
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Pseudo-Exhaustive Method
Partition large circuit into fanin conesBacktrace from each PO to PIs influencing itTest fanin cones in parallel
Reduced # of tests from 28 = 256 to 25 x 2 = 64Incomplete fault coverage
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Pseudo-Exhaustive Pattern Generation
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Random-Pattern GenerationRandom-Pattern Generation
• Flow chart for method
• Use to get tests for 60-80% of faults, then switch to deterministic ATPG for rest
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Random Pattern Testing
Bottom:Random-PatternResistantcircuit
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Path Sensitization MethodPath Sensitization Method
1 Fault Sensitization (activation)
2 Fault Propagation
3 Line Justification
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Path Sensitization Method
• Fault l s-a-v
• Activation– set l to v
• Propagation– find a path from l to a primary output that keeps
faulty value
• Justification– set the primary inputs to activate the fault
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Composite Logic Values
• consider line value for original AND faulty circuit
• v/vf = original/faulty
• Symbols D and D (Roth, 1966)
• D = 1/0
• D = 0/1
• 0 = 0/0
• 1 = 1/1
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Operations on Composite Values
• D + 0 = 0/1 + 0/0 = 0/1 = D
V/Vf 0/0 0 1/1 1 1/0 D 0/1 D
AND 0 1 D D X
0 0 0 0 0 0 1 0 1 D D XD 0 D D 0 X
D 0 D 0 D X
X 0 X X X x
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Path Sensitization MethodPath Sensitization Method
1
• Propagation
D
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Path Sensitization MethodPath Sensitization Method
Propagation: try path f – h – k – L
1D
D
DD
0
1
1
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Path Sensitization MethodPath Sensitization Method
Propagation: try path f – h – k – L
1D
D
DD
0
1
1
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Path Sensitization MethodPath Sensitization Method
Justification: Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i
10
D
D1
1
1DD
D
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Path Sensitization MethodPath Sensitization Method
Justification: Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i
1D
D
D1
1
DD1
1
1
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Path Sensitization MethodPath Sensitization Method
Backtracking!
1D
D
D1
1
DD1
1
1X X
X XXX
XX
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Try other propagation: path g – i – j – k – L
0
D D D
1 DD
11
Path Sensitization Method
D
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Try other propagation: path g – i – j – k – L
0
D D D
1 DD
11
Path Sensitization Method
D
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Try other propagation: path g – i – j – k – L
0
D D D
1 DD
1
0
1
Path Sensitization Method
D
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Major Combinational Automatic Test-Pattern Generation Algorithms
• D-Algorithm (Roth) -- 1966
• PODEM (Goel) -- 1981
• FAN (Fujiwara and Shimono) --1983
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Sequential Circuit ATPGTime-Frame Expansion
• Problem of sequential circuit ATPG
• Time-frame expansion
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Example of Sequential Circuit
CB
MB
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Sequential Circuits• A sequential circuit has memory in addition to
combinational logic.
• Test for a fault in a sequential circuit is a sequence of vectors, which
• Initializes the circuit to a known state• Activates the fault, and• Propagates the fault effect to a primary output
• Methods of sequential circuit ATPG• Time-frame expansion methods• Simulation-based methods
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Extended D-Algorithm1. Pick up a target fault f.
2. Create a copy of a combinational logic, set it time-frame 0.
3. Generate a test for f using D-algorithm for time-frame 0.
4. When the fault effect is propagate to the DFFs, continue fault propagation in the next time-frame.
5. When there are values required in the DFFs, continue the justification in the previous time-frame.
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Example for Extended D- Algorithm
st_1
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Example: Step 1
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Example: Step 2
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Example: Step 3
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SummarySummary• Hierarchical ATPG -- 9 Times speedup (Min)
– Handles adders, comparators, MUXes
• Advances over D-algorithm
• Results of 40 years research – mature – methods:– Path sensitization– Simulation-based – Boolean satisfiability and neural networks – Genetic algorithms