future of teaching vhdl
DESCRIPTION
What if students would know all of the VHDL syntax? What if VHDL tools would not freak out about a simple error in the code? Sigasi makes this possible!TRANSCRIPT
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The future of teaching VHDL
![Page 2: Future of teaching VHDL](https://reader034.vdocuments.net/reader034/viewer/2022051816/54627785af7959477b8b4f3d/html5/thumbnails/2.jpg)
The future of teaching VHDL
What if students would...
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The future of teaching VHDL
know all packages
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The future of teaching VHDL
know the syntax
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The future of teaching VHDL
know the syntax
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The future of teaching VHDL
know all declarations
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The future of teaching VHDL
know record fields
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The future of teaching VHDL
know record fields
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The future of teaching VHDL
What if tools ...
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The future of teaching VHDL
for one single error
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The future of teaching VHDL 11
would not freak out
Model Technology ModelSim ALTERA vcom 6.4a Compiler 2008.08 Oct 22 2008-- Loading package standard-- Loading package std_logic_1164-- Compiling package p** Error: p.vhd(6): near ";": expecting "RECORD"** Error: p.vhd(7): (vcom-1136) Unknown identifier "c1".** Error: p.vhd(7): Aggregate expression cannot be scalar type (error).** Error: p.vhd(9): Invalid expanded name prefix (selected name).** Error: p.vhd(11): VHDL Compiler exiting
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The future of teaching VHDL 12
but yieldone single message
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The future of teaching VHDL 13
and 4 messages for 4 errors
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The future of teaching VHDL
Wouldn’t that be great?
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The future of teaching VHDL
Students could
• write correct code,
• get immediate feedback,
• with sensible error messages,
• feel the code,
• concentrate on concepts, not syntax.
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The future of teaching VHDL
Teachers could
• teach engineering, not languages,
• not waste time on tooling,
• deliver even better graduates.
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The future of teaching VHDL 17
The future is now.and it’s free too!