vhdl 6 synthesis with vhdl leonardo

8/8/2019 VHDL 6 Synthesis With VHDL Leonardo

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Automated Synthesis from

HDL modelsLeonardo (Mentor Graphics), Design Compiler (Synopsys)


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ASIC Design Flow

BehavioralModel

VHDL/Verilog

Gate-Level

Netlist

Transistor-LevelNetlist

PhysicalLayout

Map/Place/Route

DFT/BIST& ATPG

VerifyFunction

Verify

Function

Verify Function& Timing

VerifyTiming

DRC & LVSVerification

IC Mask Data/FPGA Configuration File

Standard Cell IC& FPGA/CPLD

Synthesis

Test vectors Full-custom IC


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Automated synthesis

Leonardo Spectrum,Synopsys Design Compiler

HDL Behavioral/RTL Models

FPGA

ASIC

TechnologySynthesisLibraries

Technology-SpecificNetlist

DesignConstraints

VHDL, Verilog, SDF,EDIF, XNF

Leonardo:Level 1FPGALevel 2FPGA + TimingLevel 3FPGA + ASIC

or ASIC only


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Leonardo ASIC synthesis flow


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Synthesis design flow


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Leonardo synthesis procedure

1. Invoke leonardo2. Select & load a technology library (ASIC or FPGA)

ASIC > ADK > TSMC 0.35 micron

3. Read input VHDL/Verilog file(s): count4.vhd

4. Enter any constraints (clock freq, delays, etc.)5. Optimize for area/delay/effort level

6. Write output file(s) count4_0.vhd - VHDL netlist

count4.v -Verilog netlist(for IC layout)

count4.sdf - Standard delay format file (for timing)

count4.edf - EDIF netlist(for Xilinx/Altera FPGA)
http://../nelsovp/Desktop/Mentor%20Presentation/count4_vhd.pdfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4_0.vhdhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.vhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.sdfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.edfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.edfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.edfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.sdfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.sdfhttp://../nelsovp/Desktop/Mentor%20Presentation/count4.vhttp://../nelsovp/Desktop/Mentor%20Presentation/count4_0.vhdhttp://../nelsovp/Desktop/Mentor%20Presentation/count4_vhd.pdf


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Synthesis example

Load technology library:tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)

Load design file: modulo7.vhd

Specify constraints: clock freq, delays, etc.

Optimization: effort, performance vs. area

Write synthesized netlist output(s):

modulo7_0.vhd : VHDL netlist for ModelSim & DFT

modulo7.v : Verilog netlist for import into DA-IC

modulo7.sdf: For ModelSim to study timing

modulo7.edf: EDIF netlist for 3rd party tools

modulo7.xnf: Xilinx netlist for Xilinx ISE


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Behavioral model to be synthesized-- modulo-7 counter with asynchronous reset and synchronous load/count

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;entity modulo7 isport( count, load, reset, clk: in std_logic;

I: in unsigned(2 downto 0); -- unsigned form ofstd_logic_vector

Q: out unsigned(2 downto 0)); -- defined in IEEE numeric_std package

end modulo7;

architecture Behave of modulo7 is

signal Q_s: unsigned(2 downto 0);

begin

process (reset,clk) begin

if (reset='0') then Q_s


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Synthesized netlist (1)-- Definition of modulo7

-- Thu Sep 21 10:48:09 2006-- LeonardoSpectrum Level 3, 2005a.82

--

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity modulo7 is

port (

count : IN std_logic ;

load : IN std_logic ;

reset : IN std_logic ;

clk : IN std_logic ;

I : IN std_logic_vector (2 DOWNTO 0) ;

Q : OUT std_logic_vector (2 DOWNTO 0)) ;

end modulo7 ;


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Synthesized netlist (2)

architecture Behave of modulo7 issignal Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, NOT_reset, nx4, nx14, nx22,

nx48, nx60, nx169, nx179, nx189, nx202, nx204, nx208, nx212, nx214,nx218, nx225, nx228, nx230: std_logic ;

beginQ(2) Q_0_EXMPLR, S0=>nx225);ix15 : oai22 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>nx202, B0=>nx230,

B1=>count);ix203 : nand02 port map ( Y=>nx202, A0=>count, A1=>nx204);ix205 : nand04 port map ( Y=>nx204, A0=>count, A1=>Q_2_EXMPLR,

A2=>Q_1_EXMPLR, A3=>nx228);ix180 : oai32 port map ( Y=>nx179, A0=>nx208, A1=>count, A2=>load,B0=>nx212, B1=>nx225);

Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>nx208, D=>nx179,CLK=>clk, R=>NOT_reset);


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Synthesized netlist (3)

ix211 : inv01 port map ( Y=>NOT_reset, A=>reset);ix213 : aoi22 port map ( Y=>nx212, A0=>I(2), A1=>nx214, B0=>nx22, B1=>nx4 );ix216 : inv01 port map ( Y=>nx214, A=>count);ix219 : nand02 port map ( Y=>nx218, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR);Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx189,

CLK=>clk, R=>NOT_reset);

ix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLR, S0=>nx225);ix61 : ao32 port map ( Y=>nx60, A0=>nx48, A1=>nx218, A2=>nx4, B0=>I(1),

B1=>nx214);ix49 : or02 port map ( Y=>nx48, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);ix226 : nor02_2x port map ( Y=>nx225, A0=>count, A1=>load);Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>nx228, D=>nx169,

CLK=>clk, R=>NOT_reset);ix231 : inv01 port map ( Y=>nx230, A=>I(0));ix5 : inv01 port map ( Y=>nx4, A=>nx202);ix23 : xor2 port map ( Y=>nx22, A0=>nx208, A1=>nx218);

end Behave ;


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Synthesis steps

1. Load technology library into database2. Read HDL models into database

3. Get design constraints (timing, area)

4. Analyze design

5. Elaborate design

6. Compile/optimize design

Repeat as necessary to meet constraints

7. Generate technology-specific netlist(s)8. Generate simulation timing data (SDF file)

9. Generate reports (cells, area, timing)


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LeonardoMainWindow


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LeonardoQuick Setup Tab

Technology

HDL Files

Target Clock Freq

Optimization Effort

Output File

CommandWindow


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Leonardo commands/scripts

Enter commands at the command prompt, or read froma Tcl script file.

A variable specifies a global constraint, directive, etc.

Tcl set and unset commands change variables

set voltage 3.3 An attribute is information attached to an object

(owner of the attribute) in the memory design database.

Allows user to fine-tune the process at the object level.

Set with Tcl set_attribute command (also unset_attribute) An attribute has: owner, name, value

Example:

set_attributenet n1name max_fanout_loadvalue 10


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Technology library (ASIC)

Load synthesis library for target technology into memory Command example: load_library tsmc025_typ

Searches for $EXEMPLAR/lib/tsmc025_typ.syn

Technology variables affecting delay calculations (delay

derating factors) Use tech library defaults if variables not set

set voltage 2.5 (volts)

set temp 40 (degrees celcius/centigrade)

set process 1 (process variation #if available)

set max_fanout_load 5

Global limit on max inputs driven by one output

Override with max_fanout_load attribute on a net (prev. slide)

Leonardo splits nets or adds buffers as needed (but buffers add delay)


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Choose ASIC library

Operatingtemp/voltagefor delay

calculations

Advanced settings:Select max fanout

Technology Tab(ASIC)

FPGA options includedevice family, part,speed grade andpin selection


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TechnologyTab (FPGA)

Specify:part,speed grade,wire load,use of IOB registers


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Loading a design into the database

Input VHDL/ Verilog source file(s) to memory database Analyzesyntax check and build database

check dependencies & resolve generics/parameters

Elaboratesynthesize into generic gates and black boxes

technology-independent gates operators (arithmetic, relational, etc.) recognized and

implemented with black boxes (no logic in them yet)

Read command does analyze + elaborate + pre-optimize


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Analyze Command

analyze {f1.vhd src/f2.vhd top file.vhd} Read and analyze into default memory database library work

List VHDL files in {} in bottom up order top level last

Use quotes if embedded spaces in file name: top file.vhd

Include directory information if necessary: src/f2.vhd

Analyze command switches:

-format vhdl (or verilog) [default VHDL if file ext = .vhd/.vhdl orVerilog if file ext = .v/.verilog]

-worklib_name [lib where design to be stored (default = work.)

Different libraries might be used for comparing designs] Examples:

analyze {src/f1.vhd src/f2.vhd}

analyze {src/f1.vhd src/f2.vhd}worklib_version1


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Elaborate Command

Elaborate a design previously loaded into the memorydatabase

elaborate divider [divider = VHDL entity/Verilog module]

Switches

-single_level [only do top levelfor bottom-up design] -architecture a1 [if other than most recently analyzed]

-worklib_name [if name other than work]

-generics { size=9 use_this=TRUE initval=10011 }

List format is { generic=value generic=value . }

-parameters [format same as generics]


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Read command

Performs both analyze and elaborate steps read {f1.vhd src/f2.vhd top file.vhd}

Use switches from analyze and elaborate commands, plus:

-dont_elaborate {f1.vhd}do analysis but not elaborate

Input Flow Tab can be used to run read/analyze/elaborate

Uncheck Run Elaborate box for analyze only

Uncheck Run Pre-Optimization to skip that step for now

Select other analyze/elaborate options via the Power Tabs


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Input Flow Tab

FSM encoding

HDL file list:List VHDL files frombottom to top levels ofhierarchy.

Share resources (adders,

etc.) to do multiple ops

Run Elaborate stepafter Analysis.

Run Pre-Optimizestep after Elaborate Power Tabs below here


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Elaborate & VHDL Options Power Tabs

Elaborate: Select:top-level design name,architecture,work library,generics,top-level only

VHDL Options:Select VHDL 87 instead of 93

Other power tabs for other formats

(Verilog, SDL, etc.)


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Design Constraints

Area constraints Timing constraints

Simple: specify target clock frequency

Advanced: specify globally or on specific blocks

Clock: period/frequency, pulse width, duty cycle Input: arrival time, transition times, driver strength

Output: required time, transition times


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Design Constraints Area constraints

Timing constraints (clocks, delays, inputs, outputs)

Simple: specify target clock frequency

Advanced: specify globally or on specific blocks

Four delay variables can be specified:

Input pin to output pin (through combinational logic)

Input pin to register & register to output pin

Register (from time it is clocked) to register (to meet setup time)


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Clock-related constraints

clock_cycle

pulse_width

clock_offset


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Clock constraint examples


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Global clock and delayconstraints

- Clock fequency/period- Max delays

These apply to the entiredesign, except for objectsfor which attributes havebeen defined that specify

other clock values.


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Individual clocknet attributes

Clock name(s)

These override theglobal clock settingsfor the selected clocksignals.


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Input constraints

Arrival time at input pin from previouscircuit, relative to the clock.

Drive level of circuit driving the pin &max rise/fall time allowed used indelay/loading calculations.

Pin

Clk

D Q

Clk


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Output constraints

Time signal from an output pin isrequired the next circuit.

Max rise/fall time allowed used indelay/loading calculations.

Pin

Clk

D Q

Clk


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Sequential circuit example (Synopsys)

create_clock -period 20 -waveform {5 15} clkacreate_clock -period 30 -waveform {10 25} clkbset_input_delay 10.4 -clockclka in1set_input_delay 6.4 -clockclkb -add_delay in1set_output_delay 1.6 -clockclka -min out1set_output_delay 4.8 -clockclka -max out1

Arrival at input pin fromprevious clock edgeSetup time of output pinfrom next clock edge

Required clock periods


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Other signal constraints

Preserve signal duringoptimization(do not eliminate it)

preserve_signal attribute


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Module constraints

Dont touch: keep module as-is,including lower levels

No Opt: keep selected module,but lower levels may be optimized

Select area/delay optimizationand effort level for each module

Select modules

Commands/Attributes:

dont_touch, noopt


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Write a Constraint File

For subsequent synthesisand/or for physical place &route tool.


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Pre-Optimize Power Tab

Select specific design to pre-optimize


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Optimize Tab

Set variables for bothoptimize andoptimize_timingcommands


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Advanced SettingsOptimize Timing


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Output Tab

Write one or more files:VHDL netlistVerilog netlistSDF (timing)

Select Technology Cellsfor circuit structure ofcells from the technologylibrary.

vhdl 6 synthesis with vhdl leonardo

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