gaas/alas aspat diodes for millimetre and sub millimetre
TRANSCRIPT
GaAsAlAs ASPAT Diodes for Millimetre
and Sub-Millimetre Wave Applications
A thesis submitted to The University of Manchester for the degree of
Doctor of Philosophy
In the Faculty of Sciences and Engineering
2017
MOHD RASHID REDZA BIN ABDULLAH
SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING
2
LIST OF CONTENTS
LIST OF CONTENTS 2
LIST OF TABLES 6
LIST OF FIGURES 8
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS 13
PUBLICATIONS 13
CONFERENCE PRESENTATIONS 14
ABSTRACT 15
DECLARATION AND COPYRIGHT STATEMENT 16
ACKNOWLEDGEMENTS 17
DEDICATION 18
1 INTRODUCTION 19
11 Background 19
12 Aims and objectives 26
13 Outline of this Thesis 27
2 LITERATURE REVIEW 29
21 Introduction 29
22 Historical review of III-V Compound Semiconductor for RF applications 30
23 The Concept of Heterostructures 33
231 Homojunctions Heterojunctions and Band Discontinuities 34
232 Lattice-Matched and Pseudomorphic Materials 36
233 Quantum well and 2DEG 41
24 Metal-Semiconductor Contact 42
241 Schottky Contact 43
242 Ohmic Contact 46
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work 48
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics 50
261 Principle of Quantum Tunneling 51
262 ASPAT Structural Parameters of GaAsAlAs materials System 55
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure)
used in this study 55
3
263 ASPAT Electrical Parameters 61
27 Characterization of Ohmic Contacts 68
271 Transmission Line Measurement (TLM) 69
28 Basic Characterization Techniques and procedures 72
281 Measuring tools and apparatuses 72
282 Measurement steps using a VNA 75
283 Measurement Practice and Flowchart 76
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES 79
31 Introduction 79
32 Epitaxial Layer Growth Techniques 80
321 Molecular Beam Epitaxy (MBE) 80
33 Basic Principles of Common Fabrication techniques 81
331 Sample cleaning 81
332 Photolithography 82
333 Etching Process 86
334 Sputtering (dielectric deposition) 88
335 Metallization Process Lift-off and Annealing 88
34 GaAsAlAs ASPAT Process Optimization 92
341 ASPAT Devices used in Fabrication 93
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability 95
343 Fabrication process of GaAsAlAs ASPAT diode toward High
frequency Applications 117
35 Conclusions 125
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT DIODE USING
SILVACO 126
41 Introduction 126
42 SILVACO modelling Tools 127
43 SILVACO Implementation GaAs AlAs ASPAT Modelling 130
44 Simulation Result and Analysis 132
45 Structure Analysis of ASPAT Diode 135
451 Dependencies of current on AlAs Barrier thickness 135
452 Dependence of current on Spacer I length l1 137
4
453 Dependence of current on Spacer II length l2 138
46 Temperature Dependent Simulation 140
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes 142
48 Conclusions 147
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES 148
51 Introduction 148
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes 149
53 RF Test Fixture Theory and Experiment 153
531 On-Wafer Measurement and Small Signal One-Port Characterizations
154
54 Device Calibration 155
541 Open and Short De-Embedding Technique 155
55 S-Parameter Measurement Result and Analysis 157
551 Diode to diode uniformity 158
552 Wafer to wafer uniformity 160
553 Small devices RF measurements 161
56 Extracting RF models of ASPAT at Zero Bias Voltage 164
561 Extraction of ASPAT parasitic element 165
562 Extraction of ASPAT intrinsic elements 168
563 Capacitances -Voltage (C-V) Extraction 172
57 Conclusions 173
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR DESIGN USING
ADS 175
61 Introduction 175
62 Detection Theory 176
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis 179
64 Noise Consideration in a Detector diode 182
65 Modelling of a 100GHz Zero-biased ASPAT Detector 184
66 Conclusions 199
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING GAASALAS
ASPAT DIODES 201
71 Introduction 201
5
72 Motivation and Background 202
73 Frequency Multiplier Architecture the Basics 203
731 Types of frequency multipliers 205
74 Parameters of interest for Frequency Multipliers 206
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler 208
76 Conclusions 214
8 CONCLUSION AND FUTURE WORK 215
81 Conclusion 215
82 Future Work 217
REFERENCES 218
APPENDICES 228
Word count including footnotes and endnotes 61500(approximately)
6
LIST OF TABLES
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials
structure grown on GaAs Substrates by MBE 23
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314
grown on a GaAs substrate by MBE 24
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP
substrate 24
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary
compound semiconductors a room temperature [41 42] 38
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work 56
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and
Ammonia on GaAs and InGaAs materials 87
Table 32 Epitaxial layer of Doped substrate samples 93
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm 94
Table 34 Generic fabrication steps established by Dr Md Adzhar [101] 97
Table 35 Standard process flow for Air-Bridge design fabrication 101
Table 36 Standard fabrication process flow for Dielectric-Bridge design 107
Table 37 New arrangement of the mask number and step in Second Run 110
Table 38 New arrangement for the Third run using Dielectric-Bridge mask 113
Table 39 The outcome of the spreading resistance before and after using LOR
technique 115
Table 310 DC and RF characteristics for XMBE304 118
Table 311 3rd
Gen Mask process step 119
Table 312 Standard deviation at two different voltages 124
Table 41 The parameter values used in this simulation 134
Table 42 The calculated values of bandgap at different temperatures 140
Table 43 The calculated effective masses for each temperature used in this simulation
141
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104) 145
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics
in this work 153
Table 52 Device to device uniformity check for large ASPAT diode 159
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at
four different frequencies[117] 159
7
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B 161
Table 55 Comparison between calculated (fully Depleted) and extracted (different
biases) values from equivalent circuit parameters for different ASPAT mesa sizes at zero
bias voltage 170
Table 61 A summary of all the important parameters of the 4x4 microm2 diode 185
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode 190
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector 198
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero
bias detector at W-band (75GHz-110GHz) 199
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art
multiplier diode 213
8
LIST OF FIGURES
Figure 21 III-V compound semiconductors mobility and band gap[24] 31 Figure 22 illustration of Homojunctions band structure material before (left) and after
(right) equilibrium 34 Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium 35
Figure 24 Lattice Matching for both materials when aL=aS 37 Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40] 37 Figure 26 Lattice mismatched material 39
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and
(b) tensile strain [1] 40 Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg
GaAs (a) Structure (b) energy band diagram and (c) Conduction band diagram when
AlGaAs is n-doped[43] 41 Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact 43
Figure 210 Energy band diagram of Schottky contact on n-type material under (a)
reverse and (b) forward bias 45 Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping
concentration ND (a) Low (b) Intermediate and (c) high 47 Figure 212 Classical view of whether an electron is can surmount a barrier or not
Quantum mechanical view allows an electron to tunnel through a barrier The probability
(blue) is related to the barrier thickness 51
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave
function[70] 52
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in
this study 55 Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27] 57
Figure 216 Conduction band diagram showing band bending and 2DEG formation at
the L1 spacer 60 Figure 217 I-V characteristics of a fabricated ASPAT diode 63 Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
63 Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b
and h are not drawn to scale 65 Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304)
The dimensions are not drawn to scale 67 Figure 221 A simple TLM structure with effective length and sheet resistance
underneath 69 Figure 222 Top view of TLM ladder structure use in this work 71 Figure 223 Typical plot of resistance versus TLM spacing 71
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM 73
9
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
75 Figure 226 Actual VNA system that was used for RF characterization 75 Figure 227 Block diagram of the ASPAT measurement step 77
Figure 31 3D illustration of Optical lithography process used in this research 85 Figure 32 Actual picture of thermal evaporator used in this study 89 Figure 33 Single layer lift-off process using negative photoresist 91 Figure 34 Current-Voltage characteristic of sample XMBE368 used in this study at
two different locations on the wafer tile 96
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2
diode dimensions designed in the 1st Gen Mask 96
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates 100 Figure 37 The layout of 1
st design of Dielectric Bridge (green circle) mask design for
100 times 100microm2 emitter size with option for doped substrate processing 100
Figure 38 Dry Etching for the first run in this study 102 Figure 39 Severe undercut of 2times2 microm
2 and 6times6 microm
2 devices 103
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet
etched 104 Figure 311 SEM Images of the GaAs sample 104
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in
this study 105
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
105
Figure 314 SEM images for InP and InGaAs taken from [56] 105 Figure 315 Short circuit behaviour on one of the fabricated device in this run 106
Figure 316 The surface of the sample after final processing 108 Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2
2500 microm2 900 microm2 400 microm2 225 microm2 100 microm2 and 36 microm2 109
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm
Tolerance 110
Figure 319 After lift-off processing 111 Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
112
Figure 321 side view of lateral ASPAT structure 113
Figure 322 The measured size of the emitter area and the length D (blue color marked)
114 Figure 323 Summary of LOR technique steps 115 Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
116
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and
alignment mark structures used in this study 118 Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-
insulating substrate device type used in this study 121 Figure 327 Example finished process device with bond pad using 3
rd Gen mask 121
Figure 328 XMBE304 TLM measurement for the top contact after annealing 122
10
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing 122 Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 4times4microm2 mesa size 123
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 6times6microm2 mesa size 124
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 10times10microm2 mesa size 124
Figure 41 SILVACO Atlas simulation process flow 128 Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the
diode multilayer heterostructures on the right 131 Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor 131 Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure
(b) the energy band diagram of the ASPAT diode structure when under three different
biases 132 Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm
2) and
(4times4microm2) using SILVACO Atlas simulator for structure device XMBE304 showing
excellent agreement between simulated and experimental data 134
Figure 46 IV characteristics of the dependencies of current on AlAs barrier 136 Figure 47 Example of analysis at -1 and 1V to the current 136 Figure 48 I-V characteristic of the dependencies current to Spacer I layer 137
Figure 49 Current changes with layer thickness l1 138 Figure 410 IV characteristic of the dependencies current to Spacer 1 layer 139
Figure 411Current change with layer thickness l2 139
Figure 412 Measurement and simulation comparison result as a function of temperature
range from 100K to 398K 142 Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample
XMBE304 143
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT
Diode [3] 144
Figure 415 Log Current vs voltage as a function of temperature for SBD sample
XMBE104 145
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and
SBD 146
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2
6x6um2 and 10x10um
2 Note the good scalability 149
Figure 52 Junction resistance versus voltage 151
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT
high sensitivity near zero bias detection 152
Figure 54 One port S-parameter measurements 155
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use
for RF calibration and measurements (Note Images are not to scale) 156
11
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices
from 15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check 158
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero
bias 158
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B)
to qualify the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2
device sizes (Real and Imaginary) Note blue colour is XMBE304A and red colour is
XMBE304B 160
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and
4times4microm2
(Real and Imaginary) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm
2 diodes respectively 162
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and
4times4 microm2 (Smith Chart) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm2 diodes respectively 162
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding
equivalent circuit model 164
Figure 512 The S-parameter Touchstone file is used to read the measured files 165
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure 166
Figure 514 Equivalent circuit model for short de-embedded structure 166
Figure 515 Smith chart representative S-parameter measurement for short (left) and
open (right) CPW The blue lines represent simulated data and the red is measured data
167
Figure 516 Equivalent circuit of the ASPAT diode 169
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 (Real and Imaginary) results for various small device designs 169
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 results (Smith Chart) for various small device designs 170
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled
capacitance vs Voltage) 172
Figure 61 Block diagram represent a complete direct receiver system 177
Figure 62 The detection process of a single wave through a non-linear IV characteristic
of a diode 177
Figure 63 Lumped element illustration of microwave detector circuit 178
Figure 64 The mixing process where the signals are processed by the non-linear I-V
characteristic to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and
fRF are applied to the diode 179
Figure 65 Measurement of Tangential Sensitivity[108 129] 181
12
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted
from MATLAB to realize a virtual GaAsAlAs ASPAT diode 186
Figure 67 Verification of actual (blue measured) and virtual (red_10th order
polynomial) I-V characteristic of the 4times4 microm2 diode used in this study 186
Figure 68 Direct detector circuit topology using an ASPAT diode 187
Figure 69 Output voltage and detector sensitivity over wide range of input power 188
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load
resistance of the ASPAT detector 189
Figure 611 Junction resistance as a function of forward voltage 189
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size
of 4times4μm2 191
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power 192
Figure 614 Reflection Coefficient versus operating frequency without matching
circuitry 193
Figure 615 Detector circuit with impedance matching circuit placed in between diode
and source 194
Figure 616 Reflection Coefficient over wide frequency band with matching 195
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band
frequency 195
Figure 618 Lowest detectable signal at 100GHz operating frequency 196
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of
diode operation 197
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained
from the fabricated ASPAT in this work 198
Figure 71 performance of state-of the-art millimetre wave source [166] 202
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
204
Figure 73 Principle of operation for frequency multiplier utilising a non-linear
resistance [10] 204
Figure 74 A standard system for two port frequency multiplier circuit 207
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode 209
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool 210
Figure 77 Conversion loss and conversion efficiency as a function of input power 211
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
212
13
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS
PUBLICATIONS
1 MRR Abdullah Y K Wang J Sexton M Missous and M J Kelly ldquoGaAsAlAs
Tunnelling Structure Temperature Dependence of ASPAT Detectorsrdquo 8th UK-Europe-
China Workshop on mm-waves and THz Technologies 2015 Cardiff University IEEE
proceedings DOI 101109UCMMT20157460591
2 Yuekun Wang Mohd Rashid Redza Abdullah James Sexton and M Missous
ldquoInGaAs-AlAs asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo 8th
UK-Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings DOI 101109UCMMT20157460589
3 K N Zainul Ariffin S G Muttlak M Abdullah M R R Abdullah Y Wang and M
Missous ldquoAsymmetric Spacer Layer Tunnel In018Ga082AsAlAs (ASPAT) Diode using
Double Quantum Wells for Dual Functions Detection and Oscillationrdquo 8th UK-
Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings Doi 101109UCMMT20157460599
4 K N Zainul Ariffin M R R Abdullah Y K Wang S G Muttlak O S
Abdulwahid J Sexton MJ Kelly and M Missous ldquoAsymmetric Spacer Layer Tunnel
Diode (ASPAT) Quantum Structure Design Linked to Current-Voltage Characteristics
A Physical Simulation Studyrdquo UK-China Millimetre Waves and Terahertz Technology
Workshop September 2017 Submitted 14 July 2017 Conference held on 11th -13th
September 2017 DOI 101109UCMMT20178068358
5 K N Zainul Ariffin Y Wang M R R Abdullah S G Muttlak Omar S
Abdulwahid J Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoInvestigations of
Asymmetric Spacer Tunnel Layer (ASPAT) Diode for High-Frequency Applicationsrdquo
DOI 101109TED20172777803
6 Omar S Abdulwahid S G Muttlak M R R Abdullah K N Zainul Ariffin J
Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoA 100GHz Zero-Biased
Quantum Tunnelling ASPAT Detectorrdquo Submitted to IEEE TED on DEC 2016 under
correctionamendment Pending fabrication data
14
CONFERENCE PRESENTATIONS
1 Mohd Rashid Redza Abdullah J Sexton Kawa Ian MJKelly and M Missousldquo
G2040GHz Frequency Doubler Varistor Mode using ASPAT diodesrdquo UK
Semiconductors 2017 2017 University of Sheffield Oral presentation
2 M R R Abdullah YueKun Wang J Sexton Kawa Ian and M Missousldquo
Microwave Performance of GaAsAlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diodesrdquo UK Semiconductors 2016 2016 University of Sheffield Oral presentation
3 M R R Abdullah J Sexton and M Missousldquo GaAsAlAs Tunnelling Structures
THz RTD oscillators and ASPAT detectorsrdquo UK Semiconductors 2015 2015
University of Sheffield Oral presentation
4 Yuekun Wang Mohd Rashid Redza Abdullah and M MissousldquoInGaAs-AlAs
asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo UK
Semiconductors 2015 2015 University of Sheffield Oral presentation
5 Mohd Rashid Redza Abdullah and M Missousldquo GaAsAlAs Tunnelling
Structure Temperature Dependence of ASPAT Detectorsrdquo PGR Conference2016
2016 University of Manchester Poster presentation
6 YueKun Wang KNZainul Ariffin Mohd Rashid Redza Abdullah J Sexton
Kawa Ian and M Missous ldquoPhysical Modelling and Experimental Studies of
InGaAsAlAs Asymmetric spacer Layer Tunnel Diodesrdquo UK Semiconductors 2016
2016 University of Sheffield Oral presentation
7 K N Zainul Ariffin S G Muttlak M R R Abdullah Y Wang Omar S
Abdulwahid M Missous ldquoExperimental and Physical Modelling of Temperature
Dependence of a Double Quantum Well In018Ga082AsAlAs ASPAT Dioderdquo UK
Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral Presentation
8 Omar S Abdulwahid Mohd Rashid Redza Abdullah S G Muttlak K N Zainul
Ariffin Mohamed Missous ldquoTunnelling Barrier Diode for Millimetre Wave
Mixingrdquo UK Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral
Presentation
9 M Abdullah K N Zainul Ariffin MRR Abdullah J Sexton M Missous and
MJ Kelly ldquoA Novel In18Ga82As-AlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diode with Double Quantum Wells for Microwave Detectionrdquo UK Semiconductor
Conference 2015 Sheffield 1 ndash 2 July 2015 Oral Presentation
15
ABSTRACT
Thesis Title GaAsAlAs ASPAT Diodes for Millimetre and Sub-Millimetre Wave
Applications
Institute School of Electrical and Electronic Engineering the University of Manchester
Candidate Mohd Rashid Redza bin Abdullah
Degree Doctor of Philosophy (PhD)
Date 3 October 2017
The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in
the early 90s as an alternative to the Schottky barrier diode (SBD) technology for
microwave detector applications due to its highly stable temperature characteristics The
ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a
thin barrier which enables RF detection at zero bias from microwaves up to
submillimetre wave frequencies In this work two heavily doped GaAs contact layer on
top and bottom layers adjacent to lightly doped GaAs intermediate layers enclose
undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that
acts as a tunnel barrier The ultimate ambition of this work was to develop a MMIC
detector as well as a frequency source based on optimized ASPAT diodes for millimetre
wave (100GHz) applications The effect of material parameter and dimensions on the
ASPAT source performances was described using an empirical model for the first time
Since this is a new device keys challenges in this work were to improve DC and
RF characteristic as well as to develop a repeatable reproducible and ultimately
manufacturable fabrication process flow This was investigated using two approaches
namely air-bridge and dielectric-bridge fabrication process flows Through this work it
was found that the GaAsAlAs heterostructures ASPAT diode are more amenable to the
dielectric-bridge technique as large-scale fabrication of mesa area up to 4times4microm2 with
device yields exceeding 80 routinely produced The fabrication of the ASPAT using i-
line optical lithography which has the capability to reduce emitter area to 4times4microm2 to
lower down the device capacitance for millimetre wave application has been made
feasible in this work The former challenge was extensively studied through materials
and structural characterisations by a SILVACO physical modelling and confirmed by
comparison with experimental data The I-V characteristic of the fabricated ASPAT
demonstrated outstanding scalability demonstrating robust processing A fair
comparison has been made between ASPAT and SBD fabricated in-house indicating
ASPAT is extremely stable to the temperature The RF characterisations were carried out
with the aid of Keysight ADS software
The DC characteristic from fabricated GaAsAlAs ASPAT diodes were absorbed
into an ADS simulation tool and utilized to demonstrate the performance of MMIC
100GHz detector as well as 20GHz40GHz signal generators Zero bias ASPAT with
mesa area of 4times4microm2 with video resistance of 90KΩ junction capacitance of 23fF and
curvature coefficient of 23V-1
has demonstrated detector voltage sensitivity above
2000VW while the signal source conversion loss and conversion efficiency are 28dB
and 03 respectively An estimate noise equivalent power (NEP) for this particular
device is 188pWHz12
16
DECLARATION AND COPYRIGHT STATEMENT
No portion of the work referred to in the dissertation has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning
COPYRIGHT STATEMENT
i The author of this thesis (including any appendices andor schedules to this thesis) owns
certain copyright or related rights in it (the ldquoCopyrightrdquo) and he has given The University of
Manchester certain rights to use such Copyright including for administrative purposes
ii Copies of this thesis either in full or in extracts and whether in hard or electronic copy
may be made only in accordance with the Copyright Designs and Patents Act 1988 (as
amended) and regulations issued under it or where appropriate in accordance with licensing
agreements which the University has from time to time This page must form part of any
such copies made
iii The ownership of certain Copyright patents designs trademarks and other intellectual
property (the ldquoIntellectual Propertyrdquo) and any reproductions of copyright works in the thesis
for example graphs and tables (ldquoReproductionsrdquo) which may be described in this thesis
may not be owned by the author and may be owned by third parties Such Intellectual
Property and Reproductions cannot and must not be made available for use without the prior
written permission of the owner(s) of the relevant Intellectual Property andor
Reproductions
iv Further information on the conditions under which disclosure publication and
commercialisation of this thesis the Copyright and any Intellectual Property andor
Reproductions described in it may take place is available in the University IP Policy
(httpdocumentsmanchesteracukDocuInfoaspxDocID=487) in any relevant Thesis
restriction declarations deposited in the University Library The University Libraryrsquos
regulations (httpwwwmanchesteracuklibraryaboutusregulations) and in The
Universityrsquos policy on Presentation of Theses
17
ACKNOWLEDGEMENTS
First and foremost all gratefulness and praise is to Allah swt for everything in my
life He is the one and the only one who granted me knowledge health patience and
ability to complete this thesis as well as colouring the whole journey of my PhD
I give my deepest and sincere gratitude to my PhD supervisor Professor Mohamed
Missous for his time support patience and guidance throughout the journey of this PhD
studies His encouragements valuable advice precious ideas and a wealth of knowledge
amp experiences have had a direct inspiration on this research Special thanks also to our
experimental officer Dr James Sexton for not only sharing his knowledge advice and
semiconductor fabrication skills but also his effort in maintaining our clean room
facilities to a great level My gratitude also extends to Mr Mallachi McGowan for his
help and assist in the lab-related issue
I am also obligated to Prof MJ Kelly from University of Cambridge and Dr Kawa
Ian from ICS limited for their measurement of the ASPAT samples on realizing the RF
characteristics This collaboration effort can hopefully last longer in designing and
implementing the ASPAT MMIC detectors
My deepest appreciation also goes to my PhD colleagues Khairul Nabilah Saad
GMuttlak Omar AbdulWahid and Yuekun Wang for their support as well as working
together with me to realize this exciting project directly and indirectly A sincere
thankfulness similarly to my seniors Dr Md Adzhar Zawawi and Dr Fauzi Packeer for
their support during the first and second year of my research For other friends and staff
members under Prof Missous and Dr M Migliorato I will always remember the strong
bond and friendship we made
I am really fortunate that I been blessed with my motherrsquos care who always make doarsquo
for my success every day during my studies As for my beloved wife Dr Nik Maryam
Anisah Nik Mursquotasim who had always encouraged me supported me and gave me
patience through all the hardship in this journey thank you very much
Finally I also would like to thank and acknowledge my sponsor Majlis Amanah
Rakyat (MARA) for financially supporting me during this studies I am greatly indebted
with your kind support which was vital to my study
18
DEDICATION
This thesis dedicated to
My respected and beloved parentshellip
My loving wife dearest siblings and in-lawshellip
19
1 INTRODUCTION
11 Background
It is an undeniable fact that semiconductors have changed the world much further
than anything people could have predicted in the last 60 or 70 years ie after the lsquocats
whisker and vacuum tube eras This field of research has been expanding from year to
year starting from the discovery of the first semiconductor (silver sulfide) in 1833 by
Michael Faraday [1 2] and it still remains very active to the present Semiconductors
have a large range of applications and are not just limited to use in communications they
can be found everywhere in other applications from Earth to space The widespread
usage and sheer number of applications have led to it growing very quickly and
contributing greatly to the growth of World Economics Over time the successful
development of semiconductor growth techniques such as Molecular Beam Epitaxy
(MBE) has enabled researchers to tailor and precisely control the semiconductor
material for new electronic devices with extra functionalities This has led to the
development of advanced devices such as high electron mobility transistors (HEMTs)
and Heterojunction bipolar transistors (HBTs) for use in wireless communication
technology Given this development today electronic devices such as computers
handheld smartphone tablets etc are no longer perceived as luxury and attractive items
but rather have become crucial in everyday life Such devices provide the means to allow
for people to remain connected to each other via the sending and receiving of
information electronically The huge demand for such types of devices has resulted in
competition in both the electronic market and technologies which only goes on to
advance the semiconductor industry
Nowadays the demand for electronic devices characterised by high speed high
efficiency ultra-low power and low manufacturing cost has increased exponentially To
fulfil this growth in demand high data rate systems are required in other words the
system must work at a higher frequency for both the transmitter and receiver The
frequency of interest for advanced wireless communication is in the Millimetre and sub-
20
millimetre wave region which is around 30-300GHz and 300 - 3000GHz respectively
The second frequency region is also sometime known as the terahertz (THz)
electromagnetic region This band lies between the microwave and infrared frequency
bands From the first time it was revealed in the late 80s[3-5] the THz region has gained
a lot of international attention due to its unique properties and since then the motivation
to develop these devices has increased significantly To date the THz frequencies region
has shown its ability to fulfil various applications such as high-resolution imaging in
medical security and surveillance field atmospheric monitoring and environment radio
astronomy as well as compact range radars[3] to name a few
However despite these developments not much effort has been made in exploring
alternative compact THz devices As a result electronic THz devices are still in the state
of immaturity as compared to microwave and photonics devices This is due to their high
cost and absence of compact amp solid-state THz sources (oscillators) and receivers
(detectors) that are capable of operating at both room and extreme temperatures[6 7] A
great deal of work still continues to fill up the lsquoTHz gaprsquo (between 300GHz and 3THz)
used for the most important part of a communication system namely the front-end
receiver or first stage Such a system is responsible for receiving detecting and
processing the received signal to be translated into useful information Furthermore THz
receivers systems still require the best-integrated components such as source mixer and
detector to reach their complete competencies[8] The detector which remains the
critical part of the receiver system requires devices or components that are able to fulfil
the THz gap requirement Studies conducted over a number of years have found out that
the key element in improving THz detection relies upon the use of passive devices ie
diodes Based on these findings many types of diode ie tunnelling diode point-contact
diode and Schottky barrier diode (SBD) have been proposed for detection applications
Amongst microwave and millimetre wave detector diode devices the Schottky
Barrier Diode (SBD) is the dominant detector that has been used since the 1940s[9] The
reason for this dominance is the ease of fabrication of a SBD (by either a point-contact
or evaporated semiconductor-metal structure) and its ability to produce a non-linear
current-voltage (I-V) characteristic which is necessary for rectifyingdetecting diodes [9
10] SBDs also have high cut-off frequency good dynamic range and are low cost To
21
date the SBD has been able to detect signals up to 100GHz [11] 1THz[12] and as high
as 10 THz[13] However the current transport mechanism in a SBD relies on thermionic
emission and therefore is strongly dependent on temperature and means that using them
in extreme conditions ie military and automotive applications is complex The SBD
also suffers from high noise figure[14] and is susceptible to burnout at a modest pulse
power level this will limit the use of ultra-high frequencies and low power signal
applications Other diodes that share the same characteristics are Planar Doped Barrier
(PDB) Germanium Backward Diode (GBD) ie a type of Esaki tunnel diode These
diodes are well known and are reliably used as millimetre wave detectors However it
still proves inefficient to substitute the SDB with any of the previously mentioned
diodes This is due to some drawbacks such as strong temperature dependence limited
dynamic range fabrication complications and hence poor reproducibility (ie GBD) and
other circuit complexities
Hence there is strong compulsion to study examine and produce new detector
diode structures that are able to solve the mentioned diodes limitations and which have
high sensitivity larger dynamic range low noise strong independence to temperature as
well as being able to work efficiently in the high-frequency band and at zero bias The
advantages of working at zero-bias relates very much to the need for a system with less
power consumption so that the device (ie mobile communication) is able to run off
small batteries for a reasonable length of time eliminating extra biasing circuit as well as
noise Therefore a new tunnelling device namely the Asymmetrical Spacer Layer
Tunnel diode (ASPAT) developed by RT Syme [15 16] and refined by Missous et
al[17] has been examined in this work The ASPAT which is in essence a
Semiconductor-insulator-semiconductor structure relies on tunnelling through a barrier
to provide current compared to conventional thermionic emission in SBDs The ASPAT
diode has many advantages a zero bias turn-on voltage very weak sensitivity to changes
in temperature (due to tunnelling) very low noise large dynamic range high resistance
to pulse burn-out [18] and as demonstrated recently can be reproducibly
manufactured[17] The growing interest in THz frequencies nowadays makes the
ASPAT an excellent choice to fulfil all requirements for ultra-high speed applications
22
ie communication (mobile computer networking) radar (military equipment) scalar
analyser and built-in test equipment
In this work an ASPAT diode based on group III-V elements of the periodic table
comprising compound semiconductors of large band gap material Aluminium Arsenide
(AlAs) sandwiched between two lower bandgap Gallium Arsenide (GaAs) are used and
intensively examined The AlAs semiconductor which is ten-monolayer thick has
almost the same lattice constant as GaAs but has a larger bandgap Consequently in the
conduction band a thin barrier of the AlAs is formed from the arrangement of such
structure The structure is made up of GaAs and AlAs both materials are grown on
GaAs substrate using Solid Source Molecular Beam Epitaxy (SSMBE) Therefore in
this study the ASPAT diode will be referred to as ldquoGaAsAlAs ASPATrdquo diode The
conventional GaAsAlAs ASPAT diode has been developed and successfully fabricated
in two different stages This work was the first carried out using facilities provided by
the University of Manchester The first stage of the work was to qualify the
reproducibility and repeatability of growth and fabrication technique which is mostly
performed on larger emitteranode size The second was to develop conventional
ASPAT diodes that can perform at Millimetre and sub-millimetre wave frequencies and
which are comprised of small emitter area
Prior to this work full physical modelling using SILVACO design software was
undertaken to generate models and to fully characterise and identify the fundamental
physical phenomenon of multi-junction ASPAT diode Therefore insight into and
performance based on diode structure and electron movement can be understood and
predicted which lead to the crucial idea in helping and advising iterations to epitaxial
growth as well as diode fabrication The verification of the physical models must be set
as a priority goal by comparing the results of statistically fabricated measured data The
advantage of physical modelling is that it can help reduce materials resources cost and
fabrication time
Further research into the field has led to the development of two other types of
ASPAT diodes that are used to compare with the conventional GaAsAlAs ASPAT
diode Their configuration involved the use of a more advanced semiconductor
technology which comprises InGaAsAlAs materials and GaAsAlAs with InGaAs
23
quantum wells The latter was a novel ASPAT diode and the former is identified as
advanced ASPAT diode However these two advanced ASPAT diodes have not been
extensively studied in this thesis as they will be covered by other co-workers at
Manchester Hence due to these some important parameters are compared to the
conventional one as it is the main focus of this work In the case of temperature
dependent studies the DC characteristic of conventional ASPAT is compared to in-
house fabrication AuGaAs SBD All the ASPATs epitaxial layer materials structures are
shown in the following tables
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials structure grown
on GaAs Substrates by MBE
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE304 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~400 ~50
Spacer1 GaAs NID 50 50 50
Barrier AlAs NID 28 28 28
Spacer 2 GaAs NID 1000 2000 1000
Buffer GaAs(Si) 4times1017
50 400 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~4500 ~3500
Substrate GaAs (Si) 50000 50000 50000
Note that sample XMBE368 and XMBE304 are grown on doped GaAs
substrates Sample XMBE368 was grown un-rotated to study the effect of barrier
thickness variation
24
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314 grown on a
GaAs substrate by MBE
XMBE314
Layer Material Doping (119836119846minus120785) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018
3000 142
Emitter GaAs (Si) 1times1017
400 142
Spacer GaAs Undoped 50 142
Quantum Well In18Ga82As Undoped 60 116
Barrier AlAs Undoped 28 283
Quantum Well In18Ga82As Undoped 60 116
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017
400 142
Ohmic Layer GaAs (Si) 4times1018
4500 142
Substrate GaAs
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP substrate
XMBE326
Layer Material Doping (cm-3
) Thickness (Aring) Bandgap (eV)
Top Ohmic1 In053Ga047As(Si) 5times1019
3000 075
Buffer 1 In053Ga047As(Si) 1times1017
350 075
Spacer1 In053Ga047As NID 50 073
Barrier AlAs NID 283 283
Spacer 2 In053Ga047As NID 2000 075
Buffer In053Ga047As(Si) 1times1017
350 075
Bottom Ohmic In053Ga047As(Si) 15times1019
4200 075
Substrate InP (Si) NID 620000
From the above tables it can be noted that XMBE307 is the first batch that was grown
in-house using a Riber V100HU MBE machine followed by XMBE368 XMBE 304
XMBE314 and finally XMBE326 The two earlier batches were grown on n+
substrate hence their fabrication process flow is simpler On the other hand the three
other batches were grown on semi insulating substrate thus requiring the development
of new repeatable reproducible and robust process flow which will be covered in this
thesis
25
In general the fabrication of the ASPAT diode is based on top-down processes this
is because the ASPAT is a vertical structure device and the junction capacitance of the
ASPAT is directly associated with the size of the anodeemitter area Further to these
the capacitance directly influences the diode cut-off frequency Therefore the simplest
way to reduce the capacitance is by reducing the lateral area of the device of the ASPAT
structure since it can be represented by a parallel plate capacitor where the capacitance
is inversely proportional to the area of the device In order to achieve high cut-off
frequencies minimising capacitance via small dimensions ie sub-micrometre level is
essential However this will also increase the series resistance of the diode As a result
the cut-off frequency will be degraded Thus there is a trade-off between small
dimension of device and high cut-off frequency to be achieved
Finally successful growth and fabrication for small area GaAsAlAs ASPAT diode
in this work has led to carefully extracted RF characteristics This becomes a stepping
stone to designing a millimetre wave integrated circuit (MMIC) detector using empirical
modelling in Keysight ADS tools Therefore a predicted performance for a 4times4 um2
fabricated ASPAT is that can operate at 100GHz ASPAT as a zero-bias detector with a
voltage sensitivity of over 2000VW Additionally the design of a millimetre wave
source using similar ASPAT diodes was also carried out The performance of a 2040
GHz doubler using GaAsAlAs ASPAT in varistor mode is demonstrated for the first
time with a conversion loss of 33dB and conversion efficiency of ~ 02
26
12 Aims and objectives
The aim of this study is to further improve the performance of microwave and
millimetre wave technology by incorporating the Asymmetrical Spacer Layer Tunnel
Diode (ASPAT) for ultimate operation near THz frequencies by designing a range of
low power high-speed devices enhancing the methods of Simulation layout and
materials amp structural characterisations with fabrication process optimization using the
facilities available at the University of Manchester
There are three main objectives in this research firstly to streamline the physical
device design and modelling using the GaAsAlAsGaAs materials systems in order to
produce a zero bias detector which is basically a rectifier of a microwave signal by
using the SILVACO Atlas simulation tools
Secondly to achieve reproducibility and manufacturability of the fabrication
process for new type of GaAsAlAs ASPAT structure (lateral structure) hence small size
ASPAT emitter by improving the device processing technique and maximising the
capability limit of the conventional i-line optical lithography that is available in Prof
Missousrsquos group laboratory
Thirdly to optimise DC parameters through electrical properties investigation as a
stepping stone to the next objective that is to characterise the RF performance of the
GaAsAlAs ASPAT detector circuit The detection properties of microwave and
millimetre wave diode will also be investigated with different ASPAT diode size at
100GHz Further to these the properties of microwave signal source will also be
developed by way of utilizing the non-linearity feature of the diode Therefore this new
type of tunnelling diode can be applied to both applications of signal detection and
signal source in the microwave and millimetre wave ranges
27
13 Outline of this Thesis
This thesis is organized into eight chapters The first chapter discusses the
contextual information that motivates the undertaking of the study An overview of the
work which includes the details of the studied samples the aim and objectives of the
whole research project are also outlined in this chapter
Chapter 2 deals with the literature review of the basic principles and concepts of
the group III-V compound semiconductors The historical background of such
semiconductors which is essential to the development of ternary structures etc and the
advancement of semiconductor materials engineering is presented The types of existing
tunneling diode as well as conventional microwave diodes are also discussed and
compared The fundamentals of ASPAT diode which includes structural parameters and
its operation are then explained in detail Finally discussions of the ASPAT key DC
characteristics which are important for detection purposes are presented
Chapter 3 focusses on the development of the experimental techniques which can
be divided into two stages In the first stage the development is towards repeatability
reproducibility and manufacturability of the ASPAT grown in-house by MBE and
fabricated by conventional i-line optical lithography The second stage involves
optimisation and fine tuning such fabrication method for GaAsAlAs ASPAT samples
that can operate at high frequency ie 100GHz detector For both stages of the
fabrication process all techniques including mask design generic and special process
flow are presented The chapter ends with discussions on issues related to sample
processing and improvements that are proposed to solve these issues
Chapter 4 dwells on the modelling of the GaAsAlAs ASPAT using the SILVACO
simulation package The discussions are expected to offer a better understanding or
insight into each layer that forms the ASPAT diode structure The chapter begins with
discussions of the operation of the SILVACO Atlas tool A validation of physical
modelling is essential and presented according to the fabricated mesa sizes of the diode
28
Thereafter towards the end of the chapter the analyses of the relationship between
device current-voltage (I-V) characteristics the structural parameter including various
temperatures dependent simulations with a comparison to an in-house fabricated SBD
are offered
Chapter 5 presents relevant DC results based on optimized fabrication process and
RF characterization which enable obtaining an intrinsic and extrinsic element of the
GaAsAlAs ASPAT diode The discussions also highlight the analysis of DC zero bias
equivalent circuit and de-embedding extraction using ADS The chapter ends with
discussions on the RF reproducibility performance which includes the performance as
well for millimeter-wave and sub-millimeter wave applications
Chapter 6 discusses the main applications of ASPAT diodes The chapter begins
with discussions on detection theory followed by the parameters of interest and ends
with circuit design as well as the performance of a 100GHz detector The circuit design
was conducted using Keysight ADS software via harmonics balance simulation tool The
performance in term of sensitivity depending on measured ASPAT emitter size is
demonstrated Finally a comparison with conventional Schottky diode is presented
towards the end of the chapter
Chapter 7 discusses a secondary application that can be applied to the ASPAT by
utilizing the nonlinearity feature of the diode to create a signal source namely a 20 to
40GHz frequency doubler in varistor mode The doubler performance of ASPAT will be
explored through circuit design constructed via Keysight ADS simulation software Each
key parameter is highlighted and discussed in detail
The final chapter of this thesis that is Chapter 8 discusses the conclusions of the
study with emphasis on the overall key research findings The chapter also highlights
suggestions for further research in this particular field of study
29
2 LITERATURE REVIEW
21 Introduction
Since 1940s the development in the technology of semiconductor electronics has
been expanding and now has led to the establishment one of the most astonishing
industries of the 3rd
-millennium era Leading this advancement is the integrated circuit
(IC) or chip which was driven mostly by silicon (Si) Overtime the IC has undergone
substantial revolution in term of power economics size and efficient energy
consumption Currently it covers every aspect of human life ie from desktop personal
computers in the office and house to the compact smartphone in the pocket and from a
gigantic satellite in space to small satellite navigation in cars In other words
semiconductor technology is crucial to human life Without developments in
semiconductor materials engineering and shrinking of device size such accomplishment
may not have been realised today Therefore this chapter presents a macro view of the
development in compound semiconductor technology especially in radio frequency (RF)
towards Millimetre and submillimetre wave applications with regard to the improvement
of material and device structures
The essentials of group III-V compound semiconductor will be emphasised for its
points of interest and application in this field (RF technology) This chapter comprises
five main sections The first section is an overview of the semiconductor history with
concentration on its advantages and applications in the RF field while the second and
third discuss the effects of III-V compounds when the interface occurs between
semiconductor-semiconductor and semiconductor-metal respectively which leads to a
basic understanding of hetero-structures device as well as contacts namely Schottky and
Ohmic The fourth section is predominantly concerned with high-speed devices ie
diodes and materials in this field which leads to the exploitation of the main researchrsquos
device Then the following section describes in detail the background works basic
principle and intrinsic amp extrinsic parameters of the Asymmetric spacer Tunnel Diode
(ASPAT) Finally the basic way of characterising the device will also include giving an
overview of how the device is measured and what parameters are needed
30
22 Historical review of III-V Compound Semiconductor for RF applications
The beginning of commercial electronic devices was marked with the first point-
contact semiconductor transistor developed in 1947 by William Shockley at Bell
Laboratories in New Jersey Shockley developed a device based on a Germanium
Bipolar Junction Transistor (Ge BJT) structure [19] with operating frequency above 1
GHz Since then and until early 1950s the development of Ge BJT was fast and it
became foremost in the market of semiconductor technology However the emergence
of Silicon (Si) challenged Ge in the market in the 1960s Si has the upper hand primarily
because it has better electron transport and low manufacturing costs compared to Ge
[19] By the 1970s almost all RF transistors were based on Si BJT Additionally the
development of Si which forms a new material from the formation of native oxide
namely Silicon Dioxide (SiO2) led to the invention of the Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) [19] The future of digital electronic industries has
been ldquobrightrdquo ever since the MOSFET was ldquobornrdquo as it has become a fundamental
building block component in complex microprocessors and flash memories Despite this
development the exploitation of Si at RF frequencies did not last long since Si is not an
optimum semiconductor for RF electronic devices The emergence of GaAs has
improved RF applications for high-speed transistors
Ge and Si which are categorised as single element semiconductor are the earliest
materials used to build the first transistor devices These devices played a crucial role
towards the development of more advanced material such as GaAs of the compound
semiconductor type[20] A compound semiconductor is a semiconductor formed by the
ionic bond of different types of semiconductor material most widely known as the group
III-V compound semiconductors The main reason for the progression of the III-V
compound semiconductors is due to their better electron mobility compared to the single
element semiconductors The term ldquomobilityrdquo in the semiconductor industry refers to the
easiness of movement of charges in many directions inside a crystal In fact it is
determined by the access resistances values with saturated velocity under certain values
of electric fields (bias) the higher the electric field the faster is the carrier movement in
the crystal Figure 21 shows the electron mobility and band gap for the most common
31
group III-V compound semiconductors Besides higher mobility III-V compound
semiconductors also have light-emission capability and are suitable for bandgap-
engineering techniques
The work on III-V compound semiconductors mainly on GaAs FETs led to a new
change for the whole RF electronics industry For example in 1966 the first GaAs
MESFET was invented[21] and achieved a maximum operating frequency of operation
of 3GHz [22] Three years later the frequency increased to 30GHz [23]
Figure 21 III-V compound semiconductors mobility and band gap[24]
With better features in terms of having a higher electron mobility compared to Si
electronic devices based on III-V materials developed rapidly This attracted attention in
many aspects especially in military radar application electronic warfare system missile
guidance control electronic for smart warfare system and secure communication To be
specific those demands were fulfilled through the application of microwave mixer and
detectors [25] which were achieved based on Schottky barrier diodes and FETs
However these applications remained largely as niche markets for use only in military
and exotic scientific projects until 1980 In addition to the microwave industry two
important diodes that played a large role in very high-frequency power source namely
the Gunn diode and the Impact Avalanche and Transit Time (IMPATT) diode which
were discovered in the 1960s[26]
100
1000
10000
100000
0 05 1 15
Bu
lk M
ob
ility
(cm
2 V
-1 s
-1
BandGap (eV)
InS
b
InA
s
Ge
Ga
Sb
In
GaA
s
Si
GaA
s
InP
32
Furthermore the invention of Molecular Beam Epitaxy (MBE) growth technique at
the beginning of 1970s has enhanced the full potential of the III-V compound
semiconductors[27] This technique has led to the formation of a new class of materials
and heterojunction device with high-quality interfaces and accurate control of the
thickness during growth[28] The advancement of material engineering that tailored the
III-V compound semiconductor with MBE effect has been beneficial for both three-
terminal and two-terminal devices As a result of this more advanced devices in both
electronics and optics were developed such as quantum well (QW) laser Resonant
tunnelling diode (RTD) high electron mobility transistor (HEMT) and many more[29]
The aim was to achieve high-speed devices transporting data at high data rates and
robust devices These devices promised an excellent option to conventional transistor
(three terminal devices) in high-frequency systems especially in the terahertz (THz) or
Millimetre and sub-millimetre wave regions [30]
One of the promising diodes that received a lot of attention is the resonant
tunnelling diode (RTD) which was first described in 1974 by Chang [31] This device
which consists of a double barrier and one quantum well is the classical tunnelling diode
Due to its good symmetrical non-linearity in its current- voltage characteristic it can be
exploited for signal generation and detection However the main focus of RTD to date
has been in the generation of continuous wave (CW) ultra-high frequency and to a lesser
extent in detection Therefore other tunnelling based diodes were developed specifically
for detection purposes which are the main foci of this work The PDB and ASPAT
diodes are the workhorse candidates for detection purposes Most of these are built based
on group III-V compound semiconductors [32]
Unlike the Very Large Scale Integration (VLSI) market ie CMOS for personal
computer (PCs) the RF electronic device for civilian application reached the consumer
market only in the late 1980s through satellite television with operating frequencies
around 12GHz [19] Since then many RF application have been deployed on the mass
market depending on their operating frequency such as 09GHz ndash 25GHz for wireless
communication 20GHz to 30GHz for satellite communication 77GHz for car radar
systems and above 90GHz for different sensor applications Utilising GaAs as the main
material RF devices have become the key underpinning components for modern
33
communication systems As a result in 1998 the volume production of mobile phones
was greater than that of PCs for the first time in history Presently production is being
made for devices like smartphones cellular phones mobile internet access and new
communication services and tablets
The development of the RF field is never ending More and more improvements are
being made especially through the design and fabrication of oscillators and detectors
which are mainly built based on group III-V compound semiconductors When RF
devices were used by the military (in the 1970s to 1980s) cost was not a concern
However after getting into civil application market (ie in the 1990s) the most frequent
issues highlighted were performance and cost[19]
The ability to generate or receive high operating frequencies with high power large
bandwidth and high sensitivity is an indicator for a good performance of RF devices
(depending on specific applications) For example the highest room temperature based
oscillator of up to 186 THz was achieved in thin well AlAs-InGaAs RTD by Professor
Masahiro Asada from Tokyo Institute of Technology [33] An excellent review on THz
sources can be found in [34] For ultra-high frequency detector and mixer applications
the two terminals RF device that is mostly used is the SBD In 1996 the highest cut off
frequency achieved by a mixer utilizing the SBD was about 5THz[35] and this has kept
increasing ever since The factor that motivates the development of THz devices is the
requirement to have a compact coherent source in the THz range Undoubtedly in the
future there will be very exciting times for enthusiasts of terahertz sources and receiver
as new generations of compact broadband and tuneable solid source device based on
advanced compound semiconductor are developed
23 The Concept of Heterostructures
A III-V compound semiconductor is mostly grown on a single semiconductor
substrate forming a layer called epitaxial heterojunction layer It is a starting point and
the key feature that brings the idea of realising the most advanced semiconductor
devices currently being developed and manufactured by combining several epitaxial
semiconductors [36-38] Heterojunctions have the capability of manipulating carrier
transport ie electron and holes transport in crystal separately unlike homojunctions
34
This has resulted in the successful development of new devices for high-speed and high-
frequency applications as well as optical sources and detectors [37] This section will
discuss lattice matched material pseudomorphic material hetero-junction band
discontinuities and quantum wells
231 Homojunctions Heterojunctions and Band Discontinuities
The term homo-junction refers to the interface between identical semiconductor
materials that have different polarity ie p-type or n-type but similar in energy gap This
phenomenon is usually applied in forming p-n junction diodes and can be understood by
referring to Figure 22 below
Figure 22 illustration of Homojunctions band structure material before (left) and after (right)
equilibrium
The materials A and B which have similar bandgap (Eg) and different dopant
types ie p-type and n-type will have their Fermi levels (Ef) closer to the valence band
(EV) and conduction band (EC) respectively before ldquothermal equilibriumrdquo Once
equilibrium is achieved Ef of both p-type and n-type will be aligned causing band
bending of EC and EV As a result a built-in electric field is introduced (via diffusion of
carriers) for both holes and electrons and forcing them to move in one direction
On the contrary a heterojunction occurs when the interface between two
semiconductor materials with different bandgap energy are brought together (ie large
energy band gap material combined with a low band gap one eg wide band gap AlAs
and narrow bandgap GaAs) This results in a steep band bending which leads to the
formation of energy band discontinuities at the junction as shown in Figure 23 In a
semiconductor heterojunction the most important parameter is the band gap energy
EC
EV
Ef
Eg
p-type E
g
n-type
EC
EV
Ef
Material A
p-type
n-type
Material B Material A Material B
35
associated with each material in the structure where the degree of discontinuity can be
utilised in varying the carriers transport properties as well as the quality of the junction
depending on the interest of the designer This leads to flexibility in tailoring device
characteristics leading to vastly improved performance of the device
Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium
Based on Figure 23 above Material A indicated with blue line is a large band
gap energy material and Material B highlighted with the red line is a low band gap
material EV represents the valence band EC the conduction band and Ef is the Fermi
level of the materials Alternatively the two materials band discontinuities are denoted
by ΔEC for the conduction band and ΔEV for the valence band χ and Eg represent the
electron affinity and band gap energy respectively
At some point where by the Fermi energy of both semiconductor materials are levelled
the structure would have reached its thermal equilibrium The band gap of materials A
and B have a discontinuity at the interface (ΔEg) of these two materials In general this
is given by
120549119864119892 = 119864119892119860 minus 119864119892
119861 (21)
Furthermore when thermal equilibrium is achieved ΔEg is then divided between
conduction band and valence band discontinuities (ΔEC and ΔEV respectively) at the
material A and B junction interfaces Their relationships can be expressed as
EC
A
EV
A
Ef
A
Eg
A
Material A Material B
χA
χ
B
ΔEC
ΔEV
Ef
B
E
g
B
EC
B
EV
B
EV
A
χA
ΔE
C
ΔEV
EC
A
Ef
EC
B
EV
B
χB
Material A Material B
Vacuum
Level Vacuum
Level
36
∆119864119862 = 120594119860 minus 120594119861 (22)
∆119864119881 = (119864119892119861 minus 119864119892
119860) minus (120594119860 minus 120594119861) (23)
∆119864119892 = 119864119892119860 minus 119864119892
119861 = ∆119864119862 + ∆119864119881 (24)
However these relationships which were introduced by Anderson can only offer an
approximation In practice the results are always different since dislocation and
interface strain occur at the junction Therefore precise control during epitaxial growth is
always required and growth technologies such as MBE are employed In due course the
band gap discontinuity can be further exploited by using different types of material
combination Examples are GaAsAl052Ga048As and In053Ga047As In052Al048As [39]
232 Lattice-Matched and Pseudomorphic Materials
As discussed earlier a heterojunction happens when any two different
semiconductor materials that have different bandgap are joined together At the atomic
level both materials often differ in lattice constant The easiest way to explain this is by
setting the formation of heterojunction which can be separated into two types lattice
matched and lattice mismatched (pseudomorphic)
2321 Lattice Matched Systems
To create discontinuities for use as a high-performance device the combination of
semiconductor materials is essential Selecting the appropriate materials that have
similar or very close lattice constants to combine is crucial to avoid disruption at the
atomic level heterojunction interface Figure 24 shows that the lattice constant of a
material A ie substrate (aS) and material B ie deposited over layer (aL) are identical
or very close and their surface atoms are perfectly matched This scenario is known as
lattice matching
37
Figure 24 Lattice Matching for both materials when aL=aS
As can be seen in Figure 25 while there are restricted binary materials available to
form good heterojunction interfaces it is possible to combine semiconductor materials in
binary ternary and quaternary forms to allow the formation of a variety of lattice-
matched heterojunction interfaces The examples of materials that have successfully
been alloyed are In053Ga047As In052Al048AsInP and GaAsAlxGa(1-x)As (x=0 to 1)
Even though the materials system hetero-junction of these materials has close lattice
constant value their band-gap will experience an abrupt variation
Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40]
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
38
The existence of binary ternary and quaternary semiconductors formed by alloying
semiconductors has expanded the opportunity for heterojunction formation in devices
The alloy semiconductor which is produced by the combinations of two semiconductors
A and B has a lattice constant that obeys Vegardrsquos Law as follows
119886(119886119897119897119900119910) = 119909119886119860 + (1 minus 119909)119886(119861) (25)
For the alloy the band gap normally follows the virtual crystal approximation
119864119892(119886119897119897119900119910) = 119909119864119892(119860) + (1 minus 119909)119864119892(119861) (26)
Table 21 shows the list of the semiconductor alloy band gap and lattice constant for
common binary and ternary for group III-V compound semiconductors[41]
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary compound
semiconductors a room temperature [41 42]
Alloy Lattice constant a(Aring) Band gap EgeV)
AlAs 5661 2239
AlSb 6136 1581
GaAs 5653 1424
GaN 3189 34
InAs 6058 0417
InP 5869 1344
Al052Ga048As 5657 2072
In053Ga047As 5868 0773
In052Al048As 5852 1543
39
2322 Pseudo-morphic Materials
The other scenario is when two different materials with different lattice constants
are brought into contact The observation can be made at the atomic level where the
atom will try to match each other as shown in Figure 26 below
Figure 26 Lattice mismatched material
In fact for both situations (ie lattice matched and lattice mismatched) the atom of
the material at the hetero-interface will change their position to maintain the geometry of
the lattice Due to distortion at this atomic level a strain is then induced at the hetero-
interface In order to form a good hetero-junction interface the strain must not exceed a
certain specific critical value which will cause crystal dislocations to occur The result of
crystal dislocation is generally bad as it will affect the carriers which will be
concentrated in the defect area thus degrading the carriersrsquo mobility This then makes
the overall function or performance of the device to become poor
Nowadays the Molecular Beam Epitaxial (MBE) technique is able to grow epitaxial
layers of mismatched semiconductor layers profile ie mismatched in their lattice
constant (aLneaS) The growth method works when the grown epitaxial layer assumes the
lattice parameters of the layer it is deposited on Nonetheless the layers must be kept
within a certain limit and the deposited layer must be thin enough to avoid defect or
dislocation formations This new layer known as a ldquopseudomorphicrdquo material will alter
its original crystal structure and physical properties
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
40
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and (b) tensile
strain [1]
Figure 27 shows material A in which the pseudomorphic materials can be related to
two situations compressive and tensile strain The compressive strain occurs when the
deposited layer has a larger lattice constant than the substrate (aL gtaS) while tensile strain
happens when the deposited layer has a smaller lattice constant than the substrate
(aLltaS) These leads to aL either to compress or stretch to fit aS respectively Note that
the pseudomorphic layers can only be grown to a certain critical thickness hc From
Figure 27 the strain between the substrate and the deposited epitaxial layer is given by
휀 =119886119871 minus 119886119878
119886119878 (27)
Where Ɛ is strain between two layers aL is lattice constant of the deposited layer and
aS is lattice constant of the substrate layer The concern in deposition of the over layer is
to avoid dislocation occurring at the interface if there is too much strain at the junction
The strain is naturally influenced by the thickness of the deposited layer and thus the
thickness of growth must be controlled below the critical thickness hc which is
expresses as
(b)
41
ℎ119888 =119886119904
2Ɛ
(28)
Moreover one needs to appreciate that even though the crystal structure and their
physical properties change the total energy within the unit cell is maintained This is
possible by distortion of the deposited layer in the direction perpendicular to the growth
direction while leading to lattice matching in the lateral plane Example of lattice
matched materials is GaAsAlAs and pseudomorphic material is In08Ga02AsInP
233 Quantum well and 2DEG
A typical application of heterojunction interface is one in which utilises ΔEC and ΔEV to
form barriers for electrons and holes One example of barriers that confines these
carriers is known as a Quantum Well (QW) A QW is a layered semiconductor usually
very thin ie about ~ 100 Aring thicknesses in which many quantum mechanical effects can
occur It is formed by a thin layer of a low bandgap energy semiconductor material eg
GaAs sandwiched between two similar large bandgap energy semiconductors eg AlAs
or AlGaAs The growth technique to achieve thin layers of QW is usually MBE The
benefit of this method is that it allows the formation of heterojunction with very thin
epitaxial layer
Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg GaAs (a)
Structure (b) energy band diagram and (c) Conduction band diagram when AlGaAs is n-doped[43]
42
The thickness of the layer that can be achieved can be as thin as the electron mean free
path (De Broglie wavelength) which is around 100 Aring to 300 Aring [44] The expression for
the De Broglie wavelength is given by
120582 = ℎ120588frasl (29)
Here h and ρ are Planckrsquos constant and momentum of the electron respectively Figure
28(b) illustrates a quantum well formation in abrupt semiconductor interfaces It can be
observed that the heterojunction boundary will experience discontinuities at the edges of
the conduction band and valence band with a quantum well generated for the carriers
(both electron and holes) The quantised energy sub-bands in the quantum well structure
in Figure 28(b) can be determined from [43]
119864 = 119864119899 + (
ℏ2
2119898lowast) (119896119909
2 + 1198961199102)
(210)
Where 119864119899 = (ℏ21205872
2119898lowast ) (119899
119871)2
and n is the energy level index that can be n=1 2 3hellip
The dopants in a semiconductor with large band gap layers may supply the
carrier to the quantum well and this occurs when the base or bottom of the quantum well
is lower than the Fermi Level and hence the high energy donors will go down to the
well therefore creating a Two-Dimensional Electron Gas (2DEG) In the 2DEG the
electrons and holes move freely in the quantum well in the plane perpendicular to the
growth direction however they are not capable of moving in the crystal growth
direction (confinement direction)[45 46] The 2DEG phenomena can be seen in Figure
28(c)
24 Metal-Semiconductor Contact
A semiconductor device is incomplete if there is no connection between the
semiconductors and the outside world A metal which is usually gold (Au) or gold
germanium (AuGe) is diffused into the semiconductor to allow for electrical connection
from the outside world to the semiconductor and vice versa The metal-semiconductor
contact can be either a Schottky contact or an Ohmic contact The Schottky contact is a
43
rectifying contact while the Ohmic contact is a contact that provides a low resistance
path between semiconductor and metal
241 Schottky Contact
The Schottky contact is basically a metal contact to the gate to enter a region or
channel in a transistor Figure 29 shows a schematic band diagram of a metal-
semiconductor contact before and after contact (Schottky-Mott concept)[47]
Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact
In Figure 29 the work function of the metal is represented by qm while the
semiconductor work function is qS The qχ is the energy difference of an electron
between the vacuum level and conduction band edge ie known as the electron affinity
and qVn is the difference between the conduction band and Fermi level in the
semiconductor EV EC Ef is the valence band energy conduction band energy and the
Fermi level respectively
The metal and semiconductor are brought together as showed in Figure 29(a)
both materials are at steady state However when the metal and semiconductors are in
contact as illustrated in Figure 29(b) the electrons that flow from the conduction band
in the semiconductor into the lower energy state of the metal will cause the Fermi level
to be aligned in thermal equilibrium Due to this process the positive charge donor is
trapped in the semiconductor interface hence forming a depletion region Xdep
Thereafter the upward bending of the energy in the semiconductor takes place On the
qχ(s)
Eg(s)
Vacuum Level
EV
EF(m)
E
F
EC
qϕ(m)
qϕ(s)
Metal Semiconductor
qVn
qϕB
qϕ(s)
qVbi
X
qχ(s)
Eg(s)
Vacuum Level
EV
EF
EC
qϕ(m)
Metal Semiconductor
Xdep
(a) (b)
44
other hand the negative charge (electron) will be accumulated within a narrow region in
the metal interface The existence of two different charges at the metal-semiconductor
boundary generates an electric field This leads to a potential barrier qB as seen by
electrons in the metal moving into the semiconductor and a built-in potential qVbi as
seen by electrons in the semiconductor trying to move into the metal
The built-in potential qVbi is defined as follows
119902119881119887119894 = 119902empty119861 minus 119902119881119899 (211)
The barrier height empty119861 in the ideal case is specified by the dissimilarity between a metal
work function empty119898 and electron affinity of the semiconductor
119902empty119861 = 119902empty119898 minus 119902120594 (212)
Referring to Eq (212) above the barrier height empty119861 rises linearly with the metalrsquos work
function empty119898 Nevertheless this is only in theory as the presence of localised surface
stated at the edges causes empty119861 to become unresponsive to the metal work function
Consequently Eq(211) is then reordered to match the difference in metal and
semiconductor work function Thus the new equation becomes
119902119881119887119894
= 119902(120601119898 minus 120601119904) (213)
A Schottky contact appears when a metal-semiconductor contact has a large
barrier height (B ge kT) and low doping concentration in the semiconductor (ND le NC) In
the case when the metal-semiconductor contact is under some bias eg reverse bias the
semiconductor will react to a positive bias according to the metal by a voltage V=-VR
This condition will affect the built-in potential and leads to increase from Vbi to
(Vbi+VR) thus increasing the barrier height empty119861 in the semiconductor as well
Consequently electrons are less able to flow from the semiconductor and cross into the
metal Therefore the current flow will be very small This phenomena is shown in
Figure 210(a)
45
Figure 210 Energy band diagram of Schottky contact on n-type material under (a) reverse and (b)
forward bias
As can be seen from Figure 210(b) when a forward bias is applied the semiconductor
is biased negatively with respect to the metal by a voltage V=Vf This will result in a
reduction in built-in potential from Vbi to Vbi-Vf The electrons in the semiconductor will
lower the barrier height and a lot of electrons will escape into the metal causing a large
current to flow Thus a large current flow in the forward direction compared to the
reverse direction Essentially this is the origin why the Schottky contact is named a
rectifying contact [48 49] For the metal side both forward and reverse biases applied
do not affect the barrier high empty119861 because there is no voltage drop there
In this system the electron and holes are transported by a phenomenon called
Thermionic Emission (TE) which happens when the semiconductor layer is lightly
doped Nd lt 1x1017119888119898minus3 The electron will only be thermionically emitted into the metal
when the energy is higher than the potential barrier[50] There is another phenomenon
called Thermionic Field Emission (TFE) which happens when the potential barrier
thickness is very thin (thin enough) to allow the electron to tunnel through the barrier
This will be discussed in the next section as this phenomenon leads to the formation of
an ohmic contact
(a) (b)
46
242 Ohmic Contact
Basically an ohmic contactrsquos purpose is to provide a low resistance path from
the semiconductor to the outside world It is different to a Schottky contact as it is a non-
rectifying contact and does not control the current flow the I-V characteristic of an
ohmic contact is linear in both forward and reverse directions (equality in current flow)
The ohmic contact also has a small voltage drop across it compared to the voltage drop
across the device
If a metal and semiconductor are bought together unavoidably a Schottky
contact will be formed Therefore to create an ohmic contact some techniques to reduce
barrier height and width of the depletion region must be used ie increase Nd In carrier
transport theory there are three mechanisms of carrier transport across the barrier
Firstly the Thermionic Emission (TE) which happens when the carries are excited to
overcome the barrier when the thermal energy is present Secondly the Thermionic
Field Emission (TFE) occurs when the electronholes have enough energy to tunnel
through an adequately thin barrier and some has overcome the low barrier at the top
Finally the Field Emission (FE) which results when carriers can tunnel through the
entire barrier The FE is the most favoured mechanism in the ohmic contact approach
[51]
From the three mechanisms above the current can be determined by the following
equations
1) Current in Thermionic emission (Figure 211(a))
exp (empty119861)
119896119879
(214)
2) Current in Thermionic field emission (Figure 211(b))
exp [
(empty119861)
11986400119888119900119905ℎ11986400
119896119879
] (215)
3) Current in Field Emission (Figure 211(c))
exp (empty119861)
11986400
(216)
47
Where k is the Boltzmann constant T is the temperature 11986400 is the tunnelling parameter
and is related to the doping concentration radic119873119863 The barrier height is denoted by empty119861
Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping concentration
ND (a) Low (b) Intermediate and (c) high
Figure 211 shows that the carrier transport mechanism is varied by the doping
concentration (ND) As can be seen from Figure 211(c) the doping concentration here is
the highest and influences the depletion region width Xdep to become smaller Therefore
Field Emission (FE) becomes dominant This FE method is the favourite method for
ohmic contact formation [51] and will be utilised in the fabrication carried out in this
work
In fabricating practical devices the ohmic contact is often split into two types
alloyed and Non-Alloyed The difference between the two is that the alloyed type is used
when the semiconductor is doped with a low doping concentration ie less than
1x1018119888119898minus3 while the Non-Alloyed is designed for heavily doped semiconductors with
more than1 times 1019119888119898minus3 doping
The alloyed ohmic contact requires thermal annealing to have a good performance
for electron transport In multi-layer metals one of the metals has the role of donor or
acceptor which is used to increase the doping concentration of the semiconductor If a
temperature anneals eg 420˚ Celsius is applied the metal will diffuse into the
semiconductor and carry the dopant into the semiconductor Therefore a heavily doped
region will be formed and the depletion width becomes narrow establishing the ohmic
contact The key example of this is the usage of the Gold-Germanium-Nickel (Au-Ge-
Ni) alloy where the Ge is the n-type dopant [52] which diffuses into the semiconductor
(a) (b) (c)
48
and perform atom replacement in the semiconductor ie in GaAs it replaces Ga On the
other hand the Non-Alloyed does not require any thermal annealing as it already has a
very high doping concentration and will automatically reduce the depletion region width
The Non-Alloyed ohmic contact has some advantages such as reproducible contact
reduced processing time and good uniformity [53]
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work
In this section some historical background of the Asymmetrical Spacer-layer
Tunnel (ASPAT) diode is given Since this is the first thesis reporting about this new
device it is worth to mention some historical background about this tunnelling diode
The ASPAT was first proposed by a group of scientists from General Electrical
Company (GEC) in 1990[16] The works led by Richard T Syme and assisted by
Michael JKelly Angus Condie and Ian Dale initiated the idea of launching a new type
of tunnel diode The idea managed to attract the interest of many parties following the
development of resonant tunnelling diode (RTD) which earlier had shown a promising
weak temperature dependence [54] However the interest in RTD is mainly limited to
microwavesub-millimetre wave generation For THz detection the requirement is to
have a significantly asymmetric IV characteristic Given this the ASPAT which has
only a single energy barrier and most importantly weak temperature dependence and
large dynamic range would be a promising candidate for this application
The development of ASPAT is a kind of reverse engineering since it was built
purposely to replace the earliest receiver diode especially the Schottky Barrier Diode
(SBD) which has strong dependence on operating temperature [55] From the time when
it was first revealed a lot of works have been done to realise this most sophisticated
tunnel diode The first attempt which was reported in [56] was meant to gather some
insights into the device by using the well-known Schrodinger and Poissonrsquos equations
for simulation The second attempt on the other hand was directed to physically grow
and fabricate the device Here the real problem occurs At the first stage of qualifying
this device it was found not to be manufacturable Since then a new tunnel diode
structure based on GaAsAlAs materials system was built by both MBE and MOCVD
Its microwave performance was then tested at 94GHz [18] The same paper also
49
reported performance comparisons between ASPAT and another microwave diode ie
Germanium Backward Diode (GBD) PDB and SBD
Work on these devices stopped due to the inability to commercialise the ASPAT
and other tunnel based devices [57-60] The problems associated with low-cost
manufacture of tunnel diodes are due to firstly the thickness of the AlAs barrier layer
the dependence of tunnelling probability (electron) through a single barrier is
exponential and varies by a factor of more than 350 for one monolayer change in the
AlAs barrier thickness[61] The tunnelling of the electron through a barrier is
proportional to the current through a barrier as a function of a bias across the AlAs
barrier[62] Secondly the bandgap which is predominantly happens to be a ternary alloy
with relative composition ie AlxGa1-xAs Here the x can vary the bandgap in the
semiconductor layer For the ASPAT a 1 change in x results in a 30 change in the
current[62] To design an ASPAT for microwave and THz applications the designer
often allows at most plusmn10 variation of the absolute current through a specific diode at a
pre-identified bias This implies that within a wafer the uniformity that the ASPAT must
achieve is less than plusmn01 monolayers while between wafer to wafer the reproducibility
in barrier thickness in average must be identically controlled[63] This explains why at
the qualification stage of investigating ASPAT there was a need to focus on
GaAsAlAs-based material to diminish further errors because of the change in x This
type of work on ASPATs has been carried out by other co-workers at Manchester and
Cambridge
Thereafter the work then focused on repeatability and manufacturability tests
These result in many attempts being carried but failed with unacceptable between wafer
to wafer reproducibility [61 64] The development of reproducibility and repeatability of
the ASPAT was pursued for over 10 years until precise control of the growth of the
thickness AlAs layer was finally achieved using MBE[65] [66 67] This achievement is
confirmed by a current density produced which varied by less than plusmn30 indicating that
the reproducibility of AlAs barrier of the order of plusmn 02 monolayers A final step to
achieve the level control for the ASPATrsquos AlAs barrier thickness was carried out and
resulted in a 1 standard deviation of the IV characteristics for both within a wafer and
different wafer (2 inches wafer size)[17] In the early stage of this work some
50
repeatability and manufacturability test was also carried out Once this vital step is
accomplished further investigation on the ASPAT was made most recently and which
will be covered in this thesis ie temperature independence[68] and new ASPAT
types[69] characterisation to achieve smaller device RF measurement and development
of THz detectors The material systems that have been investigated so far are
GaAsAlAs and InGaAsAlAs both in the ManchesterCambridge group
Recently the ASPAT was commercialised by Linwave Technology as a wideband
zero-bias detector diode This was done in April 2016 Although it is now on the market
the ASPAT remains immature in term of research and development A lot of work is still
required to enhance the device ie working at the sub-millimetre wave using ternary
material etc
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics
The basic building block of the ASPAT diode is based on heterojunction of three
multilayer semiconductor structures which have two different band gaps The structure
comprises a thin layer of wider-gap semiconductor sandwiched between two
semiconductors with narrower-gap forming a tunnel barrier The basic principle of the
ASPAT device is based on the exploitation of quantum mechanics theory using
heterojunctions interface According to quantum mechanics theory moving particles
(electrons) with less energy than the barrier height have a probability of appearing on the
other side of the barrier by a tunneling through it This can be achieved in conditions
where the barrier must be very thin (~ 10 monolayer ) This is in contrast to classical
physics where a particle must have kinetic energy at least slightly greater than the
potential barrier height in order to overcome the barrier otherwise the probability of the
particle to appear on the side of the barrier is zero
Since the ASPAT diode operation is based on tunnelling through a barrier one
needs to know that the tunnelling mechanisms can be classified into two types[44]
intraband and interband The latter is described as tunnelling that occurs from
conduction band to valence band (electron) and valence band to conduction band (holes)
This normally happens in bipolar device ie p-n junction diode which has n-type and p-
type doped regions On the other hand intraband refers to tunnelling which occurs when
51
electron tunnel from the conduction band of a semiconductor to the conduction band of
its neighbouring semiconductor The same thing happens to the holes in the valence
band The device with this type of tunnelling is normally a unipolar device which is
either p-type or n-type doped The ASPAT diode can be considered as a device that is
based on intraband tunnelling mechanism Therefore the focus will be entirely based on
its principles
261 Principle of Quantum Tunneling
Generally all tunneling diodes obey the concept of quantum mechanical
tunneling Quantum mechanical tunneling is a phenomenon where a particle is able to go
through an energy barrier higher than the kinetic energy of the particle and if it is thin
enough compared to the de Broglie electron wavelength (λ) If the electron wave is
greater than the barrier the probability of the wave to occur at both side of the barrier is
higher
Figure 212 Classical view of whether an electron is can surmount a barrier or not Quantum
mechanical view allows an electron to tunnel through a barrier The probability (blue) is related to
the barrier thickness
For the case of classical physics (Figure 212(a)) the particles can be confined by
energy barriers of a semiconductor if their kinetic energy is less than the barrier energy
The particles thus require higher kinetic to escape to other states this phenomenon is
called thermal emission In quantum mechanics (Figure 212(b)) the particle is
described in two ways as a wave and as a particle If the particle moves like a wave it
will carry all the waversquos properties Therefore it will not brusquely end up at the
En
erg
y
(a) Classical view (b) Quantum mechanical view
En
erg
y
En
erg
y
52
boundary of the energy barrier Hence when the particles collide with the barrier
(incidence) there will be a probability of penetrating the barrier if the barrier is thin
enough and has a finite height For thicker barrier the probability of a wave that can be
found on the other side of the barrier is very small However the possibility of the
electron wave to appear on the other side of the barrier is increased by thinning the
barrier The potential barrier of semiconductor material technology can be determined by
using Homojunctions structures with different doping profile This will result in a
difference in band alignment and multilayer heterojunction structure (different
semiconductors have different band gap) which includes semiconductors insulators and
conductors (metals)
The easiest way to explain the phenomenon is by considering a potential barrier
Epot(x) with barrier height E0 energy bigger than the total energy E as shown in Figure
213 the potential energy occurs in a finite space between 0ltxlta and is 0 outside
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave function[70]
The electron outside the region of the potential barrier (xlt0 and xgta) is free to
move The effective mass of the electron is different inside and outside of the barrier in
real tunneling devices when implemented using semiconductor heterostructures The
quantum mechanical equations predict the wave nature of matter which states that matter
unveils wavelike properties under some conditions and particle-like properties under
other conditions The wavelike properties as described by the Schrodinger Formula of
E0 Transmitted Ψ = 119862119890minus119894119896119909
Incident Ψ = 119860119890119894119896119909
Reflected Ψ = 119861119890minus119894119896119909 Ψ = 119863119890minus119894119896119909
0 a
E
x
V(x
)
53
quantum mechanics represent a particle penetrating through a potential barrier most
likely as an evanescent wave coupling of electromagnetic waves[44]
To start the calculation of the tunnelling probability the Schrodinger equation is given
by
119894ℏ
120597
120597119905Ψ(119903 119905) = ΨΗ(r t)
(217)
Where ℏ is Planckrsquos constant (662606957 times 10119890minus341198982119896119892119904
2120587frasl ) Ψ(119903 119905)is the wave
function at position r and time t Η is the Hamiltonian operator given by
Η = minus
ℏ2
2119898nabla2 + 119881(119903 119905)
(218)
Where 119881(119903 119905)is the potential energy which is dependent on space and time 119881(119903 119905) is
considered zero for a particle traveling in free space without any potentials The plane
wave with vector r and t is given by
Ψ(119903 119905) = 119890119894(119896119903minus120596119905) (219)
This equation satisfies Eq (217) above under the condition where the particle is
travelling in free space without potential k is the wave vector which is equivalent
to2120587120582frasl and the angular frequency 120596 is 2120587 multiplied by the frequency
In the case of tunneling through a potential barrier the method of separation of
variables is used to simplify the problem as in the equation below
Ψ(119903 119905) = 119877(119903)119879(119905) (220)
It is assumed that the problem above is divided into time-dependent and time-
independent parts 119877(119903) is the spatial component and 119879(119905) is the time-based component
of the wave function The time dependent problem as shown above in the Schroumldinger
Equation (1) can easily be solved by filling up all the finite parameters The solution of
54
the time-independent part gives the tunneling probability For the one-dimensional (1D)
time-independent Schroumldinger equation[44]
119864120595(119909) = minus
ℏ2
2119898
1198892
1198891199092120595(119909) + 119881(119909)120595(119909)
(221)
E is the total energy and 120595(119909)is the spatial component of the wave function along the x
axis The combination to the wave function is given by
120595(119903 119905) = 120595(119903)119890minus(
119894119864119905ℏ
)
(222)
The time-independent plane wave solution of 120595 = 119890119894119896119909 satisfies the equation (221) for
any constant potential V0 in space Plugging in the wave solution yields the condition
that
119896 = radic2119898lowast(119864 minus 1198810)
ℏ2
(223)
Referring to Figure 213 also the barrier with exact rectangular shape with height E0 and
width W the solution of the wave functions and tunneling probability can be extracted
by using the below equation [44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2= [1 +
11986402 sin ℎ2 (119896119882)
4119864(1198640 minus 119864)]minus1 asymp
16119864(1198640 minus 119864)
11986402 exp(minus2radic
2119898lowast(1198640 minus 119864)
ℎ2119882)
(224)
For more complex barrier shape Wentzel-Kramers-Brillouin has simplified the
Schrodinger equation for tunneling probability of carrier which becomes[44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2asymp 119890minus2int |119896(119886)|119889119886
1198860 asymp 119890
minus2int radic2119898lowast
ℎ2 [119880(119886)minus119864]1198891198861198860
(225)
55
This means that the incident electron has a finite probability T of tunneling
through the potential barrier and this leads to the concept of tunneling probability as well
as a tunnelling current Therefore this becomes the basis of tunneling phenomena and
thus all devices which are related to tunneling can be modelled and analysed based on
this basic example The tunneling phenomenon is a majority-carrier effect and the
tunneling time is set by the quantum transition probability per unit time (which is on the
order of picoseconds) rather than the transit time concept [44 71] This enables the
tunneling devices to work at a much higher switching speed They can also be used in
high-frequency applications such as microwave circuit and high-speed oscillators
262 ASPAT Structural Parameters of GaAsAlAs materials System
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in this study
Conduction band profile
56
The core materials that make up the ASPAT diode in this work is based on
heterostructure of group III-V compound semiconductors Such materials are chosen due
their mature excellent properties and their band gap which can be tailored to fit the
desired design as well as to improve the carrier mobility In this work the primary layers
that form an ASPAT diode are very thin pure Aluminium Arsenic (AlAs) of thickness
ten monolayers buried in between dissimilar thickness of pure Gallium Arsenic (GaAs)
layers as can be seen in the red circle in Figure 214 above These two GaAs layers are
known as spacer layer which normally have a ratio of 401 or 201 in thickness The
asymmetrical spacers layer and the thin barrier in such arrangement lead to an
asymmetric current-voltage characteristics as proposed firstly by Syme and Kelly[15]
To examine and investigate this GaAsAlAs ASPAT structure in term of electrical and
RF characteristics the device have been grown according to Table 22 below
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work
Material Doping (cmminus3) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018 3000 142
Emitter GaAs (Si) 1times1017 400 142
Spacer GaAs Undoped 50 142
Barrier AlAs Undoped 28 283
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017 400 142
Ohmic Layer GaAs (Si) 4times1018 4500 142
Substrate GaAs - 650 microm 142
The arrangement of the multi-layers that form a lattice matched GaAsAlAs ASPAT
diode can be transformed into band structure profile view for easy understanding The
conduction band profile at equilibrium is as sketched in Figure 214 As can be seen in
the Figure 214 the ASPAT diode is generally a heterojunction multilayer structure
tunnelling diode
57
Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27]
The generic structure of ASPAT diode which is shown in Figure 215 above with a
schematic band structure comprises the following (starting from the top)
(1) A thick layer of heavily doped n++
about 4e+18cm-3
of GaAs with a thickness of
approximately 300nm
(2) An intermediate layer of lightly doped n-type about 1e+17cm-3
of GaAs with
thickness of approximately 40nm
(3) A spacer layer not intentionally doped (NID) GaAs with thickness of approximately
5nm
(4) An ultra-thin layer of NID AlAs with thickness of approximately 28nm
(5) A spacer layer of NID GaAs with thickness of approximately 200nm
(6) An intermediate layer of lightly doped n+ ~1e+17
GaAs with thickness of
approximately 40nm
(7) A thick layer of heavily doped n+ about 4e+18 of GaAs with a thickness of
approximately 750nm
Each layer has its own role For instance layer (1) and (7) are used as ohmic
contacts via connection to a AuGeNiAu metal stack This explains why they are
purposely heavily doped (gt 1018
cm-3
) for better low resistance ohmic contacts Two
intermediate layers (layers 2 and 6) are used to prevent the carrier in the contact layers
from diffusing into the undoped layers The two unequal length spacer layers with ratio
58
1198971 1198972 of about 401 are used as voltage arms to yield an asymmetric current-voltage
characteristic The asymmetry means that after a positive bias is applied from the long
spacer region an accumulation layer is formed and it is deeper than that formed by the
negative bias The thin layer positioned in the middle (Layer 4) is the tunneling barrier
The performance of a single barrier ASPAT diode can be optimised depending on
the applications by appropriate selection of the material system so that the band gap and
barrier height of such material can be modified Furthermore the mobility of electron
and doping concentration of the contacts region can be tuned The parameters to tune
during the growth for instant growth interrupt time and growth temperature will also
affect the performance of this diode The key layers that will affect the performance are
the barrier thickness and the two spacer layers enclosing it The study has shown that a
one monolayer change in thickness results in 300 change in in tunneling current for a
fixed voltage point[65]
The following discussions account for the effect of the main structure of the ASPAT
which is related to their performance
2621 Barrier Thickness and height
The probability of an electron tunnelling through a barrier depends exponentially on
the width and height of the barrier as well as the energy that is incident on the barrier[72
73] All these will affect the I-V characteristic of the ASPAT diode The tunnel current is
obtained by summing over all incidents electrons energies with tunnelling probabilities
through the barrier The tunnelling varies approximately as[74]
119879 prop 119890minus120581119889 (226)
Where d is the barrier thickness and κ is defined by the expression below
120581 =
radic2119898lowast(1198810 minus 119864)2
ℏfrasl
(227)
From textbook the tunnelling probability is given by
119879(119864) = 412058121198702
[(1205812 + 1198702)2119904119894119899ℎ2119870119897 + 412058121198702]frasl (228)
Where K is expressed as
59
119870 = radic2119898lowast119864
ℏfrasl (229)
Where ℏ represents the reduced Planckrsquos constant (h2π) E and m are the electron
energy and effective mass respectively Thus by inputting appropriate value into these
equations one finds that reducing the barrier thickness by one monolayer increases the
tunnelling probability by a factor of nearly three for every electron that tunnels through
the barrier As a result the current will also increase Further it indicates that the
tunnelling strongly depends upon barrier thickness and height By contrast the current
does not strongly depend on temperature
2622 Spacer Thickness
The reason for having two dissimilar undoped spacer lengths is mainly to avoid
diffusion of dopant to the barrier and subsequent layers during growth but in the case of
the ASPAT diode the spacer can also act as a voltage arm Varying the thick spacer
layer (1198971) results in the reverse current decreasing as the layer thickness increases and
varying the thin spacer layer (1198972) will affect the forward current which increases as the
thickness reduces To obtain appropriate asymmetrical I-V characteristics one needs to
maintain an adequate ratio between these two spacer thicknesses While a too thin
1198971 results in high leakage current at reverse bias a too thick 1198972 results in low forward
current One also needs to keep it thick enough to prevent carrier diffusion
These two spacers must be kept undoped or very low doped to allow the electron
moving in the electron mean free path region as it is clear from ionised donors Under
large forward bias an accumulation layer is formed between the spacer and barrier
segment and it is more noticeable compared to the accumulation layer that is formed if a
negative bias is applied
60
Figure 216 Conduction band diagram showing band bending and 2DEG formation at the L1
spacer
Consequently a triangular well is formed which creates an emitter 2D electron gas
(2DEG) population The electrons in this 2DEG occupy the quasi-bound states which
mean high excitation energy thus allowing the electron to tunnel through the barrier as
depicted in Figure 216
In term of RF performance it is important to highlight that a thicker spacer layer
will affect the depletion region which gets wider and thus will reduce the junction
capacitance of the device as per the following expression
119862 = 휀0휀119903
119860
119889
(230)
Where A is the area of the device d is the thickness of the main device structure which
consists of spacers barrier and well layers 휀0 is the permittivity of free space and the
relative permittivity of the spacer material is denoted by εr However the intrinsic delay
time will also increase and hence degrade the device high frequency performance
Therefore optimisation through spacer thickness requires trade-off between reducing
leakage current at reverse bias and degrading device junction capacitance
GaAs
GaAs
AlAs
2DEG
Γ
X
61
263 ASPAT Electrical Parameters
The classical approach in determining the current flow through an ASPAT diode is
by solving the Schrodinger and Poison equations Prior work had been done by Syme et
al in 1991 Due to the fact that AlAs barrier is very thin tunnelling is assumed to occur
at the Gamma valley ie AlAs bandgap= 283eV (rather than X valley)[18 75] and only
from accumulation layer (2DEG)[59] Here the DC characteristic of the ASPAT diode
can be calculated by solving Schroumldinger equation with the position vector represented
by z (in this case) Thus the equation is expressed as
minus
ћ2
2nabla
1
119898lowast(119911)nabla120569 + |119890|120593(119911)120569 = 119864120569(119911)
(231)
Supposing the current is uniform across x and y planes then this can be simplified to one
dimension Therefore the 1 D Schroumldinger equations becomes
minusћ2
2119898lowast
1198892
1198891199112120595 + |119890|(120595 minus ∆120595) = 119864119911120595
(232)
Where
120595 =
120569
exp (119894119896119911119911)
(233)
where ∆120595 is the correction term which reduces the effective barrier height The
Schroumldinger equation is solved using different values for Ez thus the quantum
mechanical current density in the z-direction is now expressed as[15]
119895119911 =
minus|119890|ћ
2119898lowast(120595lowast
119889120595
119889119911minus 120595
119889120595lowast
119889119911 )
(234)
It is different for a heavily doped contact which can describe as below the envelope
functions in the left and right contacts respectively can be described by plane wave
120595119897 = exp(119894119896119897119911) + 119877 exp(minus119894119896119897119911) (235)
120595119903 = 119879119890119909119901[119894119896119903(119911 minus 120580119873)] (236)
62
In this case the left contact covers the region zlt0 while the right contact covers the
regions zgt 120580119873 Equations (35 and 36) are then inserted into Eq (34) to form the
following expression
119895119911 =
|119890|ћ1198961
119898lowast(1 minus |119877|2) =
|119890|ћ1198961
119898lowast|119879|2
(237)
Where R (Ez) and T (Ez) are the complex reflection and transmission coefficients
respectively and they are solved by using the transfer matrix method This method has
been described in reference [56] The next step is to integrate the current in the z-
direction 119895119911 for all possible Ez values Thus the expression for the current density
becomes
119895119911 =|119890|119898lowast119896119861119879
2120587ћ2int(1 minus |119877|2)
infin
0
119897119899 |1 + exp (
119864119891 minus 119864119911
119896119861119879)
1 + exp (119864119891 minus 119881|119890| minus 119864119911
119896119861119879
|
(238)
The equations above are used to calculate the current density approximation from
the ASPAT main structure (two spacer layers and one barrier) only and based on
intraband tunnelling from the conduction band profile For real fabricated structure the
calculation must take into account both intrinsic and extrinsic elements of the diode
While the latter is mostly related to the pad and probe that is used to extract the I-V
characteristic the first element mostly comes from the epitaxial layer of the ASPAT
diode itself The ASPAT I-V characteristic is shown in Figure 217 which clearly
indicates nonlinear characteristics and thus can be used for detection applications
63
Figure 217 I-V characteristics of a fabricated ASPAT diode
2631 Intrinsic Elements of the ASPAT diode
In order to extract the intrinsic electrical characteristic of the ASPAT diode a
generic structure as shown in Figure 218 is essential Two main sources of contribution
to the electrical characteristics are the interfaces of each layer and properties of the
materials themselves
Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
64
The electrical current flowing from the top contact to the bottom contact will go
through each epitaxial layer producing a close loop Each junction interface limits the
current flow and sum up the total resistance resulting in what is known as the diode
series resistance (Rs) In the ASPAT main structure there is a junction capacitance (Cj)
due to the undoped regions surrounded by heavily doped contacts thus acting as a
parallel plate capacitor The fully depleted capacitance (Cj) of the diode can be
expressed as in Eq (230)
2632 Series resistance of the ASPAT diode
The total series resistance (Rs) of an ASPAT diode can be calculated based on the
finished fabricated diode structure In general Rs depends on three contributors namely
the non-uniformities in the contact metallization the un-depleted epitaxial layer (total
thickness) on both side of the heterostructures and the resistance caused by the
spreading current from the Mesa into the much wider second contact layer ie doped
substrate or 2nd
ohmic layer[76] In fact the contribution toward building up the total Rs
solely depends on how the structure is designed In this work two types of structures
were deployed namely lateral structures and vertical structures These will be described
in the next subsection
For both types of structures the series resistance (Rs) of the ASPAT diode consists
of aspecific Ohmic contact resistance (ρcA) contact epitaxial layer resistance (Repi-
Layers) and spreading resistance (Rspr)[33 77] where Rspr is influenced by the type of
structure The specific contact resistance is obtained from Transmission Line
Measurements (TLM) of the sample The theory of the TLM will be discussed in detail
in the next section The expression for the specific contact resistance is
120588119888 = 119877119888119871119879119908sinh119889
119871119879frasl
cosh 119889119871119879
frasl
(239)
Here Rc is the contact resistance LT is the transfer length (effective length) w is the
contact pad width and d is the length of the contact pad
65
Repi-Layer is the sum of all doped layers that sandwich the main ASPAT device For
each doped layer the resistance is given by
119877119890119901119894minus119897119886119910119890119903 = 120588
119871
119860
(240)
Where ρ is the resistivity which is given by 120588 = 1
120583119899119902119873119863 L is the epitaxial layer thickness
in cm A is the device area (emitter size) micron denotes the mobility of the electron q is the
electron charge and ND is the donor concentration The spreading resistance depends on
the structure design of the device This will be elaborated in detail in the following
section
26321 Vertical structure (doped Substrate)
The XMBE307 structures were grown on n+ GaAs substrate to provide the
simplest fabrication process The cross section of the finished single diode can be seen in
Figure 219 below
Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b and h are not
drawn to scale
66
At low frequency and in a mesa that is etched into a doped substrate material the
spreading resistance can be approximated by[76]
119877119904119901119903 =120588119904
2119889
(241)
Where ρs is the substrate resistivity and d is the ASPAT diode mesa length
However the spreading resistance is increased at high enough frequencies as the skin
depth (δ) in the substrate is much lower than the effective mesa length (d) of the diode
A new spreading resistance is then calculated also based on the assumption that the skin
depth is much lower than the chip thickness (h) but much larger than the mesa length
Thus the spreading resistance at high frequency is given by
119877119904119901119903(119891) =
120588119904
120587120575[05 ln (
119887
119889) +
ℎ
119887]
(242)
Where the skin depth (δ) is taken from standard planar formula and can be expressed as
120575 = [
2120588
(120583120596)]
12frasl
(243)
Where micro is the permeability and ω is the angular frequency During DC measurement
this type of structure requires having good suction on the stage for a good contact
However for small die (15mm times15mm) the suction sometimes is not strong enough to
provide a very good adhesion to the sample Therefore another type of ASPAT diode is
deployed which is based on the lateral structure by utilising semi-insulating substrate
and both contacts are connected to probes
67
26322 Lateral structure (Semi-insulating Substrate)
Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304) The dimensions
are not drawn to scale
In order to obtain accurate measurement results so as to avoid contact errors to the
substrate between stage and Device Under Test (DUT) a lateral structure as shown in
Figure 220 above is deployed This type of design offers many advantages ie it
provides a path for on-wafer RF measurement However the proper design has to take
into account the increase in RS due to improper attention to the spreading resistance
This spreading resistance is different from the vertical structure that was discussed
above In this case it is mainly caused by a gap at the bottom contact The gap in the
horizontal direction between epitaxial layer and metal at bottom contact is denoted as D
gap in in Figure 220 Therefore Rspr for the lateral design can be expressed as [77]
119877119904119901119903 =
1
120587120590119889119866119886119860119904ln (
119886
119886119898119890119904119886)
(244)
Where σ is the conductivity between two coaxial half-cylindrical electrodes with inner
(amesa) and outer (a) rectangular length or bottom ohmic layer which is given by (σ =1
ρ) a d and amesa are the length and thickness indicated in Figure 220 above Noticeably
68
the D gap will have direct effect on the outer length (a) of the device which is also
proportional to Rspr For high-frequency operation where the skin depth is less than
d(GaAs) σ becomes
120590(120596) =
120590(0)
[1 + (120596120591119903119890119897)2]
(245)
Where τrel =microme and micro m as well as e are the mobility effective mass and electron
charge respectively It is recommended that for high-frequency applications the device
series resistance must be as low as possible
Hence for both type of structure the ASPAT series resistance is calculated based on
all the above-stated resistances and these are set by
119877119904 =120588119862
119860+ 119877119890119901119894minus119897119886119910119890119903119904 + 119877119904119901119903
(246)
The total RS can be decreased by increasing the emitter area of the diode However a
large device will not able to reach millimetre and submillimeter wave region (THz) as
the capacitance will also increase (Eq 230) Therefore both parameters will have a
trade-off between them to be able to work at ultra-high frequencies
27 Characterization of Ohmic Contacts
The semiconductor Ohmic contact can be characterised using techniques that will
be described in the following section First is the Cox-Strack technique which is
specially designed to characterise bulk type semiconductor (thick) contact resistance on
two opposite sides The detailed description of this technique can be found in [78]
Second is a technique called Four Point Probe This technique was developed in 1954 by
Valdes etel [79] to characterise semiconductor resistivity It can also be used to
characterise the contact resistance for planar type devices As this research does not
cover this method the details of the measurement can be referred to [80] Finally the
most common method which is also extensively used in this research is the standard
Transmission Line Measurement (TLM) The details of this method will be explained in
the next section There are simplified versions of the TLM method which require just
one lithography step but are nevertheless very powerful in characterising and optimising
the contact resistance known as Circular Transmission Line Measurement (CTLM)[81
69
82] However in this research this is not to be covered as the standard TLM is already
adequate for planar type devices
271 Transmission Line Measurement (TLM)
The formation of metal and semiconductor interfaces will create a contact that
becomes very important for the characterisations of any fabricated device Additionally
it enables the quality of certain process flow to be determined This interface must be
evaluated by a technique known as the Transmission Line Measurement (TLM) TLM
which was first introduced by Murrmann and Widmand [83] in 1969 underwent some
refinements by Berger [84] in 1971 The theory of the TLM can be described by
constructing a TLM structure which comprises a set of metals contact pads placed in
series on a highly doped semiconductor layer as depicted in Figure 221 The structure is
designed like a series of the islands to permit current flow in parallel to the contact pads
[80] which is a direction defined by etched patterns Each contact metal pad behaves
like a MESA which has a thickness (t) and width (W) The distance between each metal
contact pads is defined by d1 the gap between two neighbouring contact pads which are
beneath each contact pad is defined as effective length LT This will allow current flow
in and out of the subsequent neighbouring metal pad The resistance elements that will
be extracted are RA and RB which sit under the contact and in between two metal pads
These two elements represent the sheet resistance under the metal contact pad area and a
sheet resistance of the material between two metal pads
Figure 221 A simple TLM structure with effective length and sheet resistance underneath
t L
T
LT
RA R
A R
B
dn
Probe Probe
Metal Pad
GaAs
MESA
70
The basic relationship of resistance R with respect to the size of the metal contact
or in the standard transmission line can be expressed as [44]
119877 = 120588
119871
119860= 120588
119871
119905 times 119882=
120588
119905times
119871
119882= 119877119904ℎ
119871
119882
(247)
Where ρ is the materialrsquos resistivity L is the length t is the thickness W is the width
Rsh is the sheet resistance and A is the cross-sectional area of the transmission line The
unit for ρ and Rsh are Ωm and Ωm2 respectively
The total resistance RT of this structure can be taken from the sum of the two
neighbouring padrsquos resistance RA and RB In order to relate with Eq (247) above this
RT will be substituted into Eq(247) to become
119877119879 = 2119877119860 + 119877119861 = 2119877119904ℎ119860
119871119879
119882+ 119877119904ℎ119861
119889119899
119882
(248)
As suggested in [85] RshA and RshB are assumed to be identical Therefore Eq(248)
can be reorganised into specific contact resistance RC and semiconductor sheet
resistance Rsh above as 119877119862 = 119877119904ℎ119860119871119879
119882 the new equation is then
119877119879 = 2119877119862 + 119877119904ℎ119861
119889119899
119882
(249)
The common practice throughout this research is to design a TLM structure that
has a ladder structure consisting of 10 metal pads with each one measuring to a size of
100microm width and 50microm length and the space between the first and second metal pad
5microm The gap is increased after the second metal pad by a further 5microm until ten metal
pads are completed produce a separation between the ninth and tenth pad of 45microm The
TLM ladder structure as depicted in Figure 222 is supplied by a constant current of
1mA at the very left and right metal contacts by two probes This allows the extraction
of RC (Ωmm) and Rsh (Ω) instantly from such structure The potential difference
between the two adjacent metal pads is measured by another two probes and the reading
of a voltmeter is recorded The total resistance is obtained by using Ohm law where
voltage is divided by current (VI) Another voltage reading is taken for the next two
neighbouring metal pads until the largest gap is reached The readings of (conversion
71
VI) which result in the corresponding resistance RT are then plotted against spacing and
the result can be seen in the graph in Figure 223
Figure 222 Top view of TLM ladder structure use in this work
Additionally in the measurement the voltmeter used in work has a very high resistance
Otherwise there will be leakage of current occurring through the probes and cables
Therefore the parasitic resistance of the cable or connector and the probe contact can be
ignored The key parameters that can be extracted from the graph will be discussed in
the next paragraph
Figure 223 Typical plot of resistance versus TLM spacing
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50Res
ista
nce
Rn (
Oh
ms)
TLM Spacing dn (um)
LT
d1 d
2 d
3 d
n
I (1mA)
V
V
LT
ME
SA
Su
bst
rate
72
The straight-line graph plotted in Figure 223 can be referred to Eq (249) and
this must be done by assuming the sheet resistance Rsh of the material is constant If the
straight line of the graph is extended up to initial gap (d=0) the intercept on the y-axis
provides the 2RC value To extract the 2LT further extrapolation is made until the
interception at RT = 0 is reached Therefore an important parameter which is the specific
contact resistance ρC can be found from this expression[85 86]
120588119888 = 119877119862119871119879119882sinh
119897119871119879
cosh119897
119871119879
(250)
Where l represents the total conductive semiconductor thickness The final part that can
be extracted from the graph is the slope of the line This is obtained by dividing the sheet
resistance with the width of the metal pad ie represented by expression (119877119904ℎ
119882frasl )
28 Basic Characterization Techniques and procedures
281 Measuring tools and apparatuses
The success of every experiment is determined by the backend results that are
obtained from the measurements It is important to choose an appropriate instrument
which will provide the required data for a valid and detail analysis Thus this section
will give a brief explanation of the measuring instruments and methods that were
exploited in this research The measurement apparatus systems that are available and
have been utilised in completing this thesis are ldquoset of DCrdquo and ldquoSet of RFrdquo
measurements The DC set measurement consists of room temperature and variable
temperature system This system is built to perform process monitoring during device
fabrication and it comprises of five main components
The fundamental component in the ldquoDCrsquos set toolrdquo is the Agilent B1500A
Parameter Analyser [87] used to provide fixed currentbias during testing The other
component is a Karl Suss PM5 Cascade Prober [88] which is used to receive fixed
currentvoltage and to supply its to the semiconductor contact via probe tip The PM5
Prober has at least four probe arms and each of them is fitted with ldquoneedlerdquo called probe
73
tip The size of the tip that is normally used here is 2microm and in some cases the tip size
of 1microm is also utilised The currentbias supplied to the sample must go through the two
of Source Measurement Units (SMU) namely SMU1 and SMU2 to ensure no mismatch
occurs between parameter analyser and diode All the testing are controlled using a
software called Integrated Circuit Characterization and Analysis Program (IC-CAP
2009) brought from Keysight Technologies[89] The software is installed on a standard
Personal Computer (PC) and the PC is connected to a General Purpose Bus Interface
(GPIB) to link with the B1500A Parameter Analyser This system can be organised
based on the purpose of measurements ie IV characteristics TLM Schottky Diode
and transistor as it is very flexible to change the configuration For examples
Transmission Line Measurement (TLM) configuration requires the addition of a digital
multi-meter and four-point probe tip while diode measurement just needs two point
probe tip without a digital multi-meter Figure 224 illustrates the measurement system
for a set of DC to test the TLM structure
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM
On the other hand the set of RF measurement consists of five block elements
configuration in the system namely the Vector Network Analyser (VNA) DC
sourcemonitor Cascade Microtech Prober SMU and Control PC via GPIB The RF set
Agilent B1500A
Parameter analyser
DUT
(TLM Diode
Capacitance)
Karl Suss
PM5 Cascade
Prober
PC
(MS windows 2000)
Digital Multi-meter
ICCAP 2014 Provide current
source
Measure and read the
voltage Stage and Probe
Signal
Current Source
SMU1 SMU2
General purpose bus interface
74
performs RF characterisation after the device fabrication is completed This system can
also perform DC characterisation as its basic instrument has this function too The VNA
machine used in this research is the Anritsu 37369A [90] which can perform the
Scattering Parameter (S-Parameter) measurement with a frequency range of 40MHz to
40GHz The DC sourceMonitor utilised in this experiment is the HP 4142B Modular
DC SourceMonitor [91] Both of these sub-systems are controlled by a standard PC
which exploits GPIB port to link them During operation the HP 4142B is connected to
the VNA by an internal bridge network and two SMUs to the Cascade Microtech Prober
which is then connected to the bond pads of the device It is identical to the set of DC
measurement where the SMU setting and data assembly are accomplished by IC-CAP
software package therefore the data that was obtained before and after completing the
fabrication can be compared This will enhance the validation of the data
However the stage and probes in both sets of measurement are different The
Cascade Microtech Prober has only two probe arms with each arm fitted with a 3-
fingers probe tip in the arrangement of Ground-Signal-Ground (GSG) as shown in
Figure 225 Each finger (pitch) is separated by 100microm thus to fit in with the pitch and
to reduce the mismatch in resistance the bond pad design must follow this separation
between each contact The GSG is configured by connecting the outer pads (Collector)
to the Ground probe tip while the inner pads (Emitter) are attached to the Signal probe
tip where the RF signal is sent and received through it Figure 226 shows the actual set-
up for RF measurement used in this research
75
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
Figure 226 Actual VNA system that was used for RF characterization
282 Measurement steps using a VNA
The RF measurement steps can be summarised in the following
- Step 1 Select or find the suitable VNA depending on applications
PC
(MS windows 2000)
ICCAP 2014
VNA
Anristru 32379A
40MHz to
40GHz
HP4142B
Modular DC
source
DC Bias Source
Cascade
Microtech
Probe Station
One 50microm pitch G-
S-G probe tips
Ground
SMU1
Cathode
Gen
eral
purp
ose
bus
inte
rfac
e
Lo
w P
ow
er H
igh P
ow
er
Cathode
Anode
SMU2
Ground
Ground
Signal
76
There are few factors that need to be well-thought-out before starting to use a VNA
especially for S-parameter measurements The factors are the availability of the VNA in
term of operational frequency and measurement port types air-filled metallic waveguide
or on-wafer Not all VNA can have an operational frequency for banded measurement
ie W-band Ku-band etc All these may require external signal sources to extend the
operational frequency
- Step 2 Properly setting up the VNA
The VNA can be set up depending on its application and the goal of measurement for an
instant number of point requires a desired frequency span IF bandwidth and the supplied
power level This very important to ensure the desired measurements are correct and
appropriate
- Step 3 Appropriate calibration system
In order to have a valid calibration appropriate calibration method has to be chosen
depending on the applications This will determine the accuracy and standards of
calibration As for on-wafer calibrations the de-embedding is normally used while for
the off-wafer the SOLR technique is more suitable to employ
- Step 4 Validation or verification of the calibration results
It is vital to validate the calibration results to ensure that the system has been properly
calibrated
- Step 5 Proper measurement
Proper alignment positioning and touching from probes tip to DUT is necessary to
guarantee a good repeatability and reproducibility of measurement results Normally
when positioning the probe an alignment marker is used as an aid By doing this similar
travel distance for the probes can be achieved The measuring plane will also be equally
well-defined
283 Measurement Practice and Flowchart
Essentially the device characterisation is performed in two stages ie during
fabrication as a process monitoring and after completion for data collection and
analysis Figure 227 shows the block diagram of a flow chart for testing a 15mm times
15mm wafer processing performance In the wafer processing after reaching the top and
77
bottom contactrsquos step the sample can be examined by measuring the TLM structure
according to the TLM procedure The measurement is conducted by exploiting a set of
DC measurement apparatus as mentioned above analogous to the TLM ladder structure
on the wafer surface Based on the TLM results the presence of any process issue during
the fabrication can be identified by examining the parameter such as contact resistance
and sheet resistance Thus a decision can be made either to proceed or to terminate the
fabrication should any issue is found early on As a result no materials will be wasted
further When a dielectric layer is involved Capacitance Dielectric measurement can be
tested This practise can be used to obtain the quality of the dielectric layer To connect
between a diode effective area and probe a bridge is requires It can be attached to the
diode emitter (to determine the diode size) to a bond pad for probe tip to touch This
bridge can either be left hanging in air or sticking to the isolated dielectric layer For the
GaAsAlAs material system the latter technique is preferable since it avoids issues with
the air-bridge which will be discussed in detail in Chapter 3 The opening area (via) for
metal connection can be checked by measuring the resistance on a special design pad
after a plasma dry etching step
Figure 227 Block diagram of the ASPAT measurement step
The next stage of characterising the device is the on-wafer diode measurement
which takes place after completion of all processing (including bond padsco-planar
pads) The work is carried out using the above set for RF measurement and employed
Ohmic Contact
Opening Via
TLM
Qualified
Device
Bad device
Dielectric
capacitance
Bonding pad DC and RF
Good
Good Good
Fail
Fail
Fail
78
purposely to access the DC and RF performance of each diode where the current-voltage
(I-V) characteristic and S-Parameter results are obtained In fact DC measurements are
first performed using a set of DC measurement and a rough IV characteristic can be
obtained to ensure the diode is working properly Usually the yield of any fabricated
device on 15mm times 15mm wafer in this research is between 70 to 90 In this research
the outcomes that will be discussed in the subsequent chapters are in term of the average
of measured values Thus it is very important to have a meaningful data to compare with
physical modelling and simulation in the future The diode IV characteristics are studied
by applying different DC bias at the emitter to collector terminals to extract its keys
parameters ie turn on voltage (supposedly zero bias) non-linear characteristic Rj RS
Cj etc
The device that has been measured by DC and having produced a valid result
will be marked for the next investigation ie the S-Parameter measurement This
measurement is executed using a similar system but with different probe types The
three fingers probe type is used and the device frequency response is measured via the
one-port network from the VNA The important parameters extracted from this
measurement are usually S11 (depending on how many ports are measured) Although
working devices are selected to measure accordingly there is a need to ensure the VNA
RF cable and probe tips are calibrated so that only valid data without errors will be
obtained A calibration technique called SHORT-OPEN-LOAD (SOL) is performed
prior to each daily measurement by exploiting a calibration sample with WinCal
software (Cascade Microtech)[92]
To avoid confusion it is worth mentioning that this technique used to calibrate
the device structure is different from what is used in SOL calibration to the equipment
Furthermore the de-embedding calibration is made on-wafer with the same substrate of
the actual device whereas the SOL is performed on a special calibration substrate
Normally the de-embedding results are not constantly automated with the VNA
equipment However the measurement is done separately starting with the special DUT
substrate then followed by the OPEN and SHORT de-embedding structures
79
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES
31 Introduction
This chapter presents in detail the general fabrication techniques for a generic and
development work of micron scale ASPAT diodes The discussions will focus on the
semiconductor growth technique used in this work ie MBE and the fabrication process
steps which include sample cleaning photolithography etching and contact
metallization These techniques are ample to build and deliver commercially marketable
fabricated structure Hence all photolithography techniques used to complete this
project are based on conventional i-line optical lithography which is adaptable to
industry and commercial purposes
The fabrication process in this work can be fragmented into two major works
firstly the fabrication towards reproducibility repeatability and manufacturability in
term of device structure process flow and DC amp RF characteristics This work will
involve relatively larger emitter area which varies from 15times15microm2 to 100times100microm
2 The
larger area provides for ease and fast fabrication as well as DCamp RF measurements
Once repeatability and reproducibility of the process flow and performance is confirmed
the second part of this work which is concerned with applications in millimetre and sub-
millimetre-wave then took place In this work small emitter designs varying from
2times2microm2 up to 10times10microm
2 were considered with appropriate measurement pads The
successful fabrication of smaller diode geometries in the second part of the programme
naturally leads to a further investigations to understand its epitaxial layer structure and
extracting intrinsic components ie junction resistance junction capacitance and series
resistance which will determine the device performance in high-frequency applications
The I-V characteristic is obtained from DC measurement which is usually performed at
room temperature Its results are then compiled and compared with advanced simulation
It is worth mentioning that all samples that are investigated in this project are grown by
means of MBE and the activities related to the epitaxial layer growth using MBE in the
University of Manchester were done by the Materials Growth Team (Prof Missous) and
the authors has no responsibility for this particular task
80
32 Epitaxial Layer Growth Techniques
Before discussing the principle of the common lithography technique it is
important to discuss the wafer growth technique as it comes first before the fabrication
The growth technique that is extensively used in this study as well contributing a lot in
the electronic semiconductor industry is Molecular Beam Epitaxy (MBE) The following
section will discuss the basic operating principle of solid source MBE
321 Molecular Beam Epitaxy (MBE)
The MBE technique was developed in the early 1970s [27] and is purposely used for
growing high purity epitaxial layers of compound semiconductors Such sophisticated
growth technique provides significant functionality ie precise control of the thickness
(to one atomic layer) and contributes to the growth of various types of complex
semiconductor multilayers high quality and advanced materials This level of control is
vital for an assortment of heterostructures devices that are being utilized as part of the
development of the advanced electronics devices especially for the ASPAT diode which
require 01ML control over the AlAs barrier to attain acceptable variability in device
characteristics Additionally the accurate doping profile and excellent junction
abruptness also can be achieved by using this technique
Practically the MBE system used in this work is a solid source MBE which
utilises beams produced by heating up various sources The sources can be Si Al Ga
As and other group III-V compound semiconductors When the crucibles which contain
the sources are heated atoms or molecules of the various elements are evaporated and
travel in straight lines paths like beams directed toward a target (heated and rotating
substrate surface) The condition of the vacuum during evaporation is ultra-high vacuum
(UHV) ~10-11
torr in order to have high quality crystals The substrate is heated and
rotated to provide good growth uniformity over large areas ( up to 4times4rdquo wafers) [93]
The growth rate in typical MBE growth is ~1ML second and can be controlled
by the source temperature in the crucible The abruptness at the heterojunctions interface
and switching of the growth compositions can be obtained by precise control of shutters
that are placed in front of the crucibles Therefore an abrupt junction at GaAs and AlAs
81
interface can be formed to realize the barrier in the ASPAT diode In order to monitor
the quality of the growing crystal and measure the layer by layer growth mode
Reflection High Energy Electron diffraction (RHEED) technique is utilised This
technique works based on the diffraction of electrons from the crystal surface [93]
Additionally given that the ASPAT current density is very sensitive to the barrier
thickness a study has been made using different growth techniques namely MBE and
Metal-Organic Chemical Vapour Deposition (MOCVD)[59] From this investigation it
was concluded that the percentage local variability of current density produced by MBE
grown diodes is better than those grown by MOCVD Thus in this study to get benefit
from its performance all wafers are MBE grown
33 Basic Principles of Common Fabrication techniques
This section covers the generic fabrication process which underpins
reproducibility repeatability and process optimisations for high-frequency applications
331 Sample cleaning
Essentially semiconductor processing requires a ldquoclean environmentrdquo to produce
devices The clean environment is classified according to how many ldquounwantedrdquo
particles are present in a cubic meter There are four categories of clean room available
in the industry Class 10 Class 100 Class 1000 and Class 10000 [94]
The fabrication of all ASPAT diodes in this project was performed in a clean
room environment of Class 1000 equipped with laminar air flow and filter system to
give Class 100 or better during processing Although the sample was processed in a
highly controlled particle environment there is still a high chance for a sample to get
contaminated when handled by a human Besides this the source of particle which
contributes to the contamination can be from the apparatuses and processing equipment
used in the laboratory themselves Thus the process of cleaning the sample wafer
surface before the start of each step is vital
Generally in a clean room the standard solutions that are used to clean a sample are
N-Methyl Pyrrolidone (NMP) Acetone Propan-3-ol (Iso-Propane-ol) (IPA) and
82
deionized (DI) water The sample which is cut up into 15times15mm2 size tiles is cleaned
based on the following procedures
1 Hot NMP- The sample is dipped into the solution at 80˚C for 10 minutes This
solution acts as an organic type of nature pollutants removal
2 DI water- acts as NMP remover The sample is then washed by flowing DI water
throughout the samplersquos surface
3 Acetone- to ensure any remaining NMP is completely removed from the sample
The sample is dipped into Acetone for 5 minutes in a low power ultrasonic bath
at ambient temperature
4 IPA- is used to remove the Acetone from the samplersquos surface The sample is
then dipped into the IPA for 5 minutes in a low power ultrasonic bath at room
temperature The use of low power for the ultrasonic bath is to avoid the sample
cracking or breaking
5 Once done the sample is then blow-dried using nitrogen (N2) gun to remove any
moisture coming from the IPA Fortunately it is easy to remove the IPA
completely from the sample surface given its higher rate of evaporation
Once all these steps are accomplished a visual inspection using a high magnification
optical microscope is conducted to ensure the sample surface is clean The cleanliness of
the sample is determined by the (lack) of particles or other spots (liquid mark) that can
sometime be observed during the inspection Obviously the lower the number is the
better the sample is as it is impossible to totally remove dirt especially marks
Sometimes it is hard to remove the particles in one go There is always a need to repeat
each cleaning step for a few times However this will not affect the sample in term of
electrical performance as the cleaning solutions used are non-destructive
332 Photolithography
Lithography or sometimes called pattern transfer is the most important step in
realizing microelectronic devices The designed geometry and dimensions on a quartz
glass plate called a ldquophoto-maskrdquo must be done prior to the fabrication process While
the photo mask can be designed by using various software tools in this work the design
83
is done via the Advance Design System (ADS) by Keysight The details of the design
which includes three different mask designs will be covered in Section 34 The mask
consists of the desired patterns (master) that can be printed onto solid materialrsquos surface
by means of an electrochemically sensitive polymer (photoresist) using
photolithography In fact this type of optical lithography technique can be performed
with and without a mask due to its simplicity It is also easy and cheaper compared to
other techniques such as x-ray lithography or Electron-beam lithography (EBL)
Although the latter is expensive it is still worth to have since it provides a higher
resolution which is preferable when developing sub-micrometre technology
processing[95] The special feature about EBL is that it does not need a mask to pattern
samples but can be produced by the movement of an electron beam point source and
hence writing the patterns directly on the surface
The ultra-violet (UV) based light sources are more popular among researchers
and development workers because they are cheaper and have modest resolution Usually
photolithography operates at wavelengths (λ) from 193 nm to 436nm The source that
provides the UV light is a Mercury (Hg) arc lamp which uses narrowband filters to select
single emission lines First is the i-line at λ= 365nm then the h-line which is of lower
resolution and has λ of 405nm and thirdly the g-line with a λ= 436nm[96] The
conventional optical lithography used in this research uses the ldquoi-linerdquo at a wavelength of
365nm For shorter wavelengths than these excimer laser or krypton fluoride laser with
a λ= 248nm and argon-Fluoride with a λ = 193nm are also used in the industry The
higher power levels enable higher productivity (throughput) while narrower spectral
widths reduce chromatic aberration provide better resolution and larger depth-of-focus
In this research all the fabrication process are done by utilizing a conventional optical
lithography (i-line) using a Karl Suss MA4 mask aligner Before starting any UV
exposure it is important to check the UV light intensity as it will affect the resolution
and thus desired device dimensions Therefore every corner that is exposed to the UV
light is calibrated to be at 09mWatt power exposure
The complete set of photolithography components consists of photoresist
(photosensitive polymer) photo-mask (chromium) which is used to block the UV to
form a pattern mask-aligner and developer (chemical solutions) Standard fabrication
84
process usually practiced at the University of Manchester starts with sample cleaning as
mentioned earlier Then the sample needs to go through heat treatment to remove all the
moisture with a temperature set to be 150˚C and bake for 5-10 minutes After having
cooled down the samplersquos surface is coated with a thin layer of photoresist via a
technique called spin-coating using a Laurell CZ-650 series spinner The spinning speed
is set depending on the type of resist ie 3000rpm for negative photoresist and 5000rpm
for positive photoresist The rotating speed of the spinner does not have much effect on
the coated photoresist thickness but will have consequence on the uniformity distribution
over the sample surface The coated thickness photoresist however depends on the
concentration of the specific photoresist Once spin-coated is done another short heat
treatment (1 minute) is required to ensure the resist is hard enough to contact a
photomask and to remove any excess solvent The temperature is set on the hot plate to
about 115˚C and 110˚C for positive and negative photoresists respectively
The important segments contained in the photoresist are a polymer (base resin)
a sensitizer and a casting solvent [97] The polymer will react by changing its structure
when exposed to the radiation While sensitizers will govern the reaction of the
photochemical in the polymeric phase the casting solvent will permit the spin-coated
application on the wafer surface The photoresist consists of positive and negative
photoresist both of which were used in this research Their basic difference is with
respect to the area that is exposed by UV light ie whether it will remain on the
semiconductor surface or will be removed In the case of a positive resist the exposed
area will be removed by the developer and the covered area will remain In other words
whatever is displayed on the photomask goes onto the sample surface On the other
hand for the negative photoresist the area that is covered from UV exposure will be
dissolved by the developer Figure 31 shows a 3D picture of both processes used in this
research
85
Figure 31 3D illustration of Optical lithography process used in this research
To obtain the desired pattern on the surface after UV exposure for a certain
duration the sample is required to go through a development procedure by using a
developer The developer is used to expel the dissolvable part of the photoresist after
being exposed to UV The usefulness of the developer depends on the photoresist ie
MF319 developer is specifically for positive photoresist while MIF326 is suitable for
negative photoresist Both types of developers will not harm the devices as they are a
kind of metal free ion solution Thus no free ion will change the characteristic of the
device The common practice in the clean room at the University of Manchester is to use
positive photoresist namely Shipley Microposit S1800 supplied by The Dow Chemical
and negative resist AZnLOF2020 (AZ2microm) which is supplied by MicroChem For the
S1800 series the thickness of the photoresist is determined by the last two digits ie
13microm thick for S1813 and 05microm thick for S1805 Both positive photoresists are used
Resist
GaAs
Dielectric
Photo Mask
Negative Resist Positive Resist
After Etching
86
mostly as protective area during wet chemical etching and as sacrificial dielectric layer if
higher temperature is applied ie 190˚C On the contrary AZ2microm which normally has a
thickness of 2microm is useful for patterning small dimension which leaves small gaparea
for the metallization process to fill It has good aspect ratio and useful in single layer lift-
off (post metallization process) In fact this type of resist can be thinned by diluting into
an Edge Bead Removal (EBR) solution and smaller device feature size can be obtained
The final dimension of certain devices (mesa size) is governed by the exposure
time the distance between photomask and samplersquos surface and the development time
The appropriate UV exposure time is required to avoid over-exposure which will cause
the spreading of light into the purportedly dark-field area[98] However the effect of the
exposure time differs between the photoresist types smaller opening area than the mask
pattern for negative resist and larger opening area for positive resist[45] The gap
between the photomask and wafer surface must be reduced as much as possible to avoid
the UV light going through the unwanted area To obtain a good gap value an applied
pressure from stage to the mask is required The normal pressure used in this research is
between 04 to 1 Pascal depending on the type of photoresist (negative and positive) as
well as its thickness Lastly the development time also influences the dimension of the
device Appropriate development time is required because ie over-development will
cause the polymerized photoresist to etch laterally resulting in bad patterned geometries
On the other hand under-development will cause non-uniformity in the surface after wet
chemical etching (positive resist) as well as causing lift-off problem (negative resist)
333 Etching Process
The etching process is a process of removing unwanted semiconductor layers to
define device geometry and isolate each individual device in one sample There are two
types of etching technique used in this research ie wet chemical etching and plasma
dry etching The wet chemical etching is based on Orthophosphoric(H3PO4) solution
which is a selective etchant to materials like GaAs InGaAs and AlAs The selective
etchant is referred to a solution that can etch away a specific semiconductor with a
specific etch rate The etch rate depends on the mixture ratio and concentration of the
solutions ie the higher the concentration the higher the etching rate In practice the
87
temperature humidity and epitaxial layer doping level also have an impact on the etch
rate Hence to minimize variation in the etch rate both temperature and humidity in the
clean room are constantly monitored and regulated Ambient temperature between 18degC
to 19degC is usually suitable while humidity is kept within 30 to 40 The advantage of
the wet chemical etching is that it is inexpensive controllable and with high throughput
highly selective and simple The mixture solution that is used in this work is
Orthophosphoric (H3PO4) Hydrogen Peroxide (H2O2) and Di-ionised water (H2O) with
ratios of 3150 3110 and 212 The ratio of 3150 provides an etch rate of about
600Aminute and is good to define the area and opening the under-cut in air bridges for
InGaAs samples[99] The 3110 ratio results with highly anisotropic shape but is easy to
control as the etch rate is about 1500Aminute for GaAs material system However the
212 etchant solution will provide extremely anisotropic etch rate of about
1000Asecond and is quite difficult to control For GaAsAlAs ASPAT diode it can still
be controlled since the thickness that needs to be removed is about 7000A (refer to
section 342 for details on the fabrication of ASPAT) Table 31 summarizes the etch
rate with different ratios and different selective materials Common to all the ratios
mentioned above are the isotropic side walls with lateral and vertical etch rate of 11
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and Ammonia on GaAs
and InGaAs materials
Material Etchant Ratio Etch Rate (Aringminute)
GaAs H3PO4H2O2H2O 3150 600
GaAs H3PO4H2O2H2O 3110 1500
GaAs H3PO4H2O2H2O 212 60000
GaAs NH4OHH2O2H2O 118 2000~3500
InGaAs H3PO4H2O2H2O 3150 850
The plasma dry etch is purposely run to obtain extremely high anisotropic etch
profile vertically and horizontally It can be done via mask with positive photoresist and
self-align mask which is metal contact as a mesa protector The precursors that are used
to etch away GaAs InGaAs and AlAs layer in this technique are Methane and
Hydrogen (CH4+H2) On the other hand Carbon Tetrafluoromethane (CF4) and H2 is
88
used in removing Si3N4 The etch rate is determined by how much power is applied to
the plasma to hit the sample surface the pressure inside the chamber and amount of the
precursor In this research plasma Technology is used for dry etching This machine
which is a conventional OXFORD INSTRUMENTS 1990 machine can produce an etch
rate on average of 100Aminute for an RF power of 100mWatt
334 Sputtering (dielectric deposition)
In this work a Kurt JLesker PVD 75 is used to deposit Si3N4 layer on the sample
surface The deposition rate depends on the RF power that is applied To avoid surface
damage on the sample surface a sacrificial layer formed by SiO is deposited using the
Bio-Rad Thermal evaporator before transferring to the PVD 75 to start deposition with a
low (75Watt) RF power Once the deposition time reaches 30 minutes the power is
increased up to 200Watt As a result good uniformity of the dielectric layer is obtained
335 Metallization Process Lift-off and Annealing
The metallization process is a process in which metal contacts on semiconductor
devices are created The purpose of this process is to make a proper interconnection
between the semiconductor devices to other parts of the circuit elements In other words
it is to connect the semiconductor device to the outside world This process will allow
the device to be examined electrically so that all electrical characteristics can be obtained
ie resistance I-V curve capacitance conductance etc The metal scheme used in this
process depends on the semiconductor material In the case of GaAsAlAs ASPAT
diode Gold-Germanium (AuGe) Nickel (Ni) and Gold (Au) are used However in the
case of InGaAsAlAs ASPAT diode the metal scheme used is Titanium (Ti) and Au
The technique used in this process is resistive thermal evaporation
The metallization process starts by cleaning all the metallic sources and boats
ie tungsten boat Au Ni and Ti metals by using Trichloroethylene Acetone and IPA
consecutively for 5 minutes each in a high power ultrasonic bath This step is very
important to reduce the risk of contamination during thermal evaporation Once done all
the metallic materials are dried using a high-pressure nitrogen gun and then dipped in
89
Hydrochloric acid (HCL) solution for 2 minutes to de-oxidize the metals so that it has
minimal effect on the series resistance of the ASPAT diode
Two types of thermal evaporators were used extensively in this study both
Edwards Auto 306 (one denoted as Junior Auto 306) The latter is used to deposit alloy
type of metals while the former is used for the non-alloyed type of metals In the case of
GaAsAlAs ASPAT alloy type metals are used while for InGaAsAlAs non-alloyed
metals are used The cleaned metals are then loaded in the thermal evaporators and
placed on a resistive tungsten boat Each metal is placed on its specific tungsten boat to
avoid unnecessary mixture during the evaporation
Figure 32 Actual picture of thermal evaporator used in this study
Prior to loading the sample into the evaporator a standard fabrication process for
ASPAT diodes takes place by patterning the samples with AZ2microm negative photoresist
At the end of this step an opening area is created for the metal contact to be filled and
connected to the ohmic contact of the semiconductor The sample is also deoxidised
using a mixture of HCL and water in the ratio of 11 prior to evaporation This has to be
done in a very short time in order to avoid re-development of the native oxide layer
Inside the chamber the sample is securely placed on a chuck upside down facing the
filled tungsten boat The distance between the sample and metallic source boat is about
90
40 cm Figure 32 illustrates the actual thermal evaporation system used in this study
The thermal evaporator chamber is pumped down to reach a minimum pressure below
1times10-5
mbar before vaporizing the metal It is important that the mean free path between
metal amp sample is created and each vaporized metal stick firmly on the samplersquos surface
The normal practice in this study is to keep the vacuum pressure under 1 times10-6
bar so
that better device performance can be obtained The amount of current required to melt
down the metal is between 4 Amps to 6 Amp This amount of current is forced through
the tungsten boat and generates very high heat melting down the metallic source and
vaporizing it towards the sample surface The deposition rate for each metal can be
monitored by using a built-in film thickness monitoring (FTM) on the thermal
evaporator which proportionally depends on the amount of materials deposited The
GaAsAlAs sample is started with deposit of 55nm AuGe 13nm Ni and 500nm of Au
The reason of depositing AuGe first is due to the fact that the ohmic layer of the
ASPAT only can only be doped with a maximum doping of 4 times1018
cm-3
which is not
high enough for good conductivity Thus here Ge atoms will diffuse into the GaAs and
replaces Ga atoms during annealing process leading to higher doping levels (gt1 times1019
cm-3
) and hence improved conductivity
3351 Lift-off
The use of AZ2microm allows for the exact patterning of metals without the need for etching
using a single layer lift-off technique The negative photoresist also provides an undercut
profile which will create disjointedness between the desired metal pattern (on the
semiconductor) and undesired metal (on photoresist) The process of getting rid of the
unwanted metal from a sample surface is called lift-off The process starts once the
evaporation process is accomplished The sample is soaked into 80˚C N-Methyl-2-
Pyrrolidone (NMP) solution for usually 20 minutes (fast lift-off process) In most
instances the sample is in NMP for more than 12 hours in ambient temperature (slow
lift-off process) as the NMP solution is not destructive to the sample In this solution
the negative resist will be softened and the metal part which sticks on it will also be
eliminated from the sample As depicted in Figure 33 the lift-off process for a single
device shows the usual photoresist undercut profile observed To ensure that NMP
91
residues on the sample surface are completely removed DI water is used to rinse the
sample which is then blown dry with a nitrogen gun
Figure 33 Single layer lift-off process using negative photoresist
3352 Annealing
The alloyed (AuGeNiAu) metal stack requires a thermal treatment called annealing to
improve the ohmic contact between metal and semiconductor The sample which has
deposited top and bottom contacts is loaded into an annealing furnace at a temperature of
420˚C for 2 minutes In the case of GaAs during thermal annealing Ge atoms penetrates
into the GaAs crystal for approximately 70nm-250nm depending on evaporated
thickness of the metal layers annealing temperature as well as time [100] In this work
the total metal thickness evaporated for each contact layer is around 500nm This
thermal annealing treatment will also melt down the Au if it is too thick and is subjected
to too long a heat treatment Therefore it is not advisable to do annealing after the
sample is coated with bond pad metals as it can result in short circuited devices
sometimes
Az2micro Negative
photoresist profile
after UV exposure
and development
Evaporation to
form metal layer
(AuGe Ni Au)
Desired metal
contact
Metallisation
process
Lift-off undesired metal
92
34 GaAsAlAs ASPAT Process Optimization
As mentioned earlier this section present details two major process flows of the
fabrication process for the ASPAT diodes which utilised three stages of development of
photomasks design namely a ldquoFirst generation mask designrdquo (1st Gen) a ldquoSecond
Generation mask (2nd
Gen)rdquo and a ldquoThird Generation mask (3rd
Gen)rdquo design The 1st
and 2nd
generations mask designs are the designs that were produced in the first stage of
this work to develop the fabrication process know-how and to get familiarized with the
actual fabrication techniques in the cleanroom The difference between the 1st Gen and
2nd
Gen masks is in term of the development towards realizing Air Bridges and
Dielectric Bridges which were mostly covered by the 2nd
Gen mask design The
analyses in term of reproducibility repeatability and manufacturability for process
control and current-voltage characteristic as well as ultimately RF measurement are
obtained on relatively large size devices via these two mask designs The large area
emitter dimensions range in size from 15times15 microm2 to 100times100microm
2
The 3rd
Gen mask design was designed based on the optimization of the 2nd
Gen
mask which was to realize ASPAT diodes that are able to work at very high operating
frequencies Therefore in such design the ASPAT devices have to have a minimal
amount of capacitance and low series resistance this is can be achieved by shrinking the
emitter size of the diode to the smallest area possible as well as optimising the
fabrication process ton reduce parasitics The smallest fabricated devices designed on the
new mask has an 2times2 microm2 MESA area which also includes Ground Signal Ground bond
pads for both device and de-embedding structures (open and Short) for RF
measurements
Before the commencement of any fabrications and designing any layouts on eg
Si GaAs InP etc the epitaxial layer must be grown first to a desired design In the
University of Manchester the epitaxial layer structures are grown using one of the two
Molecular Beam Epitaxy (MBE) machines which are either the RIBER V90H or the
V100HU system Both systems are managed by Professor Missous Epitaxial wafers or
sample grown by each system are identified by a prefix and numbers that are prefix
VMBE for the V90H system and XMBE for the V100 system The epitaxial layers are
93
grown on four-inch wafer diameter The maximum diameter that can be grown on using
the V100H is 8 inches but generally single 4rdquo or 4x4rdquo wafers are used The wafers are
then diced and cut using a diamond scriber into 15mm times 15mm tiles for easy handling
and fabrication in the D12 cleanroom lab in the University of Manchester
In this section the structures fabrication and performance of the various ASPAT
diodes for both repeatability and high frequency applications will be discussed further
The ASPAT is manufactured on wafer sample XMBE304 which is a GaAsAlAsGaAs
lattice matched to a GaAs semi insulating substrate is the main focus The ground works
on this ASPAT such as the initial design and fabrication process flow optimization had
been conducted by fellow PhD colleagues in the group led by Professor Missous at the
University of Manchester
341 ASPAT Devices used in Fabrication
3411 XMBE368 and XMBE307
Table 32 Epitaxial layer of Doped substrate samples
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~50
Spacer1 GaAs NID 50 50
Barrier AlAs NID 28 28
Spacer 2 GaAs NID 1000 1000
Buffer GaAs(Si) 4times1017
50 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~3500
Substrate GaAs (Si) Doped 50000 50000
These two samples were the first batch of diode structures used in this work and
were grown using the RIBER V100 MBE machine A great deal of work was expanded
to ensure that it is able to produce appropriate non-linear I-V characteristics The work
carried out including finding suitable fabrication process steps mask designs process
control limitations ie etching rates etc The results obtained from processing these
94
samples mostly on large area anode and cathode sizes and their analysis included both
growth profiles and fabrication process flows These samples were grown on doped
GaAs substrates As such the finished diodes were vertical structures and the fabrication
process has marked differences compared to undoped substrate samples While
XMBE368 had similar epitaxial layer profile to XMBE307 during growth the AlAs
layer was set to be stagnant (ie no-rotation of the substrate during growth) to
investigate the effects of slight variations in barrier thickness
3412 XMBE304
The next sets of samples were all grown on semi-insulating GaAs substrates
Table 33 details the epitaxial layer profile of sample XMBE304 the main work horse
of this research work The growth of this structure was performed on a multi-wafer
platen and consisted of 9 x 2rdquo wafers (from XMBE304A to XMBE304I)
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm
Epitaxial layer Material Doping(cm-3
) Thickness(Aring)
Emitter GaAs(Si) 4e+18
3000
Emitter 2 GaAs(Si) 1e+17
400
Spacer GaAs NID 50
Barrier AlAs NID 28
Spacer 2 GaAs NID 2000
Collector GaAs(Si) 1e+17
400
Collector 2 GaAs(Si) 4e+18
4500
Substrate GaAs(SI) Semi-Insulating
For a typical ASPAT structure the emitter is essentially highly doped to
4times10+18
cm-3
to provide accumulation of electron in the emitter contact region It was
purposely highly doped to also achieve low ohmic contact with the metal The spacers
are used to avoid diffusion of dopants to the subsequent layers The ASPAT structure as
mentioned earlier has a single AlAs barrier with a very small thickness sandwiched
between two different length GaAs spacer layers
Batch XMBE304 is the main focus in these studies All activities required for
repeatability reproducibility process flow and devices as well as qualifying new or
95
optimization fabrication technique for small devices and RF performance which were
then used for high frequency were based on the set of wafers grow in this batch
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability
As the new wafer structures have to be tested and evaluated to gauge the
performance of the ASPAT diodes their uniformity also needs to be tested so as to
ensure it exhibited fully functional diode with zero bias detection in minimal variation in
IV characteristics between diodes As described previously 4rdquo wafers are always diced
up into 15mm times15 mm size for ease of handling in the cleanroom and for masks cost
purposes
3421 Doped n+ Substrate Wafers
For wafers grown on n+ substrates (XMBE368 and XMBE307) a two-level mask
set is sufficient to complete the fabrication process In this case the devices are designed
with mesa structures and top metal contact on the upper surface of the wafer and a
bottom contact on the backside of the wafer One mask plate is used for defining the
mesa structure (wet etch) and the other mask plate is used for defining the metal pad
Since the mesa is relatively large (30times30microm2
to 100times100microm2) there is no requirement to
define bond pads for measurement purposes A prior RTD mask designed by fellow
colleague Dr Md Adzhar for his PhD work was used for processing the ASPAT diodes
as well in the first instance The detail fabrication process is summarized in appendix I
for the doped substrate wafers Figure 34 shows typical IV characteristics for 30x30microm2
emitter size diodes obtained from sample XMBE368
96
The I-V measurement was taken from two different tiles (15mm times15 mm) located
on top and bottom of a 4rdquo XMBE368 wafer The location 1 marked as a blue line in
figure 34 refers to a device on a tile taken from the top of the 4rdquo wafer while location
2 (red) refers to a device on a tile taken from the bottom of 4rdquo wafer At 07V the
separation difference in current is ~228 for both tiles This shows that the device in
tile 1 is less resistive than the sample in tile 2 implying that the AlAs layer for tile
located on the top corner of the wafer is thinner and thus allows more electrons to tunnel
through it at a given bias
3422 First Generation Mask Design (1st Gen)
-0015
0005
0025
0045
0065
0085
-15 -1 -05 0 05 1 15
I C
urr
en
t (A
mp
)
V Voltage (Volt)
Current vs Voltage (XMBE368_1) for 30x30microm2
MidLeft2
MidRight3
Figure 34 Current-Voltage characteristic of sample XMBE368 used
in this study at two different locations on the wafer tile
(a) (b) (c)
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2 diode dimensions
designed in the 1st Gen Mask
Location 2
Location 1
97
The fabrication of the GaAsAlAs ASPAT conducted in this 1st Gen mask is
followed the established generic process flow for InGaAs material which was done by
former co-worker Dr Md Adzhar Md Zawawi[101] The generic process flow is fairly
simple consisting of four mask steps as shown in Table 34 below The fabrication
process starts with the sample being cleaned in a NMP solution at a temperature of 80˚C
with Acetone and Propan-2-ol (IPA) The purpose of cleaning using NMP and Acetone
is to remove any organic material The IPA is used to remove Acetone residues
Table 34 Generic fabrication steps established by Dr Md Adzhar [101]
Step number Process
1 Top Contact
2 Mesa Etch
3 Isolation
4 Bottom Contact
In the 1st Gen mask the first step in fabricating the GaAsAlAs ASPAT diodes is
to use the first mask to define the emitter contact area The emitter has three different
sizes 100times100microm2 30times30microm
2 and 15times15microm
2 The lithography technique uses the
negative photo-resists AZ2micron with 55 second UV-photolithography to pattern the
top contact Then it is developed using MC319 developer to clear and define the
exposed area for the metals to stick to The sample is then subjected to plasma etching to
remove all organic residues and contaminants Then it is dipped into a mixture of
diluted Hydrochloric acid and water HCL H2O with a concentration of 11 for de-
oxidation This must be done in a short time right before the evaporation in order to
ensure good contact between metal and semiconductor surface with very low oxide
formation in between The ASPAT device performance depends on this step as contact
to the channel is by means of current flowing through the anode to the cathode terminals
In our lab the approach taken to achieve the Ohmic contact is by evaporation of Gold
Germanium (AuGe) Nickel (Ni) and Gold (Au) metals layers on top of the cap layer
Subsequently the metal is defined via a lift-off process using NMP
98
The next critical step is to define the MESA or island The mesa etch mask is
designed with two options with 05 microm or 10 microm tolerance The different mesa
tolerances are introduced to act as a safeguard for the emitter from producing excessive
undercut caused by lateral etching This step is to isolate and eliminate the unwanted
GaAs which will electrically link the active layers as many devices will be fabricated at
the same time on the same wafer tile (15mm times 15mm size) The lithography process in
this step uses positive resist and is developed using MC326 developer This step is
achieved using a wet etch process where a non-selective etchants mixture of
H3PO4H2O2H2O etches down the epitaxial layers until it slightly exceeds the AlAs
barrier with an etch rate of about 600Aring to 900Aring per minute The outcome of the MESA
or island step is the formation MESA active layers which are surrounded by inactive
layers of semi-insulating substrate (when using semi-insulating substrates)
The isolation mask is a step that is basically the same as the MESA etch step
eg using similar etchants mixture same lithography process but a different mask This
step is used to etch down until the GaAs substrate is reached which means that the
etching time is longer than that in the MESA etching step The purpose of this step is to
fully isolate the device from other neighboring devices hence ensuring no electrical
connection exists between each device within one sample Since these ASPAT diodes
employ an air bridge structure of size 1times5 microm the two minutes mesa etches will
simultaneously provide an initial undercut through lateral etching for the air bridge
formation
Based on the results so far obtained using the first-generation mask which
provided large mesa areas the current voltage characteristics of the ASPAT as far as the
non-linear zero bias is concerned did work very well However there was a need to
reduce the ASPAT mesa area down to very small dimensions to achieve mm-wave or
THz detection frequencies It is certainly a general rule for semiconductor device which
operate at very high frequency to have extremely small lateral dimension which
minimises the capacitance within the ASPAT device Furthermore for wider adoption of
the technology it is also important to develop a simple reproducible and low-cost
fabrication method for ASPAT diodes Details of this fabrication process are attached in
appendix II
99
3423 Second Generation (2nd
Gen) mask (ASPAT-GSG)
This work intended to enhance the 1st Gen-Large Area ASPAT photomask by
adding many features including 2 times 2microm2 mesa areas ground-signal-ground (GSG) bond
pads to enable RF measurement and three options device processing eg Air Bridge
Dielectric Bridge for semi-insulating doped substrate and dry etch-mesa Other reasons
for designing this mask was also to qualify process steps when deploying thin (1microm
width) bridge to connect small mesa area ASPAT diodes to the co-planar GSG bond pad
for DC and ultimately RF measurements
The mask was designed to fulfil the basic rules of fabricating various types of
tunnelling diode for instance RTD and ASPAT The diodes layouts were designed using
the commercial software Advanced Design Software (ADS) from Keysight
Technologies Ltd Once the design was completed it was ready to be sent to Compu-
Graphics Company for printing and patterned on a special chrome coated glass plate
The new 2nd
Gen mask design was termed ASPAT with Ground-Signal-Ground
(ASPAT-GSG) and consisted of two main designs ldquoAir Bridge and Dielectric Bridgerdquo
where each contained eight diodes with different emitter sizes (100times100μm2 50times50μm
2
30times30μm2 20times20μm
2 15times15μm
2 10times10μm
2 6times6μm
2 and 2times2μm
2) The Air Bridge
design is comprised of Design 1 (doped substrate) and Design 2 (undoped substrate)
This can be selected by changing the order of each individual layer of the mask steps
The same options are applied for Dielectric Bridge design which included processing for
doped and undoped substrates The details of the masks will be explained in the
following paragraph
(1) Air Bridge
Design 1 Contains five steps or layers mask of size 15mm times 15mm
suitable for air-bridge for undoped semi-insulating substrate
Design 2 Consist of seven layers steps mask of 15mm times 15mm size
There are 413 die chips in about 6mm times 6mm sizes in this design Figure 36 shows both
type of design for Air Bridge mask processing
(i) Mask 1- Top Contact
(ii) Mask 2- MESA
100
(iii) Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5- Collector Bond pad with GSG
(vi) Mask 2A-Dielectric
(vii) Mask 6A-Collector Bond Pad with GSG
(2) Dielectric Bridge
Design 1 Consists of seven identical steplayers masks with lateral
lengths of 15mm times 15mm each suitable for fabrication on semi-insulating
substrate
Design 2 Also has seven steps layers masked with dimension of 15mm
times15mm each suitable for doped substrate processing
There are 357 die chips in this type of mask design with an estimated size of 6mm times
6mm separately The smallest emitter size that is connected with a dielectric as the
bridge is 6times6microm2 The smallest 2times2microm
2 diodes was designed with the air-bridge
connected to the emitter bond pad due to the difficulties of opening viascavity for less
than 2 microm2 devices Figure 37 show both options for Dielectric Bridge mask processing
(i) Mask 1- Top Contact
(ii)Mask 2- MESA
(iii)Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5-GSG bond pad
(vi) Mask 6- Via Dielectric
(vii) Mask 7- Dielectric Bridge
(vii)Mask 5A- Via Dielectric
(ix) Mask 6A-GSG bond Pad
(x) Dielectric Bridge
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates
Figure 37 The layout of 1st design of Dielectric Bridge (green circle) mask design for 100 times
100microm2 emitter size with option for doped substrate processing
101
34231 Fabrication Process of the Air-Bridge Design
The fabrication using 1st Gen mask as mentioned in Section 3422 is less
complex however the fabrication process for Air-Bridge mask design contains a few
additional steps which are to add bond pads for the Ground-Signal-Ground radio
frequency (RF) layouts If the sample is on a doped substrate another layer needs to be
added leading to a total of six steps all together
Table 35 Standard process flow for Air-Bridge design fabrication
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa EtchDielectric
3 3 Isolation
4
5
4
5
Bottom Contact
Bond Pad
In this work the samples that have been processed so far are XMBE304
XMBE314 (GaAsAlAs base material system) and XMBE326 (InGaAsAlAs base
material system) All of them are built up on semi-insulating substrate thus the normal
process flow was followed Step 1 to step 4 follow exactly the same route as the 1st Gen-
ASPAT Large Area mask formerly discussed in Section 3422 This process is then
continued by spin coating AZ2microm on the surface Mask 5 is used to pattern the bond
pads The metallisation scheme used for bond pads is TiAu and the thickness must be at
least 1 micrometre thick This is to minimise series resistance at the pads and ensure a
robust surface is created when used for DC and RF measurements
342311 Air-Bridge Process Optimization
Since the Air Bridge design approach is focused more on developing air-bridges
which have a width of 1 microm and as the smallest device is 2 times2 microm2 the negative resist
(Az2microm) which was used in the 1st Gen design type was changed to Az1microm After spin
coating an Edge Bead Remover (EBR) is required to remove the beads at the edge of the
sample this is to ensure no gap is created between samples and mask when ldquohard-
102
contactrdquo is applied during the photolithography step The use of Az1microm and EBR are
critical to enable the fabrication of small air-bridges and emitter sizes
The exposure time during the photolithography technique also needs to be
increased to achieve a 1microm size air bridge A longer time than normal is required thus
95 seconds is used for exposure under UV light Once finished appropriate
development time must be applied to ensure the line for the air bridge is perfectly
opened for the metal to fill up To get impeccable result in this step both combination of
exposure and development have to be tuned naturally leading to trade off in both Too
long exposure and developing time will break the bridge whereas for too short exposure
time and developing the air bridge will not open
There are two types of etching method used in this fabrication wet
(H3PO4H2O2H2O) and dry (NH4H2) etching Both have their own advantages and
disadvantages Wet etching is faster than dry etching However the etching profile is
highly isotropic and causes serious undercut The smaller devices which have
dimensional sizes of 6times6microm2 and below will ldquoshrinkrdquo the effective area under the top
contact metal Even though dry etching can have highly anisotropic etching profile
which can prevent excessive undercuts it requires a lot of time for etching the
semiconductor layers The NH4 and H2 plasma that are used in this technique do not only
etch the GaAs and AlAs layers but also etch the metal contact at the same rate as the
semiconductors Thus the metal area must be covered with a photoresist or thicker metal
(~1microm) must be used to counter this issue Figure 38 shows that the emitter bond pad
which is not covered by the resist will eventually be etched away by the dry etching
Figure 38 Dry Etching for the first run in this study
As mentioned in section 333 the advantage of H3PO4H2O2H2O wet etching is
that it can be made using two solutions fast and slow The fast solution is based on a
concentration ratio of 212 while the slow solution is based on a 3150 mixture The
103
212 fast solution will produce good anisotropic etch profile but is tricky to control due
to the rather high etch rate of 1000Aring per second Both fast and slow wet etching
solutions being carried out in this experiment are replicated from successful recipes that
were developed by other co-worker from Prof Missousrsquos group
342312 Issue of Over Etch under Top Metal (Wet Etching for Air-Bridge
Design)
The first run using the solutions mentioned above started with the deposited
metal as a top contact (Top contact must be defined first to make a bridge) then Mesa
etching to remove ~7000Aring GaAs using the fast etch solution The next process to be
followed was to employ the slow etch solution to etch down the epitaxial layer to the
substrate Doing this ensured that air-bridge was open and the devices isolated
individually Unfortunately unexpected results were observed where large undercuts
still appeared for both 2times2 microm2 and 6times6microm
2 devices Figure 39 shows severe undercut
under the big device that can clearly be seen in the digital scope Most probably this
problem occurs due to excessive time used for the wet etching (10 seconds for fast
solution and 10 minutes for the slow etch solution)
Figure 39 Severe undercut of 2times2 microm2 and 6times6 microm
2 devices
The second run was employed to reduce the wet etching time in total thus dry
etching was needed As discussed above CH4 and H2 are used to etch away the GaAs
and AlAs semiconductor material while O2 is used to remove polymer residues To
reduce redundant generated polymer during dry etching the process must be separated
into several goes (runs) In this run at the mesa etch step the metal area is covered by
S1805 resist and then the plasma etches down until the heavily doped Ohmic layer is
reached For the isolation step the slow wet etching solution is used to ensure the
semiconductor under the bridge is removed The etching time is still long ie over 5
Zoomed Zoomed
104
minutes Hence this will still generate appreciable undercuts Although this run
managed to reduce the wet etching time it still did not solve the undercut Figure 310
shows undercuts under the effective mesa area still occurring in this run
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet etched
Further investigation has been made to find the root cause of this issue Scanning
Electron Microscopy (SEM) picture were taken to see deep into the completed devices to
investigate what is actually happening Figure 311 shows clearly that the semiconductor
under the bridge and effective area under the 2times2 microm2 device went missing The same
goes to for the large device where about half the size of the designed effective area under
to metal was also unintentionally removed by the solution
Figure 311 SEM Images of the GaAs sample
Since this work was also run together with an InGaAs based sample
(XMBE326) new knowledge regarding etching profile was acquired The lesson learnt
from this run is that the wet etch profile of the Gallium Arsenic (GaAs) material is
totally different from that of InGaAs Figure 312 shows the cross section of GaAs and
InGaAs materials after wet etching The evidences of these issues are also indicated by
the SEM images in Figure 313 and Figure 314 This more or less explained the reason
why the semiconductor under the top metal contact is always missing when wet
chemical etching is applied
Zoomed Zoomed
105
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in this study
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
Figure 314 SEM images for InP and InGaAs taken from [56]
Furthermore previous work done by co-worker Dr Md Adzhar Md Zawawi has
optimised the process for RTD samples based on InGaAs and InAlAs heterojuction
semiconductor materials In this work Dr Zawawi found out that achieving submicron
dimensions is possible when using the soft reflow technique on InGaAs[102] However
it does not apply to GaAs when using the same technique There are few reasons to
106
believe that the work that was carried out by the previous student is not repeatable to the
XMBE304 GaAsAlAs material The main reason is due to the much thicker Ohmic
layers used in the GaAs of ASPAT structures which requires longer etch time The
sample that was used in the previous submicron work namely XMBE277 (RTD) [101]
and corresponding epitaxial layer structure is attached in appendix III The thickness
needed to be removed for the MESA step is 1421Aring compared to XMBE304 (ASPAT)
which is ~6900Aring
The fabrication results shown from the Air-Bridge design does not seem
favourable to the GaAsAlAs heterojunction sample These include unreproducible IV
characteristics and excessive undercut under the metal Therefore the GaAsAlAs
ASPAT sample cannot be processed using this type of mask (Air-Bridge approach) The
fabrication efforts were then moved to the Dielectric Bridge design described below
342313 DC measurement
Fully functional ASPAT I-V characteristics were not obtainable in this run due to
severe damages caused by the undercuts that happened underneath the top metal contact
As can be seen from Figure 315 the behaviour of the current response suggests a very
leaky diode This confirms that the air bridge approach does not work with the
GaAsAlAs ASPAT diode
Figure 315 Short circuit behaviour on one of the fabricated device in this run
-0015
-001
-0005
0
0005
001
0015
002
0025
003
0035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
mp
)
Voltage (Volt)
30x30BP
107
34232 Fabrication Process of the Dielectric-Bridge Design
Since the Air-Bridge design was not successful an alternative Dielectric-bridge
process flow was then designed to solve this issue The first run in this Dielectric-bridge
process was performed to ensure that when the fabrication was completed it was able to
produce the correct and reproducible ASPAT current-voltage characteristics The
process flow in this run is to follow the initial design which identifies the steps according
to the mask number Step 1 to step 4 in the process are exactly the same as in the 1st Gen
mask design Step 5 which is the bond pad process is then continued with spin coating
the AZ2microm After exposure and development a TiAu metal scheme with a minimum
thickness of approximately 1 microm is deposited
Table 36 Standard fabrication process flow for Dielectric-Bridge design
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa Etch
3 3 Isolation
4
5
6
7
4
5
6
7
Bottom Contact
Bond Pad
Via Etch
Bridge
Step 6 is quite complicated compared to the other steps where the introduction of
S1805 resist is used as a dielectric layer to prevent short circuit between top and bottom
contacts This includes opening the smallest via (holes within the dielectric layer) of 2times2
microm2 and 6times6 microm
2 emitter sizes This step started by spin-coating the S1805 resist and
was then followed by baking it at 150˚C for 30 minutes The longer baking time is to
ensure it is hard enough to be deployed as a dielectric layer Once the S1805 had
hardened as dielectric layer the sample was then spin-coated again with S1813 (thicker
resist) on the dielectric layer to act as a mask for vias opening (to cover the dielectric
layer from via etching damages) After the S813 was developed O2 plasma etches was
108
applied to remove the S1805 that covered the top metal and bond pads The hole on the
metal was then exposed This required only two minutersquos plasma etches time
As soon as the holes were created within the dielectric layer a quick clean to
remove S1813 was performed using Acetone and IPA This has to be fast enough to
remove the S1813 without removing the S1805 dielectric layer Mask 7 then defined the
area for the metal that will fill up into the open vias This metal connected the top
contact metal of the device to the bond pad (GSG pad) The same metal scheme as
mentioned in Section 3422 was used as the bond pad
The fabrication using the dielectric bridge approach in the 2nd
Gen mask design
appeared to work successfully when initial I-V characteristics were taken and it also
showed that the ASPAT diode was fully functional However using hardened S1805 as
a dielectric layer is not a good practise for manufacturing device since there were left
over residue on the sample surface as depicted in Figure 316 This residue comes from
the non-uniformity of S1805 resit that was formed during heat treatment Therefore the
next run was to avoid using S1805 but replacing it with a standard dielectric layer based
on Silicon nitrite (Si3N4)
Figure 316 The surface of the sample after final processing
342321 DC measurements
Given that the process of qualifying mask steps for GaAsAlAs ASPAT diodes
looked promising using the dielectric bridge approaches initial I-V characteristics
measurements were carried out for XMBE304A Figure 317 shows that the I-V
characteristics are comparable to those of the other runs ie in the 1st Gen mask
Noticeably the IV characteristic (Figure 317) between each device size does not scale
109
on a single line This is attributed to the unintentional variation in the size of the emitter
during wet etching within each sample
Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2 2500 microm2 900
microm2 400 microm2 225 microm2 100 microm2 and 36 microm2
The current densities shown in Figure 317 are calculated based on a reduced
effective area of the devices by a factor of 08 This assumption is made as actual area
(without metal) is un-measurable Theoretically devices with small areas will have
higher resistances compared to larger devices However the opposite occurred in these
devices This problem is still under investigation It could be due to the spreading
resistance producing different values according to device sizes (smaller devices have
longer D while bigger devices have shorter D)
34233 Dielectric-Bridge Process Optimization (Si3N4)
Due to poor surface roughness of the sample when using S1805 as dielectric
layer this run was employed to improve the surface quality by using Si3N4 In order to
get the actual size of the emitter the processing needed to start by defining the
semiconductor area using either top contact mask or mesa etch mask and not to deposit
the metal first Smaller effective area will be obtained if the top contact mask is used to
define the area compared to the MESA mask since there are 05 microm and 1 microm tolerances
designed in the MESA mask
-000001
0
000001
000002
000003
000004
000005
-2 -1 0 1 2
Cu
rren
t D
en
sity
(A
mp
microm
2 )
Voltage (Volt)
Current Density vs Voltage
density36
density100
density225
density400
density900
density2500
density10000
110
Table 37 New arrangement of the mask number and step in Second Run
Mask Number Step number Process
3 1 Isolation
22A 2 Mesa Etch
4 3 Bottom Contact
6
1
7
5
4
5
6
7
Via Etch
Top Contact
Bridge
Bond Pad
The fabrication was initiated by isolating each device using Mask 3 to define
them individually Then MESA mask (Mask 2) was used to cover the area from wet
etching optical measurement were used to obtain the actual size of the emitter without
metal Figure 318 shows the process results after H3P04H2O2H2O etching for a ratio of
3150
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm Tolerance
Although the mask was designed with smaller size of 6times6microm2 using the slow etchant
solution the effective emitter size can still shrink to ~3times3 microm2 and ~2times2 microm
2 as can be
seen in Figure 318 The next step was to define the bottom contact using a metal scheme
that is suitable for GaAs ohmic layer ie AuGeNiAu After lift-off the samples were
then cleaned and spin-coated with AZ2microm Then the area was defined by using Mask 6
allowing the exposed area to be filled by Si3N4 which is the dielectric layer used in the
second run However a tricky issue happened here as the Si3N4 was difficult to lift-off
especially on the smallest emitter area in this mask In this run the lift-off process was
successfully done after three days Step five which uses Mask 1 was to define the top
111
contact The same metal scheme will fill up the tiny holes within the dielectric layer to
attach on the emitter semiconductor Figure 319 below shows an optical image of a
6times6microm2
device after the top contact lift-off process Once lifted-off annealing took place
to ensure Ge diffuse into the GaAs contact layer to lower the resistance
Figure 319 After lift-off processing
Step six uses Mask 7 to define the area of metal connection between active areas
to the bond pad In this step and step seven a different metal scheme from the top and
bottom contact was used to connect metal to metal Here a TiAu scheme was used The
final step (step 7) was to define the bond pad area In this context mask 5 is used The
bond pad requires thicker metal thickness to reduce the series resistance and to increase
the robustness of the metal surface when probed with needles during measurements
This second run of 2nd
Gen mask dielectric approach went well with better samplersquos
surface when using Si3N4 as the dielectric layer compared to the previous run using
S1805 Once the bond pad were defined for each device as done in previous run the
preliminary current-voltage characteristics of the Si3N4 run were obtained This is
described in the next section
342331 DC measurements
As mentioned in the previous section the Si3N4 run started with a defined emitter
area This allows actual ASPAT dimension to be measured thus the current density
versus voltage that are plotted in the following figures are based on actual measured
sizes
112
Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
Although the actual area of each device is obtainable from measurement the current
density of this sample does not scale well either Figure 320 show the current density is
not scalable from 03V to 1V This probably happened due to the same issue related to
the spreading resistance for each diode varying To investigate this issue new runs were
required with intention of reducing Rsprd and were expected to lead to more scalable
devices Therefore a study of reducing the spreading resistance (Rsprd ) due to
contribution of the large D-gap was carried out using the 2nd
Gen mask with the Si3N4
dielectric bridge approach The following section discusses in detail the steps used in
reducing the gap between the top and bottom contact for the GaAsAlAs ASPAT diode
34234 Dielectric-Bridge (Si3N4) Process Optimization by varying the D-Gap
The series resistance as discussed in detail in Section 26322 is generally due to
the total contribution of specific contact resistance in particular the diode size the sum
of all doped layer resistances that sandwich the main ASPAT layer and the spreading
resistance which comes from the lateral structure diode design[33] Thus in order to
acquire better performance at high frequency these contributors must be controlled One
parameter that can be controlled through this fabrication process is to reduce the
spreading resistance by controlling the separation between top and bottom contact ie
the D-gap as indicated in Figure 321
-000001
0
000001
000002
000003
000004
000005
-1 -05 0 05 1
Cu
rren
t D
ensi
ty
(Am
pm
2)
Voltage (Volt)
Current Density vs Voltage
D36
D100
D225
D400
D900
D2500
D10000
113
Figure 321 side view of lateral ASPAT structure
Without designing a new mask at this stage the same 2nd
Gen Dielectric-Bridge
mask was used but the process flows did not follow the sequence order of mask
numbers The reason for deciding not to design a new mask to reduce the D-Gap was
because the fabrication process flow had not yet confirmed it repeatability and
reproducibility Thus the available photo mask at that moment was fully utilised
Furthermore the feature of the 2nd
Gen mask that included the mesa tolerance can be
exploited in this study Hence the initial idea was to reduce the length of D by using the
tolerance that was designed in with Mask 2 (MESA etch mask)
Table 38 New arrangement for the Third run using Dielectric-Bridge mask
Mask Number Step number Process
1 1 Mesa Etch
3 2 Isolation
3
2
3
4
Bottom Contact
Mesa Cover
6
1
7
5
5
6
7
8
Via Etch
Top Contact
Bridge
Bond Pad
The process therefore was initiated by cleaning the sample and was then
followed by spin-coating it with S1805 to cover the emitter contact and define the actual
D-gap
114
size of the diode This first step used Mask 1 with wet chemical etching using the slow
solution (H3P04H2O2H2O etch with a ratio of 3150) Once the resist was striped
optical measurements were performed to obtain the effective area of the emitter Figure
322 below shows the smallest emitter area obtained after etching
Figure 322 The measured size of the emitter area and the length D (blue color marked)
Step two was to isolate the devices individually by using Mask 3 This was
performed using the fast etch solution (H3P04H2O2H2O etch with ratio of 212) This
took about 10 seconds to remove about 10000Aring of material
Step three which involved two masks was the most complicated in this process
Firstly Mask 3 was used to define the bottom contact by covering the sample with
AZ2microm and then the sample was hard- baked at 190 ˚C for 4- 5 minutes to ensure it had
totally dried before applying Polydimethylglutarimide (PMGI) The PMGI type used in
this process is Lift-off Resist (LOR) SF11 After spin-coating the SF11 at 7000RPM for
45 seconds it was post-baked at 190 ˚C for 4 minutes This was done to ensure that the
LOR SF11 was hard enough for the S1805 to stick on it This was followed by spin-
coating S1805 at 4000RPM for 30 seconds and exposing it under i-line UV for 20
seconds and developed using Micro Dev mix with DI water (11 ratio) for one minute
When the correct shape of S1805 was formed the sample was exposed under flood UV
for 15 minutes The SF11 was developed with 101A developer for 1 minute Figure 323
below summarizes the whole process in step three The step three processes concluded
by depositing the bottom contact with alloyed metal scheme and once lift-off had taken
place the next step continues as usual
115
Figure 323 Summary of LOR technique steps
Step four as well as the subsequent steps were completed in this run by copying
from the previous run (ie second run) which was to deposit the Si3N4 as the dielectric
layer and so on All the devices that underwent fabrication using this technique were
measured under optical microscope MC60 assisted by the Walsall software tool in the
lab From the measured value obtained it was expected that reducing the length of D in
this technique would improve the spreading resistance by up to 70 from the original
2nd
Gen mask design Table 39 summarizes the calculation of original spreading
resistance and improvement using this technique The calculation method and equation
are taken from Section 26322
Table 39 The outcome of the spreading resistance before and after using LOR technique
Device Size(microm2) D-original(microm) RSprd(Ω) D-new(microm) RSprd(Ω)
100x100 4 056 163 023
50x50 14 327 194 054
30x30 19 602 163 097
20x20 21 832 212 135
15x15 22 1007 202 18
10x10 24 1293 205 252
6x6 25 1643 230 418
116
Technically from the experiment in this run it was observed that the development time
also controlled the final length of D longer development time produced shorter D
lengths while shorter time yielded larger D gap lengths Therefore in this run the
development time was kept constant because of the desired D length from the mesa
tolerance in general is only ~2microm
342341 DC measurement
As usual when wafer processing was completed early DC measurement took
place to check the diodes performance Each diode size was measured and compiled
into one graph as shown in Figure 324 It is clear that the performance was better than
that in the previous run in term of scalability and current conductivity
Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
To compare the current conductivity from this run and the previous run current
density at 05V was measured for both 2nd
and 3rd
runs Assuming the contact resistances
(TLM) for both runs were constant for 50times50microm2 device size the improvement of
current in the 3rd
run is about 92 This showed that such approach to reduce the D-gap
-500E-06
000E+00
500E-06
100E-05
150E-05
200E-05
-2 -15 -1 -05 0 05 1 15 2Cu
rre
nt
De
nsi
ty (
Amicro
m2)
Voltage (Volt)
Den_100microm2
Den_225microm2
Den_400microm2
Den_900microm2
Den_2500microm2
Den_10000microm2
Den2_36microm2
117
was successful in this run A new mask design was ready to take the challenge for
processing toward millimetre and sub-millimetre wave application
343 Fabrication process of GaAsAlAs ASPAT diode toward High frequency
Applications
So far the information that can be gathered from previous processing is that the
optimum process flow is achieved through dielectric approach design The effort in
reducing the series resistance by lowering its biggest contribution was attained through
lowering the D-Gap in the structure Once everything had been optimized ie the
process flow series resistance junction capacitance etc it was time to develop a new
mask design which only focused on the development of small ASPAT devices for use in
the millimetre and sub-millimetre wave regions
3431 Third Generation (3rd
Gen) mask design
The 3rd
Gen mask design was developed by taking into the account every aspect
of parameters that can contribute to the device by means of robust devices that are able
to function properly at ultra-high frequency The device cut-off frequency is given by
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(31)
Here RS is the series resistance and Cj is the junction capacitance To obtain high cut-off
frequencies Rs and Cj must be kept as low as possible From the fabrication point of
view two parameters that can be directly and easily controlled are the device area (A)
and the D-gap (which contributes to Rs)
Therefore calculations were made to find the best option Table 310 shows the
calculated value of capacitance (eq230 in page 44) and cut-off frequencies (eq31
above) for the ASPAT diodes studied These two equations extract the cut-off frequency
of the ASPAT assuming no external effects and for fully depleted devices The
XMBE304 ASPAT sample is expected to be suitable for millimetre wave applications
if small devices are successfully made In real devices sub-millimetrewave operation
can be hard to achieve due to increased series resistance and other process related
parasitics
118
Table 310 DC and RF characteristics for XMBE304
Device Size (microm2) Fully depleted
Capacitance(fF)
Calculated Series
Resistance (Ω)
Fully depleted Cut-Off
Frequency(GHz)
10000 5490 04 72
900 490 15 216
36 198 7 1148
16 879 11 1646
4 22 29 2500
Therefore in the 3rd
Gen mask design the smallest device that can possibly be obtained
in the GaAs based material fabricated using i-line lithography which is available at the
University of Manchester is 2times2microm2 and the gap between top and bottom is 15microm at
least The connecting bridge technique applied only utilised dielectric bridge method for
GSG features Figure 325 shows the layout of actual 3rd
Gen mask used in this study
There are 344 die chips on this type of mask design It also includes the Ground-signal
ground pad with 50um pitch for each chip and six de-embedding test structures as well
as eight TLM structures
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and alignment mark
structures used in this study
119
This mask is designed generally from optimizations from 2nd
Gen Mask which
deploys a dielectric bridge for connection between the devices to the bond pads
Consequently the processing steps are not being much different but mostly follow what
is shown in Table 311 below The difference only applies to the much smaller mesa
size Other features included in this mask are de-embedding structures for RF
measurements via-hole test structure TLM structures and parallel plate capacitance test
structures
Table 311 3rd
Gen Mask process step
Mask Number Step number Process
1 1 Mesa Etch
2 2 Isolation
3
4
3
4
Bottom Contact
Mesa Cover
5
6
7
5
6
7
Via Etch
Top Contact
Bond Pad
The high frequency fabrication process flow is summarized in the following section
which shows illustrations in three dimensional and cross sectional (Figure 326) views
for easy understanding
34311 Step by Step Processing
0 Wafer preparation
Cleaning using NMP and DI
water or
Acetone and IPA
120
1 Mesa Etch
2 Isolation
3 Bottom Contact
4 Mesa Cover (Dielectric Deposition)
5 Via Etch
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 3110
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 212
Metal deposition with metal
scheme AuGeNiAu for
~500nm thick
Dielectric deposition 500nm
thick Si3N4
Via etch to open holes for metal
contact using reactive ion
etching using CF4
121
6 Top Contact
7 Bridge and Bond Pad
Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-insulating
substrate device type used in this study
Figure 327 Example finished process device with bond pad using 3rd
Gen mask
3432 TLM measurements
Transmission Line model (TLM) measurements for this run were carried out
after annealing (ie at 420˚C for 2 minutes) for process control monitoring by extracting
contact resistance (Rc) values These values are a measure of the quality of ohmic metal
contacts for a given process As discussed in Chapter 2 the TLM technique used four-
Metal deposition with metal
scheme AuGeNiAu for ~500nm
thickness and thermal annealing
420˚C for 2 minutes
Metal deposition with metal
scheme TiAu (1microm thick)
122
point measurement on TLM test structures located around the 15times15mm2 tiles as shown
in Figure 222 (in page 55) Normally five TLM structures are measured across the tile
for both top and bottom contacts Figures 328 and 329 display graphical TLM results
for top and bottom contact respectively As can be seen both graphs exhibit excellent
uniformity
Figure 328 XMBE304 TLM measurement for the top contact after annealing
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing
Based on the graphs above for the top metal contact the average contact
resistance (RC) value using the metal scheme of AuGeNiAu is found to be ~005Ωmicrom
and the sheet resistance (RSH) is 22Ω However for the bottom contact the average
value for contact resistance is 012Ωmicrom and sheet resistance obtained is 26Ω Both
values are in a very good agreement with the known doping of both ohmic contact
0
2
4
6
8
10
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins top contact
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins bottom contact
y = 02157x + 01053
123
layers Therefore the specific contact resistance (Eq 250) that contributes to the total
series resistance can be calculated and the value obtained is 15Ωmicrom2 and 54Ωmicrom
2 for
top and bottom TLM structures respectively
3433 DC characteristic measurements
Again once the wafer processing is completed room temperature DC
characteristics are taken using an HP 414B or HP500B parameter analyser and its actual
setup is as described in Chapter 2 This initial measurement was to ensure the
functionality of the diodes For this run using the 3rd
Gen mask the I-V measurements
for mesa active area of 4times4microm2 6times6 microm
2 and 10times10 microm
2 were taken and are depicted in
Figure 330 Figure 331 and Figure 332 respectively Nine diodes were measured for
each three device sizes to check their uniformity Thus the average current and standard
deviation are taken at two voltage steps of 1V and 15V Table 312 summarizes the
standard deviation for each measured data obtained from this final run
Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
4times4microm2 mesa size
-00005
0
00005
0001
00015
0002
00025
0003
00035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C01_4um_1P_SI
C22_4um_1P_SI
C40_4um_1P_SI
W01_4um_1P_SI
W22_4um_1P_SI
W40_4um_1P_SI
AI01_4um_1P_SI
AI22_4um_1P_SI
AI40_4um_1P_SI
124
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
6times6microm2 mesa size
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature
for 10times10microm2 mesa size
Table 312 Standard deviation at two different voltages
Device size (um2) Standard Deviation 1V () Standard Deviation 15V ()
4times4 14 14
6times6 65 72
10times10 44 39
Noticeably the standard deviation of the device increases for the smaller size
devices This trend happened probably because the active mesa area is not uniform
causing different series resistances Since the smallest mesa active area which achieved
-0001
0
0001
0002
0003
0004
0005
0006
0007
0008
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C02_6um_1P_SI
C23_6um_1P_SI
C41_6um_1P_SI
W02_6um_1P_SI
W23_6um_1P_SI
W41_6um_1P_SI
AI02_6um_1P_SI
AI23_6um_1P_SI
AI41_6um_1P_SI
-0005
0
0005
001
0015
002
0025
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C03_10um_1P_SI
C24_10um_1P_SI
C42_10um_1P_SI
W03_10um_1P_SI
W24_10um_1P_SI
W42_10um_1P_SI
AI03_10um_1P_SI
AI24_10um_1P_SI
AI42_10um_1P_SI
125
a good I-V characteristic is 4times4microm2
in this run these devices were used for the next step
of characterisation which is the S-parameter measurement to extract their behaviour at
different frequencies
35 Conclusions
In this chapter basic fabrication techniques of GaAsAlAs ASPAT on both doped
and semi insulating substrates using standard I-line lithography as well as step by step
descriptions to achieve reproducibility in the process fabrication flow has been
demonstrated with relevant initial measured results Two major outcomes have been
demonstrated firstly related to repeatability reproducibility and manufacturability
mostly done on large device areas (15times15microm2 to 100times100 microm
2) Secondly a successful
process flow for small emitter size devices (2times2 microm2 to 10times10 microm
2) has been
developed
Subsequently two types of designs during process optimization were developed
namely Air-Bridge and Dielectric-Bridge approaches The latter approach seems
favourable for GaAsAlAs materials but was only successful when reducing the series
resistance of the device This problem was addressed by optimising the D-gap between
top and bottom contact which resulted in good scalability of each ASPAT dimensions
improving current conductivity by 92 and achieving a reproducible process On the
other hand in the former approach issues were encountered with over etching underneath
the diode effective area and thus it was hard to achieve reproducible devices
Repeatability reproducibility and manufacturability fabrication processes based on
dielectric bridge method were successfully developed This new process provides a
highly efficient and economical solution for the fabrication of GaAsAlAs ASPAT
diode Emitter sizes down to 4times4 microm2 dimensions are routinely and reproducibly
achieved in this process Series resistance which is an important parameter in
determining high frequency application are greatly reduced by changing the gap between
top and bottom contact
With all the new improvements implemented the possibility of the proposed Dielectric
Bridge method fabrication process was successfully applied for the fabrication of
ASPAT diodes
126
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT
DIODE USING SILVACO
41 Introduction
Fabricating any device or circuit requires a lot of time resources cost etc
especially elements related to the production of semiconductor devices Furthermore in
realising such a device a clean room is required Hence fabrication and processing in
wafer fab need full attention to get it done with a higher rate of success reproducibility
and manufacturability One solution that can be highlighted which will be able to reduce
all the resources that are mentioned above is by using computer simulation approaches
or to be precise physical modelling For epitaxial layer based devices physical
modelling is a good choice as it would give a better understanding and insight into each
layer and how electrical characteristics are derived A software that is most suitable for
epitaxial layer physically modelled is SILVACO This software is a very comprehensive
tool to simulate epitaxial based devices and to predict their behaviour Such software
covers many aspects starting from the first principles of physic epitaxial layer
definition as well as device layout thus making it the most powerful virtual wafer fab
tool in the market
In this chapter the SILVACO packages are discussed The discussions include the
method of defining a new material defining models and constructing the AC or DC
supply to obtain the output characteristics of the virtual device Apart from these the
focus will also be on the ASPAT diode modelling simulation and analyses of the results
which will include the ASPAT structure suitable models and DC current-voltage
characteristics The dependencies of individual structure on the I-V curves will also be
highlighted Finally the discussion of results and analyses involving a range of
operational temperatures dependency as well as from comparison made to conventional
SBD used in this study will be examined
127
42 SILVACO modelling Tools
SILVACO is a modelling software introduced in 1984 by Dr Ivan Pesic It is
purposely created for electronicsrsquo devices physical modelling and characterization This
software company has become the major supplier for most of the Electronic Design
Automation (EDA) for circuit simulation amp design of analogue Mixed-Signal and RF
circuit market This Technology Computer Aided Design (TCAD) software can predict
the simulated device performances starting from first principles It has a package which
can provide Virtual Wafer Fabrication (VWF) simulation to the device designer and
which has the capability to perform two or three dimensional physical device modelling
by using the ATLAS simulator [103] SILVACO allows all parameters such as
electrical thermal and optical characteristics of a device to be simulated under desired
bias conditions It offers cost effectiveness as well as quick prediction of results for
many semiconductor devices compared to real experiments Some hands-on experiment
may not always perform hence SILVACO can be used as an alternative
The core of SILVACO is Atlas itself which provides a platform to perform DC AC
and transient analysis for such dimensional device structure regardless of the
heterojunction material type ie binary ternary quaternary etc As the brain of
SILVACO Atlas which receives input command files containing instruction text for
execution from a runtime environment known as Decbuild will process the instruction
text and display progression error and warning via Runtime Output All the calculations
of the resultsoutcomes of the simulation are plotted via a tool called TonyPlot which is a
tool to visualise the output Figure 41 below shows how precisely the physical
modelling takes place the process of building the structure how its parameters and
variables are defined how an appropriate model statement is selected how performance
is analysed and lastly how the outcomes are displayed
128
Figure 41 SILVACO Atlas simulation process flow
As can be seen in Figure 41 the structure specification statement is used to define
any desired structure by setting the command in Deckbuid of the following parameters
a) Mesh where the structure can be defined either in 2D or 3D Cartesian grids The
unit of the coordinates used is in microns and the spacing parameters which
define the netting size can be used to improve the accuracy of the analysis at any
given position The density of netting size in this statement determines the
processing time
b) Region where the multi-layers in a structure are defined and this statement has
to outline each layer that represents a separated region independently The mesh
must be assigned to a region and the sequence of the region is arranged from low
to high
-Mesh -Region -Electrode
-Contact -Material
Structure Specification
-Model -Interface
Model Specification
Method
Numerical Method
-Log -Solve -Load -Save
Solution Specification
-Tony Plot
Display Results
129
c) Electrode are used to define the location of bias point for a designed structure
when performing the electrical analysis In this work or for the case of a diode
two electrodes are allocated as an anode and a cathode In a vertical device the
latter electrode is placed at the bottom of the device while the anode is at the top
d) Doping this statement refers to doping concentration injected into the desired
region and it normally depends on the material types
e) Materials since SILVACO was developed specifically for Silicon-based devices
default parameters are set up for Silicon properties However the use of
materials statement allows SILVACO to run for different material ie GaAs
InGaAs etc In order to make it work this parameter is defined first and then
followed by the material name and its properties such as bandgap permittivity
conductionamp valence band discontinuities mobility etc
The most crucial part is to determine whether the simulated structure of a particular
device is correct or incorrect This is done by properly choosing the specific model
statement The Specific model statement is employed to express the physic equations
that are used during the device analysis The models statement depends solely on the
structure definition Examples are device structure with double barrier use Non-
equilibrium Green function (NEGF) model and single barrier uses Semiconductor-
insulator-Semiconductor (SIS) model for effective and accurate analysis process For the
case of a single barrier in SILVACO there are many model statements that can be used
for such analysis Therefore it is recommended to check model by model in order to
ensure that all the needed parameters are defined in the material statements and results
produced are valid
SILVACO is able to calculate such models by using different numerical methods
which means semiconductor device problematic is computed to make successive
solutions by random discretisation There are three different numerical methods that are
regularly used by SILVACO to perform its calculations which are Newton Gummel and
Block Basically this is solved by using a non-linear iteration procedure which begins
from an initial guess and which then uses an iterative process to find the predicted
solution The detail of these can be found in reference [103]
130
In order to turn on the problem solution the solution specification is defined This
include log solve save and load statement All these work together to provide data for
analysis by other functions The log statement is a file type that saves in memory and can
be loaded by Atlas Any solved device will be stored in the log file Therefore it is
necessary to define the LOG before SOLVE statement and close it after the calculations
While the save statement is used to store all data point to a node in the output file the
load statement is utilised to recall all the saved data to be read by Atlas
Finally all these files can be displayed or plotted on TonyPlot it is recommended to
make SET files at plotting point for a better visualisation The plotted or displayed files
in TonyPlot can be manipulated for scaling graphs overlaying different curves and most
importantly to export the data to other files formats
43 SILVACO Implementation GaAs AlAs ASPAT Modelling
The structures play an important role in determining the terminal output
characteristics Therefore to start simulating the ASPAT device the first thing that must
be specified is its structure As mentioned earlier in Section 3412 the ASPAT diode is
a top down multilayer structure This structure which is adopted from that of Section
3412 will be used as a basis to perform the ASPAT simulation Figure 42 shows the
structure of the ASPAT in this real simulation which is exactly the same as been
discussed in Section 26322 The ASPAT diode consists of two heavily doped (up to
5x1018119888119898minus3) GaAs contact layers on top and bottom slices adjacent to lightly doped (up
to 3x1017119888119898minus3) GaAs intermediate layers In between these layers is a sandwiched
structure consisting of two different lengths of undoped GaAs spacer layers and a thin
layer of AlAs that act as a tunnel barrier In this work the simulation result will be
compared with the fabricated measurement result depending on the size of the diode
The actual device that will be used to validate the simulation is the main device used in
this study (XMBE304) which is based on a lattice matched GaAsAlAs grown on a
semi-insulating substrate Therefore the design structures that are proposed in the
fabrication are compatible with the fabricated devices and are based on lateral structures
as can be seen in Figure 42
131
Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the diode
multilayer heterostructures on the right
In the consequent simulations a key observation regarding the AlAsGaAs
heterojunction is that there are two types of tunnelling processes direct tunnelling and
indirect tunnelling Figure 43 shows the Energy-Momentum (Ek) diagram depicting the
three valleys for the AlAs conduction band namely L Γ and X points In normal
circumstances the transition of electrons happens to the X-point which is the lowest
energy in the conduction band In the case of very thin barrier the tunnelling process
occurs at the Γ point in both AlAs and GaAs materials which is the direct tunnelling
process[18] It has been reported that in the case of an ASPAT diode tunnelling which
occurs at the Γ point will be the dominant component in the tunnelling current
Therefore the actual band gap will be different from the one at the X-point which is
which 216eV[15] By contrast the energy band gap at the Γ-point is around
283eV[104] Thus this simulation uses this band gap value
Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor
216eV
Γ
X
E
K
L
AlAs
CB
VB
283e
132
The simulation code as attached in Appendix IV and the output of the simulation with all
the input mentioned above are shown in Figure 44 (a) and Figure 44 (b) Figure 44 (a)
is the band diagram at equilibrium and Figure 44 (b) is the band diagram when a bias is
applied
Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure (b) the
energy band diagram of the ASPAT diode structure when under three different biases
44 Simulation Result and Analysis
Basically the SILVACOrsquos Atlas simulation package is used to calculate the I-V
characteristics from multilayers structures In the case of GaAsAlAs heterojunctions all
details of the structure as shown in Figure 44 above are calculated based on solving the
Schrodinger time-independent equation in each layer taking into account the variation of
effective mass and conduction band offset between GaAs and AlAs
For thermionic emission and tunnelling mechanism across an abrupt heterojunction
interface the general method used in SILVACO is taken from K Y Yang work [105]
The tunnelling current of the ASPAT diode uses the equation below[74]
119869 = sum2119898lowast119864119894(1 minus 119877)119896119879
1205872ħ3
119873
119894=1ln [
1 + exp (119864119865 minus 119864119894
119896119879)
1 + exp (119864119865 minus 119881 minus 119864119894
119896119879)]
(41)
Where m is the electron effective mass E denotes the energy of the electron R is the
total resistance k represent Boltzmann constant ħ is the reduced Planck constant EF is
the fermi level V is applied voltage and Ei is the electron energy perpendicular to the
-2
-15
-1
-05
0
05
1
15
1
82
16
3
24
4
32
5
40
6
48
7
56
8
64
9
73
0
81
1
89
2
97
3
Ene
rgy(
eV
)
Thickness (microm)
VB
CB
133
barrier The important parameters that enable SILVACO Atlas to perform correct
calculations and analysis are the choice of appropriate models The suitable model that is
available for evaluating the GaAsAlAs ASPAT is based on the Semiconductor-
insulator-semiconductor (SIS) model
Thus in this run Non-local Quantum Barrier Tunnelling Model (SISEL and
SISHO) are utilized specifically semiconductor-insulator-semiconductor mode This
model enables the tunnelling current between two semiconducting regions separated by a
quantum barrier to be calculated [103] It is assumed that the charge tunnels across the
whole barrier with the source or sinks at the interface with the semiconductor regions
Under the Non-Local Quantum Barrier tunnelling model another model that can be used
is semiconductor-semiconductor-semiconductor (SS) tunnelling model if the materials
are specified By correctly inserting all parameters with the right model an excellent DC
IV characteristic match between simulation and measurement can be produced as shown
in Figure 45
441 DC Current-Voltage Characteristic
In this simulation the current at each bias step and each mesh point can be set up by the
user however the detailed calculation such as formula usage methodology and
approach that is adopted by SILVACO Atlas is unknown As mentioned above in order
to produce the energy band diagram of the ASPAT the DC characteristic of the structure
can be solved by using the Schroumldinger and Poisson equation self-consistently
To ensure that these simulations are valid one fabrication was performed on an
ASPAT diode sample XMBE304 For this sample the structure parameters are the
same as has been set in this simulation The result of the measurement and simulation
are then compared Figure 45 shows that the simulation result is in excellent agreement
with the measured data for this sample
134
Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm2) and (4times4microm
2)
using SILVACO Atlas simulator for structure device XMBE304 showing excellent agreement
between simulated and experimental data
These fitted results were performed on both a large 100times100microm2 device and the
smallest obtainable from fabrication (4times4microm2) which was to be used for the repeatability
amp reproducibility studies as well as for high-frequency applications study respectively at
room temperature In order to get a good fit a few parameters had been modified in the
SILVACO software via the Deck-built tool for example energy band effective masses
and bandgap discontinuity of GaAs spacer and AlAs barrier (The mentioned parameters
values are summarized in Table 41) The percentages of bandgap discontinuity in
SILVACO using the ALIGN parameter is given by[103]
119860119897119894119892119899 =
Δ119864119862
Δ119864119862 + Δ119864119881
(42)
Where ΔEc and ΔEv are the conduction band discontinuity and valence band
discontinuity respectively The m0 in the tables denotes the electron rest mass Once all
agreement between measurement and simulation has been met the simulation is then
carried out with structure analysis at room temperature and different temperatures
simulation
Table 41 The parameter values used in this simulation
Material Bandgap(eV) ΔEg(eV) Effective mass(kg)
GaAs 1424 03 0067m0
AlAs 2835 071 0126m0
-00002
0
00002
00004
00006
00008
0001
00012
-2 -1 0 1 2
Cu
rre
nt
I (A
mp
)
Voltage V (Volt)
Current vs Voltage
Measurment
Simulation
135
45 Structure Analysis of ASPAT Diode
Once the device structure was modelled and having successfully produced a
precise band diagram as well as validated the simulation results with experimental I-V
characteristics the next step is to further analyse the relationship between basic device
structure and its I-V characteristics This approach is used to predict what would happen
to the DC output if some of the parameters were varied especially with regards to the
AlAs barrier thickness In the subsequence simulations the thickness of each main
ASPAT (unequal spacers and barrier) layer will be studied independently as a variable in
order to determine how each parameter affects the I-V characteristic in both magnitude
and curvature The analysis will also include manufacturing tolerance where the
structure parameter which will result in a 10 difference in their I-V characteristics is
examined[59 75] This will provide an overview of how precisely to manufacture each
layer of the device The following simulation is based on the XMBE304 structure with
emitter size of 4x4microm2
451 Dependencies of current on AlAs Barrier thickness
Since the AlAs barrier is what limits the transportation of electron flow and
hence the current (which depends exponentially on the tunnelling barrier thickness)
therefore the first analysis to run on the simulation is the variation on barrier thickness
In the simulation the barrier thickness is measured in term of the monolayer Generally
one monolayer can be calculated by dividing the lattice constant of the material by two
In the case of AlAs one monolayer is calculated as follows
119900119899119890 119898119900119899119900119897119886119910119890119903(1119872119871) =
119860119897119860119904 119897119886119905119905119894119888119890 119898119886119905119888ℎ119890119889 (5666Å)
2
(43)
= 283Å
The nominal value of the AlAs barrier thickness for sample XMBE304 is 283nm
ie ten monolayers In the first simulation test the current change due to the barrier
thickness variation from 9ML to 11ML was examined first followed by the amount of
barrier thickness change that would produce a 10 change in current The simulation is
setup by fixing all other parameters and varying the AlAs barrier thickness as mentioned
136
above with a step of 02ML In order to determine what fraction of a ML would yield a
10 difference in the current the barrier thickness is slightly changed to fit the curve for
both 5 above and 5 below the original curve
Figure 46 IV characteristics of the dependencies of current on AlAs barrier
The current-voltage characteristics of the ASPAT diode do change dramatically with
barrier thickness in forward bias but not that much in reverse bias (Figure 46) The
current decreases as the barrier thickness increases For a 1ML change in layer thickness
(from 9ML to 11ML) the current changes by over ~300 at 05V
Figure 47 Example of analysis at -1 and 1V to the current
-00002
0
00002
00004
00006
00008
0001
00012
00014
-15 -1 -05 0 05 1 15
Cu
rre
nt
(A)
Voltage(V)
9ML
92ML
94ML
96ML
98ML
10ML
102ML
104ML
106ML
108ML
11ML
973E-06
0
0000005
000001
0000015
000002
0000025
000003
0000035
85 95 105 115
Cu
rren
t a
t 1V
B
ias
(Am
p)
Barrier Thickness (ML)
Current change with tunnel barrier thickness
Forward Current
5
-5
137
From the simulation result shown in Figure 46 a 9945ML barrier thickness will
give a 5 higher current and a 10056ML barrier will give a 5 lower current (Figure
47) Therefore in total 01 ML difference yields 10 current difference These indicate
that in order to control the current within 10 barrier thickness difference the growth
precision in the barrier must be precise to better than 01ML Extensive studies have
also shown that the I-V characteristic of a GaAsAlAsGaAs diode is very sensitive to
the thickness of AlAs barrier This work has been reported elsewhere[17]
452 Dependence of current on Spacer I length l1
For the longer spacer length (l1) five different values are chosen from 01microm to
03microm The lengths are changed in the order of 005microm Therefore the arrangement of
length is as follows l1=01microm l1=015microm l1=02microm l1=0 25microm and l1=03microm
respectively The results are plotted from -15V to 15V anode voltage in Figure 48 The
I-V characteristic of the ASPAT diode does not change much with the length in the
forward bias region but in the reverse bias region the current decreases as the layer
thickness increases Here the l1 layer acts as a voltage arm and a small size device
cannot sustain big changes in spacer length Changing the length at the forward region
will also change the energy states on the anode side as well changing the states
distribution on the cathode side in reverse bias
Figure 48 I-V characteristic of the dependencies current to Spacer I layer
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=01
L=015
L=02
L=025
L=03
138
By fixing the current at -1V and 1V the current and the layer thickness relationship is
illustrated in Figure 49
Figure 49 Current changes with layer thickness l1
It is noticeable that there is a dramatic change in reverse current from 01 microm to
05 microm layer thicknesses However the forward current only falls slightly from 01microm to
015microm and is stable afterwards Hence for a small size device a large change in spacer
layer at the cathode will allow more current to pass
453 Dependence of current on Spacer II length l2
Finally is the variation in the spacer II Similar to spacer I above five values are
chosen for the shorter undoped GaAs layer length l2 the thickness is varied from
00025microm to 00075 microm (steps are l2=00025microm l2=000375microm l2=0005microm
l2=000625microm and l2=00075microm respectively The results are plotted from -15V to
15V anode voltage as shown in Figure 410 In this case a slight change in I-V
characteristic in the forward bias can be seen clearly which means the I-V
characteristic depends on the length of the shorter undoped layer Therefore the l2 layer
also acts as another voltage arm due to the asymmetrical length The effect is quite
similar to the spacer l1 but this times the forward current only slight changes The reason
for the small change in current is that the length change is small and it linearly affect the
states distribution
-000002
-0000018
-0000016
-0000014
-0000012
-000001
-0000008
-0000006
-0000004
-0000002
0
0
000005
00001
000015
00002
000025
00003
000035
01 015 02 025 03
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)Reverse Current(-1V)
139
Figure 410 IV characteristic of the dependencies current to Spacer 1 layer
Fixing the current at -1V and 1V the current versus layer thickness relationship is
illustrated in Figure 411
Figure 411Current change with layer thickness l2
The I-V curve depends on the length of the shorter undoped spacer layer quite linearly
The forward current changes in increase to the layer compared to the backward current
The layer thickness l2 should be small as long as it prevents carrier diffusion Therefore
all these three layers must be kept within limit to ensure that the high performance of the
ASPAT diode can be fully utilised
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=75n
L=25n
L=625n
L=5n
L=375n
-2E-07
-18E-07
-16E-07
-14E-07
-12E-07
-1E-07
-8E-08
-6E-08
-4E-08
-2E-08
0
0
00002
00004
00006
00008
0001
00012
0002 0004 0006 0008
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)
Reverse Current(-1V)
140
46 Temperature Dependent Simulation
This section will discuss in detail how changes in operating temperatures influence
the IV characteristics of the ASPAT diode The same codes as in the previous
simulation with fitted results are used for this temperature dependence study but a few
parameters were changed for different temperatures
Theoretically the material parameters that are influenced by the change of
temperature are band gap electron effective mass the density of state (NC NV) light
hole mass heavy hole mass permittivity and electron amp hole mobilities However not
all mentioned parameters will have a large impact on the IV characteristic in the
SILVACO Atlas simulation The most significant factors that give appreciable impact on
the DC output current-voltage were the energy bandgap and the effective mass The
GaAs bandgap as a function of temperature is given by the equation below [106]
119864119892 = 1198641198920 minus
120572 1198791198712
120573 + 119879119871
(44)
Here Eg is the bandgap Eg0 denotes the bandgap at 0K TL is the Temperature α=
Constant (Varshni Parameter) AlAs6e-4 GaAs5405e-4 β= Constant (Varshni
Parameter) AlAs408 and GaAs204 The calculated parameters that are used in this
simulation are shown in Table 42
Table 42 The calculated values of bandgap at different temperatures
Temperature (K) GaAs Eg(eV) AlAs Eg(eV)
77 1506 2903
100 1500 2899
125 149 2893
150 1486 2887
175 1478 2879
200 1470 2871
225 1461 2863
250 1452 2854
275 1443 2844
300 1424 2835
325 1419 2824
350 1414 2814
375 1404 2803
398 1394 2793
141
The effective mass of the materials used in this simulation can be expressed by
119898119899 = 1198980119899 + 11989810 (
119879119871
300119870)
119898119901 = 1198980119901 + 1198981119901 (119879119871
300119870) + 1198982119901 (
119879119871
300119870)2
(45)
Where mn is the effective electron mass mp represents the effective hole mass m1n and
m1p are constant number for the basic GaAs material m0n
for 119898119883119898119871 119886119903119890 119892119894119907119890119899 119887119910 119905ℎ119890 119890119902119906119886119905119894119900119899 (1198981198991199052 lowast 119898119899119897)
13 while m0p is based on the
expression 1198980119901 = (11989811990111989732
+ 119898119901ℎ32
)23 The calculated parameters are shown in Table
43
Table 43 The calculated effective masses for each temperature used in this simulation
Temperatures (K) GaAs Effective Mass (kg) AlAs Effective Mass (kg)
77 00660m0 03790 m0
100 00658 m0 03788 m0
125 00655 m0 03785 m0
150 00652 m0 03782 m0
175 00649 m0 03779 m0
200 00646 m0 03776 m0
225 00643 m0 03773 m0
250 0064 m0 0377 m0
275 00637 m0 03767 m0
300 00634 m0 03764 m0
325 00631 m0 03761 m0
350 00628 m0 03758 m0
375 00625 m0 03755 m0
398 00622 m0 03752 m0
142
Figure 412 Measurement and simulation comparison result as a function of temperature range
from 100K to 398K
Figure 412 above shows excellent agreement between simulation and
measurement results at various temperatures The IV characteristics correspond to a
device of size 100times100microm2 as presented in Chapter 3
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes
As mentioned earlier in chapter one the tunnelling diode has many advantages
over conventional Schottky barrier diodes some of which are a large dynamic range
low power consumption and very weak temperature dependence This section will
discuss the effect of variable temperature applied to the GaAsAlAs ASPAT diode and a
similarly processed TiAu Schottky diode Two samples were fabricated together for
these studies (XMBE304 and XMBE104 representing an ASPAT and a SBD
respectively) The fabrication technique is exactly the same as has been discussed in
Chapter 3 In order to make it fair for direct comparisons as well as easy probing both
diodes were fabricated with the same emitter size (100times100microm2) The DC measurements
at different temperature were carried out using a Lakeshore Cryogenic probe station over
the range of 77K to 398K in 25K step interval
-002
-001
0
001
002
003
004
005
006
-2 -15 -1 -05 0 05 1 15 2
Cu
rren
t I
(Am
p)
Voltage V (Volt)
T=100K_Simu
T=100K_Meas
T=398K_Simu
T=398K_Meas
T=200K_Simu
T=200K_Meas
T=300K_Simu
T=300K_Meas
143
471 GaAsAlAs ASPAT diode vs TiAu SBD
Once fabrication and measurement were completed both DC outputs of the diodes
were characterised and analysed Figure 413 shows a semi-logarithmic plot for
measured current versus voltage as a function of temperature for ASPAT sample
XMBE304 In forwards bias the current changes for different temperatures from 77K
to 398K are less than 5 percent This confirms the very weak temperature dependence of
current transport as it is dominated by tunnelling through the barrier On the other hand
the backward bias shows the current changes at different temperature are slightly bigger
than in forward this due to band bending occurring faster (making the effective barrier
lower) and allowing thermionic emission to significantly contribute to transport of the
current The only other study of temperature dependence for the ASPAT was made by et
el RT Syme[15] but details were not stated in their report
Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample XMBE304
The effective barrier height for the GaAsAlAs ASPAT diode is higher than that of
the SBD (See Figure 414) therefore there is an expectation of more limited thermionic
current flow in the ASPAT than the SBD As mentioned earlier the conventional
Schottky Barrier diode that is used in this study consists of a Gold Titanium and GaAs
(AuTiGaAs) interface which is the baseline for the temperature dependence study
0000001
000001
00001
0001
001
-15 -1 -05 0 05 1 15
Log
Cu
rren
t (A
)
Voltage (V)
T=77K
T=100K
T=125K
T=150K
T=175K
T=200K
T=225K
T=250K
T=275K
T=300K
T=325K
T=350K
T=375K
T=398K
144
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT Diode [3]
The SBD epitaxial layers profile is as shown in Table 44 below Theoretically the SBD
obey thermionic emission transport[44] and its I-V characteristic is given by
119868 = 1198680[exp (
119902119881
119899119896119879) minus 1]
(46)
Where q is the electron charge V is the applied voltage across the diode n denotes the
diode ideality factor k is the Boltzmann Constant T is the absolute temperature in
Kelvin and I0 is the diode saturation current which is given by the expression
1198680 = 119860119860lowast1198792 exp (minus
119902empty1198870
119899119896119879) exp (minus120572120594119890
12120575)
(47)
here A is the area of the diode A denotes the effective Richardson constant Oslashb0 is the
barrier height at zero bias δ represents the thickness of interfacial insulator layer χ
denotes the mean tunnelling barrier and α = radic(4120587
ℎ)(2119898lowast) is a constant value The
ideality factor n is taken from the slope of the SBD current-voltage characteristic and in
this study its value varies from 1 to 2 (depending on temperature) In the case of the
ASPAT diode thermionic emission can also happen if a thicker barrier is used (~ 100Aring
or thicker) as shown by CS Kyono et el [104] who concluded that when a thicker
barrier of AlAs barrier is used the current transport is dominated by thermionic emission
145
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104)
Layer Material Doping(cm-3
) Thickness(Aring) Bandgap (eV)
Schottky GaAs(Si) 500E+15 7500 14
Semiconductor GaAs(Si) 300E+16 7500 14
Semiconductor GaAs(Si) 100E+17 7500 14
Ohmic GaAs(Si) 500E+17 7500 14
Buffer GaAs(Si) 300E+18 7500 14
Substrate GaAs(Si) N+ 3000 14
The fabricated SBD was also measured and its I-V characteristic is plotted as a
function of temperature in Figure 415 Unlike the ASPAT diode the current at forward
bias for the SBD change enormously with temperature from 77K to 398K and at all
biases For the ASPAT diode the slight change in current only started after 08V bias as
the current starts to have some component of thermionic emission over barrier
Figure 415 Log Current vs voltage as a function of temperature for SBD sample XMBE104
In order to see clearly how much the current is changing in forward bias for both
ASPAT and SBDs diode a log current at different voltages versus 1000temperature is
plotted as shown in Figure 416
1E-08
00000001
0000001
000001
00001
0001
001
01
-2 -1 0 1 2
Log
Cu
rren
t (A
)
Voltage (V)
T=398K
T=375K
T=350K
T=325K
T=300K
T=275K
T=250K
T=225K
T=200K
T=175K
T=150K
T=125K
T=100K
T=77K
146
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and SBD
Semi-logarithmic plots of current (at V= 05 06 07 08V) versus inverse
temperature for both SBD and ASPAT are shown in Figure 416 When the temperature
is increased the current also increases in the SBD as a result of thermionic emission
over the barrier for sample XMBE104 This is in contrast to the temperature-
independent tunnelling through the thin AlAs barrier of sample XMBE304 ASPAT
diode where when the temperature is increased the current is almost constant
At low and high temperatures the ASPAT shows excellent temperature
independence with a constant current flow It exhibits a tunnelling current in excess of
values expected by the elastic tunnelling current calculation equation suggested by RT
Syme [16 18] above (Eq 1) using a Oslash value of 105eV (ΓGaAs to Γ AlAs tunnelling) By
contrast for the SBD at low temperature (77K-275K) the changes of currents were very
high and for every 02V there is an exponential change of more than 40 This
temperature dependent study was also reported in[68]
147
48 Conclusions
This chapter demonstrated the establishment of an excellent physical model and
comparison of room temperature I-V characteristics of GaAsAlAs ASPAT diodes for
different emitter sizes their scalability as well as an investigation of their characteristics
at different temperatures from 77K to 398K Simulation are validated on well-
characterized experimental data and excellent fitting which had been achieved in this
work permit the designer to extract all related parameters of heterojunctionmultilayer
ASPAT structures thus creating modification for future growth specification in order to
achieved precise designs
It is clear that the work which had been carried out in this chapter is able to
achieve with adequate accuracy a claim of reverse engineering capability The ability of
the GaAsAlAs ASPAT to act as a zero-bias detector has been analysed and compared
with the SBD It is clear that the temperature stability which is shown by the
GaAsAlAs ASPAT is much better than that of the SBD thus demonstrating that the
tunnelling current is dominant over the thermionic emission in ASPAT diodes
148
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES
51 Introduction
To assist in circuit designs for any type of high-frequency circuits such as
millimetre wave detectors frequency multipliers and mixer circuits which are built
based on non-linear devices (diodes) an equivalent-circuit model for the diode is
required This is among the simplest and most effective method for analysing
semiconductor devices which work at high frequency where the electrical characteristics
measured obtained from the devices are extracted and presented in a circuit consisting of
lumped elements components (resistor inductor capacitor etc) However accurate DC
and RF measurement data is essential to extract the equivalent-circuit elements quickly
and correctly The extracted parameters values from the circuit that are taken into
account usually depends on bias and frequency associated with the device physically
which is also interrelated to the semiconductor material parameters device structure as
well as fabrication process flows
In this work the DC and RF data were derived from DC and S-parameter
measurements respectively These measurements were carried out both in-house and at
the University of Cambridge by a collaborator partner (Prof MJ Kelly) The I-V
characteristics of the diode obtained from DC measurements were measured from -2V to
2V while the S-parameters were carried out over a wide frequency range from 40MHz to
40GHz with eight different biases In this chapter the DC measurements for various
sizes of the diodes with analysis of their IV characteristics will be discussed The one-
port on-wafer ASPAT measurement setup as well as the de-embedding method will
also be explained Thereafter the equivalent circuit models with all lumped element
effect will be discussed This work is carried out with the help of the VNA which
principle has been described in Chapter 2 and Keysight ADS simulation tool All
technical details regarding the equivalent circuit models will be explained together with
the method used for the ASPAT diode evaluation The equivalent circuit model also will
cover the diode intrinsic elements such as Cj Rj and Rs and extrinsic elements ie CP
149
and RP Finally an equivalent circuit model with the small signal characterization of the
fabricated ASPAT diodes will be presented
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes
The recent development of state-of-art for DC measurement apparatus has led to
capabilities for high-level accuracy of measuring voltages to a few nano Volts and
current signals in the femto Amp range[107] This can easily be obtained by exploitation
of proper connections and high-quality cables connecting the equipment to the Device
under Test (DUT) In this work the DC measurements were carried out using an Agilent
B1500A Parameter analyser whose description was covered in Chapter 2
As was discussed in Chapter 3 the GaAsAlAs ASPAT diodes have been
fabricated with different mesa areas between 2times2microm2 to 100times100microm
2 but the smallest
size obtained with good I-Vs was 4times4microm2 In this section the focus will be on how the
extracted data can be expanded further for empirical modelling Figure 51 shows typical
results for measured ASPAT diodes with various dimensions to check for their
uniformity According to our standard procedure the DC measurement has to be
conducted prior to the RF to ensure the diode is in fully working order as this will later
save a lot of time during RF characterization
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2 6x6um
2 and
10x10um2 Note the good scalability
1E-10
1E-09
1E-08
00000001
0000001
000001
00001
0001-2 -1 0 1 2
Cu
rre
nt
De
nsi
ti (
Amicro
m2)
Voltage (V)
4x4microm^2
6x6microm^2
10x10microm^2
150
Figure 51 above demonstrates the IV Characteristics of measured GaAsAlAs
ASPAT diodes (XMBE304) for emitter sizes of 4times4um2 6times6um
2 and 10times10um
2 This
sample was processed using the dielectric bridge technique developed in this work It
can be observed that current per unit area for each dimension fits and scales to each
other The scalability of each diodes measurement is very important to ensure no process
related issues are hampering the devicersquos proper operations This also confirms that the
diodes are completely functional and can be used for the next stage of measurements
The advantage of having an excellent scalability of those diode sizes is that a prediction
of smaller emitter size can be made
This type of IV characteristic shows asymmetric behaviour which results from
the unequal spacer lengths of the device This behaviour is very useful for detection
application as it obeys a square law model The square law predicts that the current is
proportional to the square of the applied bias
119868 = 1198861198812 119908ℎ119890119899 119881 gt 0
119868 = 0 119908ℎ119890119899 119881 lt 0
(51)
To extract the first order effects of ASPAT diodes DC measurements which
result in asymmetric I-V characteristics are analysed The slope of the non-linear region
is used to determine the junction resistance (Rj) which is obtained from the first
derivative of voltage versus current (dVdI) The expression of Rj is given by
119877119895 =
120597119881
120597119868
(52)
In order to understand the relationship between Rj and diode sizes of the ASPAT the IV
characteristic for each diode displayed in Figure 51 is used to extract the Rj This has
been done by using the expression in equation (52) above and their response is plotted
against bias as displayed in Figure 52
151
Figure 52 Junction resistance versus voltage
As can be seen in the Figure 52 above the Rj for each device decreases strongly
when the voltage increases At zero bias the 4times4um2 devices show the highest Rj value
followed by 6times6um2 and 10times10um
2 devices The junction resistance at zero bias obtained
from the 4times4um2 diode is around 86KΩ while reducing by a third for the 6times6um
2 and
10times10um2 diodes with Rj of 27KΩ and 10KΩ respectively A diode with a smaller
forward current under the same applied voltage will exhibit a larger Rj For a good
millimetre wave detector a device with a large value of Rj is desirable since it will
provide high detection sensitivity
The slope at the IV characteristic contributes to an important parameter that is
commonly used by electronic manufacturers to describe diode specification namely the
video impedance (RV) which is also known as the non-linear resistance The RV which is
extracted from the real part of the diode small signal impedance is highly dependent on
the DC bias current and only weakly depends on the series resistance of the diode (RS)
Therefore the video impedance is given by
119877119881 = 119877119895 + 119877119878 (53)
Where RS is the series resistance of the diode whose value is normally very small and
does not contribute much to the whole slope and hence RV is dominated by Rj The RV
changes in behaviour if any DC current is flowing through the diode Practically small
DC current in the range of 1 to 10 microAmp or total zero bias is used to maintain the
appropriate RV value (1-2KΩ to several MΩ) RV will also determine the voltage
-10
10
30
50
70
90
110
130
150
-01 0 01 02 03
Rj(
KΩ
)
Voltage (V)
6x6um^2
10x10um^2
4x4um^2
152
sensitivity of the whole detector circuit This will be explained further in the next
chapter In the case of a detector with an amplifier RV of the diode acts as the RF
impedance which needs to be matched with the video amplifier ( impedance looking into
the diode from the amplifier)[108 109]
The quotient of the second order derivative to the first derivative
((d2IdV
2)dIdV)) when calculated from the whole I-V characteristic translates directly
into a curvature coefficient (k) This is the most commonly used figure-of-merit to
quantify diode nonlinearity at zero bias Figure 53 below shows the variation of k with
bias and more importantly the zero bias rectifying action for device sizes of 4times4 um2
6times6 um2 10times10 um
2 This parameter which represents the small-signal rectifying
action of the diode will affect the performance of the detector (voltage sensitivity)
Detailed discussions on how this parameter effect the detector performance will also be
discussed in the next chapter
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT high sensitivity
near zero bias detection
Figure 53 above shows calculated curvature coefficient of the measured I-V
characteristics from the same diodes shown in Figure 51 The highest k value is
obtained from the diodes with size of 4times4um2 followed by 6times6um
2 then 10times10um
2
The curvature coefficient decreases sharply as the bias increases for each diode This can
be attributed to a significantly increasing number of electrons that tunnel through the
thin barrier which were accumulated in the 2DEG formed in the intrinsic spacer region
-5
0
5
10
15
20
25
30
-001 004 009
Cu
rvat
ure
Co
effi
cien
t(V
-1)
Voltage (V)
k(10x10 um^2)
k(6x6 um^2)
k(4x4 um^2)
153
An ASPAT diode with a smaller size will have a larger Rj with a corresponding smaller
current under the same bias condition and hence will demonstrate a larger k value In
this calculation the curvature coefficient at zero bias obtained from 4times4um2 6times6um
2
and 10times10um2 diode is 23V
-1 17V
-1 and 16V
-1 respectively
A summary of the ASPAT diodes parameters obtained from measured I-V
characteristics that have been translated into first and second order differentials are
gathered in Table 51 below and compared to other diodes in the literature
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics in this work
Sample Rj(Ω) k(1volt)
ASPAT 10times10 microm2 10K 16
ASPAT 6times6 microm2 27K 17
ASPAT 4times4 microm2 86K 23
Ge Backward diode 182K[110] 159[110]
InGaAs Backward diode 154[110] 23[110]
Sb Backward diode 5K[111] 47[111]
Si-Backward diode 135K[112] 31[112]
PDB 15K[8] -
AlGaAs SBD 20-100K[113] 34-38[113]
GaN HBD - 16[114]
From Table 51 above it is clearly that the ASPAT diode has a comparable value of Rj
and k to existing detector diode in the research community and in the commercial
market Based on literature of each diodes stated in the table the key to obtaining a high
value of k at zero bias is to minimize any forward tunnelling current Furthermore the
largest ASPAT diode used here (10times10microm2) has very close performances to that of a
commercial diode ie discrete Ge backward diode (ref[110]) where both Rj and k value
are close to each other
53 RF Test Fixture Theory and Experiment
RF measurements differ from DC measurement as they are more complicated
and it is necessary to comprehend the basic measurement principles to achieve
meaningful data This is obligatory especially for on-wafer RF characterization and
154
analysis to attain precise results Most of the electronics component measurements
which have input and output for instance antenna amplifier cables etc are based on a
two-port network configuration The characteristics which can be extracted from these
components are usually used to define their impact on a more complicated system
The performance of the two-port network can be described by a few parameters
ie scattering (S-Parameter) admittance (Y-Parameter) Impedance (Z-parameter) and
Hybrid (H-Parameter) However the S-parameter approach is favoured for high-
frequency measurements as it is relatively easier to characterize the microwave
performance and is able to convert to other parameters when necessary The advantage
of S-parameters is that they can straightforwardlydirectly convert into other two-port
parameters as mentioned above in term of currents and voltages[115] In fact to obtain
the device capacitance the appropriate S-parameters needs to be transformed into Y-
parameters using specific equations Furthermore the devicersquos cut-off frequency can
also be obtained when S-parameter measurements are performed over a wide frequency
range
531 On-Wafer Measurement and Small Signal One-Port Characterizations
In this work the arrangement of the RF measurement setup is assumed to be a
linear system as small voltage amplitude signals are used this means that the signals
have only a linear effect on the network without any gain compression or attenuation
The assumption is still acceptable even though the typical ASPAT is characterised as
non-linear in nature because it is a passive device which will act linearly at any input
power level
Generally the S-Parameter measurements on a diode can be adequately and
suitably performed using a one port measurement The technique used to characterise the
output is similar to the two ports technique but only incident and reflected waves are
used to characterise the input and output ports of the device Essentially this is because
the ASPAT has only two terminals and it is a passive device like other diodes
Therefore the analysis will revolve around the S11 parameter Figure 54 below show the
S11 is a ratio of reflected wave to the incident wave
155
11987811 =
119877119890119891119897119890119888119905119890119889
119868119899119888119894119889119890119899119905=
1198871
1198861 119908ℎ119890119899 1198862 = 0
(54)
A VNA as described in Chapter 2 is used to measure the ASPAT diodes This
powerful equipment is able to measure S-parameters up to 40 GHz To conduct accurate
S-parameter measurement at the diode the measurement setup must be calibrated prior
to the actual measurements taking place
54 Device Calibration
541 Open and Short De-Embedding Technique
Further calibration to be made involves anything related or attached to the
device The co-planar waveguide (CPW) bond pad and interconnect line that are
attached to the intrinsic diode are the main contributors of the errors also are required to
be calibrated In general the bonds pad could generate a capacitance (parasitic) in
parallel with the intrinsic diode and its contribution depends on the size of the bonds pad
as well as the operating frequency Meanwhile the CPW and interconnect line may
cause a parasitic inductance in series with the diode
The method that is used to get rid of this parasitic is called de-embedding and the
most common technique to realise it is by introducing OPEN-SHORT structure[116]
This method is based on a lumped-elements model Parasitic elements of the diode
De-Embedding Structure
Incident wave
Reflected wave
One-port device
a1
b1
Figure 54 One port S-parameter measurements
156
equivalent circuit correlate directly to the access section of the CPW hence can be
derived from de-embedding structures The aim of the de-embedding technique is to
represent these parasitic elements so that the one-port characteristic of the actual diode
can be determined
The two types of de-embedding structure OPEN and SHORT are conventional
techniques that are widely used in this study The design of all structure must be
identical (in size) to the device to avoid any discrepancy It is very simple to design all
these three structures for example open structures are obtained by eliminating the diode
layout and keeping the bond pad layer only The short structure just adds a bridge and
ensures ground and signal pad are connected to each other Through structures are
realised by disconnecting both ground pad and leaving the signal pad to connect to each
other
To gain more accuracy this external effect must be removed by the implementation of
de-embedding structures on the same tile as the actual device Figure 55 shows the
fabricated de-embedding structures used in this study
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use for RF
calibration and measurements (Note Images are not to scale)
In summary the de-embedding which is used to extract out the parasitic elements
from entire single diode measurement is a very important step as normally on-wafer
measurement requires coplanar waveguide (CPW) to access the diode structure (active
region) The CPW will have some effects which will disturb the accuracy of the device
characteristics
157
55 S-Parameter Measurement Result and Analysis
This section will only present RF measurement results after all VNA setup and
calibration were performed The S-Parameter measurements were carried out on ASPAT
diodes at five different DC biases from -2 to 05 volt with a sweep frequency from
40MHz to 40GHz using a calibrated VNA and the input power was fixed at -30dBm
The measurement procedure as described in Chapter 2 was performed on the device
(on-wafer) equipped with the appropriate bond pads This is important to ensure the
results obtained are valid The reason for using different biases is to find at what voltage
the device capacitance is fully depleted This is also very important in determining the
cut- off frequency of the devices
In this research two phases of the experiment on the S-parameter measurements
were carried out The first phase is to qualify the process flow ie for manufacturability
and repeatability which can be obtained from the consistency of the result The S-
parameter measurements taken on the same wafer dies are repeated several times on
different GaAsAlAs ASPAT diodes There are three different tiles taken from 3
different wafers namely XMBE304A XMBE304B and XMBE304C carried out in
this experiment The repeatability tests are done mostly on the large devices (15times15microm2
up to 100times100 microm2) and the results are analysed based on the reflection coefficient (S11)
on Real and Imaginary measurements
In the second phase the measurement is toward producing devices that can
perform at high-frequencies This can be realised by utilising small emitter size devices
(4times4microm2 6times6 microm
2 and 10times10 microm
2) The measurement results of these devices will be
used to build the equivalent circuit models while both the intrinsic as well as the
parasitics of the device will be evaluated Hence all the values obtained from these S-
parameter measurements will be used to design the device that can be used in
millimetres-wave applications As can be seen in Figure 56 below the extracted S-
parameter measurement results comprise of a reflection coefficient (S11) for real
imaginary and Smith chart for XMBE304A While these measurement results are
extracted at zero bias voltage the other bias voltages will be used to extract the
capacitance This will be described in the final section of this chapter
158
551 Diode to diode uniformity
In order to study within tile uniformity and reproducibility statistics of the RF
performance five devices of different mesa sizes in the same tile (XMBE304A) were
measured at zero bias and represented in term of Real and Imaginary reflection
coefficient (S11) the uniformity check is carried out at three different frequencies step
under 15GHz since the cut-off frequency for these big devices is relatively low at about
~20GHz on average The variation of the reflection coefficient is taken from the
percentage of the (standard deviationmean values) for all five diodes from this run The
following figures show Real and Imaginary S11 of large mesa area ASPAT diode from
15times15microm2 up to 100times100microm
2 which are represented by lines graph in a few different
colours
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices from
15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero bias
159
The variance data extracted from the graph (Real S11) above for each device within-
wafer (device to device) uniformity study is summarize in Table 52 below
Table 52 Device to device uniformity check for large ASPAT diode
Device Size 100times100 microm2 50times50 microm
2 30times30 microm
2 20times20 microm
2 15times15 microm
2
Variation 5GHz 181 115 405 151 145
Variation 10GHz 106 133 522 424 293
Variation 15GHz 119 198 281 76 509
The majority of diodes show that the variations of S11 measurements are below
3 and only a few are below 8 These finding still can be considered as good for
manufacturing control since absolute I-V characteristics reported in [63] is set by
designerrsquos specification to be not more than plusmn10 variation Further extensive RF
measurements were carried out by the research collaboration with the University of
Cambridge on the same GaAsAlAs ASPAT diodes wafer [117] In their study they
focused on 50times50 microm2
mesa size 17 of diodes were chosen to be measured The study of
uniformity of RF characteristic only focused on frequencies below 20GHz The same
approach was used to get the variation of the reflection coefficient for all 17 diodes but
this work was carried at four different frequencies Table 53 shows the zero bias S11
result for four different frequencies and standard deviation of the devices
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at four different
frequencies[117]
Frequency (GHz) 5 10 15 20
Variation () 197 243 26 276
From the results the variations of 50times50 microm2 mesa sizes measured in-house and
at the University of Cambridge are comparable with all variations showing good
uniformity ie recording variations below 3 This indicates that the RF performance
of the GaAs AlAs diode is valid and reproducible and is thus considered as a good
achievement for manufacturing Once the reproducibility and repeatability of the large
devices showed stable results the fabrication process then continued to obtain smaller
emitter size for work at high-frequencies
160
552 Wafer to wafer uniformity
Other RF measurements were conducted on sample XMBE304B which was
fabricated in-house using the same process steps but the only difference from
XMBE304A was the use of SiN3 as dielectric In this run three different mesa sizes
were measured (15times15mmicro2 20times20microm
2 and 30times30 microm
2) and Real and Imaginary S11
plotted against frequency The RF performances of both samples are gathered in one
graph as shown in Figure 58 below
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B) to qualify
the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2 device sizes (Real and
Imaginary) Note blue colour is XMBE304A and red colour is XMBE304B
For this wafer to wafer uniformity study four diodes with three different sizes as
specified previously were measured from sample XMBE304B and four diodes from
previous measurements of XMBE304A The blue line in Figure 58 represent
measurement result of real and imaginary for sample XMBE304A while the red line
161
represents XMBE304B The uniformity data is compared at three different frequencies
and gathered in the table below
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B
Device Size 30times30 microm2 20times20 microm
2 15times15 microm
2
Wafer A vs wafer B variation 5GHz 305 31 1 314
Wafer A vs wafer B Variation 10GHz 352 344 329
Wafer A vs wafer B Variation 15GHz 321 376 359
As can be seen in the Table 54 above the wafer to wafer uniformity is rather
large (30) on average The main reasons being that sample XMBE304A was
processed by utilizing S1805 as a dielectric layer while sample XMBE304B used
Si4N3 Although the process steps are similar for both wafer processing the use of
different dielectric layer will influence the diode parameters especially resistance and
capacitance as the dielectric constant for each materials is different Secondly the wafer
processing is not run concurrently at the same time thus the moisture and temperature in
the clean room might differ for both processing Although the wafer to wafer uniformity
test for this run might not be favourable for manufacturing tolerance at least the use of
different dielectric layer shows some significant result in term of capacitance resistance
effect to the GaAsAlAs ASPAT diode
553 Small devices RF measurements
The first objective of this study was to make smaller size mesa devices ie
1times2microm2 1times3 microm
2 2times2 microm
2 and 3times3 microm
2 However for GaAsAlAs ASPAT type this is
difficult to achieve in practise These issues were discussed in detail in Chapter 3
Hence the smallest emitter size that yields repeatable and reproducible results was
4times4um2 The final measurement which was done on sample XMBE304C focused on
small devices The measurements were done on four devices two with the diode bond
pads sitting on substrate (GaAs SI) and the other two sitting on dielectric layer (Si4N3)
Figure 59 below shows three measured results obtained from sample XMBE304C
using the 3rd
Gen Mask
162
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and 4times4microm
2 (Real and
Imaginary) Note that green red and blue colour represents 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and 4times4 microm2
(Smith Chart) Note that green red and blue colour represents 4times4microm2 6times6mmicro2 and 10times10microm2
diodes respectively
30MHz
40GHz
163
As can be seen in Figure 59 (Real Imaginary) and Figure 510 (Smith Chart) are
obtained from measurement of four diodes in the same tile The diode to diode
uniformity that is sitting on the same platform obtained at 35GHz frequency in this run
on average is ~15 25 and 1 for 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively On the other hand the uniformity between diode to diode sitting on
dielectric and substrate is quite high due to different capacitance value of devices on
average ~7 are attained from three different sizes of diode
From the measurement results above the Real S11 measurement of four different
sizes show the same trend for each frequency At low frequency resistances for each
diode is high as the S11 value is large At intermediate frequency the values drop
tremendously for big devices (30times30 mmicro2 and 20times20 mmicro
2) ie in Figure 57 At high
frequency all diode reach saturation limit as the value are constant Small devices
(4times4mmicro2 6times6mmicro
2 and 10times10microm
2) ie Figure 59 show S11 values that are higher than
those of large devices as smaller emitter diode have larger resistance value
The imaginary S11 value also shows the same trend as for big devices However
for small devices in this run (4times4mmicro2 6times6mmicro
2 and 10times10microm
2) the S11 value keep
dropping toward negative values at increasing frequencies This indicates that bigger
devices with positive value at high frequency are more capacitive than the smaller
devices It is worth mentioned that the capacitance and inductance values for device
sizes of 4times4microm2and 6times6microm
2 come from the CPW layouts and these are dominant while
for device sizes of 15times15 mmicro2 and above the device capacitance itself is dominant
The Smith Chart shows the reflection coefficient (S11) as a function of the
applied frequency (30MHz to 40GHz) All measurements from each mesa size follow
unique impedance circle which is that most of the lines are at the lower right outer ring
This means that the diode capacitance value is frequency dependent For the case of
10times10microm2
devices these impedance circles are mostly toward the outer ring meaning a
higher capacitance than the other two mesa dimensions All the device constantly follow
the outer ring without crossing any real axis at any frequency point meaning that the Cj
is not shorted at the maximum 40GHz measurement frequency (not reached cut-off
frequency) Therefore the entire small GaAsAlAs diodes in this run have capability to
work in the millimetre wave frequencies range
164
56 Extracting RF models of ASPAT at Zero Bias Voltage
The methodology used in the S-Parameters measurement for high-frequency
analysis must ensure that the derivation of the equivalent circuit corresponds to their port
characteristics In other words the component representing the ASPAT in the equivalent
circuit model must have physical significance otherwise the circuit will be meaningless
The fabricated ASPAT diodes as discussed in Chapter 3 have the cross section shown in
Figure 511
There are two main components that can be extracted from the fabricated
ASPAT depicted above ie intrinsic and parasitic The intrinsic refers to the main
structure of the diode itself and are represented by three bias dependent elements
namely Junction Resistance (Rj) Junction Capacitance (Cj) and diode Series Resistance
(Rs) The parasitic is the elements related to the bond pad of the anode and cathode as
well as interconnects They are represented by parasitic inductance (LP) resistance (RP)
and capacitance (CP)
The diode parameter extraction is different from the three terminal devices
(FETs) in the sense that FETs are a kind of direct extraction in which all the elements in
the transistor have linear functions to the port characteristics ie S-parameter Y-
Parameter Z-Parameter and can easily be solved by the matrix calculation method for
those particular parameters[118] The same extraction method cannot be applied to the
diodes because its elements will embroil with each other Therefore only one method is
used to extract the diode element which is optimisation by tuning the initial value toward
the measured S-Parameter values
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding equivalent circuit
model
165
The strategy used to model the ASPAT is based on an initial fitting value of the
lumped elements to the extracted value from measurement on three S-parameter graphs
(real imaginary and Smith chart) for the reflection coefficient (S11) The refinement is
accomplished by optimisation and fine tuning of the values which result in minimum
error between extracted and modelled values Figure 517 (on page 153) shows fitted S-
parameter result for extracted and model numbers with each one fitted in a single line as
an example However to achieve this excellent fitting key prior steps have to be used
de-embedding fitting the intrinsic value and optimisation
561 Extraction of ASPAT parasitic element
Once the S-parameter measurements achieve stability repeatability and
reproducibility for each measurement in term of S11 results as mentioned above the
results of the de-embedding structure which had been measured prior to the device
structure are then extracted to form a well-defined equivalent circuit In order to build
and analyse the equivalent circuit firstly the measured data is imported into the ADS
software prior to any fitting This can be realised via the ldquoStart The Data File Toolrdquo
features provided by this particular software When successfully imported the data is
read by the function S2PMDIF (These files are a natural extension of two-port S-
parameter Touchstone files) as depicted in Figure 512 below
Figure 512 The S-parameter Touchstone file is used to read the measured files
166
For the open and short techniques after de-embedding the equivalent circuit
model which is represented by mainly a capacitor and an inductor is built The open
structure requires resistance and the capacitance values of 20KΩ and 26fF respectively
connected in parallel to be well fitted to the real imaginary and Smith chart (S11) output
On the other hand for the short structure the Real imaginary and Smith chart (S11) have
to satisfy the values of resistance and inductance elements of 1Ω and ~47pH respectively
connected in series These values strongly rely on the bond pad or CPW dimension and
length The Equivalent circuit models and fitted data as well as measurement can be
seen in Figure 513 and Figure 514 below
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure
Figure 514 Equivalent circuit model for short de-embedded structure
To satisfy the equivalent circuit a self-consistence method introduced by
Ren[119] is utilised This approach accurately extracts the CPW capacitance (Cpad) and
inductance (Lpad) as well as intrinsic Junction capacitor (Cj) which is attained from the
one-port S-parameter measurements Therefore the pad capacitance introduced by the
self-consistence method for the open structure can be expressed by
167
119862119875 =
119868119898(11988411119874119901119890119899)
120596
(55)
Lpad which represents the short structure is given by
119871119875 =
1
120596(119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
))
(56)
Here Y is the admittance parameter (Y-parameter) converted from the S-parameter
measurement data and ω is the angular frequency The extracted measurement data
represented in the equivalent circuit fits with the simulated data in three S11 graphs as
can be seen in Figure 515 below From the Smith Chart it can be clearly seen that both
open and short S11 results are on the circumference which means the resistance of the
short structure is very small while in the open it is very large Additionally the
calculated Cpad and Lpad using Equations 55 and 56 above produce results similar to
those obtained in the equivalent circuit model for the open and short structure The
values are ~25fF and ~45pH respectively These data completely verify and validate
both results
Figure 515 Smith chart representative S-parameter measurement for short (left) and open (right)
CPW The blue lines represent simulated data and the red is measured data
Short
Open
168
562 Extraction of ASPAT intrinsic elements
Once the parasitic elements are determined it is easy to build a complete ASPAT
equivalent circuit The ASPAT is not like other tunnelling diode which their equivalent
circuit models widely studied ie RTD [120] IMPATT and PDB The only literature
which reports ASPAT equivalent circuits can be found in [15] and other RT Symersquos
journal paper[16] Fortunately its equivalent circuit model is not much different
compared to other diode video detectors Thus other literature which is based on
Schottky diode equivalent circuit model used for detector application can be referred to
The simplest form of ASPAT equivalent circuit and other video detectors intrinsically
consist of junction capacitance (Cj) series resistance (RS) and junction resistance (Rj)
First and foremost to extract the equivalent circuit one must know the theory behind
each parameter that is developedbuilt as a spine to become a complete element This is
vital to ensure the equivalent circuit is correct In the case of the ASPAT Cj is predicted
from a simple fully depleted parallel plate capacitor approximation which was discussed
previously in Eq (230)[15] Additionally for the S-parameter measurements the Cj can
also be validated by the self-consistence method mentioned earlier and thus can be
expressed by
119862119895 =
[
(1
120596)
1
1
119868119898 (11988411119905119900119905119886119897minus 11988411119874119901119890119899
)+
1
119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
)]
(57)
This approach helps to verify both the fully depleted parallel plate capacitor in S-
parameter measurements The basic component which is responsible for the ASPAT
series resistance RS was discussed in detail in Chapter 2 RS and Cj are key contributors
to the high-frequency operation as expressed by the device cut-off frequency Equation
(58) below
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(58)
The R and C parameters must be kept as low as possible in order to obtain high cut-off
frequencies for millimetre wave applications From the fabrication point of view Cj can
169
be reduced by making as small a diode emitter size as possible while for RS reducing
the D gap is of paramount importance as it dominates the series resistance The ASPAT
contact resistance in the electrodes (contacts between metal and semiconductor) can be
reduced by using high doping in the ohmic layers
The junction resistance (Rj) of the ASPAT is taken from the 1st derivative or
slope of the current-voltage characteristics Normally the value of Rj is very large
(several kilo Ω) compared to Rs The small signals ASPAT equivalent circuit built with
intrinsic and extrinsic components is shown in Figure 516 below while the fitting
results is shown in Figure 517 and Figure 518
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
(Real and Imaginary) results for various small device designs
Rj
Cj
Cpad Rpad
Rs Lpad
Figure 516 Equivalent circuit of the ASPAT diode
170
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
results (Smith Chart) for various small device designs
The equivalent circuit that was built for the ASPAT is taken from sample
XMBE304C with emitter dimensions of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 These
devices are expected to work in the millimetre-wave region and have cut-off frequencies
(intrinsic) of ~650GHz ~200GHz and ~100GHz respectively
Table 55 Comparison between calculated (fully Depleted) and extracted (different biases) values
from equivalent circuit parameters for different ASPAT mesa sizes at zero bias voltage
Parameters 4times4microm2 6times6 microm
2 10times10 microm
2
Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted
0V -05V -1V 0V -05V -1V 0V -05V -1V
Cj(fF) 879 23 7 6 198 55 148 139 549 171 486 46
Cpad(fF) - 15 15 15 - 15 152 152 - 15 15 15
Lpad(pH) - 45 43 42 - 50 473 473 - 51 51 46
Rj(KΩ) - 90 833 522 - 35 392 392 - 12 125 13
Rs(Ω) 99 11 11 11 67 95 8 7 41 95 45 37
fcut-off
Cj(GHz)
1828 629 2066 241
1
1208 192 1344 163
5
710 107 728 935
fcut-off
Cj+Cp(GHz)
- 380 658 688 - 151 663 781 - 98 556 705
171
The focus in this study is purposely to build ASPATs as zero bias detectors that are able
to work in the millimetre and sub-millimetre frequency range therefore all the
parameters which are obtained from equivalent circuit were extracted at zero bias
voltage Theoretically the calculations which are derived from both self-consistence amp
theory can only be solved for fully depleted device capacitance (using a parallel plate
configuration) Hence both extracted and calculated results are compiled in Table 55
Noticeably the calculation can only produce the intrinsic parameters of the
ASPAT for fully depleted capacitance On the other hand both intrinsic and extrinsic
parameters of GaAsAlAs ASPAT are obtainable from extraction and thus help to
determine at what bias the diode is start to deplete The junction and series resistance (Rj
and RS) of each dimensions shown in Table 55 above were achieved by fitting the
elements of the equivalent circuit with the three measured S11 graphs whereas the Cpad
and Lpad were extracted by utilising the self-consistent method from the S-parameter
measurements which is fitting the de-embedding structure Additionally the Cj values
are obtained via fitting the measured S11 data and employing the self-consistence
approach Results obtained from both techniques are identical
At zero bias all extracted junction capacitance from each device sizes are very
different from the calculated one while the extracted series resistance are closer to the
calculation This means that Cj is a highly voltage dependent parameter and Rs is
voltage independent but solely dependent on device structure and material used to
fabricate it The extraction at -05V and -1V shows that the values of junction resistance
is changing for most of the devices which means this parameter also rely on bias voltage
as discussed earlier in Section 52
The cut-off frequency for each calculated devices are near the THz range even
for the 100microm2 emitter area However with the introduction of parasitics elements ie
pad capacitances fcut-off is degraded tremendously Therefore it is important to make sure
all the intrinsic elements have optimum values so that the target operating frequency of
the ASPAT diode can be met Due to this it is advisable to operate the devices at no
more than 13 of fcut-off when designing detector systems
The parameters extraction at -05 and -1V also show that Cj values are closer the
calculated ones which means the ASPAT diode is reaching full depletion
172
563 Capacitances -Voltage (C-V) Extraction
Theoretically the junction capacitance of the ASPAT is calculated from the fully
depleted formula 119862119895 = 휀119900휀119903119860119889 which was also discussed in Equation (230) in Chapter
2 in page 43 Its value depends on the change of voltages to depletion at the emitter
contact[15] and make it one of the voltage dependent parameter for the diode[121]
Therefore the C-V characteristic of the GaAsAlAs must be precisely extracted
In practice the capacitance is difficult to measure due to the very low resistance at zero-
bias However alternatively it can be measured and extracted by applying different
voltage and identifying the point at which there is change which essentially represents
full-depletion Apart from these it can also be extracted from S-parameters measurement
which is then converted to Y-parameters A C-V characteristic of the GaAsAlAs
ASPAT from XMBE304C is extracted and plotted as depicted in Figure 518 below
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled capacitance vs
Voltage)
From the graph shown in Figure 518 the capacitance is extracted at eight
different biases for 4times4 microm2 6times6 microm
2 and 10times10 microm
2 The devicersquos junction
capacitance for each dimension increases and reaches a maximum value at 025V There
are additional quantum capacitance effect which comes from an increase in the negative
charges in the 2DEG region (when band bending happens creating an accumulation
0
50
100
150
200
250
-2 -15 -1 -05 0 05
Cap
acit
ance
(fF
)
Voltage (V)
Cj(4x4microm^2)
Cj(6x6microm^2)
Cj(10x10microm^2)
173
region at the barrier) This charge is imaged by the positive charge in the whole
depletion region Increasing the voltage toward positive values leads to a lowering of
the AlAs barrier and thus allowing thermionic emission to take place after certain bias
values leaving only the depletion capacitance and making the quantum capacitance
negligibly small
In the reverse bias case the device junction capacitance reaches a saturation
(fully depleted capacitance) at a voltage of -025V and remain constant up to -2V If the
reverse bias voltage is increased further the ASPAT may reach breakdown Therefore it
is important to know how far the diode can withstand applied reverse bias to ensure it
can still give full performance
57 Conclusions
In this chapter scalable DC characteristics of GaAsAlAs ASPAT diode derived
from three different emitter sizes of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 was
demonstrated The current density obtained at zero bias is several microAmicrom2 These allow
1st order differential effect to exhibit high value of Junction resistance (Rj) at zero bias
However Rj is highly bias dependent The 2nd
order differential effect on IV
characteristics display a high value of curvature coefficient leading to high voltage
sensitivity when applied in millimeter wave detector applications These two parameters
are vital in the design of millimeter wave detectors and especially those operating at zero
bias
Subsequently RF measurement up to 40GHz of uniformity study for both within
wafer and wafer to wafer variance were undertaken An average uniformity below 7
was obtained for within wafer study on large device area ( 15times15 microm2 to 100times100 microm
2)
while for small device area ( 4times4 microm2 to 10times10 microm
2) a smaller 3 uniformity variance
was achieved in average However for wafer to wafer study the variant uniformity was
quite high at around 30 on average for relatively large device (15x15 microm2 to 30x30
microm2) This was mainly attributed to different dielectric layers used in the process flows
of the sample rather than fundamental MBE control of the AlAs barrier thickness
174
It was demonstrated in this chapter that careful on-wafer RF measurements of small
size GaAsAlAs ASPAT diodes allow accurate device parameter extraction of both
extrinsic and intrinsic parameters The extrinsic parameters are namely pad capacitance
and inductance with obtained values of 26fF and 47pH respectively These values were
obtained from de-embedding structure fabricated on the same tile as the real devices
The intrinsic parameters such as junction capacitor junction resistor and series
resistance had different values according to device dimensions The smallest zero bias
value of Cj obtained from 4times4 microm2 diodes was 23fF ensuring a high cut-off frequency of
380GHz and hence in the next chapter a 100GHz detector will be presented working at
slightly less than 13 of this cut off frequency
The C-V data extraction confirmed that the fully depleted capacitance started to
happen at around -025V The maximum junction resistance occurs at +025V largely
caused by the depletion region and an additional quantum capacitance effect CQ This
effect is strongly related to the size of a 2DEG which occurs under forward bias (01V to
025V) and can be reduced by having a smaller thickness AlAs barrier
175
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR
DESIGN USING ADS
61 Introduction
The ASPAT diode having features of non-linear IV characteristics at zero voltage
make it useful for signals rectification ie detector and mixer for millimetre-wave
applications Additionally ASPAT diodes have a range of advantages such as large
dynamic range strong temperature insensitivity etc[15]over other rectifier diode This
makes ASPAT an appropriate candidate in RF detection applications Since 1940 the
only two terminals device that has been the workhorse for RF applications is the
Schottky Barrier Diode (SBD)[9] In its earliest form the SBD was built based on a
point-contact device which could not perform at high frequencies It was then developed
to work at higher frequencies by exploitation of epitaxial structures [10] and to date the
SBD remains the mainstay of two terminal devices that are able to work in the
millimetre and submillimetre-wave regions However as discussed in Chapter 4 the
performance of SBD is degraded at extremes of temperatures and these circuits
employing SBDs require temperature compensating circuitry Thus there is additional
complexity associated with technologies and applications related to SBDs
Before this work was carried out no model for the ASPAT diode as detector had
been available or developed especially using the empirical modelling ADS software
When the ASPAT diode was first introduced its function was conceptually explained it
was then built and tested to compare with other microwave detectors at X-band
frequency (95GHz) The comparisons were made in terms of detector parameters ie
sensitivity dynamic range temperature dependence etc[15] These early works lead by
RT Syme et al supplied the basic knowledge to model the ASPAT diode as a zero-bias
detector for mm-wave frequency gt100GHz For the SBD many models and equivalent
circuit approaches have been reported [122 123] The modelling of conventional SBD is
mostly implemented through fitting the S-parameter curves of the model to the
experimental one This approach is also carried out in this research since it is accurate to
predict the performance of the device under test [124]
176
This Chapter aims to introduce low cost reliable and sophisticated detector design
based on ASPAT diodes which is believed to be able to improvereplace SBD in
millimetre-wave applications especially in imaging The focus was on developing and
establishing an appropriate circuit design that suit the new ASPAT diode for such
applications The detector sensitivity as its key parameter ultimately limits the quality
and acquisition time of the detector In the subsequence section the theory of detection
including both direct and heterodyne will be discussed This is followed by definition of
detector characteristics of interest as well as noise consideration Section 65 present the
main focus of this chapter which is the development of 100GHz ASPAT detectors and
their result will be explained in term of all detector characteristic of interest
62 Detection Theory
Any incoming signal such as RF microwave or mm-wave in the form of envelope
function or single wave can be detected by rectification of the signal using a nonlinear
device ie transistor or diode The input and output signal (RF) signals are normally in
the form of amplitude as a function of time Typically the detector output is a low-
frequency signal known as the video signal which has amplitudes that are proportional to
the square of the input RF signalrsquos voltage amplitude
A complete receiver system as shown in Figure 61 below consists of receiver
antenna and a circuit designed to extract the signal and then amplify it The function of
the receiver system is the converse of the function of the transmitter side At the receiver
side the antenna is used to receive the signal it then conveys the signal to the extraction
circuit for detection as the information-bearing part of the signal (using the nonlinear
device as its heart) The signal is finally amplified to avoid any information strength
decay Additionally in a digital system the output signal which had been processed by
the detector circuit has to maintain an optimum input signal conveyed to in-phase and
quadrature (IQ) demodulators The output signal will go through a low pass filter then
to an analogue-to-digital converter (ADC) and thus a digital baseband output signals
will be produced
177
Figure 61 Block diagram represent a complete direct receiver system
There are two types of millimetre wave integrated circuit (MMIC) used for
detection purposes namely direct detectors and heterodyne detectors The direct detector
MMIC is the simplest circuit used for detector applications and has the simplest way of
extracting the RF information Due to its simplicity the direct detection method is
inexpensive and most attractive method used for measuring power in RF Laboratories
and Industries This detection scheme is also sometimes known as video detection[125]
The simplest way of explaining the detection process is that the incoming RF or
microwave signals depicted in Figure 62 below with an appropriate input power (Pin) is
rectified by using a diode and results in a corresponding output voltage (Vout) A detector
IC designed based on diodes is normally able to rectify very low levels of RF power (lt-
40dBm) then produces an output DC voltage that is proportional to the RF power A
rectifier diode can function at zero bias (which is very good for reducing noise) at very
small DC bias (003mA) and relatively high RF impedance which will produce around
600Ω This will affect the capacitance value and a low capacitance is needed to realise a
high detection sensitivity
Figure 62 The detection process of a single wave through a non-linear IV characteristic of a diode
Detector
Speakerdisplay unit Amplifier
Antenna
Vout
Pin
Tuner Amplifier
178
However this type of detector has a drawback which is itrsquos relatively low signal to
noise ratio Thus it will also rectify any incoming electrical noise at all frequencies and
up to the cut-off frequency (fC) The basics lumped components circuit as shown in
Figure 63 is used to build such detector which consists of Source impedance (Zo)
Rectifier diode (ASPAT or Schottky) wire or pad inductance and capacitance and Load
impedance (RL)
Figure 63 Lumped element illustration of microwave detector circuit
Another type of detector is the heterodyne method which mixes incoming RF or
microwave signal (fRF) with another constant signal produced by a secondary circuit
called the Local Oscillator (LO) The LO frequency (fLO) must be slightly higher than fRF
to enhance the RF signal This mixing between fRF and fLO happens in the nonlinear
device as depicted in the Figure 64 This will produce a signal at a different frequency
called the intermediate frequency (fIF) which can then be amplified and detected as
explained in the previous paragraph Theoretically a basic requirement of the mixer is to
have fIF as efficient as possible while practically the minimum conversion efficiency
obtained is around 20 The main reason for using a mixer is due to the fact that
selective amplifiers at RF frequencies are costly and hard to achieve Hence a mixer is a
good technique as it only convert the signal to a lower frequency in which good
selectivity and high gain can be more effortlessly realised[14] A good mixer diode is the
one that can produce a high cut-off frequency and reduce conversion losses (Lc) A
mixer and detector diode with a low driven input power result in reducing overall noise
figure and thus in the ideal case the fIF amplifier also should have a low noise figure for
better performance The advantage of the heterodyne method is that it has a higher
179
sensitivity compared to the direct detection method this is achieved by producing an fIF
which has a lower frequency than the incoming RF signal[14] Obviously a zero-bias
voltage diode is more favourable to be used in mixer and detector applications
Figure 64 The mixing process where the signals are processed by the non-linear I-V characteristic
to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and fRF are applied to the
diode
To have good detection efficiency for both types of detectors the operating
frequency (fO) must be several times smaller than fC In the case of an incoming
maximum modulated signal fM the frequency that can be acquired is in the range of fO
plusmnfM and will normally come with noise The standard method that is used to reduce the
noise is using a filter of bandwidth about 2fM at the centre of fO with the condition that fO
must be smaller than fM (f0lefM) Otherwise it would be difficult to attain However in
most cases fM is smaller than fO and fO is smaller than fC thus this will make the video
impedance (RV) (or nonlinear impedance) very close to the differential resistance of the
diode (at fO) in the equivalent circuit[74]
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis
Theoretically a transfer function measurement is preferable prior to any empirical
modelling since no assumption can be made due to the detector non-linearity
Furthermore measuring voltage output at high frequency can be very low while
measuring the power incident on the detector is hard to achieve where the linearity of
180
the typical power meter is normally less than 3 over its operating range[126]
Therefore the modelling of detector output voltage vs input power (ie transfer
function) can help to determine both nonlinearity correction and appropriate operating
range for the detector itself
The performance of the diode that is often taken into account is the transfer function
(output voltage Vout versus incident power Pin) and the main parameters that is used to
characterise and determine the quality of any detector diode are the voltage sensitivity
(βV) tangential sensitivity (TSS) dynamic range (P1dB) ie under 1 dB roll off power and
variation of output voltage when examined in extreme temperature situation (ΔV(T))
The voltage sensitivity in small signal analysis can use the approach introduced by
Torrey and Whitmer [9] then βV can be expressed as
120573119881(119894119889119890119886119897) =
119877119895119877119871120581
2(119877119881 + 119877119871) (1 +119877119904
119877119895)
2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(61)
Where ω is the angular frequency (2πf) Cj is the junction capacitance of the diode
active region RL is the load resistance RV is the video impedance taken from the
expression of Rj + Rs and κ is the curvature efficiency that give small signal rectifying
action of the ASPAT diode which is given by the second order term and itrsquos expression
is
κ =
11988921198681198891198812frasl
119889119868119889119881frasl
(62)
The curvature coefficient or responsivity (κ) is translated directly from the non-linearity
of the IV characteristics of the ASPAT diode for detector application Both RV and κ are
the parameters that can be extracted directly from diode DC measurement as discussed
in Chapter 5
The voltage sensitivity is actually a quantitative relationship between input
power and detector response Meaning that it is a change in signal output over change in
input power Normally output power is measured in Volts and input signal is measured
in Watts Therefore the unit of responsivity is VW[127 128]
181
TSS is referred to the lowest or minimum signal that the detector could detect it is
determined by the diodersquos βV and total noise available in the system (from the diode and
any amplifiers in the detector circuit) For any diode with fO=10 GHz and low noise of
1MHz bandwidth amplifier the TSS is typically less than -55 dBm[74] The TSS equation
is given by
119879119878119878 =
radic[4119884119870119861119879119861(119865119886 + 119905 minus 1)]
119872
(63)
Where M is a figure of merits and is derived based on the expression M= 120573119881 radic119877119881frasl t
denotes the diode noise temperature Fa is the noise figure B T and Y are the amplifierrsquos
bandwidth temperature and power for signal-to-noise ratio respectively For a low-level
video detector ie lt10GHz the sensitivity mainly depends upon three factors firstly on
RF matching structure secondly on the rectification efficiency output impedance and
noise properties of the diode and finally the input impedance bandwidth and noise
properties of the video amplifier at the detector output The RF matching structure
controls the quantity of overall energy at the active junction for rectification The second
factor controls the reaction of the diode to incident microwave radiation and the last
factor will influence the detector sensitivity in general[109]
In practical the Tss is a direct measure of the signal-to-noise ratio of a detector and
is achieved by varying the amplitude of the input pulse (RF signal) until a point in which
the top of the noise level with no signal applied is at the same level of noise at the
bottom level of RF signal It is commonly measured on an oscilloscope as depicted in
Figure 65 below It is defined as the input power at which a signal to noise ratio of 251
is produced[109]
Figure 65 Measurement of Tangential Sensitivity[108 129]
182
The transfer function in many detector diodes is often divided into three sections
Firstly at low incident power secondly at higher input power and finally at very high
power static (continuous) In the first region the detector diode performs as a square-law
detector in which Vout is proportional to Pin This region normally is used to extract the
dynamic range of the diode detector In the second region Vout is approximately
proportional to Vin and this region is known as the linear regime Finally at higher Pin
still the transfer function or response rolls off and thus Vout ultimately become saturated
This roll-off point where Vout has dropped by 1dB below an extrapolation of the
dependence at low Pin is termed the ldquo1dB roll-off pointrdquo and this value is usually in the
range of -11 to 12 dBm[15] Therefore a dynamic range of the detector diode can be
obtained by taking the interval between TSS and 1dB roll-off point (in dBm)
Finally the temperature dependence of Vout for a detector is normally taken from
two extreme points of the temperature (-40C˚ to +80C˚) and thus can be determined
from
Δ119881(119879) = 10 11989711990011989210 |
119881(1198791)
119881(1198792)|
(64)
This Vout variation between -40C˚ and +80C˚ normally expressed in dB
64 Noise Consideration in a Detector diode
The existence of noise in a system limits the accuracy of device performance and
the precision of measurements In a detector system specifically using a diode the noise
which can reduce the sensitivity of signal encryption is called the Noise Equivalent
Power (NEP) By definition the NEP is a noise power density over the detection
sensitivity and it can be exploited to determine the overall noise performance of a
detector[130 131] In other words NEP is defined as the power from the input source
(Pin) that is required to supply a voltage output (Vout) equal to the root means square
noise at Vout [132] For an ideal lossless match and assuming only Johnson-Nyquist is
present the NEP of a zero-bias detector can be expressed as
119873119864119875119900119901119905 = radic4119896119879119861119877119881120573119900119901119905 (65)
183
Where βopt is responsivity with an optimum match which is given by1 2frasl 119877119895120581 This type
of noise appears when changing voltages across a diode and a noise voltage (Vn)
normally will arise Theoretically the NEP has units of Watts (as it is actually a power)
but it often normalized to 1Hz as it is independent of bandwidth and thus the unit
becomes WHz12
Additionally there are also several noise sources that contribute to Vn in a
semiconductor diode which are Johnson-Nyquist noise Flicker Noise and shot noise
Johnson-Nyquist noise [133 134] appears across any conductor or semiconductor at
thermal equilibrium this is due to the thermal agitation of the carriers or charges It can
be expressed in root mean square voltage as below
119881119869minus119873 = radic4119896119879119861119877119895
(66)
Where Rj is the differential intrinsic resistance B denotes the post-detection bandwidth
T is the device temperature and k is the Boltzmann constant[134]
The second noise that is taken into consideration when dealing with semiconductor
devices is Flicker noise more commonly known as 1f noise It is a group of known and
unknown noise sources that can be observed in the frequency spectrum and normally
display an opposite to the frequency power density curve[135] It comes from a variety
of different causes ie recombination effects at a defect in semiconductor mobility
fluctuation and flow of direct current as well as interface phenomena [136-138] In term
of voltage source Flicker noise can be expressed as[139]
1198811119891 = 119870119891119881119909119891119910 (67)
Where Kf denotes a device-specific constant V is the voltage and f is the frequency The
value of x and y typically used are 2 and -1 respectively This type of noise (1f noise)
will be neglected at frequencies high enough due to the fact that the NEP of the diode is
proportional to the thermal noise and resistance of the diode
Finally the noise that causes time-dependent fluctuation in a flow of electrical
current because of the carrier or electron charge crossing a potential barrier is called shot
noise Shot noise is due to the randomness in the diffusion and recombination of both
majority and minority carriers[140] The equation of shot noise term at random time is
given by[141]
184
119881119878ℎ119900119905 = 2119902119868119861 (68)
Where q is the electron charge I is the current and B is the bandwidth This type of noise
is not affected by changes in temperature or device parameters Therefore the total noise
voltage appearing in the semiconductor is found to be [141]
1198811198992 = 119881119869minus119873
2 + 11988111198912 + 119881119904ℎ119900119905
2 (69)
However a zero-bias device will greatly eliminate both shot and flicker noise
compared to a biased device This has been explained by Equation (66) and Equation
(67) above where both noises are significantly related to the current and voltage Thus
if V and I =0 in the nonappearance of incident power then Vn will also become zero For
a detection process with bias the diode will be self-biased by ΔV which causes both
flicker and shot noise to appear But the shot noise in practical situation is much smaller
and thus normally ignored [142-144] Usually the noise in a zero-bias detector is
estimated by considering the low power limit as good first order estimation in which the
presence of only Johnson-Nyquist noise and ΔV is arbitrarily low [11 145 146]
Additionally it has been reported that the noise in tunnelling type diodes displays very
low or no excess noise in the bias region of the current-voltage characteristic[147 148]
Therefore in general most of the noise specifically in tunnelling type of diode will be
neglected this is a great advantage compared to SBD or transistors
65 Modelling of a 100GHz Zero-biased ASPAT Detector
Once the DC and RF characteristics of the ASPAT diode had been accurately
obtained the next step is to model and design a detector circuit based on S-parameter
measurement results as was explained in the previous chapter The aim is to realise a
detector circuit design which can be operated at millimetre and sub-millimetre wave
regions from an accurate diode model prior to the circuit design A diode detector model
puts experimental observations into context and offers insight into future experiment
results Consequently an electrical model based on lumped element component is vital
for a deeper understanding of how and to what extent a new device like the ASPAT
diode can affect all the key detector parameters that were previously discussed The
prediction of the detector parameters mostly depends upon the ASPAT diode
185
geometrical emitter size and material parameters However for millimetre wave
operating frequency the accuracy of the model is more sensitive not only to diode size
but also to the diode periphery ie substrate as well as coplanar amp transmission line
adopted in the circuit Therefore both extracted intrinsic and parasitic element of such a
device must be taken into account
In this work an ASPAT diode with an emitter size of 4times4microm2 which is the
smallest size that could be fabricated so far was chosen to be exploited for detector
designs The important parameters related to the 4times4microm2 GaAsAlAs ASPAT which
works at 0V is summarize in table 61 below
Table 61 A summary of all the important parameters of the 4x4 microm2 diode
Device Rj(Ω) Rs(Ω) Cj(fF) Cp(fF) κ(V-1) Intrinsic_fcut-off(GHz)
4times4microm2 90K 11 21 15 23 629
The actual measured I-V characteristic is used to model the diode since the library
in the ADS simulation tool does not have an ASPAT diode model or any tunnelling
diode for that matter The procedure of realizing the diode model is by taking the I-V
characteristic obtained from the 4times4microm2 emitter size measurement results and
converting it into a10th
orders polynomial equation via MATLAB software to create a
virtual I-V characteristic Thereafter this equation is then defined as a two terminals
device namely Symbolically-defined Device (SDD1P) ie a component of the non-
linear equation provided by ADS (Figure 66) to represent the ASPAT Figure 67
shows the measured data and 10th
orders polynomial equation fit very well to each other
Hence this new component used to represent the whole ASPAT diode will be used in
this research for MMIC detector and Frequency Multiplier designs The device chosen to
be modelled (4times4microm2) has measured junction capacitance of 21fF (at 0V at 40GHz) The
detector circuit is designed to operate at 100GHz for a safe side due to the extrinsic
calculated fcut-off is around 380GHz Since there are a lot of advantages in using unbiased
detectors compared to biased one this work will discuss the performance of millimetre-
wave detector at zero-bias and their result will be compared to the current performance
of other diodes reported in the literature
186
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted from
MATLAB to realize a virtual GaAsAlAs ASPAT diode
Figure 67 Verification of actual (blue measured) and virtual (red_10th order polynomial) I-V
characteristic of the 4times4 microm2 diode used in this study
To realize the ASPAT detector circuit a simple detector circuit topology as
depicted in Figure 68 was constructed Initial simulation was run to perform a
functionality check of the detector circuit utilizing the Harmonic Balance (HB)
simulation tool embedded in that particular software Such simulation tools will analyse
the detector performances in the frequency-domain as it is mostly beneficial and fully
compatible with microwave and millimetre wave problems The frequency domain is
also suitable for single and multi-tone power excitation The importance of harmonic
balance are described in [149]
-00005
0
00005
0001
00015
0002
00025
0003
-3 -2 -1 0 1 2 3
Cu
rre
nt
(A)
Voltage (V)
ADS
4x4
187
Figure 68 Direct detector circuit topology using an ASPAT diode
Initially the circuit topology that consists of P1_Tone power supply ASPAT
bypass capacitor and load resistance is simulated by setting up a fixed input frequency at
100GHz The ASPAT diode provides a DC output voltage proportional to the input
power strength depending on the absolute values of the DC terms associated with the
nonlinearity of the I-V characteristics The capacitance in the output part is a bypass
capacitor used to prevent millimetre-waves from leaking to the output The load
resistance is large enough to ensure the voltage divider between load impedance and
device impedance gives maximum voltage sensitivity This large load resistance is
achieved by creating an open circuit at the end of detector circuit terminals
Noted that this simulation was run using diode parameters that were extracted from on-
wafer one port S-Parameter measurements as described in chapter 5 To apply them in a
two port application ie detector circuit may or may not provide a very accurate
outcome it however worked adequately in the particular circuit described in this chapter
but may not work in other circuits in general Thus the one port extractions in this work
still provide adequate parameters to build and design specific MMIC detector circuits
but not in general applications
The main reason for these simulations and their results to be used in high frequency
applications is due to the fact that actual RF measurement were done up to 40GHz
Additionally the 100GHz operating frequency was obtained from extrapolation of each
ASPATrsquos component Since the on-wafer measurement that were carried out were
limited to one port characterization applying them to two port network applications may
188
have extra consequences which are unknown Therefore actual MMIC detectors are
needed to be built and test to validate this work
To find out what power the 4times4microm2 ASPAT diode can withstand the input power
is varied from -40dBm to 10dBm via control by the P1_tone As can be seen in Figure
69 the diode starts to saturate when the received input power is about -8 dBm Above
this power limit both output voltage and sensitivity drop dramatically
Figure 69 Output voltage and detector sensitivity over wide range of input power
This diode detector circuit can thus operate adequately at given input powers from -30
dBm to -8 dBm with a sensitivity of 950VW However for the best possible sensitivity
over a range of input frequencies only one optimized input power needs to be chosen
The parameters that directly influence the voltage sensitivity are the curvature
coefficients load resistance and video resistance as can be seen from Equation (61)
Therefore in the following simulation the values RL will be optimized according to the
diodes optimum input power with regards to the highest possible voltage sensitivity
Consequently five values of load resistance were chosen from few ohms to infinity
and with the same applied input power as depicted in Figure 610 For most load
resistors the sensitivity is constant at low input power and drop at the diode saturation
region (-8dBm and greater) However for an RL value of 100KΩ and below the loaded
voltage sensitivity shows a peak near 0dBm input power which corresponds to the
maximum slope of the ASPAT detector transfer function The highest voltage sensitivity
is obtained by using an Open circuit load impedance as shown in the graph The Open
circuit load impedance gives the highest voltage sensitivity due to the voltage divider
189
between source and load impedance therefore RL must be at least 5-10 times larger than
Rj to give a better sensitivity
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load resistance of
the ASPAT detector
Furthermore the value of voltage sensitivity (βV) depends on the junction
resistance of the diode and thus the large value of Rj of the ASPAT diode yields the high
βV observed Rj which was taken from the non-linear measured IV characteristic is a
voltage dependent parameter [142]and is inversely proportional to the forward bias
voltage as depicted in Figure 611 below
Figure 611 Junction resistance as a function of forward voltage
1
10
100
1000
-40 -30 -20 -10 0 10
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Incident Power Pin (dBm)
Infinity
1KΩ
10KΩ
1MΩ
100Ω
100KΩ
0
20
40
60
80
100
0 001 002 003 004 005 006 007 008 009 01
Ju
nct
ion
Res
ista
nce
(k
Ω)
Bias Voltage (V)
190
In fact the expression of (120597119881120597119868frasl ) contribute to the video impedance expression via the
expression RV=Rj+RS (nonlinear resistance) As RS is very small compared to Rj thus it
was ignored when calculating RV Although the large value of Rj will increase the
voltage sensitivity it will also make matching difficult to achieve Therefore there will
be a compromise between the size of the matching circuit and voltage sensitivity to
attain the correct value of Rj Additionally a very high Rj (around ~1MΩ) will also
increase the detectorrsquos noise equivalent power (NEP in Eq(65)) Thus an average value
of RJ typically around 100kΩ is satisfactory[150] By having a large value of RJ one can
benefit from a low input power to drive the diode into the non-linear region and thus the
detector can work at very low RF input power The NEP for GaAsAlAs ASPAT diode
is then calculated based on parameters obtained from this simulation at room
temperature The values are compared to other diode detector available in the literature
as shown in Table 62 below
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode
Device NEP (pWHz12) RJ(KΩ) Frequency(GHz)
ASPAT (4times4 microm2) 188 92 100
Tunnel Diode (08times08 microm2)[150] 370 26 220-330
Zero bias SBD[11] 15 3 150
Sb-Heterojunction Backward Diode[145] 024 32 94
VDI Zero bias SBD[151] 2 18 110
From the Table 62 above the NEP of the ASPAT is calculated based on RF input power
which is required to obtain an output signal-to-noise ratio of unity in a 1Hz at detector
output[142] and also the assumption of only Johnson-Nyquist (thermal noise) is
dominant for small incident power (-25dBm)[152 153] The prediction of NEP for the
ASPAT is comparable to the VDI Zero bias detector since the value of their junction
resistance is much lower than that of the ASPAT Therefore it is very important to
obtain a reasonable value of junction resistance From this it is clear that a trade-off of
high voltage sensitivity and low junction resistance is best to obtain low noise
191
Finally the curvature coefficient at specific operating voltages also influences
the voltage sensitivity of the detector Figure 612 shows the calculated curvature
coefficient of the 4times4microm2 ASPAT diode used in this work
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size of 4times4μm2
The high zero-bias curvature (23V) is reached from the mutual effect of the intra-band
tunnelling in the GaAs-AlAs-GaAs and the highly doped GaAs at the anode and cathode
(Rs amp Rj) This was shown in the numerical simulation in[154] where the combined
effects of the optimum anode AlAs composition increases the curvature coefficients by
thinning the energy tunnelling window (intraband tunnelling process)
Other approaches that can lead to a large curvature is using smaller device area
with minimum series resistance [155] as was also discussed in Section 52 Having a
better curvature coefficient leads to increased voltage sensitivity as seen from Equation
(61) above and βV is also proportional to κ [111] The curvature coefficient calculated
using the above formula is nearly 23V at 1mV peak and high voltage sensitivity can be
achieved by having large value of curvature coefficient But one needs to remember that
this will also decrease with increasing input power because RJ which will also decrease
Therefore for a safe operating region the incident power that can be applied through the
diode is in between -30dBm to -8dBm for a 100GHz operating frequency
In this simulation -25dBm is chosen to simulate the GaAsAlAs ASPTAT diode
detector working at 100GHz input frequency By fixing the P1_Tone to this input power
-5
0
5
10
15
20
25
30
-001 001 003 005 007 009
Cu
rva
ture
Co
effi
cien
t(V
-1)
Voltage (V)
k(4x4 um^2)
192
the frequency is varied from 90GHz to 110GHz and the results are depicted in Figure
613 below
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power
Noticeably the voltage sensitivity of the diode detector decreases linearly with
increasing input frequency At 100GHz a sensitivity of around 540VW is obtained
However the sensitivity in this case is roughly estimated from the Equation (61) above
and will not be sufficiently accurate because of the effect of other key factors such as
reflective power which was not included This parameter must be taken into the account
due the P_1Tone power source which provides a 50 Ω impedance source (Zin) which
does not match the load impedance (ZL) which consists of JωL 1JωC and Z and which
mainly comes from the ASPAT diode itself In order to determine the load impedance at
the diode a typical ohmrsquos law (Z=VI) equation must be used at the input side of the
diode with regards to the applied frequency (100GHz)
As a result the total load impedance obtained from the simulation is 11055-
j69057Ω which is clearly not matched to the 50Ω impedance source The mismatch
between source and load leads the available power from the source to be not fully
delivered to the load and hence there is loss of power leading to a lower detector
sensitivity Therefore actual calculation must take into the account the reflection impact
as expressed in the equation below
193
120573119881(119886119888119905119906119886119897) =
119877119869119877119871120581(1 minus |Γ|2)
2(119877119881 + 119877119871) (1 +119877119904
119877119895)2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(610)
Where the term (1-|Г|2) refers to the normalized power absorption by the ASPAT diode
and Г is the reflection coefficient due to discrepancy between 50Ω input impedance (Zin)
of the input port and the diode Consequently the calculation of reflection coefficient
(eq611) is carried out by using this expression and the result is shown in Figure 614
Γ =
119885119871 minus 119885119894119899
119885119871 + 119885119894119899
(611)
Figure 614 Reflection Coefficient versus operating frequency without matching circuitry
As can be seen in Figure 614 without the matching circuit the S11 is decrease
linearly with frequency but only very slowly This means that most of the RF power
transmitted from the source is reflected back (by that ratio) when it went through the
diode Therefore in order to resolve the mismatch a matching circuit is introduced in
between the source and load of the detector circuit as shown in Figure 615 (red
rectangular) This matching circuit works by transforming the load impedance into an
impedance that is identical to the source or input impedance Note that for any
impedance matching circuit the main purpose is usually to obtain maximum power
transfer to the load however in some cases (ie oscillators) the matching circuit is to
achieve a lower noise figure Hence in a broad sense the introduction of the matching
194
circuit in a detector circuit can be defined as a circuit that convert available impedance
into wanted impedance by obeying the maximum power transfer theorem [156]
Figure 615 Detector circuit with impedance matching circuit placed in between diode and source
There are many type of matching circuit that can be used to achieve both
objectives above such as circuits using lumped element transmission-line-impedance
matching circuit single and double-stub tuners as well as a quarter-wavelength In this
design the technique used to match source and load impedance is the single open and
short stub (in red rectangular) as it is simple convenient and very efficient in ADS
simulation The important parameter that needs to be tuned in both stubs is the electrical
length (E) at any designed frequency ie 100GHz in this case The E tuning is realized
by using the Smith Chart features available in the ADS simulation tools Figure 616
shows the reflection coefficient with matching circuit modelled over a broad frequency
band and it is clearly shown that at the desired operating frequency the reflection is very
low Note that it is difficult to obtain wide frequency band matching
Matching circuit
195
Figure 616 Reflection Coefficient over wide frequency band with matching
The simulation is continued to find the effect of the matching circuit placed in
the detector circuit on the voltage sensitivity The same input power (-25dBm) is applied
to the diode and the voltage sensitivity is plotted against frequency as depicted in Figure
617 Obviously at the desired operating frequency (100GHz) the sensitivity rises up to
a maximum value of 2100VW with this value obtained without any reflection and the
input port being completely matched with the ASPAT diode model used in this work
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band frequency
Once the matching circuit to be used for 100GHz operating frequency was confirmed
further simulations were made by applying a series of low input power to find the
tangential sensitivity (Tss) of the detector diode When determining the Tss it is very
important to include the matching circuit as it will minimize any power losses through
the diode thus a very small input power can be detected
196
Figure 618 Lowest detectable signal at 100GHz operating frequency
The transfer function depicted in Figure 618 shows incident power of -80 dBm
to -50 dBm applied and the lowest detectable signal that can be obtained with 4times4microm2
mesa size ASPAT diode is around 138microV at -68dBm Although a typical value of Tss is
normally not more than ~-55dBm as in ref [74] the lower value obtained in the
simulation is because the device is operated at zero bias operation and does not use any
amplifier therefore the noise and values related to amplifier as in Equation 63 have been
neglected Even though the TSS appeared very low it is most likely very dependant to
the 10th
order polynomial equation embedded into SDD in ADS software Therefore in
near future the TSS value has to be determined in real fabricated MMIC ASPAT detector
As discusses in Section 63 other important parameter that can be extracted from
the diode transfer function is the Dynamic Range of the diode It can be obtained in a
region called square law region which is a region where the Vout of the ASPAT diode is
proportional to the square law of the input power signal From Figure 619 the square
law region is in between -68dBm and -12dBm and the linear region or in this case
saturated region is above -12dBm Taking to the account the roll-off point where Vout
has dropped 1dB below the extrapolation of the dependence at low input power and
therefore the dynamic range of the detector diode can be obtained by taking the interval
between TSS and the 1dB roll-off point (in dBm) which is ~55dBm
197
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of diode operation
The figure of Merit (M) of the detector (ie equation 63) is 2100 (90K) 12
where 2100 is the sensitivity and 90K is the value of RJ at zero bias which is equivalent
to 652 W The M value should be large however in this case due to RJ being very
large it has dropped tremendously when compared to the voltage sensitivity obtained in
this simulation The results obtained indicate a reasonably successful design of the
MMIC detector using the 4times4microm2
emitter size GaAsAlAs ASPAT diode The results
obtained lead to the design of other MMIC detector using the other fabricated diode
sizes (6times6microm2 and 10times10microm
2) A Similar procedure to the one used for the 4times4microm
2
diode was followed The only difference was the use a slight higher input power (-
20dBm) than in the 4times4microm2 design Hence the simulation results obtained are then
compiled and compared as depicted in Figure 620
Saturated
Region
198
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained from the
fabricated ASPAT in this work
The graph plotted for each dimension was taken after matching circuits were included
As can be seen in Figure 620 the highest sensitivity is achieved using the smallest
device size as this has the highest cut off frequency Table 63 below summarises the
performances of the 100GHz ASPAT detectors obtained from the simulation in this
work
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector
Device Tss(dBm) fcut-
off(GHz)
Bv
(VW)
Dynamic range dB(dBm) M(W-12
)
4times4microm2 -68 380 2100 55 65
6times6microm2 -50 151 1445 48 45
10times10microm2 -40 98 247 40 21
From table 63 above it is clear that a lower cut-off frequency will affect the
voltage sensitivity The dynamic range between each ASPAT is different because larger
size area will allow more power to go through the diode as a result of high current that
such a device can handle before reaching the saturation their lowest detectable is higher
Small diode size will detect lowest voltage but cannot handle high power On the other
hand a large diode size is able to receive high power however can only offer lower
voltage output Therefore there is a trade-off between small diode size and receiving
input power which will directly affect Tss and 1dB roll off Once again all the
100
1000
10000
90 95 100 105 110
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Frequency (GHz)
10times10microm^2
6times6microm^2
4times4microm^2
199
parameters obtained in this simulation are just estimation from the 10th
order polynomial
equation thus real ASPAT detector has to be fabricated for verification
The best device performance among all GaAsAlAs ASPAT diodes was obtained
with the 4times4microm2 mesa area size diode which was compared to other exiting millimetre
wave detector diode available in the literature Since the 100GHz is located in the W-
band spectrum frequency therefore the comparison will be performed in this frequency
band but with low input power The parameters for the-state-of-the-art zero bias
detectors are gathered in Table 64 below
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero bias detector
at W-band (75GHz-110GHz)
Device Size(microm2) Tss(dBm) βv (VW) Pin (dBm) f (GHz)
GaAsAlAs ASPAT 4times4 -68 2100 -25 100
GaAs SBD HSCH-
9161[157]
- -49 2200 94
HBD[158] 15x15 2540 -20 95
Planar SBD[159] - -68 2100 -25 100
Note that the ASPAT diode retains its favourable temperature stable characteristics
which are not the case for all the diodes used for comparison in Table 64
66 Conclusions
In this chapter all theory regarding RF detection using diodes ie parameters of
interest noise consideration etc have been discussed The aim to design and develop a
low cost reliable and sophisticated zero bias 100GHz detector circuit was achieved
through exploitation of a 4times4microm2 GaAsAlAs ASPAT diode The design was performed
with the aid of Keysight ADS modelling software utilizing harmonic balance simulation
The effect of load resistance junction resistor to the detector voltage sensitivity was also
discussed in details The 90KΩ Rj value and open circuit load resistance was chosen for
high sensitivity
200
A step by step design of a W-band ASPAT detector was presented The effect of
matching circuit was discussed in detail and where an unmatched sensitivity of 843VW
is obtained which then increases to 2100VW after matching Through RF
characterization simulation a detection at 100GHz (W-band) was successfully achieved
with a relatively large device mesa area (4times4microm2) at an input power of -25dBm
(8microWatt) leading to a 2100VW voltage sensitivity a -68dBm TSS and 55dBm dynamic
range All these values are comparable to others fabricated diodes in the literature
The zero bias ASPAT detectors based on the GaAsAlAs material system in this
work are still at an early stage of development a lot of work is still required to realize
high yielding integrated millimeter and sub-millimeter wave (MMIC) detector circuits
However as this work is on-going at Manchester it is expected that fabricated ASPAT
MMICs with even higher voltage sensitivity will be fabricated in the near future through
collaborating bodies involved in this research especially the University of Cambridge
and ICS Limited
201
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING
GAASALAS ASPAT DIODES
71 Introduction
Originally the key application for the ASPAT diode was for use as microwave and
millimetre wave detectors[18] This is due to the fact that such diode demonstrates
strong non-linearity low noise and high cut-off frequency features as described in the
previous chapters However these features are not only beneficial for detection purposes
but also allow them to be used and designed as microwave and millimetre wave sources
The only way to generateenhance continuous wave (CW) power using a non-linear
device is through frequency multiplication techniques It is known that the frequency
multiplier is the alternative approach (to 3 terminal transistors) using non-linear devices
that are used to generate high frequency low phase noise signals Any high quality low
frequency signal that goes through a frequency multiplier circuit can be generated to any
desired high output frequency[160] Therefore the main objective of this chapter is to
demonstrate the feasibility of the ASPAT diode as a compact source of microwave and
millimeter-wave receiver for imaging applications[161]
The study of the ASPAT diode as a power source begins with a brief explanation
of the importance of a frequency source and the lack of compact device and technologies
at high-frequency signals The state-of-the-art for frequency multiplier will also be
discussed In the next section (Section 74) the fundamentals of the frequency multiplier
architecture ie the principle of operation and appropriate devices will be presented
Since this is the first attempt at using GaAsAlAs ASPAT diodes a simple multiplier
circuit design and topology was built This will be discussed in detail in the subsequent
sections where simulation results are discussed The focus of the discussion will be to
demonstrate the possibility of a GaAsAlAs ASPAT diode functioning as a frequency
multiplier and comparison with other state-of-the-art varistor mode frequency
multipliers
202
72 Motivation and Background
Typically continuous wave (CW) sources generating below 100 GHz can be
obtained through oscillators amplifiers and pin diode comb generator Below 10THz
the sources can be made from RTD IMPATT diodes and Gunn oscillators and above 10
THz it is commonly done by photonic mixing quantum cascade laser (QCL) and gas
lasers [162] Both types of sources and their performance are plotted in Figure 71
However these conventional ways of generating millimetre and sub-millimetre waves
have their own limitations ie high cost complexity and sometimes requirement for
cryonic cooling The most effective way to tackle the limitations of conventional mm-
wave and THz sources is by implementing frequency multiplication technique using
solid state nonlinear diodes [163-165] such as SBD and ASPAT diodes
Figure 71 performance of state-of the-art millimetre wave source [166]
Twenty years ago there were only two types of diodes (SBD and P-N junction
diodes) often used for frequency multiplication To date besides the SBD there are
many types of diode that have been used as frequency multipliers These include the
high electron mobility varactor (HEMV) single barrier varactor (SBV) [167] and hetero-
structure barrier varactor (HBV) (270GHz with 90mW input power and Conversion
Efficiency of 72)[168 169] Other variants that have developed to enhance the
frequency multiplier performance of the classic SBD [170] include the Barrier-intrinsic-
203
n+ (BIN)diode and Barrier N-layer N+ (BNN) diode [171] Other diodes for use in such
applications are the planar doped barrier diode (PDB) Resonant tunnelling diode (RTD)
amp it families ie Quantum well diode (QWD) and step recovery diode which is a
modification of the P-N junction diode
Although three terminal devices ie FET GaAs MESFET and HEMT had
shown better performance and are capable of achieving greater efficiency and
bandwidth as well as having additional conversion gain features [160] two terminal
devices (ie varactor diodes) which are passive multiplier are still preferred This is due
to their simplicity and most importantly their ability to generate very little noise Among
these types of device technologies the SBD is preferable as it is mature and has been
shown to be very suitable for high-frequency applications [172 173]
The ASPAT diode is exploited to investigate the possibility and the feasibility of
generating microwave and millimetre-wave power through well-known frequency
multiplication methods The utilisation of the ASPAT in frequency multiplication will
also aid in generating local oscillator sources which are critical components in
heterodyne receivers The ASPAT diode will work in resistive I-V mode (varistor mode)
and has features to work also at zero bias condition thus offering low power handling
than traditional high-efficiency varactor diode since the varactor diode requires a large
reverse bias supply of several tens of volts
73 Frequency Multiplier Architecture the Basics
In principle a frequency multiplier is an electronic circuit that gives an output
frequency that is a multiple integer of its input frequency signal pumped from a local
oscillator as depicted in Figure 72 The ability to generate any desired multiple output
signals is realised by a nonlinear device ie diode or transistor Such devices though
also can give distortion or cause sudden change to the input frequency Additionally
these devices generate multiples of the input frequency (fout) The distortion of the
sinusoidal signal refers to an abruptsudden change versus amplitude or time which thus
generates higher frequency with lower amplitudes of the input signal Usually a
frequency multiplier circuit will include a bandpass filter to select the desired harmonic
204
frequencies and deselect undesired harmonic frequencies especially fundamental
harmonic at the output for further processing
Any non-linear device either in symmetricalantisymmetric current-voltage or
capacitance-voltage can be utilised to realise a frequency multiplier source [168 174]
Figure 73 describes the method where a nonlinear resistance is utilised to convert a
harmonic input signal into periodic output signal containing components at multiples of
the input frequency Both non-linear resistance and reactance characteristics can be
extended into power series methods
Figure 73 Principle of operation for frequency multiplier utilising a non-linear resistance [10]
The operating principle of the frequency multiplier is shown in Figure 73 where
the I-V curve converts a harmonic frequency input into a periodic frequency output
including components at multiples of the input frequency The non-linear I-V
characteristic can be explained in term of a power series at the operating fixed point of
bias voltage (VB) [174]
Frequency
Multiplier Circuit
finput
foutput
= nfinput
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
205
119868(119881119861 + ∆119881) = 1198860 + 1198861∆119881 + 1198862∆1198812 + 1198863∆1198813 helliphellip (71)
For a given input voltage as below
∆119881 = 119881119904 cos120596119878119905 (72)
The input signal harmonics will become
119868(119905) = 1198680 + 1198681 cos120596119904119905 + 1198682 cos 2120596119904119905 + 1198683 cos 3120596119904119905 (73)
Where t and ω are the time and angular frequency respectively based on equation (73)
the output contains both signal source and harmonics Therefore a complete frequency
multiplier circuit has to have non-linear device and filter to allow the selection of any
frequency components needed
731 Types of frequency multipliers
Frequency multipliers can be classified into passive and active multipliers This
classification is based on the ability of the frequency multiplier to yield any conversion
gainlosses The passive multiplier is the one that only produces conversion losses In
other words it can be described as a multiplier that generates an output power level
lower than the excitation input power and it is mostly dominated by passive nonlinear
devices ie Diodes On the other hand the active multipliers refer to a device that would
produce an output signal with a power level that is greater than the input signal power
This conversion of power is termed as conversion gain These types of multipliers attract
much attention as they do not only increase the frequency at the output but also the
signal power
Passive frequency multiplier can be formed by using diodes that are classified as
being of the varistor (non-linear I-V) or varactor (non-linear C-V) type [160 174] The
varistor type will influence the frequency multiplication with a non-linear resistance or
conductance (resistive diodes) and this results in a very large potential bandwidth at the
output but poor conversion efficiency The varactor diode type where the frequency
multiplications are affected by the non-linear capacitance (reactive diode) as their
reactive element typical result is high conversion efficiency A diode that is used in this
206
application must have strong nonlinearity stable electrical characteristic repeatable and
has fast enough response to an applied frequency Therefore multipliers are classified
into Doubler Tripler quintuple and so forth depending on the highest power of output
harmonic signal
In general all varactor type diodes with such characteristics will produce high
power at odd-order harmonic oscillation if any microwave signal is pumped into them
The benefit of having odd-order in multiplier design is that it reduces the complexity of
the overall circuit ie it eliminates even-order idler frequencies [175] The varactor type
diode had been shown by Manley-Rowe to a get maximum 100 conversion efficiency
for generating an ideal harmonic [176] compared to the varistor type where the
maximum efficiency achievable ideally is 1 1198992frasl where n is the multiplication factor
(output harmonics number) [174] In the case of power handling (input excitation power)
for multipliers varactor mode diode required greater power (several milli Watt) than the
varistor mode due to the fact that reverse applied voltages are very large (many tens of
volts) Therefore these types of frequency multipliers may not be suitable for the case of
high input power excitation There no report in the literature of varistor based
multipliers working with high power excitations
74 Parameters of interest for Frequency Multipliers
The simplest way to describe an equivalent circuit for a complete frequency
multiplier is by setting a Source impedance (ZS) at the input side and load impedance
(ZL) at the output side as depicted in Figure 74 below This circuit usually has the same
properties as described in the previous chapter and most of the others two ports
networks However in this case the purpose is different and is the conversion of a sine
wave signal source (Vs) with angular frequency ωs to an output signal with frequency
nωs where n is the multiplication integer or the order of multiplication
207
Figure 74 A standard system for two port frequency multiplier circuit
Referring to Figure 74 above there are few sets of parameters for the frequency
multiplier to be taken out and compared Examples are the conversion loss maximum
input signal power Impedance at source and load Bandwidth multiplication factor or
harmonic amp subharmonic content and noise conversion properties The conversion loss
(CL) is described by the ratio of available power at source (Ps) to the output harmonic
power delivered to load resistance (PL) and is normally expressed in dB It occurs due to
the nature of passive semiconductor diodes and the electronic circuit itself that are lossy
and dissipate energy On the other hand the conversion efficiency (ηn) is a ratio of the
output power at load (PL) to the available power at the input (Ps) This is often expressed
in percentage () The conversion efficiency can be determined as
120578 =
119875119878
119875119871
(74)
while the conversion loss is expressed as[174]
119871119899[119889119861] = 10 log
119875119904
119875119871= 10 log (
|1198811199042|
4 119877119890 |119885119904||1198681198712|119877119890|119885119871|
) (75)
Where Vs is the input voltage and IL is the output current amplitude Besides this the
conversion efficiency is often referred to as the inverted value of the Ln In designing a
frequency multiplier it is crucial to minimise the conversion loss and maximise the
conversion efficiency value
To achieve a perfect multiplier with minimum conversion loss the impedance of
source and load must be at an optimum level This implies that the source impedance
Frequency
Multiplier Z
L
Zout
Z
in
V
Z
SWR Г
208
(Zs) must be very close to the complex conjugate of the multiplier input impedance
(Zin) hence minimum reflection loss will occur at the input side This can be realised by
introducing an impedance matching circuit between the diode and source The power
transfer between the source and the multiplier is quantitatively described by the value of
the multiplier input reflection coefficient (Ѓ) with source Zs assumed to represent a
reference impedance This specification also can be explained in the standing wave ratio
(SWR) Both relationships are described below respectively [174]
Γ =
119885119894119899 minus 119885119904lowast
119885119894119899 + 119885119904
(76)
119878119882119877 =
1 + |Γ|
1 minus |Γ|
(77)
Where the asterisk () represents the complex conjugate of the Zs impedance
On the other hand the situation of the load impedance is different when a standard
or an optimum value is provided by the designer This will either increase the conversion
loss or decrease the output power Thus one has to keep in mind that frequency
multipliers are non-linear devices and power transfer condition both at the input and the
output depend on each other and the input signal level[174]
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler
In this work a similar ASPAT diode (4times4microm2) to that in designing millimetre
wave detector in the previous chapter is used The main objective of designing the
frequency multiplier circuit was first to investigate the performance of the ASPAT
diode as a microwave or millimetre wave signal source A design is deemed successful
when the diode physical parameters are optimised and the suitable impedance matching
network is produced for each desired harmonic as well as maximising the output power
These goals however are hard to achieve when a higher frequency operation is targeted
for use
There are many types of multiplier circuit topologies that can be implemented
using GaAsAlAs ASPAT diode in varistor mode to achieve high order of multiplication
209
Examples are single diode multiplier series or parallel connected diode multiplier anti-
parallel amp anti-series connection diode pair multiplier anti-parallel-series connected
diode multiplier and bridge frequency multiplier as well as nonlinear transmission line
frequency multiplier [174] Before designing a circuit there is one most important
consideration to make Prior to choosing any mentioned circuits to be used for frequency
doubler the design considerations are made based on the capability of ASPAT diode to
receive an optimum amount of input excitation RF power From the discussions in
Chapter 6 the ASPAT diode will reach saturation level (linear regime) at power ~
-10dBm for a device size of 4x4microm2 Once the optimum input power was confirmed the
circuit topology was carefully chosen to balance between the requirements of the
ASPAT to work at high frequencies ie low Rs and Cj amp high diode cut-off frequency
as well as the desired output signal frequency that needs to be produced
To realise the first attempt of an ASPAT diode as a signal source a simple circuit
topology of a frequency doubler was deployed as depicted in Figure 75 below The
frequency doubler circuit consists of a voltage source (can be power source) input
filtering with matching network ASPAT diode output filtering with matching network
and load impedance (ZL)
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode
In order to investigate the doubler performance the Keysight ADS simulation
tool and similar procedure to obtain accurate ASPAT model using a 10th
order
polynomial equation as in Section 65 was used The circuit in Figure 75 is translated
into ADS format as illustrated in Figure 76 Once the circuit was constructed the
analysis was performed using the Harmonics Balance (HB) simulator The circuit
requirements are matched terminations at the input and output frequencies open
Input Filtering
and matching network
Output Filtering
and matching network
Zs
Vs
ZL
Pin
fin
Pout
nfout
210
circuited terminations at the higher harmonics and optimum reactive terminations (an
inductance which resonates with the junction capacitance) at the output frequencies
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool
The circuit in Figure 76 is the simplest way of constructing a frequency doubler
circuit which consists of the signal source (P_1Tone) input matching circuit (Stubs)
filter (Short stub) ASPAT diode low pass filter output matching circuit(Stubs) and ZL
(load resistance) The utilisation of the stubs is an ideal case of simulation since in the
real fabrication stubs are normally formed in large sizes Therefore a proper design such
as using CPW instead of stubs is essential in real fabrication
Again this simulation works for this particular circuit in this chapter as all the diode
parameters were extracted from on-wafer one port S-Parameter measurement described
in chapter 5 To apply them in such two ports applications may not very accurate
however it still provides adequate parameters to build and design particular frequency
multipliers but not in general applications These simulations and results are adequate for
high frequency applications due to the fact that the actual RF measurements on the
diodes were carried out up to 40GHz and the target operating frequency in this multiplier
design does not exceed 40GHz
Since the on-wafer measurement that were carried out were limited to one port
characterization applying them to two port network applications may have extra
consequences which are unknown Therefore actual MMIC frequency multiplier is
needed to be built and test to validate this work
Input Matching
Output Matching
211
To find the optimum output power initial simulation without matching circuit
was performed This simulation was run by varying the input power from -35dBm to
20dBm but fixing the input frequency at 20GHz As can be seen in Figure 77 the lowest
point in the conversion loss (CL) and the highest point of the conversion efficiency (CE)
are obtained from an input power of -1dBm However this amount of input power is too
high for the ASPAT diode The lowest CL at -1dBm may not be accurate since it was
applied without matching Note that it is difficult to achieve a matching between source
impedance and load impedance when varying the input power Therefore a lower input
power of -10dBm is chosen for this frequency doubler operation Figure 77 shows the
Conversion Loss and Conversion Efficiency as a function of the available power of the
given input source
Figure 77 Conversion loss and conversion efficiency as a function of input power
The circuit in Figure 76 works with a -10dBm input power and 20GHz centre
frequency input signal is pumped from the power source (P1_tone) to the ASPAT diode
and distortionabrupt change of input waveform occurs at the fundamental frequency (f0
in this case 20GHz) Such abrupt change produces harmonics and these harmonics can
be classified into desired frequency component by placing two-quarter wavelength (λ4)
stubs (90˚) at both sides of the ASPAT diode At the input side of the diode short circuit
stubs are utilised to permit the f0 tone to reach the ASPAT diode and block the second
harmonics (2f0 in this case 40GHz) back to the input side and pushes it towards the
load resistance On the contrary at the output side of the diode the open circuit stubs are
used to ldquoopen circuitrdquo the 2f0 signals while ldquoshort circuitrdquo the f0 component Thus 2f0
212
signal will not be affected due to the open circuit stubs being half wave (λ2) long The
function of both stubs is basically to isolate the input and output signal from mixing each
other Therefore the design of input and output matching circuit can be achieved easily
The input matching circuit was designed based on the mentioned input frequency
(f0=20GHz) for an available input power (Ps=-10dBm) which is set up at the power
source by using two stubs with the same configuration as used in Chapter 6 Such
configuration is purposely deployed to increase the 50Ω coming from the P1_tone
source impedance to the conjugate thus reducing the reflection coefficient to the
ASPAT diode From the simulation without matching the input impedance to the diode
is 551Ω in magnitude for an available input power of -10dBm
On the output side of the diode output matching circuit is available to transform the 50Ω
port impedance in the optimum load impedance which provides minimum conversion
loss for the ASPAT diode The output matching circuit is designed based on expected
output frequency which is in this case 2f0 =40GHz Other than this optimum
impedance between load impedance and ASPAT will not be achieved thus resulting in
higher conversion loss
To ensure the proposed circuit is valid and suitable for the specific ASPAT diode
mesa size the response of conversion loss and efficiency are plotted as a function of
output frequency from 20GHz to 100GHz The results of both conversions are illustrated
in Figure 78
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
213
As can be seen in Figure 78 the conversion loss is obtained at the lowest point where
the output frequency is needed Meanwhile the conversion efficiency is maximum at the
same output frequency Therefore this indicates that the first attempt of an ASPAT
Doubler frequency source works well However the values obtained for Ln from this
simulation is 28dB which is rather high On the contrary the η achieved in this study is
very low with a value less than 1
Since the ASPAT is in varistor mode with no bias applied the conversion
efficiency is expected to be low due to resistive losses Another factor that may
contribute to lower η is the diode model itself as it is taken from a 10th
order polynomial
equation not from a diode model provided in the ADS software tools Thus some
properties of such tunnelling diode may not be included Hence it is necessary in due
course to fabricate and build such a compact frequency doubler in the future to verify
the simulation results
From the simulation point of view the less than 1 Conversion Efficiency
obtained is still good enough for a first attempt at a frequency doubler which utilises the
new ASPAT tunnelling diode The frequency doubler obtained from this work is suitable
for use in zero bias varistor modes for low power application The varistor mode doubler
performances from this simulation work are gathered and compared to other in the
literature as summarized in Table 71 below where fout is 40GHz η is 015 Ln is 28dB
and Pi is -10dBm
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art multiplier
diode
Device fout (GHz) η() Ln(dB) Pi (dBm)
ASPAT 40 015 28 -10
SBD (Si)[177] 104 2 134 -10
SBD (GaAs)[178] 13 2 137 -16
214
The performance of the 2040GHz is compared to the literature based on their input
power below -8dBm since the ASPAT is only capable of working at low power To the
best of the author knowledge very few diodes operating in varistor mode at low power
excitation can be found in the field of research and industry Therefore this 2040GHz
ASPAT Doubler might a first for tunnel diodes if it can be fabricated and test at Ka band
and above
76 Conclusions
In this chapter another alternative application based on non-linear features of
GaAsAlAs ASPAT has been presented The simulation of a frequency multiplier
(doubler) was carried out utilizing the 4times4microm2 size ASPAT diode The theory and the
ability of the ASPAT diode to operate as a frequency source were explained in detail
A unique varistor mode frequency multiplier circuit topology for the 2040GHz
ASPAT doubler has been demonstrated and briefly discussed The details and step by
step simulation technique utilizing harmonic balance from Keysight ADS has been
presented Even though the conversion efficiency is very small at 015 and large
conversion loss of 28dB there is still space for improvement in term of design ie
different circuit topology optimized input and output matching circuit etc This design
can be a good reference for a doubler operating at very low power but produce high
frequencies in Ka band
215
8 CONCLUSION AND FUTURE WORK
81 Conclusion
The main focus of this research was the development of a new tunneling diode
namely the asymmetrical spacer layer tunnel (ASPAT) diode for process repeatability
manufacturability and reproducibility The broad study undertaken was to improve the
microwave performance technology by introducing a new type of tunneling diode
For years the asymmetrical spacer layer tunnel diode was unable to be manufactured
due to the high sensitivity of the tunneling current to the barrier thickness This changed
dramatically when the MBE method was carefully optimized to precisely control the
growth to sub-monolayer precisions When stability repeatability and reproducibility in
the epitaxial growth was achieved the next step was to qualify the fabrication process of
the diodes themselves thus ensuring high performance device can be delivered to the
market
For this purpose GaAsAlAs ASPAT diodes made of two different types of
substrates were grown The first batch was grown in the Riber V100HU SSMBE and
used doped substrates Samples XMBE307 and XMBE368 were successfully grown
and fabricated from that batch The DC characterization obtained from measurement
proved that this first batch had fully functional reproducible and manufacturable
devices Later a second batch using semi insulating substrates improvement in spacer
layer and doping concentration were grown This set of samples (9 x 2rdquo wafers grown
simultaneously) and denoted as XMBE304 also showed fully functional DC
characteristic and was used for RF characterization and detector integrated circuits
The conventional GaAsAlAs ASPAT diode structures grown on doped
substrates and developed previously in our lab were not suitable for high frequency RF
characterizations Therefore a major contribution of this work was to develop a new
fabrication technique for a new GaAsAlAs ASPAT structure using semi insulating
substrates to achieve repeatability manufacturability and reproducibility in term of
process flow DC characteristics and ultimately RF characteristics Apart from the
enhancement of the epitaxial layer the other important contribution of this research was
216
the optimization of the small 4times4microm2 emitter size by incorporating both vertical and
lateral structure based purely on low cost I-line optical lithography
To obtain a repeatable and manufacturable fabrication process of lateral
GaAsAlAs ASPAT structures the key issue was to solve the over etching of the
effective mesa area when qualifying the Air Bridge technique This issue caused all
semiconductors under the metal contact to be completely lost thus leaving the metal
contact hanging without connection to any bond pad area However the developments of
the Dielectric Bridge technique realized the true performance of the GaAsAlAs ASPAT
diode structures The samplersquos surface cleanliness as well as DC and RF performance
showed significant improvement when using Si3N4 as a dielectric layer Due to the
highly isotropic etching profile and thicker GaAs layer in XMBE304 samples and
although the smallest emitter size designed on the mask was 2times2microm2 only 4times4microm
2 were
reproducible and showed good uniformity in I-V characteristics
Upon successful optimization in the fabrication process flow of the small emitter
size diodes (4times4microm2 6times6microm
2 and 10times10microm
2) a good uniformity of better than 91
was obtained for DC measurement results within a tile containing over 1000 devices
This confirmed that the lateral GaAsAlAs ASPAT diode structure can only be realized
through the Dielectric Bridge technique These devices were further characterized with
S-parameter measurements and their intrinsic and extrinsic parameter values and
junction capacitances series resistances and junction resistances were extracted leading
to intrinsic cut-off frequencies of 600GHz 429GHz and 100GHz for the three device
sizes respectively
Temperature dependence measurements and simulations were also carried out in
order to confirm that the ASPAT diodersquos characteristics were temperature insensitive
showing less than 5 change in current at both extremes of temperatures 77K to 400K
By comparison the SBD I-V characteristics variations with temperature span orders of
magnitude Physical modelling agreed very well with measured data confirming good
and validated models that can also describe temperature effects
For the realization of the integrated ASPAT millimeter wave detector empirical
modelling using ADS simulation tools was carried out This was performed to predict
the detector performance at 100GHz to comply with the initial objective to develop a
217
millimeter wave detector circuit The simulations using the 4times4microm2 diode models led to
a successful 100GHz circuit design able to detect 100GHz incoming frequency with
2100VW voltage sensitivity
The first ever GaAsAlAs ASPAT diode frequency multiplier design was also
attempted A reasonably good result was obtained for a 20 to 40GHz frequency doubler
operating in varistor mode However the conversion efficiency obtained was less than
1 Further research on this is required to improve the efficiency by using other circuit
topology ie using a balun or other Co-planar waveguides Ultimately fabricating and
testing the actual multiplier circuits are essential to validate the simulation data
82 Future Work
This work has provided a foundation for a reproducible and repeatable GaAsAlAs
ASPAT (SI substrate) wafer fabrication process and recommendations for design and
simulation of ASPAT diode MMIC detectors and frequency source has also been
provided However the GaAsAlAs ASPAT diodes still remain immature and there are
many ways to improve its DC and RF performances both experimentally and in
simulations which will directly affect the detection performances
In term of fabrication process smaller size diodes ie submicron level can be
achieved using dry etching technique with proper calibration For wet etch technique the
etched profile still can be improved by thinning the doped layers so that etching time
will be reduced and hence dimensions down to 2times2microm2 or even 15times15microm
2 can be
reproducibly made
For simulations advanced AC and RF modelling utilizing physical device
simulation available software (SILVACO) must be include in future research hence
holistic study can be conducted to improve the understanding of the ASPAT
For MMIC detector and multiplier design it is vital to produce actual MMIC
devices so that the simulation results can be validated Ultimately tested devices with
good performances can be realized and manufactured
218
REFERENCES
1 Laeri F U Simon and M Wark Host-Guest-Systems Based on Nanoporous
Crystals 2006 John Wiley amp Sons
2 Łukasiak L and A Jakubowski History of semiconductors Journal of
Telecommunications and information technology 2010 p 3-9
3 Song H-J and T Nagatsuma Present and future of terahertz communications
IEEE Transactions on Terahertz Science and Technology 2011 1(1) p 256-
263
4 Hu B and M Nuss Imaging with terahertz waves Optics letters 1995 20(16)
p 1716-1718
5 Smith PR DH Auston and MC Nuss Subpicosecond photoconducting
dipole antennas IEEE Journal of Quantum Electronics 1988 24(2) p 255-260
6 Nagatsuma T Terahertz technologies present and future IEICE Electronics
Express 2011 8(14) p 1127-1142
7 Kumar S et al A 18-THz quantum cascade laser operating significantly above
the temperature of [planck][omega]kB Nature Physics 2011 7(2) p 166-171
8 Phillips T and D Woody Millimeter-and submillimeter-wave receivers Annual
Review of Astronomy and Astrophysics 1982 20(1) p 285-321
9 Whitmer HCTaCA Crystal Rectifiers McGraw-Hill book Company
London 1948
10 Young D and J Irvin Millimeter frequency conversion using Au-n-type GaAs
Schottky barrier epitaxial diodes with a novel contacting technique Proceedings
of the Ieee 1965 53(12) p 2130-2131
11 Liu L et al A broadband quasi-optical terahertz detector utilizing a zero bias
Schottky diode IEEE microwave and wireless components letters 2010 20(9) p
504-506
12 Sankaran S Schottky barrier diodes for millimeter wave detection in a foundry
CMOS process IEEE Electron Device Letters 2005 26(7) p 492-494
13 Chattopadhyay G Submillimeter-wave coherent and incoherent sensors for
space applications in Sensors 2008 Springer p 387-414
14 Anand Y and WJ Moroney Microwave mixer and detector diodes
Proceedings of the Ieee 1971 59(8) p 1182-1190
15 Syme RT Microwave Detection Using GaasAlas Tunnel Structures Gec
Journal of Research 1993 11(1) p 12-23
16 Syme RT et al Asymmetric superlattices for microwave detection in Physical
Concepts of Materials for Novel Optoelectronic Device Applications 1991
International Society for Optics and Photonics
17 Missous M MJ Kelly and J Sexton Extremely uniform tunnel barriers for
low-cost device manufacture IEEE Electron Device Letters 2015 36(6) p 543-
545
18 Syme RT et al Novel GaAsAlAs tunnel structures as microwave detectors in
Semiconductors 92 1992 International Society for Optics and Photonics
19 Schwierz F and JJ Liou Semiconductor devices for RF applications evolution
and current status Microelectronics Reliability 2001 41(2) p 145-168
219
20 HayasHi H Development of Compound Semiconductor DevicesmdashIn Search of
Immense Possibilitiesmdash SEI TECHNICAL REVIEW 2011(72) p 5
21 Mead C Schottky barrier gate field effect transistor Proceedings of the Ieee
1966 54(2) p 307-308
22 Hooper W and W Lehrer An epitaxial GaAs field-effect transistor Proceedings
of the Ieee 1967 55(7) p 1237-1238
23 Drangeid K R Sommerhalder and W Walter High-speed gallium-arsenide
Schottky-barrier field-effect transistors Electronics Letters 1970 6(8) p 228-
229
24 Pillarisetty R Academic and industry research progress in germanium
nanodevices Nature 2011 479(7373) p 324-328
25 Oxley TH 50 years development of the microwave mixer for heterodyne
reception IEEE transactions on microwave theory and techniques 2002 50(3)
p 867-876
26 Baca AG and CI Ashby Fabrication of GaAs devices 2005 IET
27 Cho AY and J Arthur Molecular beam epitaxy Progress in solid state
chemistry 1975 10 p 157-191
28 Cho A Growth of IIIndashV semiconductors by molecular beam epitaxy and their
properties Thin Solid Films 1983 100(4) p 291-317
29 Kiehl RA and TG Sollner High speed heterostructure devices 1994
Academic Press
30 Feiginov M et al Resonant-tunnelling-diode oscillators operating at
frequencies above 11 THz Applied Physics Letters 2011 99(23) p 233506
31 Chang LL L Esaki and R Tsu Resonant tunneling in semiconductor double
barriers Applied Physics Letters 1974 24(12) p 593-595
32 Kasjoo SR Novel Electronic Nanodevices Operating in the Terahertz Region
2012
33 Kanaya H et al Structure dependence of oscillation characteristics of
resonant-tunneling-diode terahertz oscillators associated with intrinsic and
extrinsic delay times Japanese Journal of Applied Physics 2015 54(9) p
094103
34 Chattopadhyay G Technology capabilities and performance of low power
terahertz sources IEEE Transactions on Terahertz Science and Technology
2011 1(1) p 33-53
35 Betz A and R Boreiko A practical Schottky mixer for 5 THz in Proceedings of
the 7th International Symposium on Space Terahertz Technology 1996
36 Yu D et al Ultra high-speed 025-spl mum emitter InP-InGaAs SHBTs with
fsub maxof 687 GHz in Electron Devices Meeting 2004 IEDM Technical
Digest IEEE International 2004 IEEE
37 Das MB Optoelectronic detectors and receivers speed and sensitivity limits in
Optoelectronic and Microelectronic Materials Devices 1998 Proceedings 1998
Conference on 1999 IEEE
38 Rodwell MJ et al Submicron scaling of HBTs IEEE Transactions on Electron
Devices 2001 48(11) p 2606-2624
220
39 Bouloukou A and S Missous Novel High-breakdown Low-noise InGaAs-
InA1As Transistors for Radio Astronomy Applications 2006 University of
Manchester
40 Bean J Materials and technologies 1990 John Wiley amp Sons New York p
13
41 Swaminathan V and A Macrander Materials aspects of GaAs and InP based
structures 1991 Prentice-Hall Inc
42 Vurgaftman I J Meyer and L Ram-Mohan Band parameters for IIIndashV
compound semiconductors and their alloys Journal of applied physics 2001
89(11) p 5815-5875
43 Dingle R W Wiegmann and CH Henry Quantum states of confined carriers
in very thin Al x Ga 1minus x As-GaAs-Al x Ga 1minus x As heterostructures Physical
Review Letters 1974 33(14) p 827
44 Sze SM and KK Ng Physics of semiconductor devices 2006 John wiley amp
sons
45 Tyagi MS Introduction to semiconductor materials and devices 2008 John
Wiley amp Sons
46 Schubert E Delta doping of IIIndashV compound semiconductors Fundamentals
and device applications Journal of Vacuum Science amp Technology A Vacuum
Surfaces and Films 1990 8(3) p 2980-2996
47 Rhoderick EH Metal-semiconductor contacts IEE Proceedings I-Solid-State
and Electron Devices 1982 129(1) p 1
48 Piotrowska A A Guivarch and G Pelous Ohmic contacts to IIIndashV compound
semiconductors A review of fabrication techniques Solid-State Electronics
1983 26(3) p 179-197
49 Rideout V A review of the theory and technology for ohmic contacts to group
IIIndashV compound semiconductors Solid-State Electronics 1975 18(6) p 541-
550
50 Baca A et al A survey of ohmic contacts to III-V compound semiconductors
Thin Solid Films 1997 308 p 599-606
51 Higman T et al Structural analysis of AundashNindashGe and AundashAgndashGe alloyed
ohmic contacts on modulation‐doped AlGaAsndashGaAs heterostructures Journal of
applied physics 1986 60(2) p 677-680
52 Chen KJ et al High-performance enhancement-mode InAlAsInGaAs HEMTs
using non-alloyed ohmic contact and Pt-based buried-gate in Indium Phosphide
and Related Materials 1995 Conference Proceedings Seventh International
Conference on 1995 IEEE
53 Berlin L The man behind the microchip Robert Noyce and the invention of
Silicon Valley 2005 Oxford University Press
54 Goodhue W et al Large room‐temperature effects from resonant tunneling
through AlAs barriers Applied Physics Letters 1986 49(17) p 1086-1088
55 Kerr A and Y Anand Schottky diode MM detectors with improved sensitivity
and dynamic range Microwave Journal 1981 24 p 67-71
56 Davies R Simulations of the current-voltage characteristics of semiconductor
tunnel structures Gec Journal of Research 1987 5(2) p 65-75
221
57 Kelly M Tunnel structures and devices over the coming decade Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2291-2293
58 Wilkinson V and M Kelly Manufacturability of quantum semiconductor
devices in High Performance Electron Devices for Microwave and
Optoelectronic Applications 1995 EDMO IEEE 1995 Workshop on 1995
IEEE
59 Wilkinson V M Kelly and M Carr Tunnel devices are not yet
manufacturable Semiconductor Science and Technology 1997 12(1) p 91
60 Eaves L and MJ Kelly The current status of semiconductor tunnelling devices
Philos trans of the Roy soc of London Ser A Math phys and eng sciences
1996 354(1717)
61 Billen K V Wilkinson and M Kelly Manufacturability of heterojunction
tunnel devices further progress Semiconductor Science and Technology 1997
12(7) p 894
62 Kelly M The engineering of quantumndashdot devices Philosophical Transactions
of the Royal Society of London A Mathematical Physical and Engineering
Sciences 2003 361(1803) p 393-401
63 Kelly M New statistical analysis of tunnel diode barriers Semiconductor
Science and Technology 2000 15(1) p 79
64 Hayden R et al Ex situ re-calibration method for low-cost precision epitaxial
growth of heterostructure devices Semiconductor Science and Technology
2002 17(2) p 135
65 Dasmahapatra P et al Thickness control of molecular beam epitaxy grown
layers at the 001ndash01 monolayer level Semiconductor Science and Technology
2012 27(8) p 085007
66 Hayden R M Missous and M Kelly Precision growth for the manufacture of
semiconductor heterostructure devices Semiconductor Science and Technology
2001 16(8) p 676
67 Shao C et al Highly reproducible tunnel currents in MBE-grown
semiconductor multilayers Electronics Letters 2012 48(13) p 792-794
68 Abdullah MR et al GaAsAlAs tunnelling structure Temperature dependence
of ASPAT detectors in Millimeter Waves and THz Technology Workshop
(UCMMT) 2015 8th UK Europe China 2015 IEEE
69 Ariffin KZ et al Asymmetric Spacer Layer Tunnel In0 18Ga0 82AsAlAs
(ASPAT) Diode using double quantum wells for dual functions Detection and
oscillation in Millimeter Waves and THz Technology Workshop (UCMMT)
2015 8th UK Europe China 2015 IEEE
70 Liboff RL Introductory quantum mechanics 2003 Addison-Wesley
71 Esaki L Discovery of the tunnel diode IEEE Transactions on Electron Devices
1976 23(7) p 644-647
72 Landau LD LEM Quantum Mechanics Non-relativistic Theory Pergamon 3
73 Landau LD et al Quantum Mechanics Non‐Relativistic Theory Vol 3 of
Course of Theoretical Physics 1958 AIP
222
74 Syme R Tunnelling devices as microwave mixers and detectors Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2351-2364
75 Syme R et al Tunnel diode with asymmetric spacer layers for use as
microwave detector Electronics Letters 1991 27(23) p 2192-2194
76 Brown E W Goodhue and T Sollner Fundamental oscillations up to 200 GHz
in resonant tunneling diodes and new estimates of their maximum oscillation
frequency from stationary‐state tunneling theory Journal of applied physics
1988 64(3) p 1519-1529
77 Reddy M Schottky-collector resonant tunnel diodes for sub-millimeter-wave
applications 1997 University of California Santa Barbara
78 Cox R and H Strack Ohmic contacts for GaAs devices Solid-State Electronics
1967 10(12) p 1213IN71215-1214IN81218
79 Valdes LB Resistivity measurements on germanium for transistors
Proceedings of the IRE 1954 42(2) p 420-427
80 Schroder DK Semiconductor material and device characterization 2006 John
Wiley amp Sons
81 Klootwijk J and C Timmering Merits and Limitations of Circular TLM
structures for contact resistance determination for novel 111-V HBTs Proc
fEEE 2004
82 Marlow GS and MB Das The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance Solid-State
Electronics 1982 25(2) p 91-94
83 Murrmann H and D Widmann Current crowding on metal contacts to planar
devices IEEE Transactions on Electron Devices 1969 16(12) p 1022-1024
84 Berger H Models for contacts to planar devices Solid-State Electronics 1972
15(2) p 145-158
85 Reeves G and H Harrison Obtaining the specific contact resistance from
transmission line model measurements IEEE Electron Device Letters 1982
3(5) p 111-113
86 Shur MS GaAs devices and circuits 2013 Springer Science amp Business
Media
87 Popescu D and B Odbert The Advantages Of Remote Labs In Engineering
Education Educatorrsquos Corner-Agilent Technologies-application note 2011 p
11
88 DataSheet Karl Suss- PM5 Probe System Datasheet 2013
89 Keysight IC-CAP Device Modeling Software 2016 Available from
httpwwwkeysightcomenpc-1297149ic-cap-device-modeling-software-
measurement-control-and-parameter-extractioncc=USamplc=eng
90 DataSheet Anritsu 37369A Vector Network Analyzer Datasheet 2016 Available
from httpwwwtestequipmenthqcomdatasheetsANRITSU-37397D-
Datasheetpdf
91 Packard H HP 4142B Modular DC SourceManual Operation Manual 1992
Available from httpcpliteratureagilentcomlitwebpdf04142-90010pdf
223
92 Microtech C Cascade Microtech- Wincal High Performence RF calaibration
Software (Official Website) 2016 Available from
httpswwwcascademicrotechcom
93 Singh J Electronic and optoelectronic properties of semiconductor structures
2007 Cambridge University Press
94 Whyte W Cleanroom design 1999 Wiley Online Library
95 Vieu C et al Electron beam lithography resolution limits and applications
Applied Surface Science 2000 164(1) p 111-117
96 La Fontaine B Lasers and Moorersquos law SPIE Professional October 2010 p
20
97 Madou MJ Fundamentals of microfabrication the science of miniaturization
2002 CRC press
98 Serway R Physics for Scientists and Engineers 1996 Saunders Publ
Philadelphia
99 Jalali B and S Pearton InP HBTs growth processing and applications 1995
Artech House Publishers
100 Shih YC et al Effects of interfacial microstructure on uniformity and thermal
stability of AuNiGe ohmic contact to n‐type GaAs Journal of applied physics
1987 62(2) p 582-590
101 Zawawi M Advanced In0 8Ga0 2AsAlAs Resonant Tunneling Diodes
forApplications in Integrated mm-waves MMIC Oscillators 2015
102 Zawawi MAM et al Fabrication of Submicrometer InGaAsAlAs Resonant
Tunneling Diode Using a Trilayer Soft Reflow Technique With Excellent
Scalability IEEE Transactions on Electron Devices 2014 61(7) p 2338-2342
103 Silvaco I ATLAS Users Manual Device Simulation Software 2010 Santa
Clara CA
104 Kyono C et al Dependence of apparent barrier height on barrier thickness for
perpendicular transport in AlAsGaAs single‐barrier structures grown by
molecular beam epitaxy Applied Physics Letters 1989 54(6) p 549-551
105 Yang K JR East and GI Haddad Numerical modeling of abrupt
heterojunctions using a thermionic-field emission boundary condition Solid-
State Electronics 1993 36(3) p 321-330
106 Varshni YP Temperature dependence of the energy gap in semiconductors
Physica 1967 34(1) p 149-154
107 Handbook LLM Precision DC Current Voltage and Resistance
Measurements Keithley Instruments Inc[online] 6th revision Ohio 2004
108 Lipsky SE Microwave passive direction finding 2004 SciTech Publishing
109 Howell CM and SJ Parisi Principles Applications and Selection of Receiving
Diodes MACOM Semiconductor Products Division Application note AG314
110 Schulman J D Chow and D Jang InGaAs zero bias backward diodes for
millimeter wave direct detection IEEE Electron Device Letters 2001 22(5) p
200-202
111 Zhang Z et al Sub-Micron Area Heterojunction Backward Diode Millimeter-
Wave Detectors With 018$ rm pWHz^12 $ Noise Equivalent Power IEEE
microwave and wireless components letters 2011 21(5) p 267-269
224
112 Jin N et al High sensitivity Si-based backward diodes for zero-biased square-
law detection and the effect of post-growth annealing on performance IEEE
Electron Device Letters 2005 26(8) p 575-578
113 Shashkin VI et al Millimeter-wave detectors based on antenna-coupled low-
barrier Schottky diodes International journal of infrared and millimeter waves
2007 28(11) p 945-952
114 Zhao P et al GaN Heterostructure Barrier Diodes Exploiting Polarization-
Induced $delta $-Doping IEEE Electron Device Letters 2014 35(6) p 615-
617
115 Pozar DM Microwave engineering 2009 John Wiley amp Sons
116 Koolen M J Geelen and M Versleijen An improved de-embedding technique
for on-wafer high-frequency characterization in Bipolar Circuits and
Technology Meeting 1991 Proceedings of the 1991 1991 IEEE
117 Cao M et al RF characteristics uniformity of GaAsAlAs tunnel diodes in
Infrared Millimeter and Terahertz waves (IRMMW-THz) 2016 41st
International Conference on 2016 IEEE
118 Gao J RF and microwave modeling and measurement techniques for field effect
transistors 2010 SciTec
119 Ren T et al A 340-400 GHz Zero-Biased Waveguide Detector Using an Self-
Consistent Method to Extract the Parameters of Schottky Barrier Diode Applied
Computational Electromagnetics Society Journal 2015 30(12)
120 Fobelets K et al High‐frequency capacitances in resonant interband tunneling
diodes Applied Physics Letters 1994 64(19) p 2523-2525
121 Diebold S et al Modeling and Simulation of Terahertz Resonant Tunneling
Diode-Based Circuits IEEE Transactions on Terahertz Science and Technology
2016 6(5) p 716-723
122 Yong Z et al Design of a 220 GHz frequency tripler based on EM model of
Schottky diodes JOURNAL OF INFRARED AND MILLIMETER WAVES
2014 33(4) p 405-411
123 Louhi JT and AV Raisanen On the modeling and optimization of Schottky
varactor frequency multipliers at submillimeter wavelengths IEEE transactions
on microwave theory and techniques 1995 43(4) p 922-926
124 Guo J Z Zhang and C Qian Modeling of commercial millimeter wave
Schottky diodes in Microwave and Millimeter Wave Technology (ICMMT) 2016
IEEE International Conference on 2016 IEEE
125 Schneider M Metal-semiconductor junctions as frequency converters Infrared
and Millimeter Waves 1982 6 p 209
126 Muth C et al Advanced technology microwave sounder on NPOESS and NPP
in Geoscience and Remote Sensing Symposium 2004 IGARSS04 Proceedings
2004 IEEE International 2004 IEEE
127 Putley E Thermal detectors in Optical and Infrared Detectors 1977 Springer
p 71-100
128 Martin DH Spectroscopic techniques for far infra-red submillimetre and
millimetre waves in Spectroscopic Techniques for Far Infra-red Submillimetre
and Millimetre Waves 1967
225
129 Lucas W Tangential sensitivity of a detector video system with RF
preamplification in Proceedings of the Institution of Electrical Engineers 1966
IET
130 Balocco C et al Low-frequency noise of unipolar nanorectifiers Applied
Physics Letters 2011 99(11) p 113511
131 Benford D T Hunter and TG Phillips Noise equivalent power of background
limited thermal detectors at submillimeter wavelengths International journal of
infrared and millimeter waves 1998 19(7) p 931-938
132 Papoušek D Vibration-rotational Spectroscopy and Molecular Dynamics
Advances in Quantum Chemical and Spectroscopical Studies of Molecular
Structures and Dynamics Vol 9 1997 World Scientific
133 Nyquist H Thermal agitation of electric charge in conductors Physical review
1928 32(1) p 110
134 Turner CS Johnson-Nyquist Noise url httpwww claysturner
comdspJohnson-NyquistNoise pdf(Letzter Abruf Juli 2012)
135 Voss RF 1f (flicker) noise A brief review in 33rd Annual Symposium on
Frequency Control 1979 1979 IEEE
136 McWhorter AL 1f noise and related surface effects in germanium 1955
137 Hooge FN 1ƒ noise is no surface effect Physics letters A 1969 29(3) p 139-
140
138 Van der Ziel A Noise Sources characterization measurement Prentice-Hall
Information and System Sciences Series Englewood Cliffs Prentice-Hall 1970
1970
139 Hooge F 1f noise sources IEEE Transactions on Electron Devices 1994
41(11) p 1926-1935
140 Der Ziel A Theory of shot noise in junction diodes and junction transistors
Proceedings of the IRE 1955 43(11) p 1639-1646
141 Schottky W Small-shot effect and flicker effect Physical review 1926 28(1)
p 74
142 Cowley A and H Sorensen Quantitative comparison of solid-state microwave
detectors IEEE transactions on microwave theory and techniques 1966 14(12)
p 588-602
143 Schulman J et al 1$f $ Noise of Sb-Heterostructure Diodes for Pre-Amplified
Detection IEEE microwave and wireless components letters 2007 17(5) p
355-357
144 Lynch JJ et al Passive millimeter-wave imaging module with preamplified
zero-bias detection IEEE transactions on microwave theory and techniques
2008 56(7) p 1592-1600
145 Su N et al Sb-heterostructure millimeter-wave detectors with reduced
capacitance and noise equivalent power IEEE Electron Device Letters 2008
29(6) p 536-539
146 Westlund A Self-Switching Diodes for Zero-Bias Terahertz Detection 2015
Chalmers University of Technology
147 Yajima T and L Esaki Excess noise in narrow germanium pn junctions
Journal of the physical society of Japan 1958 13(11) p 1281-1287
226
148 Sommers H Tunnel diodes as high-frequency devices Proceedings of the IRE
1959 47(7) p 1201-1206
149 Miraftab V and A Abdipour Harmonic balance analysis of a microwave
balanced power amplifier in Electrical and Computer Engineering 2001
Canadian Conference on 2001 IEEE
150 Patrashin M et al GaAsSbInAlAsInGaAs Tunnel Diodes for Millimeter Wave
Detection in 220ndash330-GHz Band IEEE Transactions on Electron Devices 2015
62(3) p 1068-1071
151 Hesler JL and TW Crowe Responsivity and noise measurements of zero-bias
Schottky diode detectors Proc ISSTT 2007 p 89-92
152 Su N et al Temperature dependence of high frequency and noise performance
of Sb-heterostructure millimeter-wave detectors IEEE Electron Device Letters
2007 28(5) p 336-339
153 Lynch J et al Unamplified direct detection sensor for passive millimeter wave
imaging in Proc of SPIE Vol 2006
154 ZHANG Z et al A physics-based tunneling model for Sb-heterostructure
backward tunnel diode millimeter-wave detectors International Journal of High
Speed Electronics and Systems 2011 20(03) p 589-596
155 Bahl IJ and P Bhartia Microwave solid state circuit design 2003 John Wiley
amp Sons
156 Yeom K-W Microwave Circuit Design A Practical Approach Using ADS
2015 Prentice Hall Press
157 Xie L et al A W-band detector with high tangential signal sensitivity and
voltage sensitivity in Microwave and Millimeter Wave Technology (ICMMT)
2010 International Conference on 2010 IEEE
158 Fay P et al High-performance antimonide-based heterostructure backward
diodes for millimeter-wave detection IEEE Electron Device Letters 2002
23(10) p 585-587
159 Hrobak M et al Planar zero bias Schottky diode detector operating in the E-
and W-band in Microwave Conference (EuMC) 2013 European 2013 IEEE
160 Maas SA Nonlinear microwave and RF circuits 2003 Artech House
161 Appleby R and RN Anderton Millimeter-wave and submillimeter-wave
imaging for security and surveillance Proceedings of the Ieee 2007 95(8) p
1683-1690
162 Crowe TW et al Opening the terahertz window with integrated diode circuits
IEEE Journal of Solid-State Circuits 2005 40(10) p 2104-2110
163 Raisanen AV Frequency multipliers for millimeter and submillimeter
wavelengths Proceedings of the Ieee 1992 80(11) p 1842-1852
164 Erickson NR Diode frequency multipliers for terahertz local-oscillator
applications in Astronomical Telescopes amp Instrumentation 1998 International
Society for Optics and Photonics
165 Mehdi I et al Terahertz local oscillator sources performance and capabilities
in Astronomical Telescopes and Instrumentation 2003 International Society for
Optics and Photonics
166 Tonouchi M Cutting-edge terahertz technology Nature photonics 2007 1(2)
p 97-105
227
167 Nilsen SM et al Single barrier varactors for submillimeter wave power
generation IEEE transactions on microwave theory and techniques 1993 41(4)
p 572-580
168 Xiao Q et al A 270-GHz tuner-less heterostructure barrier varactor frequency
tripler IEEE microwave and wireless components letters 2007 17(4) p 241-
243
169 David T et al Monolithic integrated circuits incorporating InP-based
heterostructure barrier varactors IEEE microwave and wireless components
letters 2002 12(8) p 281-283
170 Lieneweg U B Hancock and J Maserjian Barrier-intrinsic-N+(BIN) diodes
for near-millimeter wave generation in Conference Digest for the Twelft
International Conference on Infrared and Millimeter Waves 1987
171 Lieneweg U et al Modeling of planar varactor frequency multiplier devices
with blocking barriers IEEE transactions on microwave theory and techniques
1992 40(5) p 839-845
172 Chattopadhyay G et al An all-solid-state broad-band frequency multiplier
chain at 1500 GHz IEEE transactions on microwave theory and techniques
2004 52(5) p 1538-1547
173 Maestrini A et al A 17-19 THz local oscillator source IEEE microwave and
wireless components letters 2004 14(6) p 253-255
174 Faber MT J Chramiec and ME Adamski Microwave and millimeter-wave
diode frequency multipliers 1995 Artech House Publishers
175 Frerking MA and JR East Novel heterojunction varactors Proceedings of the
Ieee 1992 80(11) p 1853-1860
176 Penfield P and RP Rafuse Varactor applications 1962
177 Palazzi V et al Low-power frequency doubler in cellulose-based materials for
harmonic RFID applications IEEE microwave and wireless components letters
2014 24(12) p 896-898
178 Presas SM Microwave frequency doubler integrated with miniaturized planar
antennas 2008
228
APPENDICES
Appendix I Doped substrate process details
Mask Stage Process Stage Process step Process detail Equipment
Mask 1 (Mesa
Etch)
Sample clean NMP 10 min 80˚C Beaker
Acetone 5 min Beaker
Isopropanol (IPA) 5 min Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist S1805 - Program 4 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
1 min 09mW iline
(Compensation error set to 1)
MA4 Mask
aligner
Develop MIF 319 for 1 min Beaker
Post Exposure
Bake Oven or Bake 120C for 15
minutes Hotplate
Etch Etch Cal Cal Sample - etch for 2 minutes Beaker
Etch
H3PO4H2O2H2O 3150
time is determined by the etch cal Beaker
Resist Strip Acetone - 5 min and IPA - 5 min Beaker
Mask2 (Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3 Beaker
Acetone ultrasonic for 5 Min Power 3 Beaker
Isopropanol (IPA) ultrasonic for 5 Min Power 3 Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist AznLoF - 2um grade - Program 6 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
55 seconds 09mW i-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 326 for 1 mins Beaker
Clean O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
Surface De-oxide HCLH2O 11 40 sec Beaker
Metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Anneal 420˚C 2min Furnace
229
TLM
Measurement ICCAP
Measurement
Bench
Mask 3
(BottomBacks
ide Contact)
Sample clean Acetone Optional Beaker
Isopropanol (IPA) Optional Beaker
Apply Resist Prebake
Bake for 5mins 150C to dry
the sample Hotplate
Resist (top side) S1813 - Program 6 Laurell Spinner
Soft bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Exposure
10 seconds 09mW I-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 319 for 2 mins Beaker
De-scum O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
De-oxidise
Surface De-oxide
HCLH2O 11 40
sec Beaker
metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Clean Water 3min Beaker
TLM
Measurement ICCAP
230
Appendix II Four Mask step Process Flow
Mask Stage Process Stage Process step Process detail
Mask1 Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3
Acetone ultrasonic for 5 Min Power 3
Isopropanol (IPA) ultrasonic for 5 Min Power 3
Apply Resist Prebake Bake for 5mins 150C
1st Resist AznLoF - 2um grade - Program 6
Hot Plate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 55 seconds 09mW iline (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 1 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
Mask 2 (Mesa
Etch)
Sample clean NMP Optional
Acetone Optional
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C
1st Resist S1805 - Program 4
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 1 min 09mW i-line (Compensation error set
to 1)
Develop MIF 319 for 1 min
Post Exposure Bake Oven or Bake 120C for 15 minutes
Etch Etch Cal Cal Sample - etch for 2 minutes
Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Measure TLM
Resist Strip Acetone - 5 min and IPA - 5 min
Mask 3(Isolation) Sample clean Acetone Optional
Isopropanol (IPA) Optional
231
Apply Resist Prebake Bake for 5mins 150C
Resist S1828 - Program 4
Hot Plate 115C for 1 mins
Photolithography Mask Align mask to wafer
Expose 9 mins 09mW iline (Compensation error set
to 1)
Develop MF 319 3 mins
Post Bake Oven Bake 120C for 15mins
Etch Etch Cal Refer to Etch Cal instr tab
Sub-collector Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Resist Strip Acetone 5mins + IPA 5 mins in ultrasonic bath
power 1
inspection Microscope
Sample clean Acetone Optional
Mask 4 (Bottom
Contact)
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C 1st
Resist AznLoF - 2um grade - Program 6
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 10 seconds 09mW i-line (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 2 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide
HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
232
Appendix III Epitaxial Layer XMBE277
TABLE I The epitaxial structure for sample XMBE277
Layer Thickness (nm) Doping Concentration (cm-3)
n+- In053Ga047As 45 200 x 1019
n- In053Ga047As 25 300 x 1018
In053Ga047As 20 undoped
AlAs 13 undoped
In08Ga02As 45 undoped
AlAs 13 undoped
In053Ga047As 20 undoped
n- In053Ga047As 25 300 x 1018
n+- In053Ga047As 400 100 x 1019
Semi-insulating InP
233
Appendix IV SilVaco (Atlas) Simulation Code
go atlas
---------------------------------------------------------
Structure parameter definition (Constants) values in um
---------------------------------------------------------
Thicknesses
set t_contact1=0
set t_ohmic1=03
set t_emitter=004
set t_spacer1=0005
set t_barrier=000283
set t_spacer2=02
set t_collector=004
set t_ohmic2=045
Doping concentrations
set d_ohmic1=4e18
set d_emitter=2e17
set d_collector=2e17
set d_ohmic2=4e18
set d_gap=2
set d_mesa=4
set d_device=10
set d_etch=008
Layers
set I=$t_contact1
set A=$I+$t_ohmic1
set B=$A+$t_emitter
set C=$B+$t_spacer1
set D=$C+$t_barrier
set E=$D+$t_spacer2
set F=$E+$t_collector
set G=$F+$t_ohmic2
-------------------------------------
Mesh generator
-------------------------------------
mesh diagflip width=45
xmesh location=0 s=1
xmesh location=1 s=1
xmesh location=2 s=1
xmesh location=4 s=1
xmesh location=5 s=1
xmesh location=6 s=1
xmesh location=7 s=1
xmesh location=8 s=1
xmesh location=$d_mesa s=1
xmesh location=$d_mesa+$d_gap s=1
xmesh location=$d_device s=1
Ohmic1
ymesh l=0000 s=005
ymesh l=$I s=005
234
ymesh l=$A s=0005
ymesh l=$B s=0005
ymesh l=$C s=00005
ymesh l=$D s=00005
ymesh l=$E s=0009
ymesh l=$F s=0005
ymesh l=$G s=0005
-----------------------------------
SECTION 2 Regions Structure definition
-----------------------------------
region num=1 name=contact1 material=Gold ymin=0 ymax=$I
region num=2 name=ohmic1 material=GaAs ymin=$I ymax=$A
region num=3 name=emitter material=GaAs ymin=$A ymax=$B
region num=4 name=spacer1 material=GaAs ymin=$B ymax=$C
region num=5 name=barrier material=AlAs ymin=$C ymax=$D xmin=0 xmax=$d_mesa
calcstrain qtregion=1
region num=6 name=spacer2 material=GaAs ymin=$D ymax=$E
region num=7 name=collector material=GaAs ymin=$E ymax=$F
region num=8 name=ohmic2 material=GaAs ymin=$F ymax=$G
region num=9
name=etch material=Air ymin=0 ymax=$F+$d_etch xmin=$d_mesa xmax=$d
_device
---------------------------------
Electrodes
---------------------------------
electrode num=1 name=anode xmin=0 xmax=$d_mesa ymin=0 ymax
=$I material=Gold
electrode num=2 name=cathode xmin=$d_mesa+$d_gap xmax=$d_device ymin=$F+
$d_etch ymax=$F+$d_etch material=Gold
--------------------------------
Doping
--------------------------------
doping uniform ntype conc=$d_ohmic1 Region=2 ymin=$I ymax=$A
doping uniform ntype conc=$d_emitter Region=3 ymin=$A ymax=$B
doping uniform ntype conc=$d_collector Region=7 ymin=$E ymax=$F
doping uniform ntype conc=$d_ohmic2 Region=8 ymin=$F ymax=$G
--------------------------
Contacts
--------------------------
interface sc region=1
interface ss region=2
interface ss region=3
interface si region=4
interface si region=5
interface ss region=6
interface ss region=7
interface sc ymin=$F ymax=$F xmin=$d_mesa+$d_gap xmax=$d_device
interface tunnel region=5 dytunnel=0001
contact name=cathode
contact name=anode
235
------------------------------------------
SECTION 3 Material amp Models Definitions
------------------------------------------
material material=AlAs
permittivity=10 eg300=28 mc=004 affinity=305 nc300=4e19 nimin=1e1
material material=GaAs permittivity=139 eg300=14 mc=0067
affinity=407 nc300=09e17 nimin=1e6
BAND DIAGRAM
output tquantum bandparam qfn qfp valband conband charge polarcharge flowlines
STRUCTURE GRAPHIC
solve init
save outf=XMBE304+real2str
tonyplot XMBE304+real2str
------------------------------------------
SECTION 4 ANALYSIS
------------------------------------------
trap acceptor structure=top elevel=03 density=48e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$A ymax=$C xmin=0 xmax=$d_mesa
trap acceptor structure=BOTTOM elevel=035 density=47e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$E ymax=$F xmin=0 xmax=$d_mesa
models sisel sisnlderivs qtregion=1 print
method climit=1e-4 itlimit=50 maxtraps=20
DC ANALYSIS
log outf=XMBE304log
solve init
solve vanode=0 name=anode vstep=001 vfinal=15
save outf=XMBE304str
log off
tonyplot XMBE304str
tonyplot XMBE304log
2
LIST OF CONTENTS
LIST OF CONTENTS 2
LIST OF TABLES 6
LIST OF FIGURES 8
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS 13
PUBLICATIONS 13
CONFERENCE PRESENTATIONS 14
ABSTRACT 15
DECLARATION AND COPYRIGHT STATEMENT 16
ACKNOWLEDGEMENTS 17
DEDICATION 18
1 INTRODUCTION 19
11 Background 19
12 Aims and objectives 26
13 Outline of this Thesis 27
2 LITERATURE REVIEW 29
21 Introduction 29
22 Historical review of III-V Compound Semiconductor for RF applications 30
23 The Concept of Heterostructures 33
231 Homojunctions Heterojunctions and Band Discontinuities 34
232 Lattice-Matched and Pseudomorphic Materials 36
233 Quantum well and 2DEG 41
24 Metal-Semiconductor Contact 42
241 Schottky Contact 43
242 Ohmic Contact 46
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work 48
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics 50
261 Principle of Quantum Tunneling 51
262 ASPAT Structural Parameters of GaAsAlAs materials System 55
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure)
used in this study 55
3
263 ASPAT Electrical Parameters 61
27 Characterization of Ohmic Contacts 68
271 Transmission Line Measurement (TLM) 69
28 Basic Characterization Techniques and procedures 72
281 Measuring tools and apparatuses 72
282 Measurement steps using a VNA 75
283 Measurement Practice and Flowchart 76
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES 79
31 Introduction 79
32 Epitaxial Layer Growth Techniques 80
321 Molecular Beam Epitaxy (MBE) 80
33 Basic Principles of Common Fabrication techniques 81
331 Sample cleaning 81
332 Photolithography 82
333 Etching Process 86
334 Sputtering (dielectric deposition) 88
335 Metallization Process Lift-off and Annealing 88
34 GaAsAlAs ASPAT Process Optimization 92
341 ASPAT Devices used in Fabrication 93
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability 95
343 Fabrication process of GaAsAlAs ASPAT diode toward High
frequency Applications 117
35 Conclusions 125
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT DIODE USING
SILVACO 126
41 Introduction 126
42 SILVACO modelling Tools 127
43 SILVACO Implementation GaAs AlAs ASPAT Modelling 130
44 Simulation Result and Analysis 132
45 Structure Analysis of ASPAT Diode 135
451 Dependencies of current on AlAs Barrier thickness 135
452 Dependence of current on Spacer I length l1 137
4
453 Dependence of current on Spacer II length l2 138
46 Temperature Dependent Simulation 140
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes 142
48 Conclusions 147
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES 148
51 Introduction 148
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes 149
53 RF Test Fixture Theory and Experiment 153
531 On-Wafer Measurement and Small Signal One-Port Characterizations
154
54 Device Calibration 155
541 Open and Short De-Embedding Technique 155
55 S-Parameter Measurement Result and Analysis 157
551 Diode to diode uniformity 158
552 Wafer to wafer uniformity 160
553 Small devices RF measurements 161
56 Extracting RF models of ASPAT at Zero Bias Voltage 164
561 Extraction of ASPAT parasitic element 165
562 Extraction of ASPAT intrinsic elements 168
563 Capacitances -Voltage (C-V) Extraction 172
57 Conclusions 173
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR DESIGN USING
ADS 175
61 Introduction 175
62 Detection Theory 176
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis 179
64 Noise Consideration in a Detector diode 182
65 Modelling of a 100GHz Zero-biased ASPAT Detector 184
66 Conclusions 199
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING GAASALAS
ASPAT DIODES 201
71 Introduction 201
5
72 Motivation and Background 202
73 Frequency Multiplier Architecture the Basics 203
731 Types of frequency multipliers 205
74 Parameters of interest for Frequency Multipliers 206
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler 208
76 Conclusions 214
8 CONCLUSION AND FUTURE WORK 215
81 Conclusion 215
82 Future Work 217
REFERENCES 218
APPENDICES 228
Word count including footnotes and endnotes 61500(approximately)
6
LIST OF TABLES
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials
structure grown on GaAs Substrates by MBE 23
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314
grown on a GaAs substrate by MBE 24
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP
substrate 24
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary
compound semiconductors a room temperature [41 42] 38
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work 56
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and
Ammonia on GaAs and InGaAs materials 87
Table 32 Epitaxial layer of Doped substrate samples 93
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm 94
Table 34 Generic fabrication steps established by Dr Md Adzhar [101] 97
Table 35 Standard process flow for Air-Bridge design fabrication 101
Table 36 Standard fabrication process flow for Dielectric-Bridge design 107
Table 37 New arrangement of the mask number and step in Second Run 110
Table 38 New arrangement for the Third run using Dielectric-Bridge mask 113
Table 39 The outcome of the spreading resistance before and after using LOR
technique 115
Table 310 DC and RF characteristics for XMBE304 118
Table 311 3rd
Gen Mask process step 119
Table 312 Standard deviation at two different voltages 124
Table 41 The parameter values used in this simulation 134
Table 42 The calculated values of bandgap at different temperatures 140
Table 43 The calculated effective masses for each temperature used in this simulation
141
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104) 145
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics
in this work 153
Table 52 Device to device uniformity check for large ASPAT diode 159
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at
four different frequencies[117] 159
7
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B 161
Table 55 Comparison between calculated (fully Depleted) and extracted (different
biases) values from equivalent circuit parameters for different ASPAT mesa sizes at zero
bias voltage 170
Table 61 A summary of all the important parameters of the 4x4 microm2 diode 185
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode 190
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector 198
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero
bias detector at W-band (75GHz-110GHz) 199
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art
multiplier diode 213
8
LIST OF FIGURES
Figure 21 III-V compound semiconductors mobility and band gap[24] 31 Figure 22 illustration of Homojunctions band structure material before (left) and after
(right) equilibrium 34 Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium 35
Figure 24 Lattice Matching for both materials when aL=aS 37 Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40] 37 Figure 26 Lattice mismatched material 39
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and
(b) tensile strain [1] 40 Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg
GaAs (a) Structure (b) energy band diagram and (c) Conduction band diagram when
AlGaAs is n-doped[43] 41 Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact 43
Figure 210 Energy band diagram of Schottky contact on n-type material under (a)
reverse and (b) forward bias 45 Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping
concentration ND (a) Low (b) Intermediate and (c) high 47 Figure 212 Classical view of whether an electron is can surmount a barrier or not
Quantum mechanical view allows an electron to tunnel through a barrier The probability
(blue) is related to the barrier thickness 51
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave
function[70] 52
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in
this study 55 Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27] 57
Figure 216 Conduction band diagram showing band bending and 2DEG formation at
the L1 spacer 60 Figure 217 I-V characteristics of a fabricated ASPAT diode 63 Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
63 Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b
and h are not drawn to scale 65 Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304)
The dimensions are not drawn to scale 67 Figure 221 A simple TLM structure with effective length and sheet resistance
underneath 69 Figure 222 Top view of TLM ladder structure use in this work 71 Figure 223 Typical plot of resistance versus TLM spacing 71
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM 73
9
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
75 Figure 226 Actual VNA system that was used for RF characterization 75 Figure 227 Block diagram of the ASPAT measurement step 77
Figure 31 3D illustration of Optical lithography process used in this research 85 Figure 32 Actual picture of thermal evaporator used in this study 89 Figure 33 Single layer lift-off process using negative photoresist 91 Figure 34 Current-Voltage characteristic of sample XMBE368 used in this study at
two different locations on the wafer tile 96
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2
diode dimensions designed in the 1st Gen Mask 96
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates 100 Figure 37 The layout of 1
st design of Dielectric Bridge (green circle) mask design for
100 times 100microm2 emitter size with option for doped substrate processing 100
Figure 38 Dry Etching for the first run in this study 102 Figure 39 Severe undercut of 2times2 microm
2 and 6times6 microm
2 devices 103
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet
etched 104 Figure 311 SEM Images of the GaAs sample 104
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in
this study 105
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
105
Figure 314 SEM images for InP and InGaAs taken from [56] 105 Figure 315 Short circuit behaviour on one of the fabricated device in this run 106
Figure 316 The surface of the sample after final processing 108 Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2
2500 microm2 900 microm2 400 microm2 225 microm2 100 microm2 and 36 microm2 109
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm
Tolerance 110
Figure 319 After lift-off processing 111 Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
112
Figure 321 side view of lateral ASPAT structure 113
Figure 322 The measured size of the emitter area and the length D (blue color marked)
114 Figure 323 Summary of LOR technique steps 115 Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
116
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and
alignment mark structures used in this study 118 Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-
insulating substrate device type used in this study 121 Figure 327 Example finished process device with bond pad using 3
rd Gen mask 121
Figure 328 XMBE304 TLM measurement for the top contact after annealing 122
10
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing 122 Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 4times4microm2 mesa size 123
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 6times6microm2 mesa size 124
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 10times10microm2 mesa size 124
Figure 41 SILVACO Atlas simulation process flow 128 Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the
diode multilayer heterostructures on the right 131 Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor 131 Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure
(b) the energy band diagram of the ASPAT diode structure when under three different
biases 132 Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm
2) and
(4times4microm2) using SILVACO Atlas simulator for structure device XMBE304 showing
excellent agreement between simulated and experimental data 134
Figure 46 IV characteristics of the dependencies of current on AlAs barrier 136 Figure 47 Example of analysis at -1 and 1V to the current 136 Figure 48 I-V characteristic of the dependencies current to Spacer I layer 137
Figure 49 Current changes with layer thickness l1 138 Figure 410 IV characteristic of the dependencies current to Spacer 1 layer 139
Figure 411Current change with layer thickness l2 139
Figure 412 Measurement and simulation comparison result as a function of temperature
range from 100K to 398K 142 Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample
XMBE304 143
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT
Diode [3] 144
Figure 415 Log Current vs voltage as a function of temperature for SBD sample
XMBE104 145
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and
SBD 146
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2
6x6um2 and 10x10um
2 Note the good scalability 149
Figure 52 Junction resistance versus voltage 151
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT
high sensitivity near zero bias detection 152
Figure 54 One port S-parameter measurements 155
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use
for RF calibration and measurements (Note Images are not to scale) 156
11
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices
from 15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check 158
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero
bias 158
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B)
to qualify the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2
device sizes (Real and Imaginary) Note blue colour is XMBE304A and red colour is
XMBE304B 160
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and
4times4microm2
(Real and Imaginary) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm
2 diodes respectively 162
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and
4times4 microm2 (Smith Chart) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm2 diodes respectively 162
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding
equivalent circuit model 164
Figure 512 The S-parameter Touchstone file is used to read the measured files 165
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure 166
Figure 514 Equivalent circuit model for short de-embedded structure 166
Figure 515 Smith chart representative S-parameter measurement for short (left) and
open (right) CPW The blue lines represent simulated data and the red is measured data
167
Figure 516 Equivalent circuit of the ASPAT diode 169
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 (Real and Imaginary) results for various small device designs 169
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 results (Smith Chart) for various small device designs 170
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled
capacitance vs Voltage) 172
Figure 61 Block diagram represent a complete direct receiver system 177
Figure 62 The detection process of a single wave through a non-linear IV characteristic
of a diode 177
Figure 63 Lumped element illustration of microwave detector circuit 178
Figure 64 The mixing process where the signals are processed by the non-linear I-V
characteristic to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and
fRF are applied to the diode 179
Figure 65 Measurement of Tangential Sensitivity[108 129] 181
12
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted
from MATLAB to realize a virtual GaAsAlAs ASPAT diode 186
Figure 67 Verification of actual (blue measured) and virtual (red_10th order
polynomial) I-V characteristic of the 4times4 microm2 diode used in this study 186
Figure 68 Direct detector circuit topology using an ASPAT diode 187
Figure 69 Output voltage and detector sensitivity over wide range of input power 188
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load
resistance of the ASPAT detector 189
Figure 611 Junction resistance as a function of forward voltage 189
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size
of 4times4μm2 191
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power 192
Figure 614 Reflection Coefficient versus operating frequency without matching
circuitry 193
Figure 615 Detector circuit with impedance matching circuit placed in between diode
and source 194
Figure 616 Reflection Coefficient over wide frequency band with matching 195
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band
frequency 195
Figure 618 Lowest detectable signal at 100GHz operating frequency 196
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of
diode operation 197
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained
from the fabricated ASPAT in this work 198
Figure 71 performance of state-of the-art millimetre wave source [166] 202
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
204
Figure 73 Principle of operation for frequency multiplier utilising a non-linear
resistance [10] 204
Figure 74 A standard system for two port frequency multiplier circuit 207
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode 209
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool 210
Figure 77 Conversion loss and conversion efficiency as a function of input power 211
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
212
13
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS
PUBLICATIONS
1 MRR Abdullah Y K Wang J Sexton M Missous and M J Kelly ldquoGaAsAlAs
Tunnelling Structure Temperature Dependence of ASPAT Detectorsrdquo 8th UK-Europe-
China Workshop on mm-waves and THz Technologies 2015 Cardiff University IEEE
proceedings DOI 101109UCMMT20157460591
2 Yuekun Wang Mohd Rashid Redza Abdullah James Sexton and M Missous
ldquoInGaAs-AlAs asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo 8th
UK-Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings DOI 101109UCMMT20157460589
3 K N Zainul Ariffin S G Muttlak M Abdullah M R R Abdullah Y Wang and M
Missous ldquoAsymmetric Spacer Layer Tunnel In018Ga082AsAlAs (ASPAT) Diode using
Double Quantum Wells for Dual Functions Detection and Oscillationrdquo 8th UK-
Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings Doi 101109UCMMT20157460599
4 K N Zainul Ariffin M R R Abdullah Y K Wang S G Muttlak O S
Abdulwahid J Sexton MJ Kelly and M Missous ldquoAsymmetric Spacer Layer Tunnel
Diode (ASPAT) Quantum Structure Design Linked to Current-Voltage Characteristics
A Physical Simulation Studyrdquo UK-China Millimetre Waves and Terahertz Technology
Workshop September 2017 Submitted 14 July 2017 Conference held on 11th -13th
September 2017 DOI 101109UCMMT20178068358
5 K N Zainul Ariffin Y Wang M R R Abdullah S G Muttlak Omar S
Abdulwahid J Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoInvestigations of
Asymmetric Spacer Tunnel Layer (ASPAT) Diode for High-Frequency Applicationsrdquo
DOI 101109TED20172777803
6 Omar S Abdulwahid S G Muttlak M R R Abdullah K N Zainul Ariffin J
Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoA 100GHz Zero-Biased
Quantum Tunnelling ASPAT Detectorrdquo Submitted to IEEE TED on DEC 2016 under
correctionamendment Pending fabrication data
14
CONFERENCE PRESENTATIONS
1 Mohd Rashid Redza Abdullah J Sexton Kawa Ian MJKelly and M Missousldquo
G2040GHz Frequency Doubler Varistor Mode using ASPAT diodesrdquo UK
Semiconductors 2017 2017 University of Sheffield Oral presentation
2 M R R Abdullah YueKun Wang J Sexton Kawa Ian and M Missousldquo
Microwave Performance of GaAsAlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diodesrdquo UK Semiconductors 2016 2016 University of Sheffield Oral presentation
3 M R R Abdullah J Sexton and M Missousldquo GaAsAlAs Tunnelling Structures
THz RTD oscillators and ASPAT detectorsrdquo UK Semiconductors 2015 2015
University of Sheffield Oral presentation
4 Yuekun Wang Mohd Rashid Redza Abdullah and M MissousldquoInGaAs-AlAs
asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo UK
Semiconductors 2015 2015 University of Sheffield Oral presentation
5 Mohd Rashid Redza Abdullah and M Missousldquo GaAsAlAs Tunnelling
Structure Temperature Dependence of ASPAT Detectorsrdquo PGR Conference2016
2016 University of Manchester Poster presentation
6 YueKun Wang KNZainul Ariffin Mohd Rashid Redza Abdullah J Sexton
Kawa Ian and M Missous ldquoPhysical Modelling and Experimental Studies of
InGaAsAlAs Asymmetric spacer Layer Tunnel Diodesrdquo UK Semiconductors 2016
2016 University of Sheffield Oral presentation
7 K N Zainul Ariffin S G Muttlak M R R Abdullah Y Wang Omar S
Abdulwahid M Missous ldquoExperimental and Physical Modelling of Temperature
Dependence of a Double Quantum Well In018Ga082AsAlAs ASPAT Dioderdquo UK
Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral Presentation
8 Omar S Abdulwahid Mohd Rashid Redza Abdullah S G Muttlak K N Zainul
Ariffin Mohamed Missous ldquoTunnelling Barrier Diode for Millimetre Wave
Mixingrdquo UK Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral
Presentation
9 M Abdullah K N Zainul Ariffin MRR Abdullah J Sexton M Missous and
MJ Kelly ldquoA Novel In18Ga82As-AlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diode with Double Quantum Wells for Microwave Detectionrdquo UK Semiconductor
Conference 2015 Sheffield 1 ndash 2 July 2015 Oral Presentation
15
ABSTRACT
Thesis Title GaAsAlAs ASPAT Diodes for Millimetre and Sub-Millimetre Wave
Applications
Institute School of Electrical and Electronic Engineering the University of Manchester
Candidate Mohd Rashid Redza bin Abdullah
Degree Doctor of Philosophy (PhD)
Date 3 October 2017
The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in
the early 90s as an alternative to the Schottky barrier diode (SBD) technology for
microwave detector applications due to its highly stable temperature characteristics The
ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a
thin barrier which enables RF detection at zero bias from microwaves up to
submillimetre wave frequencies In this work two heavily doped GaAs contact layer on
top and bottom layers adjacent to lightly doped GaAs intermediate layers enclose
undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that
acts as a tunnel barrier The ultimate ambition of this work was to develop a MMIC
detector as well as a frequency source based on optimized ASPAT diodes for millimetre
wave (100GHz) applications The effect of material parameter and dimensions on the
ASPAT source performances was described using an empirical model for the first time
Since this is a new device keys challenges in this work were to improve DC and
RF characteristic as well as to develop a repeatable reproducible and ultimately
manufacturable fabrication process flow This was investigated using two approaches
namely air-bridge and dielectric-bridge fabrication process flows Through this work it
was found that the GaAsAlAs heterostructures ASPAT diode are more amenable to the
dielectric-bridge technique as large-scale fabrication of mesa area up to 4times4microm2 with
device yields exceeding 80 routinely produced The fabrication of the ASPAT using i-
line optical lithography which has the capability to reduce emitter area to 4times4microm2 to
lower down the device capacitance for millimetre wave application has been made
feasible in this work The former challenge was extensively studied through materials
and structural characterisations by a SILVACO physical modelling and confirmed by
comparison with experimental data The I-V characteristic of the fabricated ASPAT
demonstrated outstanding scalability demonstrating robust processing A fair
comparison has been made between ASPAT and SBD fabricated in-house indicating
ASPAT is extremely stable to the temperature The RF characterisations were carried out
with the aid of Keysight ADS software
The DC characteristic from fabricated GaAsAlAs ASPAT diodes were absorbed
into an ADS simulation tool and utilized to demonstrate the performance of MMIC
100GHz detector as well as 20GHz40GHz signal generators Zero bias ASPAT with
mesa area of 4times4microm2 with video resistance of 90KΩ junction capacitance of 23fF and
curvature coefficient of 23V-1
has demonstrated detector voltage sensitivity above
2000VW while the signal source conversion loss and conversion efficiency are 28dB
and 03 respectively An estimate noise equivalent power (NEP) for this particular
device is 188pWHz12
16
DECLARATION AND COPYRIGHT STATEMENT
No portion of the work referred to in the dissertation has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning
COPYRIGHT STATEMENT
i The author of this thesis (including any appendices andor schedules to this thesis) owns
certain copyright or related rights in it (the ldquoCopyrightrdquo) and he has given The University of
Manchester certain rights to use such Copyright including for administrative purposes
ii Copies of this thesis either in full or in extracts and whether in hard or electronic copy
may be made only in accordance with the Copyright Designs and Patents Act 1988 (as
amended) and regulations issued under it or where appropriate in accordance with licensing
agreements which the University has from time to time This page must form part of any
such copies made
iii The ownership of certain Copyright patents designs trademarks and other intellectual
property (the ldquoIntellectual Propertyrdquo) and any reproductions of copyright works in the thesis
for example graphs and tables (ldquoReproductionsrdquo) which may be described in this thesis
may not be owned by the author and may be owned by third parties Such Intellectual
Property and Reproductions cannot and must not be made available for use without the prior
written permission of the owner(s) of the relevant Intellectual Property andor
Reproductions
iv Further information on the conditions under which disclosure publication and
commercialisation of this thesis the Copyright and any Intellectual Property andor
Reproductions described in it may take place is available in the University IP Policy
(httpdocumentsmanchesteracukDocuInfoaspxDocID=487) in any relevant Thesis
restriction declarations deposited in the University Library The University Libraryrsquos
regulations (httpwwwmanchesteracuklibraryaboutusregulations) and in The
Universityrsquos policy on Presentation of Theses
17
ACKNOWLEDGEMENTS
First and foremost all gratefulness and praise is to Allah swt for everything in my
life He is the one and the only one who granted me knowledge health patience and
ability to complete this thesis as well as colouring the whole journey of my PhD
I give my deepest and sincere gratitude to my PhD supervisor Professor Mohamed
Missous for his time support patience and guidance throughout the journey of this PhD
studies His encouragements valuable advice precious ideas and a wealth of knowledge
amp experiences have had a direct inspiration on this research Special thanks also to our
experimental officer Dr James Sexton for not only sharing his knowledge advice and
semiconductor fabrication skills but also his effort in maintaining our clean room
facilities to a great level My gratitude also extends to Mr Mallachi McGowan for his
help and assist in the lab-related issue
I am also obligated to Prof MJ Kelly from University of Cambridge and Dr Kawa
Ian from ICS limited for their measurement of the ASPAT samples on realizing the RF
characteristics This collaboration effort can hopefully last longer in designing and
implementing the ASPAT MMIC detectors
My deepest appreciation also goes to my PhD colleagues Khairul Nabilah Saad
GMuttlak Omar AbdulWahid and Yuekun Wang for their support as well as working
together with me to realize this exciting project directly and indirectly A sincere
thankfulness similarly to my seniors Dr Md Adzhar Zawawi and Dr Fauzi Packeer for
their support during the first and second year of my research For other friends and staff
members under Prof Missous and Dr M Migliorato I will always remember the strong
bond and friendship we made
I am really fortunate that I been blessed with my motherrsquos care who always make doarsquo
for my success every day during my studies As for my beloved wife Dr Nik Maryam
Anisah Nik Mursquotasim who had always encouraged me supported me and gave me
patience through all the hardship in this journey thank you very much
Finally I also would like to thank and acknowledge my sponsor Majlis Amanah
Rakyat (MARA) for financially supporting me during this studies I am greatly indebted
with your kind support which was vital to my study
18
DEDICATION
This thesis dedicated to
My respected and beloved parentshellip
My loving wife dearest siblings and in-lawshellip
19
1 INTRODUCTION
11 Background
It is an undeniable fact that semiconductors have changed the world much further
than anything people could have predicted in the last 60 or 70 years ie after the lsquocats
whisker and vacuum tube eras This field of research has been expanding from year to
year starting from the discovery of the first semiconductor (silver sulfide) in 1833 by
Michael Faraday [1 2] and it still remains very active to the present Semiconductors
have a large range of applications and are not just limited to use in communications they
can be found everywhere in other applications from Earth to space The widespread
usage and sheer number of applications have led to it growing very quickly and
contributing greatly to the growth of World Economics Over time the successful
development of semiconductor growth techniques such as Molecular Beam Epitaxy
(MBE) has enabled researchers to tailor and precisely control the semiconductor
material for new electronic devices with extra functionalities This has led to the
development of advanced devices such as high electron mobility transistors (HEMTs)
and Heterojunction bipolar transistors (HBTs) for use in wireless communication
technology Given this development today electronic devices such as computers
handheld smartphone tablets etc are no longer perceived as luxury and attractive items
but rather have become crucial in everyday life Such devices provide the means to allow
for people to remain connected to each other via the sending and receiving of
information electronically The huge demand for such types of devices has resulted in
competition in both the electronic market and technologies which only goes on to
advance the semiconductor industry
Nowadays the demand for electronic devices characterised by high speed high
efficiency ultra-low power and low manufacturing cost has increased exponentially To
fulfil this growth in demand high data rate systems are required in other words the
system must work at a higher frequency for both the transmitter and receiver The
frequency of interest for advanced wireless communication is in the Millimetre and sub-
20
millimetre wave region which is around 30-300GHz and 300 - 3000GHz respectively
The second frequency region is also sometime known as the terahertz (THz)
electromagnetic region This band lies between the microwave and infrared frequency
bands From the first time it was revealed in the late 80s[3-5] the THz region has gained
a lot of international attention due to its unique properties and since then the motivation
to develop these devices has increased significantly To date the THz frequencies region
has shown its ability to fulfil various applications such as high-resolution imaging in
medical security and surveillance field atmospheric monitoring and environment radio
astronomy as well as compact range radars[3] to name a few
However despite these developments not much effort has been made in exploring
alternative compact THz devices As a result electronic THz devices are still in the state
of immaturity as compared to microwave and photonics devices This is due to their high
cost and absence of compact amp solid-state THz sources (oscillators) and receivers
(detectors) that are capable of operating at both room and extreme temperatures[6 7] A
great deal of work still continues to fill up the lsquoTHz gaprsquo (between 300GHz and 3THz)
used for the most important part of a communication system namely the front-end
receiver or first stage Such a system is responsible for receiving detecting and
processing the received signal to be translated into useful information Furthermore THz
receivers systems still require the best-integrated components such as source mixer and
detector to reach their complete competencies[8] The detector which remains the
critical part of the receiver system requires devices or components that are able to fulfil
the THz gap requirement Studies conducted over a number of years have found out that
the key element in improving THz detection relies upon the use of passive devices ie
diodes Based on these findings many types of diode ie tunnelling diode point-contact
diode and Schottky barrier diode (SBD) have been proposed for detection applications
Amongst microwave and millimetre wave detector diode devices the Schottky
Barrier Diode (SBD) is the dominant detector that has been used since the 1940s[9] The
reason for this dominance is the ease of fabrication of a SBD (by either a point-contact
or evaporated semiconductor-metal structure) and its ability to produce a non-linear
current-voltage (I-V) characteristic which is necessary for rectifyingdetecting diodes [9
10] SBDs also have high cut-off frequency good dynamic range and are low cost To
21
date the SBD has been able to detect signals up to 100GHz [11] 1THz[12] and as high
as 10 THz[13] However the current transport mechanism in a SBD relies on thermionic
emission and therefore is strongly dependent on temperature and means that using them
in extreme conditions ie military and automotive applications is complex The SBD
also suffers from high noise figure[14] and is susceptible to burnout at a modest pulse
power level this will limit the use of ultra-high frequencies and low power signal
applications Other diodes that share the same characteristics are Planar Doped Barrier
(PDB) Germanium Backward Diode (GBD) ie a type of Esaki tunnel diode These
diodes are well known and are reliably used as millimetre wave detectors However it
still proves inefficient to substitute the SDB with any of the previously mentioned
diodes This is due to some drawbacks such as strong temperature dependence limited
dynamic range fabrication complications and hence poor reproducibility (ie GBD) and
other circuit complexities
Hence there is strong compulsion to study examine and produce new detector
diode structures that are able to solve the mentioned diodes limitations and which have
high sensitivity larger dynamic range low noise strong independence to temperature as
well as being able to work efficiently in the high-frequency band and at zero bias The
advantages of working at zero-bias relates very much to the need for a system with less
power consumption so that the device (ie mobile communication) is able to run off
small batteries for a reasonable length of time eliminating extra biasing circuit as well as
noise Therefore a new tunnelling device namely the Asymmetrical Spacer Layer
Tunnel diode (ASPAT) developed by RT Syme [15 16] and refined by Missous et
al[17] has been examined in this work The ASPAT which is in essence a
Semiconductor-insulator-semiconductor structure relies on tunnelling through a barrier
to provide current compared to conventional thermionic emission in SBDs The ASPAT
diode has many advantages a zero bias turn-on voltage very weak sensitivity to changes
in temperature (due to tunnelling) very low noise large dynamic range high resistance
to pulse burn-out [18] and as demonstrated recently can be reproducibly
manufactured[17] The growing interest in THz frequencies nowadays makes the
ASPAT an excellent choice to fulfil all requirements for ultra-high speed applications
22
ie communication (mobile computer networking) radar (military equipment) scalar
analyser and built-in test equipment
In this work an ASPAT diode based on group III-V elements of the periodic table
comprising compound semiconductors of large band gap material Aluminium Arsenide
(AlAs) sandwiched between two lower bandgap Gallium Arsenide (GaAs) are used and
intensively examined The AlAs semiconductor which is ten-monolayer thick has
almost the same lattice constant as GaAs but has a larger bandgap Consequently in the
conduction band a thin barrier of the AlAs is formed from the arrangement of such
structure The structure is made up of GaAs and AlAs both materials are grown on
GaAs substrate using Solid Source Molecular Beam Epitaxy (SSMBE) Therefore in
this study the ASPAT diode will be referred to as ldquoGaAsAlAs ASPATrdquo diode The
conventional GaAsAlAs ASPAT diode has been developed and successfully fabricated
in two different stages This work was the first carried out using facilities provided by
the University of Manchester The first stage of the work was to qualify the
reproducibility and repeatability of growth and fabrication technique which is mostly
performed on larger emitteranode size The second was to develop conventional
ASPAT diodes that can perform at Millimetre and sub-millimetre wave frequencies and
which are comprised of small emitter area
Prior to this work full physical modelling using SILVACO design software was
undertaken to generate models and to fully characterise and identify the fundamental
physical phenomenon of multi-junction ASPAT diode Therefore insight into and
performance based on diode structure and electron movement can be understood and
predicted which lead to the crucial idea in helping and advising iterations to epitaxial
growth as well as diode fabrication The verification of the physical models must be set
as a priority goal by comparing the results of statistically fabricated measured data The
advantage of physical modelling is that it can help reduce materials resources cost and
fabrication time
Further research into the field has led to the development of two other types of
ASPAT diodes that are used to compare with the conventional GaAsAlAs ASPAT
diode Their configuration involved the use of a more advanced semiconductor
technology which comprises InGaAsAlAs materials and GaAsAlAs with InGaAs
23
quantum wells The latter was a novel ASPAT diode and the former is identified as
advanced ASPAT diode However these two advanced ASPAT diodes have not been
extensively studied in this thesis as they will be covered by other co-workers at
Manchester Hence due to these some important parameters are compared to the
conventional one as it is the main focus of this work In the case of temperature
dependent studies the DC characteristic of conventional ASPAT is compared to in-
house fabrication AuGaAs SBD All the ASPATs epitaxial layer materials structures are
shown in the following tables
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials structure grown
on GaAs Substrates by MBE
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE304 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~400 ~50
Spacer1 GaAs NID 50 50 50
Barrier AlAs NID 28 28 28
Spacer 2 GaAs NID 1000 2000 1000
Buffer GaAs(Si) 4times1017
50 400 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~4500 ~3500
Substrate GaAs (Si) 50000 50000 50000
Note that sample XMBE368 and XMBE304 are grown on doped GaAs
substrates Sample XMBE368 was grown un-rotated to study the effect of barrier
thickness variation
24
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314 grown on a
GaAs substrate by MBE
XMBE314
Layer Material Doping (119836119846minus120785) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018
3000 142
Emitter GaAs (Si) 1times1017
400 142
Spacer GaAs Undoped 50 142
Quantum Well In18Ga82As Undoped 60 116
Barrier AlAs Undoped 28 283
Quantum Well In18Ga82As Undoped 60 116
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017
400 142
Ohmic Layer GaAs (Si) 4times1018
4500 142
Substrate GaAs
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP substrate
XMBE326
Layer Material Doping (cm-3
) Thickness (Aring) Bandgap (eV)
Top Ohmic1 In053Ga047As(Si) 5times1019
3000 075
Buffer 1 In053Ga047As(Si) 1times1017
350 075
Spacer1 In053Ga047As NID 50 073
Barrier AlAs NID 283 283
Spacer 2 In053Ga047As NID 2000 075
Buffer In053Ga047As(Si) 1times1017
350 075
Bottom Ohmic In053Ga047As(Si) 15times1019
4200 075
Substrate InP (Si) NID 620000
From the above tables it can be noted that XMBE307 is the first batch that was grown
in-house using a Riber V100HU MBE machine followed by XMBE368 XMBE 304
XMBE314 and finally XMBE326 The two earlier batches were grown on n+
substrate hence their fabrication process flow is simpler On the other hand the three
other batches were grown on semi insulating substrate thus requiring the development
of new repeatable reproducible and robust process flow which will be covered in this
thesis
25
In general the fabrication of the ASPAT diode is based on top-down processes this
is because the ASPAT is a vertical structure device and the junction capacitance of the
ASPAT is directly associated with the size of the anodeemitter area Further to these
the capacitance directly influences the diode cut-off frequency Therefore the simplest
way to reduce the capacitance is by reducing the lateral area of the device of the ASPAT
structure since it can be represented by a parallel plate capacitor where the capacitance
is inversely proportional to the area of the device In order to achieve high cut-off
frequencies minimising capacitance via small dimensions ie sub-micrometre level is
essential However this will also increase the series resistance of the diode As a result
the cut-off frequency will be degraded Thus there is a trade-off between small
dimension of device and high cut-off frequency to be achieved
Finally successful growth and fabrication for small area GaAsAlAs ASPAT diode
in this work has led to carefully extracted RF characteristics This becomes a stepping
stone to designing a millimetre wave integrated circuit (MMIC) detector using empirical
modelling in Keysight ADS tools Therefore a predicted performance for a 4times4 um2
fabricated ASPAT is that can operate at 100GHz ASPAT as a zero-bias detector with a
voltage sensitivity of over 2000VW Additionally the design of a millimetre wave
source using similar ASPAT diodes was also carried out The performance of a 2040
GHz doubler using GaAsAlAs ASPAT in varistor mode is demonstrated for the first
time with a conversion loss of 33dB and conversion efficiency of ~ 02
26
12 Aims and objectives
The aim of this study is to further improve the performance of microwave and
millimetre wave technology by incorporating the Asymmetrical Spacer Layer Tunnel
Diode (ASPAT) for ultimate operation near THz frequencies by designing a range of
low power high-speed devices enhancing the methods of Simulation layout and
materials amp structural characterisations with fabrication process optimization using the
facilities available at the University of Manchester
There are three main objectives in this research firstly to streamline the physical
device design and modelling using the GaAsAlAsGaAs materials systems in order to
produce a zero bias detector which is basically a rectifier of a microwave signal by
using the SILVACO Atlas simulation tools
Secondly to achieve reproducibility and manufacturability of the fabrication
process for new type of GaAsAlAs ASPAT structure (lateral structure) hence small size
ASPAT emitter by improving the device processing technique and maximising the
capability limit of the conventional i-line optical lithography that is available in Prof
Missousrsquos group laboratory
Thirdly to optimise DC parameters through electrical properties investigation as a
stepping stone to the next objective that is to characterise the RF performance of the
GaAsAlAs ASPAT detector circuit The detection properties of microwave and
millimetre wave diode will also be investigated with different ASPAT diode size at
100GHz Further to these the properties of microwave signal source will also be
developed by way of utilizing the non-linearity feature of the diode Therefore this new
type of tunnelling diode can be applied to both applications of signal detection and
signal source in the microwave and millimetre wave ranges
27
13 Outline of this Thesis
This thesis is organized into eight chapters The first chapter discusses the
contextual information that motivates the undertaking of the study An overview of the
work which includes the details of the studied samples the aim and objectives of the
whole research project are also outlined in this chapter
Chapter 2 deals with the literature review of the basic principles and concepts of
the group III-V compound semiconductors The historical background of such
semiconductors which is essential to the development of ternary structures etc and the
advancement of semiconductor materials engineering is presented The types of existing
tunneling diode as well as conventional microwave diodes are also discussed and
compared The fundamentals of ASPAT diode which includes structural parameters and
its operation are then explained in detail Finally discussions of the ASPAT key DC
characteristics which are important for detection purposes are presented
Chapter 3 focusses on the development of the experimental techniques which can
be divided into two stages In the first stage the development is towards repeatability
reproducibility and manufacturability of the ASPAT grown in-house by MBE and
fabricated by conventional i-line optical lithography The second stage involves
optimisation and fine tuning such fabrication method for GaAsAlAs ASPAT samples
that can operate at high frequency ie 100GHz detector For both stages of the
fabrication process all techniques including mask design generic and special process
flow are presented The chapter ends with discussions on issues related to sample
processing and improvements that are proposed to solve these issues
Chapter 4 dwells on the modelling of the GaAsAlAs ASPAT using the SILVACO
simulation package The discussions are expected to offer a better understanding or
insight into each layer that forms the ASPAT diode structure The chapter begins with
discussions of the operation of the SILVACO Atlas tool A validation of physical
modelling is essential and presented according to the fabricated mesa sizes of the diode
28
Thereafter towards the end of the chapter the analyses of the relationship between
device current-voltage (I-V) characteristics the structural parameter including various
temperatures dependent simulations with a comparison to an in-house fabricated SBD
are offered
Chapter 5 presents relevant DC results based on optimized fabrication process and
RF characterization which enable obtaining an intrinsic and extrinsic element of the
GaAsAlAs ASPAT diode The discussions also highlight the analysis of DC zero bias
equivalent circuit and de-embedding extraction using ADS The chapter ends with
discussions on the RF reproducibility performance which includes the performance as
well for millimeter-wave and sub-millimeter wave applications
Chapter 6 discusses the main applications of ASPAT diodes The chapter begins
with discussions on detection theory followed by the parameters of interest and ends
with circuit design as well as the performance of a 100GHz detector The circuit design
was conducted using Keysight ADS software via harmonics balance simulation tool The
performance in term of sensitivity depending on measured ASPAT emitter size is
demonstrated Finally a comparison with conventional Schottky diode is presented
towards the end of the chapter
Chapter 7 discusses a secondary application that can be applied to the ASPAT by
utilizing the nonlinearity feature of the diode to create a signal source namely a 20 to
40GHz frequency doubler in varistor mode The doubler performance of ASPAT will be
explored through circuit design constructed via Keysight ADS simulation software Each
key parameter is highlighted and discussed in detail
The final chapter of this thesis that is Chapter 8 discusses the conclusions of the
study with emphasis on the overall key research findings The chapter also highlights
suggestions for further research in this particular field of study
29
2 LITERATURE REVIEW
21 Introduction
Since 1940s the development in the technology of semiconductor electronics has
been expanding and now has led to the establishment one of the most astonishing
industries of the 3rd
-millennium era Leading this advancement is the integrated circuit
(IC) or chip which was driven mostly by silicon (Si) Overtime the IC has undergone
substantial revolution in term of power economics size and efficient energy
consumption Currently it covers every aspect of human life ie from desktop personal
computers in the office and house to the compact smartphone in the pocket and from a
gigantic satellite in space to small satellite navigation in cars In other words
semiconductor technology is crucial to human life Without developments in
semiconductor materials engineering and shrinking of device size such accomplishment
may not have been realised today Therefore this chapter presents a macro view of the
development in compound semiconductor technology especially in radio frequency (RF)
towards Millimetre and submillimetre wave applications with regard to the improvement
of material and device structures
The essentials of group III-V compound semiconductor will be emphasised for its
points of interest and application in this field (RF technology) This chapter comprises
five main sections The first section is an overview of the semiconductor history with
concentration on its advantages and applications in the RF field while the second and
third discuss the effects of III-V compounds when the interface occurs between
semiconductor-semiconductor and semiconductor-metal respectively which leads to a
basic understanding of hetero-structures device as well as contacts namely Schottky and
Ohmic The fourth section is predominantly concerned with high-speed devices ie
diodes and materials in this field which leads to the exploitation of the main researchrsquos
device Then the following section describes in detail the background works basic
principle and intrinsic amp extrinsic parameters of the Asymmetric spacer Tunnel Diode
(ASPAT) Finally the basic way of characterising the device will also include giving an
overview of how the device is measured and what parameters are needed
30
22 Historical review of III-V Compound Semiconductor for RF applications
The beginning of commercial electronic devices was marked with the first point-
contact semiconductor transistor developed in 1947 by William Shockley at Bell
Laboratories in New Jersey Shockley developed a device based on a Germanium
Bipolar Junction Transistor (Ge BJT) structure [19] with operating frequency above 1
GHz Since then and until early 1950s the development of Ge BJT was fast and it
became foremost in the market of semiconductor technology However the emergence
of Silicon (Si) challenged Ge in the market in the 1960s Si has the upper hand primarily
because it has better electron transport and low manufacturing costs compared to Ge
[19] By the 1970s almost all RF transistors were based on Si BJT Additionally the
development of Si which forms a new material from the formation of native oxide
namely Silicon Dioxide (SiO2) led to the invention of the Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) [19] The future of digital electronic industries has
been ldquobrightrdquo ever since the MOSFET was ldquobornrdquo as it has become a fundamental
building block component in complex microprocessors and flash memories Despite this
development the exploitation of Si at RF frequencies did not last long since Si is not an
optimum semiconductor for RF electronic devices The emergence of GaAs has
improved RF applications for high-speed transistors
Ge and Si which are categorised as single element semiconductor are the earliest
materials used to build the first transistor devices These devices played a crucial role
towards the development of more advanced material such as GaAs of the compound
semiconductor type[20] A compound semiconductor is a semiconductor formed by the
ionic bond of different types of semiconductor material most widely known as the group
III-V compound semiconductors The main reason for the progression of the III-V
compound semiconductors is due to their better electron mobility compared to the single
element semiconductors The term ldquomobilityrdquo in the semiconductor industry refers to the
easiness of movement of charges in many directions inside a crystal In fact it is
determined by the access resistances values with saturated velocity under certain values
of electric fields (bias) the higher the electric field the faster is the carrier movement in
the crystal Figure 21 shows the electron mobility and band gap for the most common
31
group III-V compound semiconductors Besides higher mobility III-V compound
semiconductors also have light-emission capability and are suitable for bandgap-
engineering techniques
The work on III-V compound semiconductors mainly on GaAs FETs led to a new
change for the whole RF electronics industry For example in 1966 the first GaAs
MESFET was invented[21] and achieved a maximum operating frequency of operation
of 3GHz [22] Three years later the frequency increased to 30GHz [23]
Figure 21 III-V compound semiconductors mobility and band gap[24]
With better features in terms of having a higher electron mobility compared to Si
electronic devices based on III-V materials developed rapidly This attracted attention in
many aspects especially in military radar application electronic warfare system missile
guidance control electronic for smart warfare system and secure communication To be
specific those demands were fulfilled through the application of microwave mixer and
detectors [25] which were achieved based on Schottky barrier diodes and FETs
However these applications remained largely as niche markets for use only in military
and exotic scientific projects until 1980 In addition to the microwave industry two
important diodes that played a large role in very high-frequency power source namely
the Gunn diode and the Impact Avalanche and Transit Time (IMPATT) diode which
were discovered in the 1960s[26]
100
1000
10000
100000
0 05 1 15
Bu
lk M
ob
ility
(cm
2 V
-1 s
-1
BandGap (eV)
InS
b
InA
s
Ge
Ga
Sb
In
GaA
s
Si
GaA
s
InP
32
Furthermore the invention of Molecular Beam Epitaxy (MBE) growth technique at
the beginning of 1970s has enhanced the full potential of the III-V compound
semiconductors[27] This technique has led to the formation of a new class of materials
and heterojunction device with high-quality interfaces and accurate control of the
thickness during growth[28] The advancement of material engineering that tailored the
III-V compound semiconductor with MBE effect has been beneficial for both three-
terminal and two-terminal devices As a result of this more advanced devices in both
electronics and optics were developed such as quantum well (QW) laser Resonant
tunnelling diode (RTD) high electron mobility transistor (HEMT) and many more[29]
The aim was to achieve high-speed devices transporting data at high data rates and
robust devices These devices promised an excellent option to conventional transistor
(three terminal devices) in high-frequency systems especially in the terahertz (THz) or
Millimetre and sub-millimetre wave regions [30]
One of the promising diodes that received a lot of attention is the resonant
tunnelling diode (RTD) which was first described in 1974 by Chang [31] This device
which consists of a double barrier and one quantum well is the classical tunnelling diode
Due to its good symmetrical non-linearity in its current- voltage characteristic it can be
exploited for signal generation and detection However the main focus of RTD to date
has been in the generation of continuous wave (CW) ultra-high frequency and to a lesser
extent in detection Therefore other tunnelling based diodes were developed specifically
for detection purposes which are the main foci of this work The PDB and ASPAT
diodes are the workhorse candidates for detection purposes Most of these are built based
on group III-V compound semiconductors [32]
Unlike the Very Large Scale Integration (VLSI) market ie CMOS for personal
computer (PCs) the RF electronic device for civilian application reached the consumer
market only in the late 1980s through satellite television with operating frequencies
around 12GHz [19] Since then many RF application have been deployed on the mass
market depending on their operating frequency such as 09GHz ndash 25GHz for wireless
communication 20GHz to 30GHz for satellite communication 77GHz for car radar
systems and above 90GHz for different sensor applications Utilising GaAs as the main
material RF devices have become the key underpinning components for modern
33
communication systems As a result in 1998 the volume production of mobile phones
was greater than that of PCs for the first time in history Presently production is being
made for devices like smartphones cellular phones mobile internet access and new
communication services and tablets
The development of the RF field is never ending More and more improvements are
being made especially through the design and fabrication of oscillators and detectors
which are mainly built based on group III-V compound semiconductors When RF
devices were used by the military (in the 1970s to 1980s) cost was not a concern
However after getting into civil application market (ie in the 1990s) the most frequent
issues highlighted were performance and cost[19]
The ability to generate or receive high operating frequencies with high power large
bandwidth and high sensitivity is an indicator for a good performance of RF devices
(depending on specific applications) For example the highest room temperature based
oscillator of up to 186 THz was achieved in thin well AlAs-InGaAs RTD by Professor
Masahiro Asada from Tokyo Institute of Technology [33] An excellent review on THz
sources can be found in [34] For ultra-high frequency detector and mixer applications
the two terminals RF device that is mostly used is the SBD In 1996 the highest cut off
frequency achieved by a mixer utilizing the SBD was about 5THz[35] and this has kept
increasing ever since The factor that motivates the development of THz devices is the
requirement to have a compact coherent source in the THz range Undoubtedly in the
future there will be very exciting times for enthusiasts of terahertz sources and receiver
as new generations of compact broadband and tuneable solid source device based on
advanced compound semiconductor are developed
23 The Concept of Heterostructures
A III-V compound semiconductor is mostly grown on a single semiconductor
substrate forming a layer called epitaxial heterojunction layer It is a starting point and
the key feature that brings the idea of realising the most advanced semiconductor
devices currently being developed and manufactured by combining several epitaxial
semiconductors [36-38] Heterojunctions have the capability of manipulating carrier
transport ie electron and holes transport in crystal separately unlike homojunctions
34
This has resulted in the successful development of new devices for high-speed and high-
frequency applications as well as optical sources and detectors [37] This section will
discuss lattice matched material pseudomorphic material hetero-junction band
discontinuities and quantum wells
231 Homojunctions Heterojunctions and Band Discontinuities
The term homo-junction refers to the interface between identical semiconductor
materials that have different polarity ie p-type or n-type but similar in energy gap This
phenomenon is usually applied in forming p-n junction diodes and can be understood by
referring to Figure 22 below
Figure 22 illustration of Homojunctions band structure material before (left) and after (right)
equilibrium
The materials A and B which have similar bandgap (Eg) and different dopant
types ie p-type and n-type will have their Fermi levels (Ef) closer to the valence band
(EV) and conduction band (EC) respectively before ldquothermal equilibriumrdquo Once
equilibrium is achieved Ef of both p-type and n-type will be aligned causing band
bending of EC and EV As a result a built-in electric field is introduced (via diffusion of
carriers) for both holes and electrons and forcing them to move in one direction
On the contrary a heterojunction occurs when the interface between two
semiconductor materials with different bandgap energy are brought together (ie large
energy band gap material combined with a low band gap one eg wide band gap AlAs
and narrow bandgap GaAs) This results in a steep band bending which leads to the
formation of energy band discontinuities at the junction as shown in Figure 23 In a
semiconductor heterojunction the most important parameter is the band gap energy
EC
EV
Ef
Eg
p-type E
g
n-type
EC
EV
Ef
Material A
p-type
n-type
Material B Material A Material B
35
associated with each material in the structure where the degree of discontinuity can be
utilised in varying the carriers transport properties as well as the quality of the junction
depending on the interest of the designer This leads to flexibility in tailoring device
characteristics leading to vastly improved performance of the device
Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium
Based on Figure 23 above Material A indicated with blue line is a large band
gap energy material and Material B highlighted with the red line is a low band gap
material EV represents the valence band EC the conduction band and Ef is the Fermi
level of the materials Alternatively the two materials band discontinuities are denoted
by ΔEC for the conduction band and ΔEV for the valence band χ and Eg represent the
electron affinity and band gap energy respectively
At some point where by the Fermi energy of both semiconductor materials are levelled
the structure would have reached its thermal equilibrium The band gap of materials A
and B have a discontinuity at the interface (ΔEg) of these two materials In general this
is given by
120549119864119892 = 119864119892119860 minus 119864119892
119861 (21)
Furthermore when thermal equilibrium is achieved ΔEg is then divided between
conduction band and valence band discontinuities (ΔEC and ΔEV respectively) at the
material A and B junction interfaces Their relationships can be expressed as
EC
A
EV
A
Ef
A
Eg
A
Material A Material B
χA
χ
B
ΔEC
ΔEV
Ef
B
E
g
B
EC
B
EV
B
EV
A
χA
ΔE
C
ΔEV
EC
A
Ef
EC
B
EV
B
χB
Material A Material B
Vacuum
Level Vacuum
Level
36
∆119864119862 = 120594119860 minus 120594119861 (22)
∆119864119881 = (119864119892119861 minus 119864119892
119860) minus (120594119860 minus 120594119861) (23)
∆119864119892 = 119864119892119860 minus 119864119892
119861 = ∆119864119862 + ∆119864119881 (24)
However these relationships which were introduced by Anderson can only offer an
approximation In practice the results are always different since dislocation and
interface strain occur at the junction Therefore precise control during epitaxial growth is
always required and growth technologies such as MBE are employed In due course the
band gap discontinuity can be further exploited by using different types of material
combination Examples are GaAsAl052Ga048As and In053Ga047As In052Al048As [39]
232 Lattice-Matched and Pseudomorphic Materials
As discussed earlier a heterojunction happens when any two different
semiconductor materials that have different bandgap are joined together At the atomic
level both materials often differ in lattice constant The easiest way to explain this is by
setting the formation of heterojunction which can be separated into two types lattice
matched and lattice mismatched (pseudomorphic)
2321 Lattice Matched Systems
To create discontinuities for use as a high-performance device the combination of
semiconductor materials is essential Selecting the appropriate materials that have
similar or very close lattice constants to combine is crucial to avoid disruption at the
atomic level heterojunction interface Figure 24 shows that the lattice constant of a
material A ie substrate (aS) and material B ie deposited over layer (aL) are identical
or very close and their surface atoms are perfectly matched This scenario is known as
lattice matching
37
Figure 24 Lattice Matching for both materials when aL=aS
As can be seen in Figure 25 while there are restricted binary materials available to
form good heterojunction interfaces it is possible to combine semiconductor materials in
binary ternary and quaternary forms to allow the formation of a variety of lattice-
matched heterojunction interfaces The examples of materials that have successfully
been alloyed are In053Ga047As In052Al048AsInP and GaAsAlxGa(1-x)As (x=0 to 1)
Even though the materials system hetero-junction of these materials has close lattice
constant value their band-gap will experience an abrupt variation
Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40]
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
38
The existence of binary ternary and quaternary semiconductors formed by alloying
semiconductors has expanded the opportunity for heterojunction formation in devices
The alloy semiconductor which is produced by the combinations of two semiconductors
A and B has a lattice constant that obeys Vegardrsquos Law as follows
119886(119886119897119897119900119910) = 119909119886119860 + (1 minus 119909)119886(119861) (25)
For the alloy the band gap normally follows the virtual crystal approximation
119864119892(119886119897119897119900119910) = 119909119864119892(119860) + (1 minus 119909)119864119892(119861) (26)
Table 21 shows the list of the semiconductor alloy band gap and lattice constant for
common binary and ternary for group III-V compound semiconductors[41]
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary compound
semiconductors a room temperature [41 42]
Alloy Lattice constant a(Aring) Band gap EgeV)
AlAs 5661 2239
AlSb 6136 1581
GaAs 5653 1424
GaN 3189 34
InAs 6058 0417
InP 5869 1344
Al052Ga048As 5657 2072
In053Ga047As 5868 0773
In052Al048As 5852 1543
39
2322 Pseudo-morphic Materials
The other scenario is when two different materials with different lattice constants
are brought into contact The observation can be made at the atomic level where the
atom will try to match each other as shown in Figure 26 below
Figure 26 Lattice mismatched material
In fact for both situations (ie lattice matched and lattice mismatched) the atom of
the material at the hetero-interface will change their position to maintain the geometry of
the lattice Due to distortion at this atomic level a strain is then induced at the hetero-
interface In order to form a good hetero-junction interface the strain must not exceed a
certain specific critical value which will cause crystal dislocations to occur The result of
crystal dislocation is generally bad as it will affect the carriers which will be
concentrated in the defect area thus degrading the carriersrsquo mobility This then makes
the overall function or performance of the device to become poor
Nowadays the Molecular Beam Epitaxial (MBE) technique is able to grow epitaxial
layers of mismatched semiconductor layers profile ie mismatched in their lattice
constant (aLneaS) The growth method works when the grown epitaxial layer assumes the
lattice parameters of the layer it is deposited on Nonetheless the layers must be kept
within a certain limit and the deposited layer must be thin enough to avoid defect or
dislocation formations This new layer known as a ldquopseudomorphicrdquo material will alter
its original crystal structure and physical properties
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
40
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and (b) tensile
strain [1]
Figure 27 shows material A in which the pseudomorphic materials can be related to
two situations compressive and tensile strain The compressive strain occurs when the
deposited layer has a larger lattice constant than the substrate (aL gtaS) while tensile strain
happens when the deposited layer has a smaller lattice constant than the substrate
(aLltaS) These leads to aL either to compress or stretch to fit aS respectively Note that
the pseudomorphic layers can only be grown to a certain critical thickness hc From
Figure 27 the strain between the substrate and the deposited epitaxial layer is given by
휀 =119886119871 minus 119886119878
119886119878 (27)
Where Ɛ is strain between two layers aL is lattice constant of the deposited layer and
aS is lattice constant of the substrate layer The concern in deposition of the over layer is
to avoid dislocation occurring at the interface if there is too much strain at the junction
The strain is naturally influenced by the thickness of the deposited layer and thus the
thickness of growth must be controlled below the critical thickness hc which is
expresses as
(b)
41
ℎ119888 =119886119904
2Ɛ
(28)
Moreover one needs to appreciate that even though the crystal structure and their
physical properties change the total energy within the unit cell is maintained This is
possible by distortion of the deposited layer in the direction perpendicular to the growth
direction while leading to lattice matching in the lateral plane Example of lattice
matched materials is GaAsAlAs and pseudomorphic material is In08Ga02AsInP
233 Quantum well and 2DEG
A typical application of heterojunction interface is one in which utilises ΔEC and ΔEV to
form barriers for electrons and holes One example of barriers that confines these
carriers is known as a Quantum Well (QW) A QW is a layered semiconductor usually
very thin ie about ~ 100 Aring thicknesses in which many quantum mechanical effects can
occur It is formed by a thin layer of a low bandgap energy semiconductor material eg
GaAs sandwiched between two similar large bandgap energy semiconductors eg AlAs
or AlGaAs The growth technique to achieve thin layers of QW is usually MBE The
benefit of this method is that it allows the formation of heterojunction with very thin
epitaxial layer
Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg GaAs (a)
Structure (b) energy band diagram and (c) Conduction band diagram when AlGaAs is n-doped[43]
42
The thickness of the layer that can be achieved can be as thin as the electron mean free
path (De Broglie wavelength) which is around 100 Aring to 300 Aring [44] The expression for
the De Broglie wavelength is given by
120582 = ℎ120588frasl (29)
Here h and ρ are Planckrsquos constant and momentum of the electron respectively Figure
28(b) illustrates a quantum well formation in abrupt semiconductor interfaces It can be
observed that the heterojunction boundary will experience discontinuities at the edges of
the conduction band and valence band with a quantum well generated for the carriers
(both electron and holes) The quantised energy sub-bands in the quantum well structure
in Figure 28(b) can be determined from [43]
119864 = 119864119899 + (
ℏ2
2119898lowast) (119896119909
2 + 1198961199102)
(210)
Where 119864119899 = (ℏ21205872
2119898lowast ) (119899
119871)2
and n is the energy level index that can be n=1 2 3hellip
The dopants in a semiconductor with large band gap layers may supply the
carrier to the quantum well and this occurs when the base or bottom of the quantum well
is lower than the Fermi Level and hence the high energy donors will go down to the
well therefore creating a Two-Dimensional Electron Gas (2DEG) In the 2DEG the
electrons and holes move freely in the quantum well in the plane perpendicular to the
growth direction however they are not capable of moving in the crystal growth
direction (confinement direction)[45 46] The 2DEG phenomena can be seen in Figure
28(c)
24 Metal-Semiconductor Contact
A semiconductor device is incomplete if there is no connection between the
semiconductors and the outside world A metal which is usually gold (Au) or gold
germanium (AuGe) is diffused into the semiconductor to allow for electrical connection
from the outside world to the semiconductor and vice versa The metal-semiconductor
contact can be either a Schottky contact or an Ohmic contact The Schottky contact is a
43
rectifying contact while the Ohmic contact is a contact that provides a low resistance
path between semiconductor and metal
241 Schottky Contact
The Schottky contact is basically a metal contact to the gate to enter a region or
channel in a transistor Figure 29 shows a schematic band diagram of a metal-
semiconductor contact before and after contact (Schottky-Mott concept)[47]
Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact
In Figure 29 the work function of the metal is represented by qm while the
semiconductor work function is qS The qχ is the energy difference of an electron
between the vacuum level and conduction band edge ie known as the electron affinity
and qVn is the difference between the conduction band and Fermi level in the
semiconductor EV EC Ef is the valence band energy conduction band energy and the
Fermi level respectively
The metal and semiconductor are brought together as showed in Figure 29(a)
both materials are at steady state However when the metal and semiconductors are in
contact as illustrated in Figure 29(b) the electrons that flow from the conduction band
in the semiconductor into the lower energy state of the metal will cause the Fermi level
to be aligned in thermal equilibrium Due to this process the positive charge donor is
trapped in the semiconductor interface hence forming a depletion region Xdep
Thereafter the upward bending of the energy in the semiconductor takes place On the
qχ(s)
Eg(s)
Vacuum Level
EV
EF(m)
E
F
EC
qϕ(m)
qϕ(s)
Metal Semiconductor
qVn
qϕB
qϕ(s)
qVbi
X
qχ(s)
Eg(s)
Vacuum Level
EV
EF
EC
qϕ(m)
Metal Semiconductor
Xdep
(a) (b)
44
other hand the negative charge (electron) will be accumulated within a narrow region in
the metal interface The existence of two different charges at the metal-semiconductor
boundary generates an electric field This leads to a potential barrier qB as seen by
electrons in the metal moving into the semiconductor and a built-in potential qVbi as
seen by electrons in the semiconductor trying to move into the metal
The built-in potential qVbi is defined as follows
119902119881119887119894 = 119902empty119861 minus 119902119881119899 (211)
The barrier height empty119861 in the ideal case is specified by the dissimilarity between a metal
work function empty119898 and electron affinity of the semiconductor
119902empty119861 = 119902empty119898 minus 119902120594 (212)
Referring to Eq (212) above the barrier height empty119861 rises linearly with the metalrsquos work
function empty119898 Nevertheless this is only in theory as the presence of localised surface
stated at the edges causes empty119861 to become unresponsive to the metal work function
Consequently Eq(211) is then reordered to match the difference in metal and
semiconductor work function Thus the new equation becomes
119902119881119887119894
= 119902(120601119898 minus 120601119904) (213)
A Schottky contact appears when a metal-semiconductor contact has a large
barrier height (B ge kT) and low doping concentration in the semiconductor (ND le NC) In
the case when the metal-semiconductor contact is under some bias eg reverse bias the
semiconductor will react to a positive bias according to the metal by a voltage V=-VR
This condition will affect the built-in potential and leads to increase from Vbi to
(Vbi+VR) thus increasing the barrier height empty119861 in the semiconductor as well
Consequently electrons are less able to flow from the semiconductor and cross into the
metal Therefore the current flow will be very small This phenomena is shown in
Figure 210(a)
45
Figure 210 Energy band diagram of Schottky contact on n-type material under (a) reverse and (b)
forward bias
As can be seen from Figure 210(b) when a forward bias is applied the semiconductor
is biased negatively with respect to the metal by a voltage V=Vf This will result in a
reduction in built-in potential from Vbi to Vbi-Vf The electrons in the semiconductor will
lower the barrier height and a lot of electrons will escape into the metal causing a large
current to flow Thus a large current flow in the forward direction compared to the
reverse direction Essentially this is the origin why the Schottky contact is named a
rectifying contact [48 49] For the metal side both forward and reverse biases applied
do not affect the barrier high empty119861 because there is no voltage drop there
In this system the electron and holes are transported by a phenomenon called
Thermionic Emission (TE) which happens when the semiconductor layer is lightly
doped Nd lt 1x1017119888119898minus3 The electron will only be thermionically emitted into the metal
when the energy is higher than the potential barrier[50] There is another phenomenon
called Thermionic Field Emission (TFE) which happens when the potential barrier
thickness is very thin (thin enough) to allow the electron to tunnel through the barrier
This will be discussed in the next section as this phenomenon leads to the formation of
an ohmic contact
(a) (b)
46
242 Ohmic Contact
Basically an ohmic contactrsquos purpose is to provide a low resistance path from
the semiconductor to the outside world It is different to a Schottky contact as it is a non-
rectifying contact and does not control the current flow the I-V characteristic of an
ohmic contact is linear in both forward and reverse directions (equality in current flow)
The ohmic contact also has a small voltage drop across it compared to the voltage drop
across the device
If a metal and semiconductor are bought together unavoidably a Schottky
contact will be formed Therefore to create an ohmic contact some techniques to reduce
barrier height and width of the depletion region must be used ie increase Nd In carrier
transport theory there are three mechanisms of carrier transport across the barrier
Firstly the Thermionic Emission (TE) which happens when the carries are excited to
overcome the barrier when the thermal energy is present Secondly the Thermionic
Field Emission (TFE) occurs when the electronholes have enough energy to tunnel
through an adequately thin barrier and some has overcome the low barrier at the top
Finally the Field Emission (FE) which results when carriers can tunnel through the
entire barrier The FE is the most favoured mechanism in the ohmic contact approach
[51]
From the three mechanisms above the current can be determined by the following
equations
1) Current in Thermionic emission (Figure 211(a))
exp (empty119861)
119896119879
(214)
2) Current in Thermionic field emission (Figure 211(b))
exp [
(empty119861)
11986400119888119900119905ℎ11986400
119896119879
] (215)
3) Current in Field Emission (Figure 211(c))
exp (empty119861)
11986400
(216)
47
Where k is the Boltzmann constant T is the temperature 11986400 is the tunnelling parameter
and is related to the doping concentration radic119873119863 The barrier height is denoted by empty119861
Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping concentration
ND (a) Low (b) Intermediate and (c) high
Figure 211 shows that the carrier transport mechanism is varied by the doping
concentration (ND) As can be seen from Figure 211(c) the doping concentration here is
the highest and influences the depletion region width Xdep to become smaller Therefore
Field Emission (FE) becomes dominant This FE method is the favourite method for
ohmic contact formation [51] and will be utilised in the fabrication carried out in this
work
In fabricating practical devices the ohmic contact is often split into two types
alloyed and Non-Alloyed The difference between the two is that the alloyed type is used
when the semiconductor is doped with a low doping concentration ie less than
1x1018119888119898minus3 while the Non-Alloyed is designed for heavily doped semiconductors with
more than1 times 1019119888119898minus3 doping
The alloyed ohmic contact requires thermal annealing to have a good performance
for electron transport In multi-layer metals one of the metals has the role of donor or
acceptor which is used to increase the doping concentration of the semiconductor If a
temperature anneals eg 420˚ Celsius is applied the metal will diffuse into the
semiconductor and carry the dopant into the semiconductor Therefore a heavily doped
region will be formed and the depletion width becomes narrow establishing the ohmic
contact The key example of this is the usage of the Gold-Germanium-Nickel (Au-Ge-
Ni) alloy where the Ge is the n-type dopant [52] which diffuses into the semiconductor
(a) (b) (c)
48
and perform atom replacement in the semiconductor ie in GaAs it replaces Ga On the
other hand the Non-Alloyed does not require any thermal annealing as it already has a
very high doping concentration and will automatically reduce the depletion region width
The Non-Alloyed ohmic contact has some advantages such as reproducible contact
reduced processing time and good uniformity [53]
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work
In this section some historical background of the Asymmetrical Spacer-layer
Tunnel (ASPAT) diode is given Since this is the first thesis reporting about this new
device it is worth to mention some historical background about this tunnelling diode
The ASPAT was first proposed by a group of scientists from General Electrical
Company (GEC) in 1990[16] The works led by Richard T Syme and assisted by
Michael JKelly Angus Condie and Ian Dale initiated the idea of launching a new type
of tunnel diode The idea managed to attract the interest of many parties following the
development of resonant tunnelling diode (RTD) which earlier had shown a promising
weak temperature dependence [54] However the interest in RTD is mainly limited to
microwavesub-millimetre wave generation For THz detection the requirement is to
have a significantly asymmetric IV characteristic Given this the ASPAT which has
only a single energy barrier and most importantly weak temperature dependence and
large dynamic range would be a promising candidate for this application
The development of ASPAT is a kind of reverse engineering since it was built
purposely to replace the earliest receiver diode especially the Schottky Barrier Diode
(SBD) which has strong dependence on operating temperature [55] From the time when
it was first revealed a lot of works have been done to realise this most sophisticated
tunnel diode The first attempt which was reported in [56] was meant to gather some
insights into the device by using the well-known Schrodinger and Poissonrsquos equations
for simulation The second attempt on the other hand was directed to physically grow
and fabricate the device Here the real problem occurs At the first stage of qualifying
this device it was found not to be manufacturable Since then a new tunnel diode
structure based on GaAsAlAs materials system was built by both MBE and MOCVD
Its microwave performance was then tested at 94GHz [18] The same paper also
49
reported performance comparisons between ASPAT and another microwave diode ie
Germanium Backward Diode (GBD) PDB and SBD
Work on these devices stopped due to the inability to commercialise the ASPAT
and other tunnel based devices [57-60] The problems associated with low-cost
manufacture of tunnel diodes are due to firstly the thickness of the AlAs barrier layer
the dependence of tunnelling probability (electron) through a single barrier is
exponential and varies by a factor of more than 350 for one monolayer change in the
AlAs barrier thickness[61] The tunnelling of the electron through a barrier is
proportional to the current through a barrier as a function of a bias across the AlAs
barrier[62] Secondly the bandgap which is predominantly happens to be a ternary alloy
with relative composition ie AlxGa1-xAs Here the x can vary the bandgap in the
semiconductor layer For the ASPAT a 1 change in x results in a 30 change in the
current[62] To design an ASPAT for microwave and THz applications the designer
often allows at most plusmn10 variation of the absolute current through a specific diode at a
pre-identified bias This implies that within a wafer the uniformity that the ASPAT must
achieve is less than plusmn01 monolayers while between wafer to wafer the reproducibility
in barrier thickness in average must be identically controlled[63] This explains why at
the qualification stage of investigating ASPAT there was a need to focus on
GaAsAlAs-based material to diminish further errors because of the change in x This
type of work on ASPATs has been carried out by other co-workers at Manchester and
Cambridge
Thereafter the work then focused on repeatability and manufacturability tests
These result in many attempts being carried but failed with unacceptable between wafer
to wafer reproducibility [61 64] The development of reproducibility and repeatability of
the ASPAT was pursued for over 10 years until precise control of the growth of the
thickness AlAs layer was finally achieved using MBE[65] [66 67] This achievement is
confirmed by a current density produced which varied by less than plusmn30 indicating that
the reproducibility of AlAs barrier of the order of plusmn 02 monolayers A final step to
achieve the level control for the ASPATrsquos AlAs barrier thickness was carried out and
resulted in a 1 standard deviation of the IV characteristics for both within a wafer and
different wafer (2 inches wafer size)[17] In the early stage of this work some
50
repeatability and manufacturability test was also carried out Once this vital step is
accomplished further investigation on the ASPAT was made most recently and which
will be covered in this thesis ie temperature independence[68] and new ASPAT
types[69] characterisation to achieve smaller device RF measurement and development
of THz detectors The material systems that have been investigated so far are
GaAsAlAs and InGaAsAlAs both in the ManchesterCambridge group
Recently the ASPAT was commercialised by Linwave Technology as a wideband
zero-bias detector diode This was done in April 2016 Although it is now on the market
the ASPAT remains immature in term of research and development A lot of work is still
required to enhance the device ie working at the sub-millimetre wave using ternary
material etc
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics
The basic building block of the ASPAT diode is based on heterojunction of three
multilayer semiconductor structures which have two different band gaps The structure
comprises a thin layer of wider-gap semiconductor sandwiched between two
semiconductors with narrower-gap forming a tunnel barrier The basic principle of the
ASPAT device is based on the exploitation of quantum mechanics theory using
heterojunctions interface According to quantum mechanics theory moving particles
(electrons) with less energy than the barrier height have a probability of appearing on the
other side of the barrier by a tunneling through it This can be achieved in conditions
where the barrier must be very thin (~ 10 monolayer ) This is in contrast to classical
physics where a particle must have kinetic energy at least slightly greater than the
potential barrier height in order to overcome the barrier otherwise the probability of the
particle to appear on the side of the barrier is zero
Since the ASPAT diode operation is based on tunnelling through a barrier one
needs to know that the tunnelling mechanisms can be classified into two types[44]
intraband and interband The latter is described as tunnelling that occurs from
conduction band to valence band (electron) and valence band to conduction band (holes)
This normally happens in bipolar device ie p-n junction diode which has n-type and p-
type doped regions On the other hand intraband refers to tunnelling which occurs when
51
electron tunnel from the conduction band of a semiconductor to the conduction band of
its neighbouring semiconductor The same thing happens to the holes in the valence
band The device with this type of tunnelling is normally a unipolar device which is
either p-type or n-type doped The ASPAT diode can be considered as a device that is
based on intraband tunnelling mechanism Therefore the focus will be entirely based on
its principles
261 Principle of Quantum Tunneling
Generally all tunneling diodes obey the concept of quantum mechanical
tunneling Quantum mechanical tunneling is a phenomenon where a particle is able to go
through an energy barrier higher than the kinetic energy of the particle and if it is thin
enough compared to the de Broglie electron wavelength (λ) If the electron wave is
greater than the barrier the probability of the wave to occur at both side of the barrier is
higher
Figure 212 Classical view of whether an electron is can surmount a barrier or not Quantum
mechanical view allows an electron to tunnel through a barrier The probability (blue) is related to
the barrier thickness
For the case of classical physics (Figure 212(a)) the particles can be confined by
energy barriers of a semiconductor if their kinetic energy is less than the barrier energy
The particles thus require higher kinetic to escape to other states this phenomenon is
called thermal emission In quantum mechanics (Figure 212(b)) the particle is
described in two ways as a wave and as a particle If the particle moves like a wave it
will carry all the waversquos properties Therefore it will not brusquely end up at the
En
erg
y
(a) Classical view (b) Quantum mechanical view
En
erg
y
En
erg
y
52
boundary of the energy barrier Hence when the particles collide with the barrier
(incidence) there will be a probability of penetrating the barrier if the barrier is thin
enough and has a finite height For thicker barrier the probability of a wave that can be
found on the other side of the barrier is very small However the possibility of the
electron wave to appear on the other side of the barrier is increased by thinning the
barrier The potential barrier of semiconductor material technology can be determined by
using Homojunctions structures with different doping profile This will result in a
difference in band alignment and multilayer heterojunction structure (different
semiconductors have different band gap) which includes semiconductors insulators and
conductors (metals)
The easiest way to explain the phenomenon is by considering a potential barrier
Epot(x) with barrier height E0 energy bigger than the total energy E as shown in Figure
213 the potential energy occurs in a finite space between 0ltxlta and is 0 outside
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave function[70]
The electron outside the region of the potential barrier (xlt0 and xgta) is free to
move The effective mass of the electron is different inside and outside of the barrier in
real tunneling devices when implemented using semiconductor heterostructures The
quantum mechanical equations predict the wave nature of matter which states that matter
unveils wavelike properties under some conditions and particle-like properties under
other conditions The wavelike properties as described by the Schrodinger Formula of
E0 Transmitted Ψ = 119862119890minus119894119896119909
Incident Ψ = 119860119890119894119896119909
Reflected Ψ = 119861119890minus119894119896119909 Ψ = 119863119890minus119894119896119909
0 a
E
x
V(x
)
53
quantum mechanics represent a particle penetrating through a potential barrier most
likely as an evanescent wave coupling of electromagnetic waves[44]
To start the calculation of the tunnelling probability the Schrodinger equation is given
by
119894ℏ
120597
120597119905Ψ(119903 119905) = ΨΗ(r t)
(217)
Where ℏ is Planckrsquos constant (662606957 times 10119890minus341198982119896119892119904
2120587frasl ) Ψ(119903 119905)is the wave
function at position r and time t Η is the Hamiltonian operator given by
Η = minus
ℏ2
2119898nabla2 + 119881(119903 119905)
(218)
Where 119881(119903 119905)is the potential energy which is dependent on space and time 119881(119903 119905) is
considered zero for a particle traveling in free space without any potentials The plane
wave with vector r and t is given by
Ψ(119903 119905) = 119890119894(119896119903minus120596119905) (219)
This equation satisfies Eq (217) above under the condition where the particle is
travelling in free space without potential k is the wave vector which is equivalent
to2120587120582frasl and the angular frequency 120596 is 2120587 multiplied by the frequency
In the case of tunneling through a potential barrier the method of separation of
variables is used to simplify the problem as in the equation below
Ψ(119903 119905) = 119877(119903)119879(119905) (220)
It is assumed that the problem above is divided into time-dependent and time-
independent parts 119877(119903) is the spatial component and 119879(119905) is the time-based component
of the wave function The time dependent problem as shown above in the Schroumldinger
Equation (1) can easily be solved by filling up all the finite parameters The solution of
54
the time-independent part gives the tunneling probability For the one-dimensional (1D)
time-independent Schroumldinger equation[44]
119864120595(119909) = minus
ℏ2
2119898
1198892
1198891199092120595(119909) + 119881(119909)120595(119909)
(221)
E is the total energy and 120595(119909)is the spatial component of the wave function along the x
axis The combination to the wave function is given by
120595(119903 119905) = 120595(119903)119890minus(
119894119864119905ℏ
)
(222)
The time-independent plane wave solution of 120595 = 119890119894119896119909 satisfies the equation (221) for
any constant potential V0 in space Plugging in the wave solution yields the condition
that
119896 = radic2119898lowast(119864 minus 1198810)
ℏ2
(223)
Referring to Figure 213 also the barrier with exact rectangular shape with height E0 and
width W the solution of the wave functions and tunneling probability can be extracted
by using the below equation [44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2= [1 +
11986402 sin ℎ2 (119896119882)
4119864(1198640 minus 119864)]minus1 asymp
16119864(1198640 minus 119864)
11986402 exp(minus2radic
2119898lowast(1198640 minus 119864)
ℎ2119882)
(224)
For more complex barrier shape Wentzel-Kramers-Brillouin has simplified the
Schrodinger equation for tunneling probability of carrier which becomes[44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2asymp 119890minus2int |119896(119886)|119889119886
1198860 asymp 119890
minus2int radic2119898lowast
ℎ2 [119880(119886)minus119864]1198891198861198860
(225)
55
This means that the incident electron has a finite probability T of tunneling
through the potential barrier and this leads to the concept of tunneling probability as well
as a tunnelling current Therefore this becomes the basis of tunneling phenomena and
thus all devices which are related to tunneling can be modelled and analysed based on
this basic example The tunneling phenomenon is a majority-carrier effect and the
tunneling time is set by the quantum transition probability per unit time (which is on the
order of picoseconds) rather than the transit time concept [44 71] This enables the
tunneling devices to work at a much higher switching speed They can also be used in
high-frequency applications such as microwave circuit and high-speed oscillators
262 ASPAT Structural Parameters of GaAsAlAs materials System
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in this study
Conduction band profile
56
The core materials that make up the ASPAT diode in this work is based on
heterostructure of group III-V compound semiconductors Such materials are chosen due
their mature excellent properties and their band gap which can be tailored to fit the
desired design as well as to improve the carrier mobility In this work the primary layers
that form an ASPAT diode are very thin pure Aluminium Arsenic (AlAs) of thickness
ten monolayers buried in between dissimilar thickness of pure Gallium Arsenic (GaAs)
layers as can be seen in the red circle in Figure 214 above These two GaAs layers are
known as spacer layer which normally have a ratio of 401 or 201 in thickness The
asymmetrical spacers layer and the thin barrier in such arrangement lead to an
asymmetric current-voltage characteristics as proposed firstly by Syme and Kelly[15]
To examine and investigate this GaAsAlAs ASPAT structure in term of electrical and
RF characteristics the device have been grown according to Table 22 below
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work
Material Doping (cmminus3) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018 3000 142
Emitter GaAs (Si) 1times1017 400 142
Spacer GaAs Undoped 50 142
Barrier AlAs Undoped 28 283
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017 400 142
Ohmic Layer GaAs (Si) 4times1018 4500 142
Substrate GaAs - 650 microm 142
The arrangement of the multi-layers that form a lattice matched GaAsAlAs ASPAT
diode can be transformed into band structure profile view for easy understanding The
conduction band profile at equilibrium is as sketched in Figure 214 As can be seen in
the Figure 214 the ASPAT diode is generally a heterojunction multilayer structure
tunnelling diode
57
Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27]
The generic structure of ASPAT diode which is shown in Figure 215 above with a
schematic band structure comprises the following (starting from the top)
(1) A thick layer of heavily doped n++
about 4e+18cm-3
of GaAs with a thickness of
approximately 300nm
(2) An intermediate layer of lightly doped n-type about 1e+17cm-3
of GaAs with
thickness of approximately 40nm
(3) A spacer layer not intentionally doped (NID) GaAs with thickness of approximately
5nm
(4) An ultra-thin layer of NID AlAs with thickness of approximately 28nm
(5) A spacer layer of NID GaAs with thickness of approximately 200nm
(6) An intermediate layer of lightly doped n+ ~1e+17
GaAs with thickness of
approximately 40nm
(7) A thick layer of heavily doped n+ about 4e+18 of GaAs with a thickness of
approximately 750nm
Each layer has its own role For instance layer (1) and (7) are used as ohmic
contacts via connection to a AuGeNiAu metal stack This explains why they are
purposely heavily doped (gt 1018
cm-3
) for better low resistance ohmic contacts Two
intermediate layers (layers 2 and 6) are used to prevent the carrier in the contact layers
from diffusing into the undoped layers The two unequal length spacer layers with ratio
58
1198971 1198972 of about 401 are used as voltage arms to yield an asymmetric current-voltage
characteristic The asymmetry means that after a positive bias is applied from the long
spacer region an accumulation layer is formed and it is deeper than that formed by the
negative bias The thin layer positioned in the middle (Layer 4) is the tunneling barrier
The performance of a single barrier ASPAT diode can be optimised depending on
the applications by appropriate selection of the material system so that the band gap and
barrier height of such material can be modified Furthermore the mobility of electron
and doping concentration of the contacts region can be tuned The parameters to tune
during the growth for instant growth interrupt time and growth temperature will also
affect the performance of this diode The key layers that will affect the performance are
the barrier thickness and the two spacer layers enclosing it The study has shown that a
one monolayer change in thickness results in 300 change in in tunneling current for a
fixed voltage point[65]
The following discussions account for the effect of the main structure of the ASPAT
which is related to their performance
2621 Barrier Thickness and height
The probability of an electron tunnelling through a barrier depends exponentially on
the width and height of the barrier as well as the energy that is incident on the barrier[72
73] All these will affect the I-V characteristic of the ASPAT diode The tunnel current is
obtained by summing over all incidents electrons energies with tunnelling probabilities
through the barrier The tunnelling varies approximately as[74]
119879 prop 119890minus120581119889 (226)
Where d is the barrier thickness and κ is defined by the expression below
120581 =
radic2119898lowast(1198810 minus 119864)2
ℏfrasl
(227)
From textbook the tunnelling probability is given by
119879(119864) = 412058121198702
[(1205812 + 1198702)2119904119894119899ℎ2119870119897 + 412058121198702]frasl (228)
Where K is expressed as
59
119870 = radic2119898lowast119864
ℏfrasl (229)
Where ℏ represents the reduced Planckrsquos constant (h2π) E and m are the electron
energy and effective mass respectively Thus by inputting appropriate value into these
equations one finds that reducing the barrier thickness by one monolayer increases the
tunnelling probability by a factor of nearly three for every electron that tunnels through
the barrier As a result the current will also increase Further it indicates that the
tunnelling strongly depends upon barrier thickness and height By contrast the current
does not strongly depend on temperature
2622 Spacer Thickness
The reason for having two dissimilar undoped spacer lengths is mainly to avoid
diffusion of dopant to the barrier and subsequent layers during growth but in the case of
the ASPAT diode the spacer can also act as a voltage arm Varying the thick spacer
layer (1198971) results in the reverse current decreasing as the layer thickness increases and
varying the thin spacer layer (1198972) will affect the forward current which increases as the
thickness reduces To obtain appropriate asymmetrical I-V characteristics one needs to
maintain an adequate ratio between these two spacer thicknesses While a too thin
1198971 results in high leakage current at reverse bias a too thick 1198972 results in low forward
current One also needs to keep it thick enough to prevent carrier diffusion
These two spacers must be kept undoped or very low doped to allow the electron
moving in the electron mean free path region as it is clear from ionised donors Under
large forward bias an accumulation layer is formed between the spacer and barrier
segment and it is more noticeable compared to the accumulation layer that is formed if a
negative bias is applied
60
Figure 216 Conduction band diagram showing band bending and 2DEG formation at the L1
spacer
Consequently a triangular well is formed which creates an emitter 2D electron gas
(2DEG) population The electrons in this 2DEG occupy the quasi-bound states which
mean high excitation energy thus allowing the electron to tunnel through the barrier as
depicted in Figure 216
In term of RF performance it is important to highlight that a thicker spacer layer
will affect the depletion region which gets wider and thus will reduce the junction
capacitance of the device as per the following expression
119862 = 휀0휀119903
119860
119889
(230)
Where A is the area of the device d is the thickness of the main device structure which
consists of spacers barrier and well layers 휀0 is the permittivity of free space and the
relative permittivity of the spacer material is denoted by εr However the intrinsic delay
time will also increase and hence degrade the device high frequency performance
Therefore optimisation through spacer thickness requires trade-off between reducing
leakage current at reverse bias and degrading device junction capacitance
GaAs
GaAs
AlAs
2DEG
Γ
X
61
263 ASPAT Electrical Parameters
The classical approach in determining the current flow through an ASPAT diode is
by solving the Schrodinger and Poison equations Prior work had been done by Syme et
al in 1991 Due to the fact that AlAs barrier is very thin tunnelling is assumed to occur
at the Gamma valley ie AlAs bandgap= 283eV (rather than X valley)[18 75] and only
from accumulation layer (2DEG)[59] Here the DC characteristic of the ASPAT diode
can be calculated by solving Schroumldinger equation with the position vector represented
by z (in this case) Thus the equation is expressed as
minus
ћ2
2nabla
1
119898lowast(119911)nabla120569 + |119890|120593(119911)120569 = 119864120569(119911)
(231)
Supposing the current is uniform across x and y planes then this can be simplified to one
dimension Therefore the 1 D Schroumldinger equations becomes
minusћ2
2119898lowast
1198892
1198891199112120595 + |119890|(120595 minus ∆120595) = 119864119911120595
(232)
Where
120595 =
120569
exp (119894119896119911119911)
(233)
where ∆120595 is the correction term which reduces the effective barrier height The
Schroumldinger equation is solved using different values for Ez thus the quantum
mechanical current density in the z-direction is now expressed as[15]
119895119911 =
minus|119890|ћ
2119898lowast(120595lowast
119889120595
119889119911minus 120595
119889120595lowast
119889119911 )
(234)
It is different for a heavily doped contact which can describe as below the envelope
functions in the left and right contacts respectively can be described by plane wave
120595119897 = exp(119894119896119897119911) + 119877 exp(minus119894119896119897119911) (235)
120595119903 = 119879119890119909119901[119894119896119903(119911 minus 120580119873)] (236)
62
In this case the left contact covers the region zlt0 while the right contact covers the
regions zgt 120580119873 Equations (35 and 36) are then inserted into Eq (34) to form the
following expression
119895119911 =
|119890|ћ1198961
119898lowast(1 minus |119877|2) =
|119890|ћ1198961
119898lowast|119879|2
(237)
Where R (Ez) and T (Ez) are the complex reflection and transmission coefficients
respectively and they are solved by using the transfer matrix method This method has
been described in reference [56] The next step is to integrate the current in the z-
direction 119895119911 for all possible Ez values Thus the expression for the current density
becomes
119895119911 =|119890|119898lowast119896119861119879
2120587ћ2int(1 minus |119877|2)
infin
0
119897119899 |1 + exp (
119864119891 minus 119864119911
119896119861119879)
1 + exp (119864119891 minus 119881|119890| minus 119864119911
119896119861119879
|
(238)
The equations above are used to calculate the current density approximation from
the ASPAT main structure (two spacer layers and one barrier) only and based on
intraband tunnelling from the conduction band profile For real fabricated structure the
calculation must take into account both intrinsic and extrinsic elements of the diode
While the latter is mostly related to the pad and probe that is used to extract the I-V
characteristic the first element mostly comes from the epitaxial layer of the ASPAT
diode itself The ASPAT I-V characteristic is shown in Figure 217 which clearly
indicates nonlinear characteristics and thus can be used for detection applications
63
Figure 217 I-V characteristics of a fabricated ASPAT diode
2631 Intrinsic Elements of the ASPAT diode
In order to extract the intrinsic electrical characteristic of the ASPAT diode a
generic structure as shown in Figure 218 is essential Two main sources of contribution
to the electrical characteristics are the interfaces of each layer and properties of the
materials themselves
Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
64
The electrical current flowing from the top contact to the bottom contact will go
through each epitaxial layer producing a close loop Each junction interface limits the
current flow and sum up the total resistance resulting in what is known as the diode
series resistance (Rs) In the ASPAT main structure there is a junction capacitance (Cj)
due to the undoped regions surrounded by heavily doped contacts thus acting as a
parallel plate capacitor The fully depleted capacitance (Cj) of the diode can be
expressed as in Eq (230)
2632 Series resistance of the ASPAT diode
The total series resistance (Rs) of an ASPAT diode can be calculated based on the
finished fabricated diode structure In general Rs depends on three contributors namely
the non-uniformities in the contact metallization the un-depleted epitaxial layer (total
thickness) on both side of the heterostructures and the resistance caused by the
spreading current from the Mesa into the much wider second contact layer ie doped
substrate or 2nd
ohmic layer[76] In fact the contribution toward building up the total Rs
solely depends on how the structure is designed In this work two types of structures
were deployed namely lateral structures and vertical structures These will be described
in the next subsection
For both types of structures the series resistance (Rs) of the ASPAT diode consists
of aspecific Ohmic contact resistance (ρcA) contact epitaxial layer resistance (Repi-
Layers) and spreading resistance (Rspr)[33 77] where Rspr is influenced by the type of
structure The specific contact resistance is obtained from Transmission Line
Measurements (TLM) of the sample The theory of the TLM will be discussed in detail
in the next section The expression for the specific contact resistance is
120588119888 = 119877119888119871119879119908sinh119889
119871119879frasl
cosh 119889119871119879
frasl
(239)
Here Rc is the contact resistance LT is the transfer length (effective length) w is the
contact pad width and d is the length of the contact pad
65
Repi-Layer is the sum of all doped layers that sandwich the main ASPAT device For
each doped layer the resistance is given by
119877119890119901119894minus119897119886119910119890119903 = 120588
119871
119860
(240)
Where ρ is the resistivity which is given by 120588 = 1
120583119899119902119873119863 L is the epitaxial layer thickness
in cm A is the device area (emitter size) micron denotes the mobility of the electron q is the
electron charge and ND is the donor concentration The spreading resistance depends on
the structure design of the device This will be elaborated in detail in the following
section
26321 Vertical structure (doped Substrate)
The XMBE307 structures were grown on n+ GaAs substrate to provide the
simplest fabrication process The cross section of the finished single diode can be seen in
Figure 219 below
Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b and h are not
drawn to scale
66
At low frequency and in a mesa that is etched into a doped substrate material the
spreading resistance can be approximated by[76]
119877119904119901119903 =120588119904
2119889
(241)
Where ρs is the substrate resistivity and d is the ASPAT diode mesa length
However the spreading resistance is increased at high enough frequencies as the skin
depth (δ) in the substrate is much lower than the effective mesa length (d) of the diode
A new spreading resistance is then calculated also based on the assumption that the skin
depth is much lower than the chip thickness (h) but much larger than the mesa length
Thus the spreading resistance at high frequency is given by
119877119904119901119903(119891) =
120588119904
120587120575[05 ln (
119887
119889) +
ℎ
119887]
(242)
Where the skin depth (δ) is taken from standard planar formula and can be expressed as
120575 = [
2120588
(120583120596)]
12frasl
(243)
Where micro is the permeability and ω is the angular frequency During DC measurement
this type of structure requires having good suction on the stage for a good contact
However for small die (15mm times15mm) the suction sometimes is not strong enough to
provide a very good adhesion to the sample Therefore another type of ASPAT diode is
deployed which is based on the lateral structure by utilising semi-insulating substrate
and both contacts are connected to probes
67
26322 Lateral structure (Semi-insulating Substrate)
Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304) The dimensions
are not drawn to scale
In order to obtain accurate measurement results so as to avoid contact errors to the
substrate between stage and Device Under Test (DUT) a lateral structure as shown in
Figure 220 above is deployed This type of design offers many advantages ie it
provides a path for on-wafer RF measurement However the proper design has to take
into account the increase in RS due to improper attention to the spreading resistance
This spreading resistance is different from the vertical structure that was discussed
above In this case it is mainly caused by a gap at the bottom contact The gap in the
horizontal direction between epitaxial layer and metal at bottom contact is denoted as D
gap in in Figure 220 Therefore Rspr for the lateral design can be expressed as [77]
119877119904119901119903 =
1
120587120590119889119866119886119860119904ln (
119886
119886119898119890119904119886)
(244)
Where σ is the conductivity between two coaxial half-cylindrical electrodes with inner
(amesa) and outer (a) rectangular length or bottom ohmic layer which is given by (σ =1
ρ) a d and amesa are the length and thickness indicated in Figure 220 above Noticeably
68
the D gap will have direct effect on the outer length (a) of the device which is also
proportional to Rspr For high-frequency operation where the skin depth is less than
d(GaAs) σ becomes
120590(120596) =
120590(0)
[1 + (120596120591119903119890119897)2]
(245)
Where τrel =microme and micro m as well as e are the mobility effective mass and electron
charge respectively It is recommended that for high-frequency applications the device
series resistance must be as low as possible
Hence for both type of structure the ASPAT series resistance is calculated based on
all the above-stated resistances and these are set by
119877119904 =120588119862
119860+ 119877119890119901119894minus119897119886119910119890119903119904 + 119877119904119901119903
(246)
The total RS can be decreased by increasing the emitter area of the diode However a
large device will not able to reach millimetre and submillimeter wave region (THz) as
the capacitance will also increase (Eq 230) Therefore both parameters will have a
trade-off between them to be able to work at ultra-high frequencies
27 Characterization of Ohmic Contacts
The semiconductor Ohmic contact can be characterised using techniques that will
be described in the following section First is the Cox-Strack technique which is
specially designed to characterise bulk type semiconductor (thick) contact resistance on
two opposite sides The detailed description of this technique can be found in [78]
Second is a technique called Four Point Probe This technique was developed in 1954 by
Valdes etel [79] to characterise semiconductor resistivity It can also be used to
characterise the contact resistance for planar type devices As this research does not
cover this method the details of the measurement can be referred to [80] Finally the
most common method which is also extensively used in this research is the standard
Transmission Line Measurement (TLM) The details of this method will be explained in
the next section There are simplified versions of the TLM method which require just
one lithography step but are nevertheless very powerful in characterising and optimising
the contact resistance known as Circular Transmission Line Measurement (CTLM)[81
69
82] However in this research this is not to be covered as the standard TLM is already
adequate for planar type devices
271 Transmission Line Measurement (TLM)
The formation of metal and semiconductor interfaces will create a contact that
becomes very important for the characterisations of any fabricated device Additionally
it enables the quality of certain process flow to be determined This interface must be
evaluated by a technique known as the Transmission Line Measurement (TLM) TLM
which was first introduced by Murrmann and Widmand [83] in 1969 underwent some
refinements by Berger [84] in 1971 The theory of the TLM can be described by
constructing a TLM structure which comprises a set of metals contact pads placed in
series on a highly doped semiconductor layer as depicted in Figure 221 The structure is
designed like a series of the islands to permit current flow in parallel to the contact pads
[80] which is a direction defined by etched patterns Each contact metal pad behaves
like a MESA which has a thickness (t) and width (W) The distance between each metal
contact pads is defined by d1 the gap between two neighbouring contact pads which are
beneath each contact pad is defined as effective length LT This will allow current flow
in and out of the subsequent neighbouring metal pad The resistance elements that will
be extracted are RA and RB which sit under the contact and in between two metal pads
These two elements represent the sheet resistance under the metal contact pad area and a
sheet resistance of the material between two metal pads
Figure 221 A simple TLM structure with effective length and sheet resistance underneath
t L
T
LT
RA R
A R
B
dn
Probe Probe
Metal Pad
GaAs
MESA
70
The basic relationship of resistance R with respect to the size of the metal contact
or in the standard transmission line can be expressed as [44]
119877 = 120588
119871
119860= 120588
119871
119905 times 119882=
120588
119905times
119871
119882= 119877119904ℎ
119871
119882
(247)
Where ρ is the materialrsquos resistivity L is the length t is the thickness W is the width
Rsh is the sheet resistance and A is the cross-sectional area of the transmission line The
unit for ρ and Rsh are Ωm and Ωm2 respectively
The total resistance RT of this structure can be taken from the sum of the two
neighbouring padrsquos resistance RA and RB In order to relate with Eq (247) above this
RT will be substituted into Eq(247) to become
119877119879 = 2119877119860 + 119877119861 = 2119877119904ℎ119860
119871119879
119882+ 119877119904ℎ119861
119889119899
119882
(248)
As suggested in [85] RshA and RshB are assumed to be identical Therefore Eq(248)
can be reorganised into specific contact resistance RC and semiconductor sheet
resistance Rsh above as 119877119862 = 119877119904ℎ119860119871119879
119882 the new equation is then
119877119879 = 2119877119862 + 119877119904ℎ119861
119889119899
119882
(249)
The common practice throughout this research is to design a TLM structure that
has a ladder structure consisting of 10 metal pads with each one measuring to a size of
100microm width and 50microm length and the space between the first and second metal pad
5microm The gap is increased after the second metal pad by a further 5microm until ten metal
pads are completed produce a separation between the ninth and tenth pad of 45microm The
TLM ladder structure as depicted in Figure 222 is supplied by a constant current of
1mA at the very left and right metal contacts by two probes This allows the extraction
of RC (Ωmm) and Rsh (Ω) instantly from such structure The potential difference
between the two adjacent metal pads is measured by another two probes and the reading
of a voltmeter is recorded The total resistance is obtained by using Ohm law where
voltage is divided by current (VI) Another voltage reading is taken for the next two
neighbouring metal pads until the largest gap is reached The readings of (conversion
71
VI) which result in the corresponding resistance RT are then plotted against spacing and
the result can be seen in the graph in Figure 223
Figure 222 Top view of TLM ladder structure use in this work
Additionally in the measurement the voltmeter used in work has a very high resistance
Otherwise there will be leakage of current occurring through the probes and cables
Therefore the parasitic resistance of the cable or connector and the probe contact can be
ignored The key parameters that can be extracted from the graph will be discussed in
the next paragraph
Figure 223 Typical plot of resistance versus TLM spacing
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50Res
ista
nce
Rn (
Oh
ms)
TLM Spacing dn (um)
LT
d1 d
2 d
3 d
n
I (1mA)
V
V
LT
ME
SA
Su
bst
rate
72
The straight-line graph plotted in Figure 223 can be referred to Eq (249) and
this must be done by assuming the sheet resistance Rsh of the material is constant If the
straight line of the graph is extended up to initial gap (d=0) the intercept on the y-axis
provides the 2RC value To extract the 2LT further extrapolation is made until the
interception at RT = 0 is reached Therefore an important parameter which is the specific
contact resistance ρC can be found from this expression[85 86]
120588119888 = 119877119862119871119879119882sinh
119897119871119879
cosh119897
119871119879
(250)
Where l represents the total conductive semiconductor thickness The final part that can
be extracted from the graph is the slope of the line This is obtained by dividing the sheet
resistance with the width of the metal pad ie represented by expression (119877119904ℎ
119882frasl )
28 Basic Characterization Techniques and procedures
281 Measuring tools and apparatuses
The success of every experiment is determined by the backend results that are
obtained from the measurements It is important to choose an appropriate instrument
which will provide the required data for a valid and detail analysis Thus this section
will give a brief explanation of the measuring instruments and methods that were
exploited in this research The measurement apparatus systems that are available and
have been utilised in completing this thesis are ldquoset of DCrdquo and ldquoSet of RFrdquo
measurements The DC set measurement consists of room temperature and variable
temperature system This system is built to perform process monitoring during device
fabrication and it comprises of five main components
The fundamental component in the ldquoDCrsquos set toolrdquo is the Agilent B1500A
Parameter Analyser [87] used to provide fixed currentbias during testing The other
component is a Karl Suss PM5 Cascade Prober [88] which is used to receive fixed
currentvoltage and to supply its to the semiconductor contact via probe tip The PM5
Prober has at least four probe arms and each of them is fitted with ldquoneedlerdquo called probe
73
tip The size of the tip that is normally used here is 2microm and in some cases the tip size
of 1microm is also utilised The currentbias supplied to the sample must go through the two
of Source Measurement Units (SMU) namely SMU1 and SMU2 to ensure no mismatch
occurs between parameter analyser and diode All the testing are controlled using a
software called Integrated Circuit Characterization and Analysis Program (IC-CAP
2009) brought from Keysight Technologies[89] The software is installed on a standard
Personal Computer (PC) and the PC is connected to a General Purpose Bus Interface
(GPIB) to link with the B1500A Parameter Analyser This system can be organised
based on the purpose of measurements ie IV characteristics TLM Schottky Diode
and transistor as it is very flexible to change the configuration For examples
Transmission Line Measurement (TLM) configuration requires the addition of a digital
multi-meter and four-point probe tip while diode measurement just needs two point
probe tip without a digital multi-meter Figure 224 illustrates the measurement system
for a set of DC to test the TLM structure
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM
On the other hand the set of RF measurement consists of five block elements
configuration in the system namely the Vector Network Analyser (VNA) DC
sourcemonitor Cascade Microtech Prober SMU and Control PC via GPIB The RF set
Agilent B1500A
Parameter analyser
DUT
(TLM Diode
Capacitance)
Karl Suss
PM5 Cascade
Prober
PC
(MS windows 2000)
Digital Multi-meter
ICCAP 2014 Provide current
source
Measure and read the
voltage Stage and Probe
Signal
Current Source
SMU1 SMU2
General purpose bus interface
74
performs RF characterisation after the device fabrication is completed This system can
also perform DC characterisation as its basic instrument has this function too The VNA
machine used in this research is the Anritsu 37369A [90] which can perform the
Scattering Parameter (S-Parameter) measurement with a frequency range of 40MHz to
40GHz The DC sourceMonitor utilised in this experiment is the HP 4142B Modular
DC SourceMonitor [91] Both of these sub-systems are controlled by a standard PC
which exploits GPIB port to link them During operation the HP 4142B is connected to
the VNA by an internal bridge network and two SMUs to the Cascade Microtech Prober
which is then connected to the bond pads of the device It is identical to the set of DC
measurement where the SMU setting and data assembly are accomplished by IC-CAP
software package therefore the data that was obtained before and after completing the
fabrication can be compared This will enhance the validation of the data
However the stage and probes in both sets of measurement are different The
Cascade Microtech Prober has only two probe arms with each arm fitted with a 3-
fingers probe tip in the arrangement of Ground-Signal-Ground (GSG) as shown in
Figure 225 Each finger (pitch) is separated by 100microm thus to fit in with the pitch and
to reduce the mismatch in resistance the bond pad design must follow this separation
between each contact The GSG is configured by connecting the outer pads (Collector)
to the Ground probe tip while the inner pads (Emitter) are attached to the Signal probe
tip where the RF signal is sent and received through it Figure 226 shows the actual set-
up for RF measurement used in this research
75
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
Figure 226 Actual VNA system that was used for RF characterization
282 Measurement steps using a VNA
The RF measurement steps can be summarised in the following
- Step 1 Select or find the suitable VNA depending on applications
PC
(MS windows 2000)
ICCAP 2014
VNA
Anristru 32379A
40MHz to
40GHz
HP4142B
Modular DC
source
DC Bias Source
Cascade
Microtech
Probe Station
One 50microm pitch G-
S-G probe tips
Ground
SMU1
Cathode
Gen
eral
purp
ose
bus
inte
rfac
e
Lo
w P
ow
er H
igh P
ow
er
Cathode
Anode
SMU2
Ground
Ground
Signal
76
There are few factors that need to be well-thought-out before starting to use a VNA
especially for S-parameter measurements The factors are the availability of the VNA in
term of operational frequency and measurement port types air-filled metallic waveguide
or on-wafer Not all VNA can have an operational frequency for banded measurement
ie W-band Ku-band etc All these may require external signal sources to extend the
operational frequency
- Step 2 Properly setting up the VNA
The VNA can be set up depending on its application and the goal of measurement for an
instant number of point requires a desired frequency span IF bandwidth and the supplied
power level This very important to ensure the desired measurements are correct and
appropriate
- Step 3 Appropriate calibration system
In order to have a valid calibration appropriate calibration method has to be chosen
depending on the applications This will determine the accuracy and standards of
calibration As for on-wafer calibrations the de-embedding is normally used while for
the off-wafer the SOLR technique is more suitable to employ
- Step 4 Validation or verification of the calibration results
It is vital to validate the calibration results to ensure that the system has been properly
calibrated
- Step 5 Proper measurement
Proper alignment positioning and touching from probes tip to DUT is necessary to
guarantee a good repeatability and reproducibility of measurement results Normally
when positioning the probe an alignment marker is used as an aid By doing this similar
travel distance for the probes can be achieved The measuring plane will also be equally
well-defined
283 Measurement Practice and Flowchart
Essentially the device characterisation is performed in two stages ie during
fabrication as a process monitoring and after completion for data collection and
analysis Figure 227 shows the block diagram of a flow chart for testing a 15mm times
15mm wafer processing performance In the wafer processing after reaching the top and
77
bottom contactrsquos step the sample can be examined by measuring the TLM structure
according to the TLM procedure The measurement is conducted by exploiting a set of
DC measurement apparatus as mentioned above analogous to the TLM ladder structure
on the wafer surface Based on the TLM results the presence of any process issue during
the fabrication can be identified by examining the parameter such as contact resistance
and sheet resistance Thus a decision can be made either to proceed or to terminate the
fabrication should any issue is found early on As a result no materials will be wasted
further When a dielectric layer is involved Capacitance Dielectric measurement can be
tested This practise can be used to obtain the quality of the dielectric layer To connect
between a diode effective area and probe a bridge is requires It can be attached to the
diode emitter (to determine the diode size) to a bond pad for probe tip to touch This
bridge can either be left hanging in air or sticking to the isolated dielectric layer For the
GaAsAlAs material system the latter technique is preferable since it avoids issues with
the air-bridge which will be discussed in detail in Chapter 3 The opening area (via) for
metal connection can be checked by measuring the resistance on a special design pad
after a plasma dry etching step
Figure 227 Block diagram of the ASPAT measurement step
The next stage of characterising the device is the on-wafer diode measurement
which takes place after completion of all processing (including bond padsco-planar
pads) The work is carried out using the above set for RF measurement and employed
Ohmic Contact
Opening Via
TLM
Qualified
Device
Bad device
Dielectric
capacitance
Bonding pad DC and RF
Good
Good Good
Fail
Fail
Fail
78
purposely to access the DC and RF performance of each diode where the current-voltage
(I-V) characteristic and S-Parameter results are obtained In fact DC measurements are
first performed using a set of DC measurement and a rough IV characteristic can be
obtained to ensure the diode is working properly Usually the yield of any fabricated
device on 15mm times 15mm wafer in this research is between 70 to 90 In this research
the outcomes that will be discussed in the subsequent chapters are in term of the average
of measured values Thus it is very important to have a meaningful data to compare with
physical modelling and simulation in the future The diode IV characteristics are studied
by applying different DC bias at the emitter to collector terminals to extract its keys
parameters ie turn on voltage (supposedly zero bias) non-linear characteristic Rj RS
Cj etc
The device that has been measured by DC and having produced a valid result
will be marked for the next investigation ie the S-Parameter measurement This
measurement is executed using a similar system but with different probe types The
three fingers probe type is used and the device frequency response is measured via the
one-port network from the VNA The important parameters extracted from this
measurement are usually S11 (depending on how many ports are measured) Although
working devices are selected to measure accordingly there is a need to ensure the VNA
RF cable and probe tips are calibrated so that only valid data without errors will be
obtained A calibration technique called SHORT-OPEN-LOAD (SOL) is performed
prior to each daily measurement by exploiting a calibration sample with WinCal
software (Cascade Microtech)[92]
To avoid confusion it is worth mentioning that this technique used to calibrate
the device structure is different from what is used in SOL calibration to the equipment
Furthermore the de-embedding calibration is made on-wafer with the same substrate of
the actual device whereas the SOL is performed on a special calibration substrate
Normally the de-embedding results are not constantly automated with the VNA
equipment However the measurement is done separately starting with the special DUT
substrate then followed by the OPEN and SHORT de-embedding structures
79
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES
31 Introduction
This chapter presents in detail the general fabrication techniques for a generic and
development work of micron scale ASPAT diodes The discussions will focus on the
semiconductor growth technique used in this work ie MBE and the fabrication process
steps which include sample cleaning photolithography etching and contact
metallization These techniques are ample to build and deliver commercially marketable
fabricated structure Hence all photolithography techniques used to complete this
project are based on conventional i-line optical lithography which is adaptable to
industry and commercial purposes
The fabrication process in this work can be fragmented into two major works
firstly the fabrication towards reproducibility repeatability and manufacturability in
term of device structure process flow and DC amp RF characteristics This work will
involve relatively larger emitter area which varies from 15times15microm2 to 100times100microm
2 The
larger area provides for ease and fast fabrication as well as DCamp RF measurements
Once repeatability and reproducibility of the process flow and performance is confirmed
the second part of this work which is concerned with applications in millimetre and sub-
millimetre-wave then took place In this work small emitter designs varying from
2times2microm2 up to 10times10microm
2 were considered with appropriate measurement pads The
successful fabrication of smaller diode geometries in the second part of the programme
naturally leads to a further investigations to understand its epitaxial layer structure and
extracting intrinsic components ie junction resistance junction capacitance and series
resistance which will determine the device performance in high-frequency applications
The I-V characteristic is obtained from DC measurement which is usually performed at
room temperature Its results are then compiled and compared with advanced simulation
It is worth mentioning that all samples that are investigated in this project are grown by
means of MBE and the activities related to the epitaxial layer growth using MBE in the
University of Manchester were done by the Materials Growth Team (Prof Missous) and
the authors has no responsibility for this particular task
80
32 Epitaxial Layer Growth Techniques
Before discussing the principle of the common lithography technique it is
important to discuss the wafer growth technique as it comes first before the fabrication
The growth technique that is extensively used in this study as well contributing a lot in
the electronic semiconductor industry is Molecular Beam Epitaxy (MBE) The following
section will discuss the basic operating principle of solid source MBE
321 Molecular Beam Epitaxy (MBE)
The MBE technique was developed in the early 1970s [27] and is purposely used for
growing high purity epitaxial layers of compound semiconductors Such sophisticated
growth technique provides significant functionality ie precise control of the thickness
(to one atomic layer) and contributes to the growth of various types of complex
semiconductor multilayers high quality and advanced materials This level of control is
vital for an assortment of heterostructures devices that are being utilized as part of the
development of the advanced electronics devices especially for the ASPAT diode which
require 01ML control over the AlAs barrier to attain acceptable variability in device
characteristics Additionally the accurate doping profile and excellent junction
abruptness also can be achieved by using this technique
Practically the MBE system used in this work is a solid source MBE which
utilises beams produced by heating up various sources The sources can be Si Al Ga
As and other group III-V compound semiconductors When the crucibles which contain
the sources are heated atoms or molecules of the various elements are evaporated and
travel in straight lines paths like beams directed toward a target (heated and rotating
substrate surface) The condition of the vacuum during evaporation is ultra-high vacuum
(UHV) ~10-11
torr in order to have high quality crystals The substrate is heated and
rotated to provide good growth uniformity over large areas ( up to 4times4rdquo wafers) [93]
The growth rate in typical MBE growth is ~1ML second and can be controlled
by the source temperature in the crucible The abruptness at the heterojunctions interface
and switching of the growth compositions can be obtained by precise control of shutters
that are placed in front of the crucibles Therefore an abrupt junction at GaAs and AlAs
81
interface can be formed to realize the barrier in the ASPAT diode In order to monitor
the quality of the growing crystal and measure the layer by layer growth mode
Reflection High Energy Electron diffraction (RHEED) technique is utilised This
technique works based on the diffraction of electrons from the crystal surface [93]
Additionally given that the ASPAT current density is very sensitive to the barrier
thickness a study has been made using different growth techniques namely MBE and
Metal-Organic Chemical Vapour Deposition (MOCVD)[59] From this investigation it
was concluded that the percentage local variability of current density produced by MBE
grown diodes is better than those grown by MOCVD Thus in this study to get benefit
from its performance all wafers are MBE grown
33 Basic Principles of Common Fabrication techniques
This section covers the generic fabrication process which underpins
reproducibility repeatability and process optimisations for high-frequency applications
331 Sample cleaning
Essentially semiconductor processing requires a ldquoclean environmentrdquo to produce
devices The clean environment is classified according to how many ldquounwantedrdquo
particles are present in a cubic meter There are four categories of clean room available
in the industry Class 10 Class 100 Class 1000 and Class 10000 [94]
The fabrication of all ASPAT diodes in this project was performed in a clean
room environment of Class 1000 equipped with laminar air flow and filter system to
give Class 100 or better during processing Although the sample was processed in a
highly controlled particle environment there is still a high chance for a sample to get
contaminated when handled by a human Besides this the source of particle which
contributes to the contamination can be from the apparatuses and processing equipment
used in the laboratory themselves Thus the process of cleaning the sample wafer
surface before the start of each step is vital
Generally in a clean room the standard solutions that are used to clean a sample are
N-Methyl Pyrrolidone (NMP) Acetone Propan-3-ol (Iso-Propane-ol) (IPA) and
82
deionized (DI) water The sample which is cut up into 15times15mm2 size tiles is cleaned
based on the following procedures
1 Hot NMP- The sample is dipped into the solution at 80˚C for 10 minutes This
solution acts as an organic type of nature pollutants removal
2 DI water- acts as NMP remover The sample is then washed by flowing DI water
throughout the samplersquos surface
3 Acetone- to ensure any remaining NMP is completely removed from the sample
The sample is dipped into Acetone for 5 minutes in a low power ultrasonic bath
at ambient temperature
4 IPA- is used to remove the Acetone from the samplersquos surface The sample is
then dipped into the IPA for 5 minutes in a low power ultrasonic bath at room
temperature The use of low power for the ultrasonic bath is to avoid the sample
cracking or breaking
5 Once done the sample is then blow-dried using nitrogen (N2) gun to remove any
moisture coming from the IPA Fortunately it is easy to remove the IPA
completely from the sample surface given its higher rate of evaporation
Once all these steps are accomplished a visual inspection using a high magnification
optical microscope is conducted to ensure the sample surface is clean The cleanliness of
the sample is determined by the (lack) of particles or other spots (liquid mark) that can
sometime be observed during the inspection Obviously the lower the number is the
better the sample is as it is impossible to totally remove dirt especially marks
Sometimes it is hard to remove the particles in one go There is always a need to repeat
each cleaning step for a few times However this will not affect the sample in term of
electrical performance as the cleaning solutions used are non-destructive
332 Photolithography
Lithography or sometimes called pattern transfer is the most important step in
realizing microelectronic devices The designed geometry and dimensions on a quartz
glass plate called a ldquophoto-maskrdquo must be done prior to the fabrication process While
the photo mask can be designed by using various software tools in this work the design
83
is done via the Advance Design System (ADS) by Keysight The details of the design
which includes three different mask designs will be covered in Section 34 The mask
consists of the desired patterns (master) that can be printed onto solid materialrsquos surface
by means of an electrochemically sensitive polymer (photoresist) using
photolithography In fact this type of optical lithography technique can be performed
with and without a mask due to its simplicity It is also easy and cheaper compared to
other techniques such as x-ray lithography or Electron-beam lithography (EBL)
Although the latter is expensive it is still worth to have since it provides a higher
resolution which is preferable when developing sub-micrometre technology
processing[95] The special feature about EBL is that it does not need a mask to pattern
samples but can be produced by the movement of an electron beam point source and
hence writing the patterns directly on the surface
The ultra-violet (UV) based light sources are more popular among researchers
and development workers because they are cheaper and have modest resolution Usually
photolithography operates at wavelengths (λ) from 193 nm to 436nm The source that
provides the UV light is a Mercury (Hg) arc lamp which uses narrowband filters to select
single emission lines First is the i-line at λ= 365nm then the h-line which is of lower
resolution and has λ of 405nm and thirdly the g-line with a λ= 436nm[96] The
conventional optical lithography used in this research uses the ldquoi-linerdquo at a wavelength of
365nm For shorter wavelengths than these excimer laser or krypton fluoride laser with
a λ= 248nm and argon-Fluoride with a λ = 193nm are also used in the industry The
higher power levels enable higher productivity (throughput) while narrower spectral
widths reduce chromatic aberration provide better resolution and larger depth-of-focus
In this research all the fabrication process are done by utilizing a conventional optical
lithography (i-line) using a Karl Suss MA4 mask aligner Before starting any UV
exposure it is important to check the UV light intensity as it will affect the resolution
and thus desired device dimensions Therefore every corner that is exposed to the UV
light is calibrated to be at 09mWatt power exposure
The complete set of photolithography components consists of photoresist
(photosensitive polymer) photo-mask (chromium) which is used to block the UV to
form a pattern mask-aligner and developer (chemical solutions) Standard fabrication
84
process usually practiced at the University of Manchester starts with sample cleaning as
mentioned earlier Then the sample needs to go through heat treatment to remove all the
moisture with a temperature set to be 150˚C and bake for 5-10 minutes After having
cooled down the samplersquos surface is coated with a thin layer of photoresist via a
technique called spin-coating using a Laurell CZ-650 series spinner The spinning speed
is set depending on the type of resist ie 3000rpm for negative photoresist and 5000rpm
for positive photoresist The rotating speed of the spinner does not have much effect on
the coated photoresist thickness but will have consequence on the uniformity distribution
over the sample surface The coated thickness photoresist however depends on the
concentration of the specific photoresist Once spin-coated is done another short heat
treatment (1 minute) is required to ensure the resist is hard enough to contact a
photomask and to remove any excess solvent The temperature is set on the hot plate to
about 115˚C and 110˚C for positive and negative photoresists respectively
The important segments contained in the photoresist are a polymer (base resin)
a sensitizer and a casting solvent [97] The polymer will react by changing its structure
when exposed to the radiation While sensitizers will govern the reaction of the
photochemical in the polymeric phase the casting solvent will permit the spin-coated
application on the wafer surface The photoresist consists of positive and negative
photoresist both of which were used in this research Their basic difference is with
respect to the area that is exposed by UV light ie whether it will remain on the
semiconductor surface or will be removed In the case of a positive resist the exposed
area will be removed by the developer and the covered area will remain In other words
whatever is displayed on the photomask goes onto the sample surface On the other
hand for the negative photoresist the area that is covered from UV exposure will be
dissolved by the developer Figure 31 shows a 3D picture of both processes used in this
research
85
Figure 31 3D illustration of Optical lithography process used in this research
To obtain the desired pattern on the surface after UV exposure for a certain
duration the sample is required to go through a development procedure by using a
developer The developer is used to expel the dissolvable part of the photoresist after
being exposed to UV The usefulness of the developer depends on the photoresist ie
MF319 developer is specifically for positive photoresist while MIF326 is suitable for
negative photoresist Both types of developers will not harm the devices as they are a
kind of metal free ion solution Thus no free ion will change the characteristic of the
device The common practice in the clean room at the University of Manchester is to use
positive photoresist namely Shipley Microposit S1800 supplied by The Dow Chemical
and negative resist AZnLOF2020 (AZ2microm) which is supplied by MicroChem For the
S1800 series the thickness of the photoresist is determined by the last two digits ie
13microm thick for S1813 and 05microm thick for S1805 Both positive photoresists are used
Resist
GaAs
Dielectric
Photo Mask
Negative Resist Positive Resist
After Etching
86
mostly as protective area during wet chemical etching and as sacrificial dielectric layer if
higher temperature is applied ie 190˚C On the contrary AZ2microm which normally has a
thickness of 2microm is useful for patterning small dimension which leaves small gaparea
for the metallization process to fill It has good aspect ratio and useful in single layer lift-
off (post metallization process) In fact this type of resist can be thinned by diluting into
an Edge Bead Removal (EBR) solution and smaller device feature size can be obtained
The final dimension of certain devices (mesa size) is governed by the exposure
time the distance between photomask and samplersquos surface and the development time
The appropriate UV exposure time is required to avoid over-exposure which will cause
the spreading of light into the purportedly dark-field area[98] However the effect of the
exposure time differs between the photoresist types smaller opening area than the mask
pattern for negative resist and larger opening area for positive resist[45] The gap
between the photomask and wafer surface must be reduced as much as possible to avoid
the UV light going through the unwanted area To obtain a good gap value an applied
pressure from stage to the mask is required The normal pressure used in this research is
between 04 to 1 Pascal depending on the type of photoresist (negative and positive) as
well as its thickness Lastly the development time also influences the dimension of the
device Appropriate development time is required because ie over-development will
cause the polymerized photoresist to etch laterally resulting in bad patterned geometries
On the other hand under-development will cause non-uniformity in the surface after wet
chemical etching (positive resist) as well as causing lift-off problem (negative resist)
333 Etching Process
The etching process is a process of removing unwanted semiconductor layers to
define device geometry and isolate each individual device in one sample There are two
types of etching technique used in this research ie wet chemical etching and plasma
dry etching The wet chemical etching is based on Orthophosphoric(H3PO4) solution
which is a selective etchant to materials like GaAs InGaAs and AlAs The selective
etchant is referred to a solution that can etch away a specific semiconductor with a
specific etch rate The etch rate depends on the mixture ratio and concentration of the
solutions ie the higher the concentration the higher the etching rate In practice the
87
temperature humidity and epitaxial layer doping level also have an impact on the etch
rate Hence to minimize variation in the etch rate both temperature and humidity in the
clean room are constantly monitored and regulated Ambient temperature between 18degC
to 19degC is usually suitable while humidity is kept within 30 to 40 The advantage of
the wet chemical etching is that it is inexpensive controllable and with high throughput
highly selective and simple The mixture solution that is used in this work is
Orthophosphoric (H3PO4) Hydrogen Peroxide (H2O2) and Di-ionised water (H2O) with
ratios of 3150 3110 and 212 The ratio of 3150 provides an etch rate of about
600Aminute and is good to define the area and opening the under-cut in air bridges for
InGaAs samples[99] The 3110 ratio results with highly anisotropic shape but is easy to
control as the etch rate is about 1500Aminute for GaAs material system However the
212 etchant solution will provide extremely anisotropic etch rate of about
1000Asecond and is quite difficult to control For GaAsAlAs ASPAT diode it can still
be controlled since the thickness that needs to be removed is about 7000A (refer to
section 342 for details on the fabrication of ASPAT) Table 31 summarizes the etch
rate with different ratios and different selective materials Common to all the ratios
mentioned above are the isotropic side walls with lateral and vertical etch rate of 11
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and Ammonia on GaAs
and InGaAs materials
Material Etchant Ratio Etch Rate (Aringminute)
GaAs H3PO4H2O2H2O 3150 600
GaAs H3PO4H2O2H2O 3110 1500
GaAs H3PO4H2O2H2O 212 60000
GaAs NH4OHH2O2H2O 118 2000~3500
InGaAs H3PO4H2O2H2O 3150 850
The plasma dry etch is purposely run to obtain extremely high anisotropic etch
profile vertically and horizontally It can be done via mask with positive photoresist and
self-align mask which is metal contact as a mesa protector The precursors that are used
to etch away GaAs InGaAs and AlAs layer in this technique are Methane and
Hydrogen (CH4+H2) On the other hand Carbon Tetrafluoromethane (CF4) and H2 is
88
used in removing Si3N4 The etch rate is determined by how much power is applied to
the plasma to hit the sample surface the pressure inside the chamber and amount of the
precursor In this research plasma Technology is used for dry etching This machine
which is a conventional OXFORD INSTRUMENTS 1990 machine can produce an etch
rate on average of 100Aminute for an RF power of 100mWatt
334 Sputtering (dielectric deposition)
In this work a Kurt JLesker PVD 75 is used to deposit Si3N4 layer on the sample
surface The deposition rate depends on the RF power that is applied To avoid surface
damage on the sample surface a sacrificial layer formed by SiO is deposited using the
Bio-Rad Thermal evaporator before transferring to the PVD 75 to start deposition with a
low (75Watt) RF power Once the deposition time reaches 30 minutes the power is
increased up to 200Watt As a result good uniformity of the dielectric layer is obtained
335 Metallization Process Lift-off and Annealing
The metallization process is a process in which metal contacts on semiconductor
devices are created The purpose of this process is to make a proper interconnection
between the semiconductor devices to other parts of the circuit elements In other words
it is to connect the semiconductor device to the outside world This process will allow
the device to be examined electrically so that all electrical characteristics can be obtained
ie resistance I-V curve capacitance conductance etc The metal scheme used in this
process depends on the semiconductor material In the case of GaAsAlAs ASPAT
diode Gold-Germanium (AuGe) Nickel (Ni) and Gold (Au) are used However in the
case of InGaAsAlAs ASPAT diode the metal scheme used is Titanium (Ti) and Au
The technique used in this process is resistive thermal evaporation
The metallization process starts by cleaning all the metallic sources and boats
ie tungsten boat Au Ni and Ti metals by using Trichloroethylene Acetone and IPA
consecutively for 5 minutes each in a high power ultrasonic bath This step is very
important to reduce the risk of contamination during thermal evaporation Once done all
the metallic materials are dried using a high-pressure nitrogen gun and then dipped in
89
Hydrochloric acid (HCL) solution for 2 minutes to de-oxidize the metals so that it has
minimal effect on the series resistance of the ASPAT diode
Two types of thermal evaporators were used extensively in this study both
Edwards Auto 306 (one denoted as Junior Auto 306) The latter is used to deposit alloy
type of metals while the former is used for the non-alloyed type of metals In the case of
GaAsAlAs ASPAT alloy type metals are used while for InGaAsAlAs non-alloyed
metals are used The cleaned metals are then loaded in the thermal evaporators and
placed on a resistive tungsten boat Each metal is placed on its specific tungsten boat to
avoid unnecessary mixture during the evaporation
Figure 32 Actual picture of thermal evaporator used in this study
Prior to loading the sample into the evaporator a standard fabrication process for
ASPAT diodes takes place by patterning the samples with AZ2microm negative photoresist
At the end of this step an opening area is created for the metal contact to be filled and
connected to the ohmic contact of the semiconductor The sample is also deoxidised
using a mixture of HCL and water in the ratio of 11 prior to evaporation This has to be
done in a very short time in order to avoid re-development of the native oxide layer
Inside the chamber the sample is securely placed on a chuck upside down facing the
filled tungsten boat The distance between the sample and metallic source boat is about
90
40 cm Figure 32 illustrates the actual thermal evaporation system used in this study
The thermal evaporator chamber is pumped down to reach a minimum pressure below
1times10-5
mbar before vaporizing the metal It is important that the mean free path between
metal amp sample is created and each vaporized metal stick firmly on the samplersquos surface
The normal practice in this study is to keep the vacuum pressure under 1 times10-6
bar so
that better device performance can be obtained The amount of current required to melt
down the metal is between 4 Amps to 6 Amp This amount of current is forced through
the tungsten boat and generates very high heat melting down the metallic source and
vaporizing it towards the sample surface The deposition rate for each metal can be
monitored by using a built-in film thickness monitoring (FTM) on the thermal
evaporator which proportionally depends on the amount of materials deposited The
GaAsAlAs sample is started with deposit of 55nm AuGe 13nm Ni and 500nm of Au
The reason of depositing AuGe first is due to the fact that the ohmic layer of the
ASPAT only can only be doped with a maximum doping of 4 times1018
cm-3
which is not
high enough for good conductivity Thus here Ge atoms will diffuse into the GaAs and
replaces Ga atoms during annealing process leading to higher doping levels (gt1 times1019
cm-3
) and hence improved conductivity
3351 Lift-off
The use of AZ2microm allows for the exact patterning of metals without the need for etching
using a single layer lift-off technique The negative photoresist also provides an undercut
profile which will create disjointedness between the desired metal pattern (on the
semiconductor) and undesired metal (on photoresist) The process of getting rid of the
unwanted metal from a sample surface is called lift-off The process starts once the
evaporation process is accomplished The sample is soaked into 80˚C N-Methyl-2-
Pyrrolidone (NMP) solution for usually 20 minutes (fast lift-off process) In most
instances the sample is in NMP for more than 12 hours in ambient temperature (slow
lift-off process) as the NMP solution is not destructive to the sample In this solution
the negative resist will be softened and the metal part which sticks on it will also be
eliminated from the sample As depicted in Figure 33 the lift-off process for a single
device shows the usual photoresist undercut profile observed To ensure that NMP
91
residues on the sample surface are completely removed DI water is used to rinse the
sample which is then blown dry with a nitrogen gun
Figure 33 Single layer lift-off process using negative photoresist
3352 Annealing
The alloyed (AuGeNiAu) metal stack requires a thermal treatment called annealing to
improve the ohmic contact between metal and semiconductor The sample which has
deposited top and bottom contacts is loaded into an annealing furnace at a temperature of
420˚C for 2 minutes In the case of GaAs during thermal annealing Ge atoms penetrates
into the GaAs crystal for approximately 70nm-250nm depending on evaporated
thickness of the metal layers annealing temperature as well as time [100] In this work
the total metal thickness evaporated for each contact layer is around 500nm This
thermal annealing treatment will also melt down the Au if it is too thick and is subjected
to too long a heat treatment Therefore it is not advisable to do annealing after the
sample is coated with bond pad metals as it can result in short circuited devices
sometimes
Az2micro Negative
photoresist profile
after UV exposure
and development
Evaporation to
form metal layer
(AuGe Ni Au)
Desired metal
contact
Metallisation
process
Lift-off undesired metal
92
34 GaAsAlAs ASPAT Process Optimization
As mentioned earlier this section present details two major process flows of the
fabrication process for the ASPAT diodes which utilised three stages of development of
photomasks design namely a ldquoFirst generation mask designrdquo (1st Gen) a ldquoSecond
Generation mask (2nd
Gen)rdquo and a ldquoThird Generation mask (3rd
Gen)rdquo design The 1st
and 2nd
generations mask designs are the designs that were produced in the first stage of
this work to develop the fabrication process know-how and to get familiarized with the
actual fabrication techniques in the cleanroom The difference between the 1st Gen and
2nd
Gen masks is in term of the development towards realizing Air Bridges and
Dielectric Bridges which were mostly covered by the 2nd
Gen mask design The
analyses in term of reproducibility repeatability and manufacturability for process
control and current-voltage characteristic as well as ultimately RF measurement are
obtained on relatively large size devices via these two mask designs The large area
emitter dimensions range in size from 15times15 microm2 to 100times100microm
2
The 3rd
Gen mask design was designed based on the optimization of the 2nd
Gen
mask which was to realize ASPAT diodes that are able to work at very high operating
frequencies Therefore in such design the ASPAT devices have to have a minimal
amount of capacitance and low series resistance this is can be achieved by shrinking the
emitter size of the diode to the smallest area possible as well as optimising the
fabrication process ton reduce parasitics The smallest fabricated devices designed on the
new mask has an 2times2 microm2 MESA area which also includes Ground Signal Ground bond
pads for both device and de-embedding structures (open and Short) for RF
measurements
Before the commencement of any fabrications and designing any layouts on eg
Si GaAs InP etc the epitaxial layer must be grown first to a desired design In the
University of Manchester the epitaxial layer structures are grown using one of the two
Molecular Beam Epitaxy (MBE) machines which are either the RIBER V90H or the
V100HU system Both systems are managed by Professor Missous Epitaxial wafers or
sample grown by each system are identified by a prefix and numbers that are prefix
VMBE for the V90H system and XMBE for the V100 system The epitaxial layers are
93
grown on four-inch wafer diameter The maximum diameter that can be grown on using
the V100H is 8 inches but generally single 4rdquo or 4x4rdquo wafers are used The wafers are
then diced and cut using a diamond scriber into 15mm times 15mm tiles for easy handling
and fabrication in the D12 cleanroom lab in the University of Manchester
In this section the structures fabrication and performance of the various ASPAT
diodes for both repeatability and high frequency applications will be discussed further
The ASPAT is manufactured on wafer sample XMBE304 which is a GaAsAlAsGaAs
lattice matched to a GaAs semi insulating substrate is the main focus The ground works
on this ASPAT such as the initial design and fabrication process flow optimization had
been conducted by fellow PhD colleagues in the group led by Professor Missous at the
University of Manchester
341 ASPAT Devices used in Fabrication
3411 XMBE368 and XMBE307
Table 32 Epitaxial layer of Doped substrate samples
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~50
Spacer1 GaAs NID 50 50
Barrier AlAs NID 28 28
Spacer 2 GaAs NID 1000 1000
Buffer GaAs(Si) 4times1017
50 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~3500
Substrate GaAs (Si) Doped 50000 50000
These two samples were the first batch of diode structures used in this work and
were grown using the RIBER V100 MBE machine A great deal of work was expanded
to ensure that it is able to produce appropriate non-linear I-V characteristics The work
carried out including finding suitable fabrication process steps mask designs process
control limitations ie etching rates etc The results obtained from processing these
94
samples mostly on large area anode and cathode sizes and their analysis included both
growth profiles and fabrication process flows These samples were grown on doped
GaAs substrates As such the finished diodes were vertical structures and the fabrication
process has marked differences compared to undoped substrate samples While
XMBE368 had similar epitaxial layer profile to XMBE307 during growth the AlAs
layer was set to be stagnant (ie no-rotation of the substrate during growth) to
investigate the effects of slight variations in barrier thickness
3412 XMBE304
The next sets of samples were all grown on semi-insulating GaAs substrates
Table 33 details the epitaxial layer profile of sample XMBE304 the main work horse
of this research work The growth of this structure was performed on a multi-wafer
platen and consisted of 9 x 2rdquo wafers (from XMBE304A to XMBE304I)
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm
Epitaxial layer Material Doping(cm-3
) Thickness(Aring)
Emitter GaAs(Si) 4e+18
3000
Emitter 2 GaAs(Si) 1e+17
400
Spacer GaAs NID 50
Barrier AlAs NID 28
Spacer 2 GaAs NID 2000
Collector GaAs(Si) 1e+17
400
Collector 2 GaAs(Si) 4e+18
4500
Substrate GaAs(SI) Semi-Insulating
For a typical ASPAT structure the emitter is essentially highly doped to
4times10+18
cm-3
to provide accumulation of electron in the emitter contact region It was
purposely highly doped to also achieve low ohmic contact with the metal The spacers
are used to avoid diffusion of dopants to the subsequent layers The ASPAT structure as
mentioned earlier has a single AlAs barrier with a very small thickness sandwiched
between two different length GaAs spacer layers
Batch XMBE304 is the main focus in these studies All activities required for
repeatability reproducibility process flow and devices as well as qualifying new or
95
optimization fabrication technique for small devices and RF performance which were
then used for high frequency were based on the set of wafers grow in this batch
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability
As the new wafer structures have to be tested and evaluated to gauge the
performance of the ASPAT diodes their uniformity also needs to be tested so as to
ensure it exhibited fully functional diode with zero bias detection in minimal variation in
IV characteristics between diodes As described previously 4rdquo wafers are always diced
up into 15mm times15 mm size for ease of handling in the cleanroom and for masks cost
purposes
3421 Doped n+ Substrate Wafers
For wafers grown on n+ substrates (XMBE368 and XMBE307) a two-level mask
set is sufficient to complete the fabrication process In this case the devices are designed
with mesa structures and top metal contact on the upper surface of the wafer and a
bottom contact on the backside of the wafer One mask plate is used for defining the
mesa structure (wet etch) and the other mask plate is used for defining the metal pad
Since the mesa is relatively large (30times30microm2
to 100times100microm2) there is no requirement to
define bond pads for measurement purposes A prior RTD mask designed by fellow
colleague Dr Md Adzhar for his PhD work was used for processing the ASPAT diodes
as well in the first instance The detail fabrication process is summarized in appendix I
for the doped substrate wafers Figure 34 shows typical IV characteristics for 30x30microm2
emitter size diodes obtained from sample XMBE368
96
The I-V measurement was taken from two different tiles (15mm times15 mm) located
on top and bottom of a 4rdquo XMBE368 wafer The location 1 marked as a blue line in
figure 34 refers to a device on a tile taken from the top of the 4rdquo wafer while location
2 (red) refers to a device on a tile taken from the bottom of 4rdquo wafer At 07V the
separation difference in current is ~228 for both tiles This shows that the device in
tile 1 is less resistive than the sample in tile 2 implying that the AlAs layer for tile
located on the top corner of the wafer is thinner and thus allows more electrons to tunnel
through it at a given bias
3422 First Generation Mask Design (1st Gen)
-0015
0005
0025
0045
0065
0085
-15 -1 -05 0 05 1 15
I C
urr
en
t (A
mp
)
V Voltage (Volt)
Current vs Voltage (XMBE368_1) for 30x30microm2
MidLeft2
MidRight3
Figure 34 Current-Voltage characteristic of sample XMBE368 used
in this study at two different locations on the wafer tile
(a) (b) (c)
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2 diode dimensions
designed in the 1st Gen Mask
Location 2
Location 1
97
The fabrication of the GaAsAlAs ASPAT conducted in this 1st Gen mask is
followed the established generic process flow for InGaAs material which was done by
former co-worker Dr Md Adzhar Md Zawawi[101] The generic process flow is fairly
simple consisting of four mask steps as shown in Table 34 below The fabrication
process starts with the sample being cleaned in a NMP solution at a temperature of 80˚C
with Acetone and Propan-2-ol (IPA) The purpose of cleaning using NMP and Acetone
is to remove any organic material The IPA is used to remove Acetone residues
Table 34 Generic fabrication steps established by Dr Md Adzhar [101]
Step number Process
1 Top Contact
2 Mesa Etch
3 Isolation
4 Bottom Contact
In the 1st Gen mask the first step in fabricating the GaAsAlAs ASPAT diodes is
to use the first mask to define the emitter contact area The emitter has three different
sizes 100times100microm2 30times30microm
2 and 15times15microm
2 The lithography technique uses the
negative photo-resists AZ2micron with 55 second UV-photolithography to pattern the
top contact Then it is developed using MC319 developer to clear and define the
exposed area for the metals to stick to The sample is then subjected to plasma etching to
remove all organic residues and contaminants Then it is dipped into a mixture of
diluted Hydrochloric acid and water HCL H2O with a concentration of 11 for de-
oxidation This must be done in a short time right before the evaporation in order to
ensure good contact between metal and semiconductor surface with very low oxide
formation in between The ASPAT device performance depends on this step as contact
to the channel is by means of current flowing through the anode to the cathode terminals
In our lab the approach taken to achieve the Ohmic contact is by evaporation of Gold
Germanium (AuGe) Nickel (Ni) and Gold (Au) metals layers on top of the cap layer
Subsequently the metal is defined via a lift-off process using NMP
98
The next critical step is to define the MESA or island The mesa etch mask is
designed with two options with 05 microm or 10 microm tolerance The different mesa
tolerances are introduced to act as a safeguard for the emitter from producing excessive
undercut caused by lateral etching This step is to isolate and eliminate the unwanted
GaAs which will electrically link the active layers as many devices will be fabricated at
the same time on the same wafer tile (15mm times 15mm size) The lithography process in
this step uses positive resist and is developed using MC326 developer This step is
achieved using a wet etch process where a non-selective etchants mixture of
H3PO4H2O2H2O etches down the epitaxial layers until it slightly exceeds the AlAs
barrier with an etch rate of about 600Aring to 900Aring per minute The outcome of the MESA
or island step is the formation MESA active layers which are surrounded by inactive
layers of semi-insulating substrate (when using semi-insulating substrates)
The isolation mask is a step that is basically the same as the MESA etch step
eg using similar etchants mixture same lithography process but a different mask This
step is used to etch down until the GaAs substrate is reached which means that the
etching time is longer than that in the MESA etching step The purpose of this step is to
fully isolate the device from other neighboring devices hence ensuring no electrical
connection exists between each device within one sample Since these ASPAT diodes
employ an air bridge structure of size 1times5 microm the two minutes mesa etches will
simultaneously provide an initial undercut through lateral etching for the air bridge
formation
Based on the results so far obtained using the first-generation mask which
provided large mesa areas the current voltage characteristics of the ASPAT as far as the
non-linear zero bias is concerned did work very well However there was a need to
reduce the ASPAT mesa area down to very small dimensions to achieve mm-wave or
THz detection frequencies It is certainly a general rule for semiconductor device which
operate at very high frequency to have extremely small lateral dimension which
minimises the capacitance within the ASPAT device Furthermore for wider adoption of
the technology it is also important to develop a simple reproducible and low-cost
fabrication method for ASPAT diodes Details of this fabrication process are attached in
appendix II
99
3423 Second Generation (2nd
Gen) mask (ASPAT-GSG)
This work intended to enhance the 1st Gen-Large Area ASPAT photomask by
adding many features including 2 times 2microm2 mesa areas ground-signal-ground (GSG) bond
pads to enable RF measurement and three options device processing eg Air Bridge
Dielectric Bridge for semi-insulating doped substrate and dry etch-mesa Other reasons
for designing this mask was also to qualify process steps when deploying thin (1microm
width) bridge to connect small mesa area ASPAT diodes to the co-planar GSG bond pad
for DC and ultimately RF measurements
The mask was designed to fulfil the basic rules of fabricating various types of
tunnelling diode for instance RTD and ASPAT The diodes layouts were designed using
the commercial software Advanced Design Software (ADS) from Keysight
Technologies Ltd Once the design was completed it was ready to be sent to Compu-
Graphics Company for printing and patterned on a special chrome coated glass plate
The new 2nd
Gen mask design was termed ASPAT with Ground-Signal-Ground
(ASPAT-GSG) and consisted of two main designs ldquoAir Bridge and Dielectric Bridgerdquo
where each contained eight diodes with different emitter sizes (100times100μm2 50times50μm
2
30times30μm2 20times20μm
2 15times15μm
2 10times10μm
2 6times6μm
2 and 2times2μm
2) The Air Bridge
design is comprised of Design 1 (doped substrate) and Design 2 (undoped substrate)
This can be selected by changing the order of each individual layer of the mask steps
The same options are applied for Dielectric Bridge design which included processing for
doped and undoped substrates The details of the masks will be explained in the
following paragraph
(1) Air Bridge
Design 1 Contains five steps or layers mask of size 15mm times 15mm
suitable for air-bridge for undoped semi-insulating substrate
Design 2 Consist of seven layers steps mask of 15mm times 15mm size
There are 413 die chips in about 6mm times 6mm sizes in this design Figure 36 shows both
type of design for Air Bridge mask processing
(i) Mask 1- Top Contact
(ii) Mask 2- MESA
100
(iii) Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5- Collector Bond pad with GSG
(vi) Mask 2A-Dielectric
(vii) Mask 6A-Collector Bond Pad with GSG
(2) Dielectric Bridge
Design 1 Consists of seven identical steplayers masks with lateral
lengths of 15mm times 15mm each suitable for fabrication on semi-insulating
substrate
Design 2 Also has seven steps layers masked with dimension of 15mm
times15mm each suitable for doped substrate processing
There are 357 die chips in this type of mask design with an estimated size of 6mm times
6mm separately The smallest emitter size that is connected with a dielectric as the
bridge is 6times6microm2 The smallest 2times2microm
2 diodes was designed with the air-bridge
connected to the emitter bond pad due to the difficulties of opening viascavity for less
than 2 microm2 devices Figure 37 show both options for Dielectric Bridge mask processing
(i) Mask 1- Top Contact
(ii)Mask 2- MESA
(iii)Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5-GSG bond pad
(vi) Mask 6- Via Dielectric
(vii) Mask 7- Dielectric Bridge
(vii)Mask 5A- Via Dielectric
(ix) Mask 6A-GSG bond Pad
(x) Dielectric Bridge
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates
Figure 37 The layout of 1st design of Dielectric Bridge (green circle) mask design for 100 times
100microm2 emitter size with option for doped substrate processing
101
34231 Fabrication Process of the Air-Bridge Design
The fabrication using 1st Gen mask as mentioned in Section 3422 is less
complex however the fabrication process for Air-Bridge mask design contains a few
additional steps which are to add bond pads for the Ground-Signal-Ground radio
frequency (RF) layouts If the sample is on a doped substrate another layer needs to be
added leading to a total of six steps all together
Table 35 Standard process flow for Air-Bridge design fabrication
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa EtchDielectric
3 3 Isolation
4
5
4
5
Bottom Contact
Bond Pad
In this work the samples that have been processed so far are XMBE304
XMBE314 (GaAsAlAs base material system) and XMBE326 (InGaAsAlAs base
material system) All of them are built up on semi-insulating substrate thus the normal
process flow was followed Step 1 to step 4 follow exactly the same route as the 1st Gen-
ASPAT Large Area mask formerly discussed in Section 3422 This process is then
continued by spin coating AZ2microm on the surface Mask 5 is used to pattern the bond
pads The metallisation scheme used for bond pads is TiAu and the thickness must be at
least 1 micrometre thick This is to minimise series resistance at the pads and ensure a
robust surface is created when used for DC and RF measurements
342311 Air-Bridge Process Optimization
Since the Air Bridge design approach is focused more on developing air-bridges
which have a width of 1 microm and as the smallest device is 2 times2 microm2 the negative resist
(Az2microm) which was used in the 1st Gen design type was changed to Az1microm After spin
coating an Edge Bead Remover (EBR) is required to remove the beads at the edge of the
sample this is to ensure no gap is created between samples and mask when ldquohard-
102
contactrdquo is applied during the photolithography step The use of Az1microm and EBR are
critical to enable the fabrication of small air-bridges and emitter sizes
The exposure time during the photolithography technique also needs to be
increased to achieve a 1microm size air bridge A longer time than normal is required thus
95 seconds is used for exposure under UV light Once finished appropriate
development time must be applied to ensure the line for the air bridge is perfectly
opened for the metal to fill up To get impeccable result in this step both combination of
exposure and development have to be tuned naturally leading to trade off in both Too
long exposure and developing time will break the bridge whereas for too short exposure
time and developing the air bridge will not open
There are two types of etching method used in this fabrication wet
(H3PO4H2O2H2O) and dry (NH4H2) etching Both have their own advantages and
disadvantages Wet etching is faster than dry etching However the etching profile is
highly isotropic and causes serious undercut The smaller devices which have
dimensional sizes of 6times6microm2 and below will ldquoshrinkrdquo the effective area under the top
contact metal Even though dry etching can have highly anisotropic etching profile
which can prevent excessive undercuts it requires a lot of time for etching the
semiconductor layers The NH4 and H2 plasma that are used in this technique do not only
etch the GaAs and AlAs layers but also etch the metal contact at the same rate as the
semiconductors Thus the metal area must be covered with a photoresist or thicker metal
(~1microm) must be used to counter this issue Figure 38 shows that the emitter bond pad
which is not covered by the resist will eventually be etched away by the dry etching
Figure 38 Dry Etching for the first run in this study
As mentioned in section 333 the advantage of H3PO4H2O2H2O wet etching is
that it can be made using two solutions fast and slow The fast solution is based on a
concentration ratio of 212 while the slow solution is based on a 3150 mixture The
103
212 fast solution will produce good anisotropic etch profile but is tricky to control due
to the rather high etch rate of 1000Aring per second Both fast and slow wet etching
solutions being carried out in this experiment are replicated from successful recipes that
were developed by other co-worker from Prof Missousrsquos group
342312 Issue of Over Etch under Top Metal (Wet Etching for Air-Bridge
Design)
The first run using the solutions mentioned above started with the deposited
metal as a top contact (Top contact must be defined first to make a bridge) then Mesa
etching to remove ~7000Aring GaAs using the fast etch solution The next process to be
followed was to employ the slow etch solution to etch down the epitaxial layer to the
substrate Doing this ensured that air-bridge was open and the devices isolated
individually Unfortunately unexpected results were observed where large undercuts
still appeared for both 2times2 microm2 and 6times6microm
2 devices Figure 39 shows severe undercut
under the big device that can clearly be seen in the digital scope Most probably this
problem occurs due to excessive time used for the wet etching (10 seconds for fast
solution and 10 minutes for the slow etch solution)
Figure 39 Severe undercut of 2times2 microm2 and 6times6 microm
2 devices
The second run was employed to reduce the wet etching time in total thus dry
etching was needed As discussed above CH4 and H2 are used to etch away the GaAs
and AlAs semiconductor material while O2 is used to remove polymer residues To
reduce redundant generated polymer during dry etching the process must be separated
into several goes (runs) In this run at the mesa etch step the metal area is covered by
S1805 resist and then the plasma etches down until the heavily doped Ohmic layer is
reached For the isolation step the slow wet etching solution is used to ensure the
semiconductor under the bridge is removed The etching time is still long ie over 5
Zoomed Zoomed
104
minutes Hence this will still generate appreciable undercuts Although this run
managed to reduce the wet etching time it still did not solve the undercut Figure 310
shows undercuts under the effective mesa area still occurring in this run
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet etched
Further investigation has been made to find the root cause of this issue Scanning
Electron Microscopy (SEM) picture were taken to see deep into the completed devices to
investigate what is actually happening Figure 311 shows clearly that the semiconductor
under the bridge and effective area under the 2times2 microm2 device went missing The same
goes to for the large device where about half the size of the designed effective area under
to metal was also unintentionally removed by the solution
Figure 311 SEM Images of the GaAs sample
Since this work was also run together with an InGaAs based sample
(XMBE326) new knowledge regarding etching profile was acquired The lesson learnt
from this run is that the wet etch profile of the Gallium Arsenic (GaAs) material is
totally different from that of InGaAs Figure 312 shows the cross section of GaAs and
InGaAs materials after wet etching The evidences of these issues are also indicated by
the SEM images in Figure 313 and Figure 314 This more or less explained the reason
why the semiconductor under the top metal contact is always missing when wet
chemical etching is applied
Zoomed Zoomed
105
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in this study
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
Figure 314 SEM images for InP and InGaAs taken from [56]
Furthermore previous work done by co-worker Dr Md Adzhar Md Zawawi has
optimised the process for RTD samples based on InGaAs and InAlAs heterojuction
semiconductor materials In this work Dr Zawawi found out that achieving submicron
dimensions is possible when using the soft reflow technique on InGaAs[102] However
it does not apply to GaAs when using the same technique There are few reasons to
106
believe that the work that was carried out by the previous student is not repeatable to the
XMBE304 GaAsAlAs material The main reason is due to the much thicker Ohmic
layers used in the GaAs of ASPAT structures which requires longer etch time The
sample that was used in the previous submicron work namely XMBE277 (RTD) [101]
and corresponding epitaxial layer structure is attached in appendix III The thickness
needed to be removed for the MESA step is 1421Aring compared to XMBE304 (ASPAT)
which is ~6900Aring
The fabrication results shown from the Air-Bridge design does not seem
favourable to the GaAsAlAs heterojunction sample These include unreproducible IV
characteristics and excessive undercut under the metal Therefore the GaAsAlAs
ASPAT sample cannot be processed using this type of mask (Air-Bridge approach) The
fabrication efforts were then moved to the Dielectric Bridge design described below
342313 DC measurement
Fully functional ASPAT I-V characteristics were not obtainable in this run due to
severe damages caused by the undercuts that happened underneath the top metal contact
As can be seen from Figure 315 the behaviour of the current response suggests a very
leaky diode This confirms that the air bridge approach does not work with the
GaAsAlAs ASPAT diode
Figure 315 Short circuit behaviour on one of the fabricated device in this run
-0015
-001
-0005
0
0005
001
0015
002
0025
003
0035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
mp
)
Voltage (Volt)
30x30BP
107
34232 Fabrication Process of the Dielectric-Bridge Design
Since the Air-Bridge design was not successful an alternative Dielectric-bridge
process flow was then designed to solve this issue The first run in this Dielectric-bridge
process was performed to ensure that when the fabrication was completed it was able to
produce the correct and reproducible ASPAT current-voltage characteristics The
process flow in this run is to follow the initial design which identifies the steps according
to the mask number Step 1 to step 4 in the process are exactly the same as in the 1st Gen
mask design Step 5 which is the bond pad process is then continued with spin coating
the AZ2microm After exposure and development a TiAu metal scheme with a minimum
thickness of approximately 1 microm is deposited
Table 36 Standard fabrication process flow for Dielectric-Bridge design
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa Etch
3 3 Isolation
4
5
6
7
4
5
6
7
Bottom Contact
Bond Pad
Via Etch
Bridge
Step 6 is quite complicated compared to the other steps where the introduction of
S1805 resist is used as a dielectric layer to prevent short circuit between top and bottom
contacts This includes opening the smallest via (holes within the dielectric layer) of 2times2
microm2 and 6times6 microm
2 emitter sizes This step started by spin-coating the S1805 resist and
was then followed by baking it at 150˚C for 30 minutes The longer baking time is to
ensure it is hard enough to be deployed as a dielectric layer Once the S1805 had
hardened as dielectric layer the sample was then spin-coated again with S1813 (thicker
resist) on the dielectric layer to act as a mask for vias opening (to cover the dielectric
layer from via etching damages) After the S813 was developed O2 plasma etches was
108
applied to remove the S1805 that covered the top metal and bond pads The hole on the
metal was then exposed This required only two minutersquos plasma etches time
As soon as the holes were created within the dielectric layer a quick clean to
remove S1813 was performed using Acetone and IPA This has to be fast enough to
remove the S1813 without removing the S1805 dielectric layer Mask 7 then defined the
area for the metal that will fill up into the open vias This metal connected the top
contact metal of the device to the bond pad (GSG pad) The same metal scheme as
mentioned in Section 3422 was used as the bond pad
The fabrication using the dielectric bridge approach in the 2nd
Gen mask design
appeared to work successfully when initial I-V characteristics were taken and it also
showed that the ASPAT diode was fully functional However using hardened S1805 as
a dielectric layer is not a good practise for manufacturing device since there were left
over residue on the sample surface as depicted in Figure 316 This residue comes from
the non-uniformity of S1805 resit that was formed during heat treatment Therefore the
next run was to avoid using S1805 but replacing it with a standard dielectric layer based
on Silicon nitrite (Si3N4)
Figure 316 The surface of the sample after final processing
342321 DC measurements
Given that the process of qualifying mask steps for GaAsAlAs ASPAT diodes
looked promising using the dielectric bridge approaches initial I-V characteristics
measurements were carried out for XMBE304A Figure 317 shows that the I-V
characteristics are comparable to those of the other runs ie in the 1st Gen mask
Noticeably the IV characteristic (Figure 317) between each device size does not scale
109
on a single line This is attributed to the unintentional variation in the size of the emitter
during wet etching within each sample
Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2 2500 microm2 900
microm2 400 microm2 225 microm2 100 microm2 and 36 microm2
The current densities shown in Figure 317 are calculated based on a reduced
effective area of the devices by a factor of 08 This assumption is made as actual area
(without metal) is un-measurable Theoretically devices with small areas will have
higher resistances compared to larger devices However the opposite occurred in these
devices This problem is still under investigation It could be due to the spreading
resistance producing different values according to device sizes (smaller devices have
longer D while bigger devices have shorter D)
34233 Dielectric-Bridge Process Optimization (Si3N4)
Due to poor surface roughness of the sample when using S1805 as dielectric
layer this run was employed to improve the surface quality by using Si3N4 In order to
get the actual size of the emitter the processing needed to start by defining the
semiconductor area using either top contact mask or mesa etch mask and not to deposit
the metal first Smaller effective area will be obtained if the top contact mask is used to
define the area compared to the MESA mask since there are 05 microm and 1 microm tolerances
designed in the MESA mask
-000001
0
000001
000002
000003
000004
000005
-2 -1 0 1 2
Cu
rren
t D
en
sity
(A
mp
microm
2 )
Voltage (Volt)
Current Density vs Voltage
density36
density100
density225
density400
density900
density2500
density10000
110
Table 37 New arrangement of the mask number and step in Second Run
Mask Number Step number Process
3 1 Isolation
22A 2 Mesa Etch
4 3 Bottom Contact
6
1
7
5
4
5
6
7
Via Etch
Top Contact
Bridge
Bond Pad
The fabrication was initiated by isolating each device using Mask 3 to define
them individually Then MESA mask (Mask 2) was used to cover the area from wet
etching optical measurement were used to obtain the actual size of the emitter without
metal Figure 318 shows the process results after H3P04H2O2H2O etching for a ratio of
3150
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm Tolerance
Although the mask was designed with smaller size of 6times6microm2 using the slow etchant
solution the effective emitter size can still shrink to ~3times3 microm2 and ~2times2 microm
2 as can be
seen in Figure 318 The next step was to define the bottom contact using a metal scheme
that is suitable for GaAs ohmic layer ie AuGeNiAu After lift-off the samples were
then cleaned and spin-coated with AZ2microm Then the area was defined by using Mask 6
allowing the exposed area to be filled by Si3N4 which is the dielectric layer used in the
second run However a tricky issue happened here as the Si3N4 was difficult to lift-off
especially on the smallest emitter area in this mask In this run the lift-off process was
successfully done after three days Step five which uses Mask 1 was to define the top
111
contact The same metal scheme will fill up the tiny holes within the dielectric layer to
attach on the emitter semiconductor Figure 319 below shows an optical image of a
6times6microm2
device after the top contact lift-off process Once lifted-off annealing took place
to ensure Ge diffuse into the GaAs contact layer to lower the resistance
Figure 319 After lift-off processing
Step six uses Mask 7 to define the area of metal connection between active areas
to the bond pad In this step and step seven a different metal scheme from the top and
bottom contact was used to connect metal to metal Here a TiAu scheme was used The
final step (step 7) was to define the bond pad area In this context mask 5 is used The
bond pad requires thicker metal thickness to reduce the series resistance and to increase
the robustness of the metal surface when probed with needles during measurements
This second run of 2nd
Gen mask dielectric approach went well with better samplersquos
surface when using Si3N4 as the dielectric layer compared to the previous run using
S1805 Once the bond pad were defined for each device as done in previous run the
preliminary current-voltage characteristics of the Si3N4 run were obtained This is
described in the next section
342331 DC measurements
As mentioned in the previous section the Si3N4 run started with a defined emitter
area This allows actual ASPAT dimension to be measured thus the current density
versus voltage that are plotted in the following figures are based on actual measured
sizes
112
Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
Although the actual area of each device is obtainable from measurement the current
density of this sample does not scale well either Figure 320 show the current density is
not scalable from 03V to 1V This probably happened due to the same issue related to
the spreading resistance for each diode varying To investigate this issue new runs were
required with intention of reducing Rsprd and were expected to lead to more scalable
devices Therefore a study of reducing the spreading resistance (Rsprd ) due to
contribution of the large D-gap was carried out using the 2nd
Gen mask with the Si3N4
dielectric bridge approach The following section discusses in detail the steps used in
reducing the gap between the top and bottom contact for the GaAsAlAs ASPAT diode
34234 Dielectric-Bridge (Si3N4) Process Optimization by varying the D-Gap
The series resistance as discussed in detail in Section 26322 is generally due to
the total contribution of specific contact resistance in particular the diode size the sum
of all doped layer resistances that sandwich the main ASPAT layer and the spreading
resistance which comes from the lateral structure diode design[33] Thus in order to
acquire better performance at high frequency these contributors must be controlled One
parameter that can be controlled through this fabrication process is to reduce the
spreading resistance by controlling the separation between top and bottom contact ie
the D-gap as indicated in Figure 321
-000001
0
000001
000002
000003
000004
000005
-1 -05 0 05 1
Cu
rren
t D
ensi
ty
(Am
pm
2)
Voltage (Volt)
Current Density vs Voltage
D36
D100
D225
D400
D900
D2500
D10000
113
Figure 321 side view of lateral ASPAT structure
Without designing a new mask at this stage the same 2nd
Gen Dielectric-Bridge
mask was used but the process flows did not follow the sequence order of mask
numbers The reason for deciding not to design a new mask to reduce the D-Gap was
because the fabrication process flow had not yet confirmed it repeatability and
reproducibility Thus the available photo mask at that moment was fully utilised
Furthermore the feature of the 2nd
Gen mask that included the mesa tolerance can be
exploited in this study Hence the initial idea was to reduce the length of D by using the
tolerance that was designed in with Mask 2 (MESA etch mask)
Table 38 New arrangement for the Third run using Dielectric-Bridge mask
Mask Number Step number Process
1 1 Mesa Etch
3 2 Isolation
3
2
3
4
Bottom Contact
Mesa Cover
6
1
7
5
5
6
7
8
Via Etch
Top Contact
Bridge
Bond Pad
The process therefore was initiated by cleaning the sample and was then
followed by spin-coating it with S1805 to cover the emitter contact and define the actual
D-gap
114
size of the diode This first step used Mask 1 with wet chemical etching using the slow
solution (H3P04H2O2H2O etch with a ratio of 3150) Once the resist was striped
optical measurements were performed to obtain the effective area of the emitter Figure
322 below shows the smallest emitter area obtained after etching
Figure 322 The measured size of the emitter area and the length D (blue color marked)
Step two was to isolate the devices individually by using Mask 3 This was
performed using the fast etch solution (H3P04H2O2H2O etch with ratio of 212) This
took about 10 seconds to remove about 10000Aring of material
Step three which involved two masks was the most complicated in this process
Firstly Mask 3 was used to define the bottom contact by covering the sample with
AZ2microm and then the sample was hard- baked at 190 ˚C for 4- 5 minutes to ensure it had
totally dried before applying Polydimethylglutarimide (PMGI) The PMGI type used in
this process is Lift-off Resist (LOR) SF11 After spin-coating the SF11 at 7000RPM for
45 seconds it was post-baked at 190 ˚C for 4 minutes This was done to ensure that the
LOR SF11 was hard enough for the S1805 to stick on it This was followed by spin-
coating S1805 at 4000RPM for 30 seconds and exposing it under i-line UV for 20
seconds and developed using Micro Dev mix with DI water (11 ratio) for one minute
When the correct shape of S1805 was formed the sample was exposed under flood UV
for 15 minutes The SF11 was developed with 101A developer for 1 minute Figure 323
below summarizes the whole process in step three The step three processes concluded
by depositing the bottom contact with alloyed metal scheme and once lift-off had taken
place the next step continues as usual
115
Figure 323 Summary of LOR technique steps
Step four as well as the subsequent steps were completed in this run by copying
from the previous run (ie second run) which was to deposit the Si3N4 as the dielectric
layer and so on All the devices that underwent fabrication using this technique were
measured under optical microscope MC60 assisted by the Walsall software tool in the
lab From the measured value obtained it was expected that reducing the length of D in
this technique would improve the spreading resistance by up to 70 from the original
2nd
Gen mask design Table 39 summarizes the calculation of original spreading
resistance and improvement using this technique The calculation method and equation
are taken from Section 26322
Table 39 The outcome of the spreading resistance before and after using LOR technique
Device Size(microm2) D-original(microm) RSprd(Ω) D-new(microm) RSprd(Ω)
100x100 4 056 163 023
50x50 14 327 194 054
30x30 19 602 163 097
20x20 21 832 212 135
15x15 22 1007 202 18
10x10 24 1293 205 252
6x6 25 1643 230 418
116
Technically from the experiment in this run it was observed that the development time
also controlled the final length of D longer development time produced shorter D
lengths while shorter time yielded larger D gap lengths Therefore in this run the
development time was kept constant because of the desired D length from the mesa
tolerance in general is only ~2microm
342341 DC measurement
As usual when wafer processing was completed early DC measurement took
place to check the diodes performance Each diode size was measured and compiled
into one graph as shown in Figure 324 It is clear that the performance was better than
that in the previous run in term of scalability and current conductivity
Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
To compare the current conductivity from this run and the previous run current
density at 05V was measured for both 2nd
and 3rd
runs Assuming the contact resistances
(TLM) for both runs were constant for 50times50microm2 device size the improvement of
current in the 3rd
run is about 92 This showed that such approach to reduce the D-gap
-500E-06
000E+00
500E-06
100E-05
150E-05
200E-05
-2 -15 -1 -05 0 05 1 15 2Cu
rre
nt
De
nsi
ty (
Amicro
m2)
Voltage (Volt)
Den_100microm2
Den_225microm2
Den_400microm2
Den_900microm2
Den_2500microm2
Den_10000microm2
Den2_36microm2
117
was successful in this run A new mask design was ready to take the challenge for
processing toward millimetre and sub-millimetre wave application
343 Fabrication process of GaAsAlAs ASPAT diode toward High frequency
Applications
So far the information that can be gathered from previous processing is that the
optimum process flow is achieved through dielectric approach design The effort in
reducing the series resistance by lowering its biggest contribution was attained through
lowering the D-Gap in the structure Once everything had been optimized ie the
process flow series resistance junction capacitance etc it was time to develop a new
mask design which only focused on the development of small ASPAT devices for use in
the millimetre and sub-millimetre wave regions
3431 Third Generation (3rd
Gen) mask design
The 3rd
Gen mask design was developed by taking into the account every aspect
of parameters that can contribute to the device by means of robust devices that are able
to function properly at ultra-high frequency The device cut-off frequency is given by
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(31)
Here RS is the series resistance and Cj is the junction capacitance To obtain high cut-off
frequencies Rs and Cj must be kept as low as possible From the fabrication point of
view two parameters that can be directly and easily controlled are the device area (A)
and the D-gap (which contributes to Rs)
Therefore calculations were made to find the best option Table 310 shows the
calculated value of capacitance (eq230 in page 44) and cut-off frequencies (eq31
above) for the ASPAT diodes studied These two equations extract the cut-off frequency
of the ASPAT assuming no external effects and for fully depleted devices The
XMBE304 ASPAT sample is expected to be suitable for millimetre wave applications
if small devices are successfully made In real devices sub-millimetrewave operation
can be hard to achieve due to increased series resistance and other process related
parasitics
118
Table 310 DC and RF characteristics for XMBE304
Device Size (microm2) Fully depleted
Capacitance(fF)
Calculated Series
Resistance (Ω)
Fully depleted Cut-Off
Frequency(GHz)
10000 5490 04 72
900 490 15 216
36 198 7 1148
16 879 11 1646
4 22 29 2500
Therefore in the 3rd
Gen mask design the smallest device that can possibly be obtained
in the GaAs based material fabricated using i-line lithography which is available at the
University of Manchester is 2times2microm2 and the gap between top and bottom is 15microm at
least The connecting bridge technique applied only utilised dielectric bridge method for
GSG features Figure 325 shows the layout of actual 3rd
Gen mask used in this study
There are 344 die chips on this type of mask design It also includes the Ground-signal
ground pad with 50um pitch for each chip and six de-embedding test structures as well
as eight TLM structures
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and alignment mark
structures used in this study
119
This mask is designed generally from optimizations from 2nd
Gen Mask which
deploys a dielectric bridge for connection between the devices to the bond pads
Consequently the processing steps are not being much different but mostly follow what
is shown in Table 311 below The difference only applies to the much smaller mesa
size Other features included in this mask are de-embedding structures for RF
measurements via-hole test structure TLM structures and parallel plate capacitance test
structures
Table 311 3rd
Gen Mask process step
Mask Number Step number Process
1 1 Mesa Etch
2 2 Isolation
3
4
3
4
Bottom Contact
Mesa Cover
5
6
7
5
6
7
Via Etch
Top Contact
Bond Pad
The high frequency fabrication process flow is summarized in the following section
which shows illustrations in three dimensional and cross sectional (Figure 326) views
for easy understanding
34311 Step by Step Processing
0 Wafer preparation
Cleaning using NMP and DI
water or
Acetone and IPA
120
1 Mesa Etch
2 Isolation
3 Bottom Contact
4 Mesa Cover (Dielectric Deposition)
5 Via Etch
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 3110
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 212
Metal deposition with metal
scheme AuGeNiAu for
~500nm thick
Dielectric deposition 500nm
thick Si3N4
Via etch to open holes for metal
contact using reactive ion
etching using CF4
121
6 Top Contact
7 Bridge and Bond Pad
Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-insulating
substrate device type used in this study
Figure 327 Example finished process device with bond pad using 3rd
Gen mask
3432 TLM measurements
Transmission Line model (TLM) measurements for this run were carried out
after annealing (ie at 420˚C for 2 minutes) for process control monitoring by extracting
contact resistance (Rc) values These values are a measure of the quality of ohmic metal
contacts for a given process As discussed in Chapter 2 the TLM technique used four-
Metal deposition with metal
scheme AuGeNiAu for ~500nm
thickness and thermal annealing
420˚C for 2 minutes
Metal deposition with metal
scheme TiAu (1microm thick)
122
point measurement on TLM test structures located around the 15times15mm2 tiles as shown
in Figure 222 (in page 55) Normally five TLM structures are measured across the tile
for both top and bottom contacts Figures 328 and 329 display graphical TLM results
for top and bottom contact respectively As can be seen both graphs exhibit excellent
uniformity
Figure 328 XMBE304 TLM measurement for the top contact after annealing
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing
Based on the graphs above for the top metal contact the average contact
resistance (RC) value using the metal scheme of AuGeNiAu is found to be ~005Ωmicrom
and the sheet resistance (RSH) is 22Ω However for the bottom contact the average
value for contact resistance is 012Ωmicrom and sheet resistance obtained is 26Ω Both
values are in a very good agreement with the known doping of both ohmic contact
0
2
4
6
8
10
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins top contact
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins bottom contact
y = 02157x + 01053
123
layers Therefore the specific contact resistance (Eq 250) that contributes to the total
series resistance can be calculated and the value obtained is 15Ωmicrom2 and 54Ωmicrom
2 for
top and bottom TLM structures respectively
3433 DC characteristic measurements
Again once the wafer processing is completed room temperature DC
characteristics are taken using an HP 414B or HP500B parameter analyser and its actual
setup is as described in Chapter 2 This initial measurement was to ensure the
functionality of the diodes For this run using the 3rd
Gen mask the I-V measurements
for mesa active area of 4times4microm2 6times6 microm
2 and 10times10 microm
2 were taken and are depicted in
Figure 330 Figure 331 and Figure 332 respectively Nine diodes were measured for
each three device sizes to check their uniformity Thus the average current and standard
deviation are taken at two voltage steps of 1V and 15V Table 312 summarizes the
standard deviation for each measured data obtained from this final run
Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
4times4microm2 mesa size
-00005
0
00005
0001
00015
0002
00025
0003
00035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C01_4um_1P_SI
C22_4um_1P_SI
C40_4um_1P_SI
W01_4um_1P_SI
W22_4um_1P_SI
W40_4um_1P_SI
AI01_4um_1P_SI
AI22_4um_1P_SI
AI40_4um_1P_SI
124
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
6times6microm2 mesa size
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature
for 10times10microm2 mesa size
Table 312 Standard deviation at two different voltages
Device size (um2) Standard Deviation 1V () Standard Deviation 15V ()
4times4 14 14
6times6 65 72
10times10 44 39
Noticeably the standard deviation of the device increases for the smaller size
devices This trend happened probably because the active mesa area is not uniform
causing different series resistances Since the smallest mesa active area which achieved
-0001
0
0001
0002
0003
0004
0005
0006
0007
0008
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C02_6um_1P_SI
C23_6um_1P_SI
C41_6um_1P_SI
W02_6um_1P_SI
W23_6um_1P_SI
W41_6um_1P_SI
AI02_6um_1P_SI
AI23_6um_1P_SI
AI41_6um_1P_SI
-0005
0
0005
001
0015
002
0025
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C03_10um_1P_SI
C24_10um_1P_SI
C42_10um_1P_SI
W03_10um_1P_SI
W24_10um_1P_SI
W42_10um_1P_SI
AI03_10um_1P_SI
AI24_10um_1P_SI
AI42_10um_1P_SI
125
a good I-V characteristic is 4times4microm2
in this run these devices were used for the next step
of characterisation which is the S-parameter measurement to extract their behaviour at
different frequencies
35 Conclusions
In this chapter basic fabrication techniques of GaAsAlAs ASPAT on both doped
and semi insulating substrates using standard I-line lithography as well as step by step
descriptions to achieve reproducibility in the process fabrication flow has been
demonstrated with relevant initial measured results Two major outcomes have been
demonstrated firstly related to repeatability reproducibility and manufacturability
mostly done on large device areas (15times15microm2 to 100times100 microm
2) Secondly a successful
process flow for small emitter size devices (2times2 microm2 to 10times10 microm
2) has been
developed
Subsequently two types of designs during process optimization were developed
namely Air-Bridge and Dielectric-Bridge approaches The latter approach seems
favourable for GaAsAlAs materials but was only successful when reducing the series
resistance of the device This problem was addressed by optimising the D-gap between
top and bottom contact which resulted in good scalability of each ASPAT dimensions
improving current conductivity by 92 and achieving a reproducible process On the
other hand in the former approach issues were encountered with over etching underneath
the diode effective area and thus it was hard to achieve reproducible devices
Repeatability reproducibility and manufacturability fabrication processes based on
dielectric bridge method were successfully developed This new process provides a
highly efficient and economical solution for the fabrication of GaAsAlAs ASPAT
diode Emitter sizes down to 4times4 microm2 dimensions are routinely and reproducibly
achieved in this process Series resistance which is an important parameter in
determining high frequency application are greatly reduced by changing the gap between
top and bottom contact
With all the new improvements implemented the possibility of the proposed Dielectric
Bridge method fabrication process was successfully applied for the fabrication of
ASPAT diodes
126
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT
DIODE USING SILVACO
41 Introduction
Fabricating any device or circuit requires a lot of time resources cost etc
especially elements related to the production of semiconductor devices Furthermore in
realising such a device a clean room is required Hence fabrication and processing in
wafer fab need full attention to get it done with a higher rate of success reproducibility
and manufacturability One solution that can be highlighted which will be able to reduce
all the resources that are mentioned above is by using computer simulation approaches
or to be precise physical modelling For epitaxial layer based devices physical
modelling is a good choice as it would give a better understanding and insight into each
layer and how electrical characteristics are derived A software that is most suitable for
epitaxial layer physically modelled is SILVACO This software is a very comprehensive
tool to simulate epitaxial based devices and to predict their behaviour Such software
covers many aspects starting from the first principles of physic epitaxial layer
definition as well as device layout thus making it the most powerful virtual wafer fab
tool in the market
In this chapter the SILVACO packages are discussed The discussions include the
method of defining a new material defining models and constructing the AC or DC
supply to obtain the output characteristics of the virtual device Apart from these the
focus will also be on the ASPAT diode modelling simulation and analyses of the results
which will include the ASPAT structure suitable models and DC current-voltage
characteristics The dependencies of individual structure on the I-V curves will also be
highlighted Finally the discussion of results and analyses involving a range of
operational temperatures dependency as well as from comparison made to conventional
SBD used in this study will be examined
127
42 SILVACO modelling Tools
SILVACO is a modelling software introduced in 1984 by Dr Ivan Pesic It is
purposely created for electronicsrsquo devices physical modelling and characterization This
software company has become the major supplier for most of the Electronic Design
Automation (EDA) for circuit simulation amp design of analogue Mixed-Signal and RF
circuit market This Technology Computer Aided Design (TCAD) software can predict
the simulated device performances starting from first principles It has a package which
can provide Virtual Wafer Fabrication (VWF) simulation to the device designer and
which has the capability to perform two or three dimensional physical device modelling
by using the ATLAS simulator [103] SILVACO allows all parameters such as
electrical thermal and optical characteristics of a device to be simulated under desired
bias conditions It offers cost effectiveness as well as quick prediction of results for
many semiconductor devices compared to real experiments Some hands-on experiment
may not always perform hence SILVACO can be used as an alternative
The core of SILVACO is Atlas itself which provides a platform to perform DC AC
and transient analysis for such dimensional device structure regardless of the
heterojunction material type ie binary ternary quaternary etc As the brain of
SILVACO Atlas which receives input command files containing instruction text for
execution from a runtime environment known as Decbuild will process the instruction
text and display progression error and warning via Runtime Output All the calculations
of the resultsoutcomes of the simulation are plotted via a tool called TonyPlot which is a
tool to visualise the output Figure 41 below shows how precisely the physical
modelling takes place the process of building the structure how its parameters and
variables are defined how an appropriate model statement is selected how performance
is analysed and lastly how the outcomes are displayed
128
Figure 41 SILVACO Atlas simulation process flow
As can be seen in Figure 41 the structure specification statement is used to define
any desired structure by setting the command in Deckbuid of the following parameters
a) Mesh where the structure can be defined either in 2D or 3D Cartesian grids The
unit of the coordinates used is in microns and the spacing parameters which
define the netting size can be used to improve the accuracy of the analysis at any
given position The density of netting size in this statement determines the
processing time
b) Region where the multi-layers in a structure are defined and this statement has
to outline each layer that represents a separated region independently The mesh
must be assigned to a region and the sequence of the region is arranged from low
to high
-Mesh -Region -Electrode
-Contact -Material
Structure Specification
-Model -Interface
Model Specification
Method
Numerical Method
-Log -Solve -Load -Save
Solution Specification
-Tony Plot
Display Results
129
c) Electrode are used to define the location of bias point for a designed structure
when performing the electrical analysis In this work or for the case of a diode
two electrodes are allocated as an anode and a cathode In a vertical device the
latter electrode is placed at the bottom of the device while the anode is at the top
d) Doping this statement refers to doping concentration injected into the desired
region and it normally depends on the material types
e) Materials since SILVACO was developed specifically for Silicon-based devices
default parameters are set up for Silicon properties However the use of
materials statement allows SILVACO to run for different material ie GaAs
InGaAs etc In order to make it work this parameter is defined first and then
followed by the material name and its properties such as bandgap permittivity
conductionamp valence band discontinuities mobility etc
The most crucial part is to determine whether the simulated structure of a particular
device is correct or incorrect This is done by properly choosing the specific model
statement The Specific model statement is employed to express the physic equations
that are used during the device analysis The models statement depends solely on the
structure definition Examples are device structure with double barrier use Non-
equilibrium Green function (NEGF) model and single barrier uses Semiconductor-
insulator-Semiconductor (SIS) model for effective and accurate analysis process For the
case of a single barrier in SILVACO there are many model statements that can be used
for such analysis Therefore it is recommended to check model by model in order to
ensure that all the needed parameters are defined in the material statements and results
produced are valid
SILVACO is able to calculate such models by using different numerical methods
which means semiconductor device problematic is computed to make successive
solutions by random discretisation There are three different numerical methods that are
regularly used by SILVACO to perform its calculations which are Newton Gummel and
Block Basically this is solved by using a non-linear iteration procedure which begins
from an initial guess and which then uses an iterative process to find the predicted
solution The detail of these can be found in reference [103]
130
In order to turn on the problem solution the solution specification is defined This
include log solve save and load statement All these work together to provide data for
analysis by other functions The log statement is a file type that saves in memory and can
be loaded by Atlas Any solved device will be stored in the log file Therefore it is
necessary to define the LOG before SOLVE statement and close it after the calculations
While the save statement is used to store all data point to a node in the output file the
load statement is utilised to recall all the saved data to be read by Atlas
Finally all these files can be displayed or plotted on TonyPlot it is recommended to
make SET files at plotting point for a better visualisation The plotted or displayed files
in TonyPlot can be manipulated for scaling graphs overlaying different curves and most
importantly to export the data to other files formats
43 SILVACO Implementation GaAs AlAs ASPAT Modelling
The structures play an important role in determining the terminal output
characteristics Therefore to start simulating the ASPAT device the first thing that must
be specified is its structure As mentioned earlier in Section 3412 the ASPAT diode is
a top down multilayer structure This structure which is adopted from that of Section
3412 will be used as a basis to perform the ASPAT simulation Figure 42 shows the
structure of the ASPAT in this real simulation which is exactly the same as been
discussed in Section 26322 The ASPAT diode consists of two heavily doped (up to
5x1018119888119898minus3) GaAs contact layers on top and bottom slices adjacent to lightly doped (up
to 3x1017119888119898minus3) GaAs intermediate layers In between these layers is a sandwiched
structure consisting of two different lengths of undoped GaAs spacer layers and a thin
layer of AlAs that act as a tunnel barrier In this work the simulation result will be
compared with the fabricated measurement result depending on the size of the diode
The actual device that will be used to validate the simulation is the main device used in
this study (XMBE304) which is based on a lattice matched GaAsAlAs grown on a
semi-insulating substrate Therefore the design structures that are proposed in the
fabrication are compatible with the fabricated devices and are based on lateral structures
as can be seen in Figure 42
131
Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the diode
multilayer heterostructures on the right
In the consequent simulations a key observation regarding the AlAsGaAs
heterojunction is that there are two types of tunnelling processes direct tunnelling and
indirect tunnelling Figure 43 shows the Energy-Momentum (Ek) diagram depicting the
three valleys for the AlAs conduction band namely L Γ and X points In normal
circumstances the transition of electrons happens to the X-point which is the lowest
energy in the conduction band In the case of very thin barrier the tunnelling process
occurs at the Γ point in both AlAs and GaAs materials which is the direct tunnelling
process[18] It has been reported that in the case of an ASPAT diode tunnelling which
occurs at the Γ point will be the dominant component in the tunnelling current
Therefore the actual band gap will be different from the one at the X-point which is
which 216eV[15] By contrast the energy band gap at the Γ-point is around
283eV[104] Thus this simulation uses this band gap value
Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor
216eV
Γ
X
E
K
L
AlAs
CB
VB
283e
132
The simulation code as attached in Appendix IV and the output of the simulation with all
the input mentioned above are shown in Figure 44 (a) and Figure 44 (b) Figure 44 (a)
is the band diagram at equilibrium and Figure 44 (b) is the band diagram when a bias is
applied
Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure (b) the
energy band diagram of the ASPAT diode structure when under three different biases
44 Simulation Result and Analysis
Basically the SILVACOrsquos Atlas simulation package is used to calculate the I-V
characteristics from multilayers structures In the case of GaAsAlAs heterojunctions all
details of the structure as shown in Figure 44 above are calculated based on solving the
Schrodinger time-independent equation in each layer taking into account the variation of
effective mass and conduction band offset between GaAs and AlAs
For thermionic emission and tunnelling mechanism across an abrupt heterojunction
interface the general method used in SILVACO is taken from K Y Yang work [105]
The tunnelling current of the ASPAT diode uses the equation below[74]
119869 = sum2119898lowast119864119894(1 minus 119877)119896119879
1205872ħ3
119873
119894=1ln [
1 + exp (119864119865 minus 119864119894
119896119879)
1 + exp (119864119865 minus 119881 minus 119864119894
119896119879)]
(41)
Where m is the electron effective mass E denotes the energy of the electron R is the
total resistance k represent Boltzmann constant ħ is the reduced Planck constant EF is
the fermi level V is applied voltage and Ei is the electron energy perpendicular to the
-2
-15
-1
-05
0
05
1
15
1
82
16
3
24
4
32
5
40
6
48
7
56
8
64
9
73
0
81
1
89
2
97
3
Ene
rgy(
eV
)
Thickness (microm)
VB
CB
133
barrier The important parameters that enable SILVACO Atlas to perform correct
calculations and analysis are the choice of appropriate models The suitable model that is
available for evaluating the GaAsAlAs ASPAT is based on the Semiconductor-
insulator-semiconductor (SIS) model
Thus in this run Non-local Quantum Barrier Tunnelling Model (SISEL and
SISHO) are utilized specifically semiconductor-insulator-semiconductor mode This
model enables the tunnelling current between two semiconducting regions separated by a
quantum barrier to be calculated [103] It is assumed that the charge tunnels across the
whole barrier with the source or sinks at the interface with the semiconductor regions
Under the Non-Local Quantum Barrier tunnelling model another model that can be used
is semiconductor-semiconductor-semiconductor (SS) tunnelling model if the materials
are specified By correctly inserting all parameters with the right model an excellent DC
IV characteristic match between simulation and measurement can be produced as shown
in Figure 45
441 DC Current-Voltage Characteristic
In this simulation the current at each bias step and each mesh point can be set up by the
user however the detailed calculation such as formula usage methodology and
approach that is adopted by SILVACO Atlas is unknown As mentioned above in order
to produce the energy band diagram of the ASPAT the DC characteristic of the structure
can be solved by using the Schroumldinger and Poisson equation self-consistently
To ensure that these simulations are valid one fabrication was performed on an
ASPAT diode sample XMBE304 For this sample the structure parameters are the
same as has been set in this simulation The result of the measurement and simulation
are then compared Figure 45 shows that the simulation result is in excellent agreement
with the measured data for this sample
134
Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm2) and (4times4microm
2)
using SILVACO Atlas simulator for structure device XMBE304 showing excellent agreement
between simulated and experimental data
These fitted results were performed on both a large 100times100microm2 device and the
smallest obtainable from fabrication (4times4microm2) which was to be used for the repeatability
amp reproducibility studies as well as for high-frequency applications study respectively at
room temperature In order to get a good fit a few parameters had been modified in the
SILVACO software via the Deck-built tool for example energy band effective masses
and bandgap discontinuity of GaAs spacer and AlAs barrier (The mentioned parameters
values are summarized in Table 41) The percentages of bandgap discontinuity in
SILVACO using the ALIGN parameter is given by[103]
119860119897119894119892119899 =
Δ119864119862
Δ119864119862 + Δ119864119881
(42)
Where ΔEc and ΔEv are the conduction band discontinuity and valence band
discontinuity respectively The m0 in the tables denotes the electron rest mass Once all
agreement between measurement and simulation has been met the simulation is then
carried out with structure analysis at room temperature and different temperatures
simulation
Table 41 The parameter values used in this simulation
Material Bandgap(eV) ΔEg(eV) Effective mass(kg)
GaAs 1424 03 0067m0
AlAs 2835 071 0126m0
-00002
0
00002
00004
00006
00008
0001
00012
-2 -1 0 1 2
Cu
rre
nt
I (A
mp
)
Voltage V (Volt)
Current vs Voltage
Measurment
Simulation
135
45 Structure Analysis of ASPAT Diode
Once the device structure was modelled and having successfully produced a
precise band diagram as well as validated the simulation results with experimental I-V
characteristics the next step is to further analyse the relationship between basic device
structure and its I-V characteristics This approach is used to predict what would happen
to the DC output if some of the parameters were varied especially with regards to the
AlAs barrier thickness In the subsequence simulations the thickness of each main
ASPAT (unequal spacers and barrier) layer will be studied independently as a variable in
order to determine how each parameter affects the I-V characteristic in both magnitude
and curvature The analysis will also include manufacturing tolerance where the
structure parameter which will result in a 10 difference in their I-V characteristics is
examined[59 75] This will provide an overview of how precisely to manufacture each
layer of the device The following simulation is based on the XMBE304 structure with
emitter size of 4x4microm2
451 Dependencies of current on AlAs Barrier thickness
Since the AlAs barrier is what limits the transportation of electron flow and
hence the current (which depends exponentially on the tunnelling barrier thickness)
therefore the first analysis to run on the simulation is the variation on barrier thickness
In the simulation the barrier thickness is measured in term of the monolayer Generally
one monolayer can be calculated by dividing the lattice constant of the material by two
In the case of AlAs one monolayer is calculated as follows
119900119899119890 119898119900119899119900119897119886119910119890119903(1119872119871) =
119860119897119860119904 119897119886119905119905119894119888119890 119898119886119905119888ℎ119890119889 (5666Å)
2
(43)
= 283Å
The nominal value of the AlAs barrier thickness for sample XMBE304 is 283nm
ie ten monolayers In the first simulation test the current change due to the barrier
thickness variation from 9ML to 11ML was examined first followed by the amount of
barrier thickness change that would produce a 10 change in current The simulation is
setup by fixing all other parameters and varying the AlAs barrier thickness as mentioned
136
above with a step of 02ML In order to determine what fraction of a ML would yield a
10 difference in the current the barrier thickness is slightly changed to fit the curve for
both 5 above and 5 below the original curve
Figure 46 IV characteristics of the dependencies of current on AlAs barrier
The current-voltage characteristics of the ASPAT diode do change dramatically with
barrier thickness in forward bias but not that much in reverse bias (Figure 46) The
current decreases as the barrier thickness increases For a 1ML change in layer thickness
(from 9ML to 11ML) the current changes by over ~300 at 05V
Figure 47 Example of analysis at -1 and 1V to the current
-00002
0
00002
00004
00006
00008
0001
00012
00014
-15 -1 -05 0 05 1 15
Cu
rre
nt
(A)
Voltage(V)
9ML
92ML
94ML
96ML
98ML
10ML
102ML
104ML
106ML
108ML
11ML
973E-06
0
0000005
000001
0000015
000002
0000025
000003
0000035
85 95 105 115
Cu
rren
t a
t 1V
B
ias
(Am
p)
Barrier Thickness (ML)
Current change with tunnel barrier thickness
Forward Current
5
-5
137
From the simulation result shown in Figure 46 a 9945ML barrier thickness will
give a 5 higher current and a 10056ML barrier will give a 5 lower current (Figure
47) Therefore in total 01 ML difference yields 10 current difference These indicate
that in order to control the current within 10 barrier thickness difference the growth
precision in the barrier must be precise to better than 01ML Extensive studies have
also shown that the I-V characteristic of a GaAsAlAsGaAs diode is very sensitive to
the thickness of AlAs barrier This work has been reported elsewhere[17]
452 Dependence of current on Spacer I length l1
For the longer spacer length (l1) five different values are chosen from 01microm to
03microm The lengths are changed in the order of 005microm Therefore the arrangement of
length is as follows l1=01microm l1=015microm l1=02microm l1=0 25microm and l1=03microm
respectively The results are plotted from -15V to 15V anode voltage in Figure 48 The
I-V characteristic of the ASPAT diode does not change much with the length in the
forward bias region but in the reverse bias region the current decreases as the layer
thickness increases Here the l1 layer acts as a voltage arm and a small size device
cannot sustain big changes in spacer length Changing the length at the forward region
will also change the energy states on the anode side as well changing the states
distribution on the cathode side in reverse bias
Figure 48 I-V characteristic of the dependencies current to Spacer I layer
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=01
L=015
L=02
L=025
L=03
138
By fixing the current at -1V and 1V the current and the layer thickness relationship is
illustrated in Figure 49
Figure 49 Current changes with layer thickness l1
It is noticeable that there is a dramatic change in reverse current from 01 microm to
05 microm layer thicknesses However the forward current only falls slightly from 01microm to
015microm and is stable afterwards Hence for a small size device a large change in spacer
layer at the cathode will allow more current to pass
453 Dependence of current on Spacer II length l2
Finally is the variation in the spacer II Similar to spacer I above five values are
chosen for the shorter undoped GaAs layer length l2 the thickness is varied from
00025microm to 00075 microm (steps are l2=00025microm l2=000375microm l2=0005microm
l2=000625microm and l2=00075microm respectively The results are plotted from -15V to
15V anode voltage as shown in Figure 410 In this case a slight change in I-V
characteristic in the forward bias can be seen clearly which means the I-V
characteristic depends on the length of the shorter undoped layer Therefore the l2 layer
also acts as another voltage arm due to the asymmetrical length The effect is quite
similar to the spacer l1 but this times the forward current only slight changes The reason
for the small change in current is that the length change is small and it linearly affect the
states distribution
-000002
-0000018
-0000016
-0000014
-0000012
-000001
-0000008
-0000006
-0000004
-0000002
0
0
000005
00001
000015
00002
000025
00003
000035
01 015 02 025 03
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)Reverse Current(-1V)
139
Figure 410 IV characteristic of the dependencies current to Spacer 1 layer
Fixing the current at -1V and 1V the current versus layer thickness relationship is
illustrated in Figure 411
Figure 411Current change with layer thickness l2
The I-V curve depends on the length of the shorter undoped spacer layer quite linearly
The forward current changes in increase to the layer compared to the backward current
The layer thickness l2 should be small as long as it prevents carrier diffusion Therefore
all these three layers must be kept within limit to ensure that the high performance of the
ASPAT diode can be fully utilised
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=75n
L=25n
L=625n
L=5n
L=375n
-2E-07
-18E-07
-16E-07
-14E-07
-12E-07
-1E-07
-8E-08
-6E-08
-4E-08
-2E-08
0
0
00002
00004
00006
00008
0001
00012
0002 0004 0006 0008
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)
Reverse Current(-1V)
140
46 Temperature Dependent Simulation
This section will discuss in detail how changes in operating temperatures influence
the IV characteristics of the ASPAT diode The same codes as in the previous
simulation with fitted results are used for this temperature dependence study but a few
parameters were changed for different temperatures
Theoretically the material parameters that are influenced by the change of
temperature are band gap electron effective mass the density of state (NC NV) light
hole mass heavy hole mass permittivity and electron amp hole mobilities However not
all mentioned parameters will have a large impact on the IV characteristic in the
SILVACO Atlas simulation The most significant factors that give appreciable impact on
the DC output current-voltage were the energy bandgap and the effective mass The
GaAs bandgap as a function of temperature is given by the equation below [106]
119864119892 = 1198641198920 minus
120572 1198791198712
120573 + 119879119871
(44)
Here Eg is the bandgap Eg0 denotes the bandgap at 0K TL is the Temperature α=
Constant (Varshni Parameter) AlAs6e-4 GaAs5405e-4 β= Constant (Varshni
Parameter) AlAs408 and GaAs204 The calculated parameters that are used in this
simulation are shown in Table 42
Table 42 The calculated values of bandgap at different temperatures
Temperature (K) GaAs Eg(eV) AlAs Eg(eV)
77 1506 2903
100 1500 2899
125 149 2893
150 1486 2887
175 1478 2879
200 1470 2871
225 1461 2863
250 1452 2854
275 1443 2844
300 1424 2835
325 1419 2824
350 1414 2814
375 1404 2803
398 1394 2793
141
The effective mass of the materials used in this simulation can be expressed by
119898119899 = 1198980119899 + 11989810 (
119879119871
300119870)
119898119901 = 1198980119901 + 1198981119901 (119879119871
300119870) + 1198982119901 (
119879119871
300119870)2
(45)
Where mn is the effective electron mass mp represents the effective hole mass m1n and
m1p are constant number for the basic GaAs material m0n
for 119898119883119898119871 119886119903119890 119892119894119907119890119899 119887119910 119905ℎ119890 119890119902119906119886119905119894119900119899 (1198981198991199052 lowast 119898119899119897)
13 while m0p is based on the
expression 1198980119901 = (11989811990111989732
+ 119898119901ℎ32
)23 The calculated parameters are shown in Table
43
Table 43 The calculated effective masses for each temperature used in this simulation
Temperatures (K) GaAs Effective Mass (kg) AlAs Effective Mass (kg)
77 00660m0 03790 m0
100 00658 m0 03788 m0
125 00655 m0 03785 m0
150 00652 m0 03782 m0
175 00649 m0 03779 m0
200 00646 m0 03776 m0
225 00643 m0 03773 m0
250 0064 m0 0377 m0
275 00637 m0 03767 m0
300 00634 m0 03764 m0
325 00631 m0 03761 m0
350 00628 m0 03758 m0
375 00625 m0 03755 m0
398 00622 m0 03752 m0
142
Figure 412 Measurement and simulation comparison result as a function of temperature range
from 100K to 398K
Figure 412 above shows excellent agreement between simulation and
measurement results at various temperatures The IV characteristics correspond to a
device of size 100times100microm2 as presented in Chapter 3
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes
As mentioned earlier in chapter one the tunnelling diode has many advantages
over conventional Schottky barrier diodes some of which are a large dynamic range
low power consumption and very weak temperature dependence This section will
discuss the effect of variable temperature applied to the GaAsAlAs ASPAT diode and a
similarly processed TiAu Schottky diode Two samples were fabricated together for
these studies (XMBE304 and XMBE104 representing an ASPAT and a SBD
respectively) The fabrication technique is exactly the same as has been discussed in
Chapter 3 In order to make it fair for direct comparisons as well as easy probing both
diodes were fabricated with the same emitter size (100times100microm2) The DC measurements
at different temperature were carried out using a Lakeshore Cryogenic probe station over
the range of 77K to 398K in 25K step interval
-002
-001
0
001
002
003
004
005
006
-2 -15 -1 -05 0 05 1 15 2
Cu
rren
t I
(Am
p)
Voltage V (Volt)
T=100K_Simu
T=100K_Meas
T=398K_Simu
T=398K_Meas
T=200K_Simu
T=200K_Meas
T=300K_Simu
T=300K_Meas
143
471 GaAsAlAs ASPAT diode vs TiAu SBD
Once fabrication and measurement were completed both DC outputs of the diodes
were characterised and analysed Figure 413 shows a semi-logarithmic plot for
measured current versus voltage as a function of temperature for ASPAT sample
XMBE304 In forwards bias the current changes for different temperatures from 77K
to 398K are less than 5 percent This confirms the very weak temperature dependence of
current transport as it is dominated by tunnelling through the barrier On the other hand
the backward bias shows the current changes at different temperature are slightly bigger
than in forward this due to band bending occurring faster (making the effective barrier
lower) and allowing thermionic emission to significantly contribute to transport of the
current The only other study of temperature dependence for the ASPAT was made by et
el RT Syme[15] but details were not stated in their report
Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample XMBE304
The effective barrier height for the GaAsAlAs ASPAT diode is higher than that of
the SBD (See Figure 414) therefore there is an expectation of more limited thermionic
current flow in the ASPAT than the SBD As mentioned earlier the conventional
Schottky Barrier diode that is used in this study consists of a Gold Titanium and GaAs
(AuTiGaAs) interface which is the baseline for the temperature dependence study
0000001
000001
00001
0001
001
-15 -1 -05 0 05 1 15
Log
Cu
rren
t (A
)
Voltage (V)
T=77K
T=100K
T=125K
T=150K
T=175K
T=200K
T=225K
T=250K
T=275K
T=300K
T=325K
T=350K
T=375K
T=398K
144
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT Diode [3]
The SBD epitaxial layers profile is as shown in Table 44 below Theoretically the SBD
obey thermionic emission transport[44] and its I-V characteristic is given by
119868 = 1198680[exp (
119902119881
119899119896119879) minus 1]
(46)
Where q is the electron charge V is the applied voltage across the diode n denotes the
diode ideality factor k is the Boltzmann Constant T is the absolute temperature in
Kelvin and I0 is the diode saturation current which is given by the expression
1198680 = 119860119860lowast1198792 exp (minus
119902empty1198870
119899119896119879) exp (minus120572120594119890
12120575)
(47)
here A is the area of the diode A denotes the effective Richardson constant Oslashb0 is the
barrier height at zero bias δ represents the thickness of interfacial insulator layer χ
denotes the mean tunnelling barrier and α = radic(4120587
ℎ)(2119898lowast) is a constant value The
ideality factor n is taken from the slope of the SBD current-voltage characteristic and in
this study its value varies from 1 to 2 (depending on temperature) In the case of the
ASPAT diode thermionic emission can also happen if a thicker barrier is used (~ 100Aring
or thicker) as shown by CS Kyono et el [104] who concluded that when a thicker
barrier of AlAs barrier is used the current transport is dominated by thermionic emission
145
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104)
Layer Material Doping(cm-3
) Thickness(Aring) Bandgap (eV)
Schottky GaAs(Si) 500E+15 7500 14
Semiconductor GaAs(Si) 300E+16 7500 14
Semiconductor GaAs(Si) 100E+17 7500 14
Ohmic GaAs(Si) 500E+17 7500 14
Buffer GaAs(Si) 300E+18 7500 14
Substrate GaAs(Si) N+ 3000 14
The fabricated SBD was also measured and its I-V characteristic is plotted as a
function of temperature in Figure 415 Unlike the ASPAT diode the current at forward
bias for the SBD change enormously with temperature from 77K to 398K and at all
biases For the ASPAT diode the slight change in current only started after 08V bias as
the current starts to have some component of thermionic emission over barrier
Figure 415 Log Current vs voltage as a function of temperature for SBD sample XMBE104
In order to see clearly how much the current is changing in forward bias for both
ASPAT and SBDs diode a log current at different voltages versus 1000temperature is
plotted as shown in Figure 416
1E-08
00000001
0000001
000001
00001
0001
001
01
-2 -1 0 1 2
Log
Cu
rren
t (A
)
Voltage (V)
T=398K
T=375K
T=350K
T=325K
T=300K
T=275K
T=250K
T=225K
T=200K
T=175K
T=150K
T=125K
T=100K
T=77K
146
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and SBD
Semi-logarithmic plots of current (at V= 05 06 07 08V) versus inverse
temperature for both SBD and ASPAT are shown in Figure 416 When the temperature
is increased the current also increases in the SBD as a result of thermionic emission
over the barrier for sample XMBE104 This is in contrast to the temperature-
independent tunnelling through the thin AlAs barrier of sample XMBE304 ASPAT
diode where when the temperature is increased the current is almost constant
At low and high temperatures the ASPAT shows excellent temperature
independence with a constant current flow It exhibits a tunnelling current in excess of
values expected by the elastic tunnelling current calculation equation suggested by RT
Syme [16 18] above (Eq 1) using a Oslash value of 105eV (ΓGaAs to Γ AlAs tunnelling) By
contrast for the SBD at low temperature (77K-275K) the changes of currents were very
high and for every 02V there is an exponential change of more than 40 This
temperature dependent study was also reported in[68]
147
48 Conclusions
This chapter demonstrated the establishment of an excellent physical model and
comparison of room temperature I-V characteristics of GaAsAlAs ASPAT diodes for
different emitter sizes their scalability as well as an investigation of their characteristics
at different temperatures from 77K to 398K Simulation are validated on well-
characterized experimental data and excellent fitting which had been achieved in this
work permit the designer to extract all related parameters of heterojunctionmultilayer
ASPAT structures thus creating modification for future growth specification in order to
achieved precise designs
It is clear that the work which had been carried out in this chapter is able to
achieve with adequate accuracy a claim of reverse engineering capability The ability of
the GaAsAlAs ASPAT to act as a zero-bias detector has been analysed and compared
with the SBD It is clear that the temperature stability which is shown by the
GaAsAlAs ASPAT is much better than that of the SBD thus demonstrating that the
tunnelling current is dominant over the thermionic emission in ASPAT diodes
148
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES
51 Introduction
To assist in circuit designs for any type of high-frequency circuits such as
millimetre wave detectors frequency multipliers and mixer circuits which are built
based on non-linear devices (diodes) an equivalent-circuit model for the diode is
required This is among the simplest and most effective method for analysing
semiconductor devices which work at high frequency where the electrical characteristics
measured obtained from the devices are extracted and presented in a circuit consisting of
lumped elements components (resistor inductor capacitor etc) However accurate DC
and RF measurement data is essential to extract the equivalent-circuit elements quickly
and correctly The extracted parameters values from the circuit that are taken into
account usually depends on bias and frequency associated with the device physically
which is also interrelated to the semiconductor material parameters device structure as
well as fabrication process flows
In this work the DC and RF data were derived from DC and S-parameter
measurements respectively These measurements were carried out both in-house and at
the University of Cambridge by a collaborator partner (Prof MJ Kelly) The I-V
characteristics of the diode obtained from DC measurements were measured from -2V to
2V while the S-parameters were carried out over a wide frequency range from 40MHz to
40GHz with eight different biases In this chapter the DC measurements for various
sizes of the diodes with analysis of their IV characteristics will be discussed The one-
port on-wafer ASPAT measurement setup as well as the de-embedding method will
also be explained Thereafter the equivalent circuit models with all lumped element
effect will be discussed This work is carried out with the help of the VNA which
principle has been described in Chapter 2 and Keysight ADS simulation tool All
technical details regarding the equivalent circuit models will be explained together with
the method used for the ASPAT diode evaluation The equivalent circuit model also will
cover the diode intrinsic elements such as Cj Rj and Rs and extrinsic elements ie CP
149
and RP Finally an equivalent circuit model with the small signal characterization of the
fabricated ASPAT diodes will be presented
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes
The recent development of state-of-art for DC measurement apparatus has led to
capabilities for high-level accuracy of measuring voltages to a few nano Volts and
current signals in the femto Amp range[107] This can easily be obtained by exploitation
of proper connections and high-quality cables connecting the equipment to the Device
under Test (DUT) In this work the DC measurements were carried out using an Agilent
B1500A Parameter analyser whose description was covered in Chapter 2
As was discussed in Chapter 3 the GaAsAlAs ASPAT diodes have been
fabricated with different mesa areas between 2times2microm2 to 100times100microm
2 but the smallest
size obtained with good I-Vs was 4times4microm2 In this section the focus will be on how the
extracted data can be expanded further for empirical modelling Figure 51 shows typical
results for measured ASPAT diodes with various dimensions to check for their
uniformity According to our standard procedure the DC measurement has to be
conducted prior to the RF to ensure the diode is in fully working order as this will later
save a lot of time during RF characterization
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2 6x6um
2 and
10x10um2 Note the good scalability
1E-10
1E-09
1E-08
00000001
0000001
000001
00001
0001-2 -1 0 1 2
Cu
rre
nt
De
nsi
ti (
Amicro
m2)
Voltage (V)
4x4microm^2
6x6microm^2
10x10microm^2
150
Figure 51 above demonstrates the IV Characteristics of measured GaAsAlAs
ASPAT diodes (XMBE304) for emitter sizes of 4times4um2 6times6um
2 and 10times10um
2 This
sample was processed using the dielectric bridge technique developed in this work It
can be observed that current per unit area for each dimension fits and scales to each
other The scalability of each diodes measurement is very important to ensure no process
related issues are hampering the devicersquos proper operations This also confirms that the
diodes are completely functional and can be used for the next stage of measurements
The advantage of having an excellent scalability of those diode sizes is that a prediction
of smaller emitter size can be made
This type of IV characteristic shows asymmetric behaviour which results from
the unequal spacer lengths of the device This behaviour is very useful for detection
application as it obeys a square law model The square law predicts that the current is
proportional to the square of the applied bias
119868 = 1198861198812 119908ℎ119890119899 119881 gt 0
119868 = 0 119908ℎ119890119899 119881 lt 0
(51)
To extract the first order effects of ASPAT diodes DC measurements which
result in asymmetric I-V characteristics are analysed The slope of the non-linear region
is used to determine the junction resistance (Rj) which is obtained from the first
derivative of voltage versus current (dVdI) The expression of Rj is given by
119877119895 =
120597119881
120597119868
(52)
In order to understand the relationship between Rj and diode sizes of the ASPAT the IV
characteristic for each diode displayed in Figure 51 is used to extract the Rj This has
been done by using the expression in equation (52) above and their response is plotted
against bias as displayed in Figure 52
151
Figure 52 Junction resistance versus voltage
As can be seen in the Figure 52 above the Rj for each device decreases strongly
when the voltage increases At zero bias the 4times4um2 devices show the highest Rj value
followed by 6times6um2 and 10times10um
2 devices The junction resistance at zero bias obtained
from the 4times4um2 diode is around 86KΩ while reducing by a third for the 6times6um
2 and
10times10um2 diodes with Rj of 27KΩ and 10KΩ respectively A diode with a smaller
forward current under the same applied voltage will exhibit a larger Rj For a good
millimetre wave detector a device with a large value of Rj is desirable since it will
provide high detection sensitivity
The slope at the IV characteristic contributes to an important parameter that is
commonly used by electronic manufacturers to describe diode specification namely the
video impedance (RV) which is also known as the non-linear resistance The RV which is
extracted from the real part of the diode small signal impedance is highly dependent on
the DC bias current and only weakly depends on the series resistance of the diode (RS)
Therefore the video impedance is given by
119877119881 = 119877119895 + 119877119878 (53)
Where RS is the series resistance of the diode whose value is normally very small and
does not contribute much to the whole slope and hence RV is dominated by Rj The RV
changes in behaviour if any DC current is flowing through the diode Practically small
DC current in the range of 1 to 10 microAmp or total zero bias is used to maintain the
appropriate RV value (1-2KΩ to several MΩ) RV will also determine the voltage
-10
10
30
50
70
90
110
130
150
-01 0 01 02 03
Rj(
KΩ
)
Voltage (V)
6x6um^2
10x10um^2
4x4um^2
152
sensitivity of the whole detector circuit This will be explained further in the next
chapter In the case of a detector with an amplifier RV of the diode acts as the RF
impedance which needs to be matched with the video amplifier ( impedance looking into
the diode from the amplifier)[108 109]
The quotient of the second order derivative to the first derivative
((d2IdV
2)dIdV)) when calculated from the whole I-V characteristic translates directly
into a curvature coefficient (k) This is the most commonly used figure-of-merit to
quantify diode nonlinearity at zero bias Figure 53 below shows the variation of k with
bias and more importantly the zero bias rectifying action for device sizes of 4times4 um2
6times6 um2 10times10 um
2 This parameter which represents the small-signal rectifying
action of the diode will affect the performance of the detector (voltage sensitivity)
Detailed discussions on how this parameter effect the detector performance will also be
discussed in the next chapter
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT high sensitivity
near zero bias detection
Figure 53 above shows calculated curvature coefficient of the measured I-V
characteristics from the same diodes shown in Figure 51 The highest k value is
obtained from the diodes with size of 4times4um2 followed by 6times6um
2 then 10times10um
2
The curvature coefficient decreases sharply as the bias increases for each diode This can
be attributed to a significantly increasing number of electrons that tunnel through the
thin barrier which were accumulated in the 2DEG formed in the intrinsic spacer region
-5
0
5
10
15
20
25
30
-001 004 009
Cu
rvat
ure
Co
effi
cien
t(V
-1)
Voltage (V)
k(10x10 um^2)
k(6x6 um^2)
k(4x4 um^2)
153
An ASPAT diode with a smaller size will have a larger Rj with a corresponding smaller
current under the same bias condition and hence will demonstrate a larger k value In
this calculation the curvature coefficient at zero bias obtained from 4times4um2 6times6um
2
and 10times10um2 diode is 23V
-1 17V
-1 and 16V
-1 respectively
A summary of the ASPAT diodes parameters obtained from measured I-V
characteristics that have been translated into first and second order differentials are
gathered in Table 51 below and compared to other diodes in the literature
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics in this work
Sample Rj(Ω) k(1volt)
ASPAT 10times10 microm2 10K 16
ASPAT 6times6 microm2 27K 17
ASPAT 4times4 microm2 86K 23
Ge Backward diode 182K[110] 159[110]
InGaAs Backward diode 154[110] 23[110]
Sb Backward diode 5K[111] 47[111]
Si-Backward diode 135K[112] 31[112]
PDB 15K[8] -
AlGaAs SBD 20-100K[113] 34-38[113]
GaN HBD - 16[114]
From Table 51 above it is clearly that the ASPAT diode has a comparable value of Rj
and k to existing detector diode in the research community and in the commercial
market Based on literature of each diodes stated in the table the key to obtaining a high
value of k at zero bias is to minimize any forward tunnelling current Furthermore the
largest ASPAT diode used here (10times10microm2) has very close performances to that of a
commercial diode ie discrete Ge backward diode (ref[110]) where both Rj and k value
are close to each other
53 RF Test Fixture Theory and Experiment
RF measurements differ from DC measurement as they are more complicated
and it is necessary to comprehend the basic measurement principles to achieve
meaningful data This is obligatory especially for on-wafer RF characterization and
154
analysis to attain precise results Most of the electronics component measurements
which have input and output for instance antenna amplifier cables etc are based on a
two-port network configuration The characteristics which can be extracted from these
components are usually used to define their impact on a more complicated system
The performance of the two-port network can be described by a few parameters
ie scattering (S-Parameter) admittance (Y-Parameter) Impedance (Z-parameter) and
Hybrid (H-Parameter) However the S-parameter approach is favoured for high-
frequency measurements as it is relatively easier to characterize the microwave
performance and is able to convert to other parameters when necessary The advantage
of S-parameters is that they can straightforwardlydirectly convert into other two-port
parameters as mentioned above in term of currents and voltages[115] In fact to obtain
the device capacitance the appropriate S-parameters needs to be transformed into Y-
parameters using specific equations Furthermore the devicersquos cut-off frequency can
also be obtained when S-parameter measurements are performed over a wide frequency
range
531 On-Wafer Measurement and Small Signal One-Port Characterizations
In this work the arrangement of the RF measurement setup is assumed to be a
linear system as small voltage amplitude signals are used this means that the signals
have only a linear effect on the network without any gain compression or attenuation
The assumption is still acceptable even though the typical ASPAT is characterised as
non-linear in nature because it is a passive device which will act linearly at any input
power level
Generally the S-Parameter measurements on a diode can be adequately and
suitably performed using a one port measurement The technique used to characterise the
output is similar to the two ports technique but only incident and reflected waves are
used to characterise the input and output ports of the device Essentially this is because
the ASPAT has only two terminals and it is a passive device like other diodes
Therefore the analysis will revolve around the S11 parameter Figure 54 below show the
S11 is a ratio of reflected wave to the incident wave
155
11987811 =
119877119890119891119897119890119888119905119890119889
119868119899119888119894119889119890119899119905=
1198871
1198861 119908ℎ119890119899 1198862 = 0
(54)
A VNA as described in Chapter 2 is used to measure the ASPAT diodes This
powerful equipment is able to measure S-parameters up to 40 GHz To conduct accurate
S-parameter measurement at the diode the measurement setup must be calibrated prior
to the actual measurements taking place
54 Device Calibration
541 Open and Short De-Embedding Technique
Further calibration to be made involves anything related or attached to the
device The co-planar waveguide (CPW) bond pad and interconnect line that are
attached to the intrinsic diode are the main contributors of the errors also are required to
be calibrated In general the bonds pad could generate a capacitance (parasitic) in
parallel with the intrinsic diode and its contribution depends on the size of the bonds pad
as well as the operating frequency Meanwhile the CPW and interconnect line may
cause a parasitic inductance in series with the diode
The method that is used to get rid of this parasitic is called de-embedding and the
most common technique to realise it is by introducing OPEN-SHORT structure[116]
This method is based on a lumped-elements model Parasitic elements of the diode
De-Embedding Structure
Incident wave
Reflected wave
One-port device
a1
b1
Figure 54 One port S-parameter measurements
156
equivalent circuit correlate directly to the access section of the CPW hence can be
derived from de-embedding structures The aim of the de-embedding technique is to
represent these parasitic elements so that the one-port characteristic of the actual diode
can be determined
The two types of de-embedding structure OPEN and SHORT are conventional
techniques that are widely used in this study The design of all structure must be
identical (in size) to the device to avoid any discrepancy It is very simple to design all
these three structures for example open structures are obtained by eliminating the diode
layout and keeping the bond pad layer only The short structure just adds a bridge and
ensures ground and signal pad are connected to each other Through structures are
realised by disconnecting both ground pad and leaving the signal pad to connect to each
other
To gain more accuracy this external effect must be removed by the implementation of
de-embedding structures on the same tile as the actual device Figure 55 shows the
fabricated de-embedding structures used in this study
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use for RF
calibration and measurements (Note Images are not to scale)
In summary the de-embedding which is used to extract out the parasitic elements
from entire single diode measurement is a very important step as normally on-wafer
measurement requires coplanar waveguide (CPW) to access the diode structure (active
region) The CPW will have some effects which will disturb the accuracy of the device
characteristics
157
55 S-Parameter Measurement Result and Analysis
This section will only present RF measurement results after all VNA setup and
calibration were performed The S-Parameter measurements were carried out on ASPAT
diodes at five different DC biases from -2 to 05 volt with a sweep frequency from
40MHz to 40GHz using a calibrated VNA and the input power was fixed at -30dBm
The measurement procedure as described in Chapter 2 was performed on the device
(on-wafer) equipped with the appropriate bond pads This is important to ensure the
results obtained are valid The reason for using different biases is to find at what voltage
the device capacitance is fully depleted This is also very important in determining the
cut- off frequency of the devices
In this research two phases of the experiment on the S-parameter measurements
were carried out The first phase is to qualify the process flow ie for manufacturability
and repeatability which can be obtained from the consistency of the result The S-
parameter measurements taken on the same wafer dies are repeated several times on
different GaAsAlAs ASPAT diodes There are three different tiles taken from 3
different wafers namely XMBE304A XMBE304B and XMBE304C carried out in
this experiment The repeatability tests are done mostly on the large devices (15times15microm2
up to 100times100 microm2) and the results are analysed based on the reflection coefficient (S11)
on Real and Imaginary measurements
In the second phase the measurement is toward producing devices that can
perform at high-frequencies This can be realised by utilising small emitter size devices
(4times4microm2 6times6 microm
2 and 10times10 microm
2) The measurement results of these devices will be
used to build the equivalent circuit models while both the intrinsic as well as the
parasitics of the device will be evaluated Hence all the values obtained from these S-
parameter measurements will be used to design the device that can be used in
millimetres-wave applications As can be seen in Figure 56 below the extracted S-
parameter measurement results comprise of a reflection coefficient (S11) for real
imaginary and Smith chart for XMBE304A While these measurement results are
extracted at zero bias voltage the other bias voltages will be used to extract the
capacitance This will be described in the final section of this chapter
158
551 Diode to diode uniformity
In order to study within tile uniformity and reproducibility statistics of the RF
performance five devices of different mesa sizes in the same tile (XMBE304A) were
measured at zero bias and represented in term of Real and Imaginary reflection
coefficient (S11) the uniformity check is carried out at three different frequencies step
under 15GHz since the cut-off frequency for these big devices is relatively low at about
~20GHz on average The variation of the reflection coefficient is taken from the
percentage of the (standard deviationmean values) for all five diodes from this run The
following figures show Real and Imaginary S11 of large mesa area ASPAT diode from
15times15microm2 up to 100times100microm
2 which are represented by lines graph in a few different
colours
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices from
15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero bias
159
The variance data extracted from the graph (Real S11) above for each device within-
wafer (device to device) uniformity study is summarize in Table 52 below
Table 52 Device to device uniformity check for large ASPAT diode
Device Size 100times100 microm2 50times50 microm
2 30times30 microm
2 20times20 microm
2 15times15 microm
2
Variation 5GHz 181 115 405 151 145
Variation 10GHz 106 133 522 424 293
Variation 15GHz 119 198 281 76 509
The majority of diodes show that the variations of S11 measurements are below
3 and only a few are below 8 These finding still can be considered as good for
manufacturing control since absolute I-V characteristics reported in [63] is set by
designerrsquos specification to be not more than plusmn10 variation Further extensive RF
measurements were carried out by the research collaboration with the University of
Cambridge on the same GaAsAlAs ASPAT diodes wafer [117] In their study they
focused on 50times50 microm2
mesa size 17 of diodes were chosen to be measured The study of
uniformity of RF characteristic only focused on frequencies below 20GHz The same
approach was used to get the variation of the reflection coefficient for all 17 diodes but
this work was carried at four different frequencies Table 53 shows the zero bias S11
result for four different frequencies and standard deviation of the devices
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at four different
frequencies[117]
Frequency (GHz) 5 10 15 20
Variation () 197 243 26 276
From the results the variations of 50times50 microm2 mesa sizes measured in-house and
at the University of Cambridge are comparable with all variations showing good
uniformity ie recording variations below 3 This indicates that the RF performance
of the GaAs AlAs diode is valid and reproducible and is thus considered as a good
achievement for manufacturing Once the reproducibility and repeatability of the large
devices showed stable results the fabrication process then continued to obtain smaller
emitter size for work at high-frequencies
160
552 Wafer to wafer uniformity
Other RF measurements were conducted on sample XMBE304B which was
fabricated in-house using the same process steps but the only difference from
XMBE304A was the use of SiN3 as dielectric In this run three different mesa sizes
were measured (15times15mmicro2 20times20microm
2 and 30times30 microm
2) and Real and Imaginary S11
plotted against frequency The RF performances of both samples are gathered in one
graph as shown in Figure 58 below
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B) to qualify
the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2 device sizes (Real and
Imaginary) Note blue colour is XMBE304A and red colour is XMBE304B
For this wafer to wafer uniformity study four diodes with three different sizes as
specified previously were measured from sample XMBE304B and four diodes from
previous measurements of XMBE304A The blue line in Figure 58 represent
measurement result of real and imaginary for sample XMBE304A while the red line
161
represents XMBE304B The uniformity data is compared at three different frequencies
and gathered in the table below
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B
Device Size 30times30 microm2 20times20 microm
2 15times15 microm
2
Wafer A vs wafer B variation 5GHz 305 31 1 314
Wafer A vs wafer B Variation 10GHz 352 344 329
Wafer A vs wafer B Variation 15GHz 321 376 359
As can be seen in the Table 54 above the wafer to wafer uniformity is rather
large (30) on average The main reasons being that sample XMBE304A was
processed by utilizing S1805 as a dielectric layer while sample XMBE304B used
Si4N3 Although the process steps are similar for both wafer processing the use of
different dielectric layer will influence the diode parameters especially resistance and
capacitance as the dielectric constant for each materials is different Secondly the wafer
processing is not run concurrently at the same time thus the moisture and temperature in
the clean room might differ for both processing Although the wafer to wafer uniformity
test for this run might not be favourable for manufacturing tolerance at least the use of
different dielectric layer shows some significant result in term of capacitance resistance
effect to the GaAsAlAs ASPAT diode
553 Small devices RF measurements
The first objective of this study was to make smaller size mesa devices ie
1times2microm2 1times3 microm
2 2times2 microm
2 and 3times3 microm
2 However for GaAsAlAs ASPAT type this is
difficult to achieve in practise These issues were discussed in detail in Chapter 3
Hence the smallest emitter size that yields repeatable and reproducible results was
4times4um2 The final measurement which was done on sample XMBE304C focused on
small devices The measurements were done on four devices two with the diode bond
pads sitting on substrate (GaAs SI) and the other two sitting on dielectric layer (Si4N3)
Figure 59 below shows three measured results obtained from sample XMBE304C
using the 3rd
Gen Mask
162
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and 4times4microm
2 (Real and
Imaginary) Note that green red and blue colour represents 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and 4times4 microm2
(Smith Chart) Note that green red and blue colour represents 4times4microm2 6times6mmicro2 and 10times10microm2
diodes respectively
30MHz
40GHz
163
As can be seen in Figure 59 (Real Imaginary) and Figure 510 (Smith Chart) are
obtained from measurement of four diodes in the same tile The diode to diode
uniformity that is sitting on the same platform obtained at 35GHz frequency in this run
on average is ~15 25 and 1 for 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively On the other hand the uniformity between diode to diode sitting on
dielectric and substrate is quite high due to different capacitance value of devices on
average ~7 are attained from three different sizes of diode
From the measurement results above the Real S11 measurement of four different
sizes show the same trend for each frequency At low frequency resistances for each
diode is high as the S11 value is large At intermediate frequency the values drop
tremendously for big devices (30times30 mmicro2 and 20times20 mmicro
2) ie in Figure 57 At high
frequency all diode reach saturation limit as the value are constant Small devices
(4times4mmicro2 6times6mmicro
2 and 10times10microm
2) ie Figure 59 show S11 values that are higher than
those of large devices as smaller emitter diode have larger resistance value
The imaginary S11 value also shows the same trend as for big devices However
for small devices in this run (4times4mmicro2 6times6mmicro
2 and 10times10microm
2) the S11 value keep
dropping toward negative values at increasing frequencies This indicates that bigger
devices with positive value at high frequency are more capacitive than the smaller
devices It is worth mentioned that the capacitance and inductance values for device
sizes of 4times4microm2and 6times6microm
2 come from the CPW layouts and these are dominant while
for device sizes of 15times15 mmicro2 and above the device capacitance itself is dominant
The Smith Chart shows the reflection coefficient (S11) as a function of the
applied frequency (30MHz to 40GHz) All measurements from each mesa size follow
unique impedance circle which is that most of the lines are at the lower right outer ring
This means that the diode capacitance value is frequency dependent For the case of
10times10microm2
devices these impedance circles are mostly toward the outer ring meaning a
higher capacitance than the other two mesa dimensions All the device constantly follow
the outer ring without crossing any real axis at any frequency point meaning that the Cj
is not shorted at the maximum 40GHz measurement frequency (not reached cut-off
frequency) Therefore the entire small GaAsAlAs diodes in this run have capability to
work in the millimetre wave frequencies range
164
56 Extracting RF models of ASPAT at Zero Bias Voltage
The methodology used in the S-Parameters measurement for high-frequency
analysis must ensure that the derivation of the equivalent circuit corresponds to their port
characteristics In other words the component representing the ASPAT in the equivalent
circuit model must have physical significance otherwise the circuit will be meaningless
The fabricated ASPAT diodes as discussed in Chapter 3 have the cross section shown in
Figure 511
There are two main components that can be extracted from the fabricated
ASPAT depicted above ie intrinsic and parasitic The intrinsic refers to the main
structure of the diode itself and are represented by three bias dependent elements
namely Junction Resistance (Rj) Junction Capacitance (Cj) and diode Series Resistance
(Rs) The parasitic is the elements related to the bond pad of the anode and cathode as
well as interconnects They are represented by parasitic inductance (LP) resistance (RP)
and capacitance (CP)
The diode parameter extraction is different from the three terminal devices
(FETs) in the sense that FETs are a kind of direct extraction in which all the elements in
the transistor have linear functions to the port characteristics ie S-parameter Y-
Parameter Z-Parameter and can easily be solved by the matrix calculation method for
those particular parameters[118] The same extraction method cannot be applied to the
diodes because its elements will embroil with each other Therefore only one method is
used to extract the diode element which is optimisation by tuning the initial value toward
the measured S-Parameter values
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding equivalent circuit
model
165
The strategy used to model the ASPAT is based on an initial fitting value of the
lumped elements to the extracted value from measurement on three S-parameter graphs
(real imaginary and Smith chart) for the reflection coefficient (S11) The refinement is
accomplished by optimisation and fine tuning of the values which result in minimum
error between extracted and modelled values Figure 517 (on page 153) shows fitted S-
parameter result for extracted and model numbers with each one fitted in a single line as
an example However to achieve this excellent fitting key prior steps have to be used
de-embedding fitting the intrinsic value and optimisation
561 Extraction of ASPAT parasitic element
Once the S-parameter measurements achieve stability repeatability and
reproducibility for each measurement in term of S11 results as mentioned above the
results of the de-embedding structure which had been measured prior to the device
structure are then extracted to form a well-defined equivalent circuit In order to build
and analyse the equivalent circuit firstly the measured data is imported into the ADS
software prior to any fitting This can be realised via the ldquoStart The Data File Toolrdquo
features provided by this particular software When successfully imported the data is
read by the function S2PMDIF (These files are a natural extension of two-port S-
parameter Touchstone files) as depicted in Figure 512 below
Figure 512 The S-parameter Touchstone file is used to read the measured files
166
For the open and short techniques after de-embedding the equivalent circuit
model which is represented by mainly a capacitor and an inductor is built The open
structure requires resistance and the capacitance values of 20KΩ and 26fF respectively
connected in parallel to be well fitted to the real imaginary and Smith chart (S11) output
On the other hand for the short structure the Real imaginary and Smith chart (S11) have
to satisfy the values of resistance and inductance elements of 1Ω and ~47pH respectively
connected in series These values strongly rely on the bond pad or CPW dimension and
length The Equivalent circuit models and fitted data as well as measurement can be
seen in Figure 513 and Figure 514 below
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure
Figure 514 Equivalent circuit model for short de-embedded structure
To satisfy the equivalent circuit a self-consistence method introduced by
Ren[119] is utilised This approach accurately extracts the CPW capacitance (Cpad) and
inductance (Lpad) as well as intrinsic Junction capacitor (Cj) which is attained from the
one-port S-parameter measurements Therefore the pad capacitance introduced by the
self-consistence method for the open structure can be expressed by
167
119862119875 =
119868119898(11988411119874119901119890119899)
120596
(55)
Lpad which represents the short structure is given by
119871119875 =
1
120596(119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
))
(56)
Here Y is the admittance parameter (Y-parameter) converted from the S-parameter
measurement data and ω is the angular frequency The extracted measurement data
represented in the equivalent circuit fits with the simulated data in three S11 graphs as
can be seen in Figure 515 below From the Smith Chart it can be clearly seen that both
open and short S11 results are on the circumference which means the resistance of the
short structure is very small while in the open it is very large Additionally the
calculated Cpad and Lpad using Equations 55 and 56 above produce results similar to
those obtained in the equivalent circuit model for the open and short structure The
values are ~25fF and ~45pH respectively These data completely verify and validate
both results
Figure 515 Smith chart representative S-parameter measurement for short (left) and open (right)
CPW The blue lines represent simulated data and the red is measured data
Short
Open
168
562 Extraction of ASPAT intrinsic elements
Once the parasitic elements are determined it is easy to build a complete ASPAT
equivalent circuit The ASPAT is not like other tunnelling diode which their equivalent
circuit models widely studied ie RTD [120] IMPATT and PDB The only literature
which reports ASPAT equivalent circuits can be found in [15] and other RT Symersquos
journal paper[16] Fortunately its equivalent circuit model is not much different
compared to other diode video detectors Thus other literature which is based on
Schottky diode equivalent circuit model used for detector application can be referred to
The simplest form of ASPAT equivalent circuit and other video detectors intrinsically
consist of junction capacitance (Cj) series resistance (RS) and junction resistance (Rj)
First and foremost to extract the equivalent circuit one must know the theory behind
each parameter that is developedbuilt as a spine to become a complete element This is
vital to ensure the equivalent circuit is correct In the case of the ASPAT Cj is predicted
from a simple fully depleted parallel plate capacitor approximation which was discussed
previously in Eq (230)[15] Additionally for the S-parameter measurements the Cj can
also be validated by the self-consistence method mentioned earlier and thus can be
expressed by
119862119895 =
[
(1
120596)
1
1
119868119898 (11988411119905119900119905119886119897minus 11988411119874119901119890119899
)+
1
119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
)]
(57)
This approach helps to verify both the fully depleted parallel plate capacitor in S-
parameter measurements The basic component which is responsible for the ASPAT
series resistance RS was discussed in detail in Chapter 2 RS and Cj are key contributors
to the high-frequency operation as expressed by the device cut-off frequency Equation
(58) below
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(58)
The R and C parameters must be kept as low as possible in order to obtain high cut-off
frequencies for millimetre wave applications From the fabrication point of view Cj can
169
be reduced by making as small a diode emitter size as possible while for RS reducing
the D gap is of paramount importance as it dominates the series resistance The ASPAT
contact resistance in the electrodes (contacts between metal and semiconductor) can be
reduced by using high doping in the ohmic layers
The junction resistance (Rj) of the ASPAT is taken from the 1st derivative or
slope of the current-voltage characteristics Normally the value of Rj is very large
(several kilo Ω) compared to Rs The small signals ASPAT equivalent circuit built with
intrinsic and extrinsic components is shown in Figure 516 below while the fitting
results is shown in Figure 517 and Figure 518
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
(Real and Imaginary) results for various small device designs
Rj
Cj
Cpad Rpad
Rs Lpad
Figure 516 Equivalent circuit of the ASPAT diode
170
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
results (Smith Chart) for various small device designs
The equivalent circuit that was built for the ASPAT is taken from sample
XMBE304C with emitter dimensions of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 These
devices are expected to work in the millimetre-wave region and have cut-off frequencies
(intrinsic) of ~650GHz ~200GHz and ~100GHz respectively
Table 55 Comparison between calculated (fully Depleted) and extracted (different biases) values
from equivalent circuit parameters for different ASPAT mesa sizes at zero bias voltage
Parameters 4times4microm2 6times6 microm
2 10times10 microm
2
Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted
0V -05V -1V 0V -05V -1V 0V -05V -1V
Cj(fF) 879 23 7 6 198 55 148 139 549 171 486 46
Cpad(fF) - 15 15 15 - 15 152 152 - 15 15 15
Lpad(pH) - 45 43 42 - 50 473 473 - 51 51 46
Rj(KΩ) - 90 833 522 - 35 392 392 - 12 125 13
Rs(Ω) 99 11 11 11 67 95 8 7 41 95 45 37
fcut-off
Cj(GHz)
1828 629 2066 241
1
1208 192 1344 163
5
710 107 728 935
fcut-off
Cj+Cp(GHz)
- 380 658 688 - 151 663 781 - 98 556 705
171
The focus in this study is purposely to build ASPATs as zero bias detectors that are able
to work in the millimetre and sub-millimetre frequency range therefore all the
parameters which are obtained from equivalent circuit were extracted at zero bias
voltage Theoretically the calculations which are derived from both self-consistence amp
theory can only be solved for fully depleted device capacitance (using a parallel plate
configuration) Hence both extracted and calculated results are compiled in Table 55
Noticeably the calculation can only produce the intrinsic parameters of the
ASPAT for fully depleted capacitance On the other hand both intrinsic and extrinsic
parameters of GaAsAlAs ASPAT are obtainable from extraction and thus help to
determine at what bias the diode is start to deplete The junction and series resistance (Rj
and RS) of each dimensions shown in Table 55 above were achieved by fitting the
elements of the equivalent circuit with the three measured S11 graphs whereas the Cpad
and Lpad were extracted by utilising the self-consistent method from the S-parameter
measurements which is fitting the de-embedding structure Additionally the Cj values
are obtained via fitting the measured S11 data and employing the self-consistence
approach Results obtained from both techniques are identical
At zero bias all extracted junction capacitance from each device sizes are very
different from the calculated one while the extracted series resistance are closer to the
calculation This means that Cj is a highly voltage dependent parameter and Rs is
voltage independent but solely dependent on device structure and material used to
fabricate it The extraction at -05V and -1V shows that the values of junction resistance
is changing for most of the devices which means this parameter also rely on bias voltage
as discussed earlier in Section 52
The cut-off frequency for each calculated devices are near the THz range even
for the 100microm2 emitter area However with the introduction of parasitics elements ie
pad capacitances fcut-off is degraded tremendously Therefore it is important to make sure
all the intrinsic elements have optimum values so that the target operating frequency of
the ASPAT diode can be met Due to this it is advisable to operate the devices at no
more than 13 of fcut-off when designing detector systems
The parameters extraction at -05 and -1V also show that Cj values are closer the
calculated ones which means the ASPAT diode is reaching full depletion
172
563 Capacitances -Voltage (C-V) Extraction
Theoretically the junction capacitance of the ASPAT is calculated from the fully
depleted formula 119862119895 = 휀119900휀119903119860119889 which was also discussed in Equation (230) in Chapter
2 in page 43 Its value depends on the change of voltages to depletion at the emitter
contact[15] and make it one of the voltage dependent parameter for the diode[121]
Therefore the C-V characteristic of the GaAsAlAs must be precisely extracted
In practice the capacitance is difficult to measure due to the very low resistance at zero-
bias However alternatively it can be measured and extracted by applying different
voltage and identifying the point at which there is change which essentially represents
full-depletion Apart from these it can also be extracted from S-parameters measurement
which is then converted to Y-parameters A C-V characteristic of the GaAsAlAs
ASPAT from XMBE304C is extracted and plotted as depicted in Figure 518 below
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled capacitance vs
Voltage)
From the graph shown in Figure 518 the capacitance is extracted at eight
different biases for 4times4 microm2 6times6 microm
2 and 10times10 microm
2 The devicersquos junction
capacitance for each dimension increases and reaches a maximum value at 025V There
are additional quantum capacitance effect which comes from an increase in the negative
charges in the 2DEG region (when band bending happens creating an accumulation
0
50
100
150
200
250
-2 -15 -1 -05 0 05
Cap
acit
ance
(fF
)
Voltage (V)
Cj(4x4microm^2)
Cj(6x6microm^2)
Cj(10x10microm^2)
173
region at the barrier) This charge is imaged by the positive charge in the whole
depletion region Increasing the voltage toward positive values leads to a lowering of
the AlAs barrier and thus allowing thermionic emission to take place after certain bias
values leaving only the depletion capacitance and making the quantum capacitance
negligibly small
In the reverse bias case the device junction capacitance reaches a saturation
(fully depleted capacitance) at a voltage of -025V and remain constant up to -2V If the
reverse bias voltage is increased further the ASPAT may reach breakdown Therefore it
is important to know how far the diode can withstand applied reverse bias to ensure it
can still give full performance
57 Conclusions
In this chapter scalable DC characteristics of GaAsAlAs ASPAT diode derived
from three different emitter sizes of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 was
demonstrated The current density obtained at zero bias is several microAmicrom2 These allow
1st order differential effect to exhibit high value of Junction resistance (Rj) at zero bias
However Rj is highly bias dependent The 2nd
order differential effect on IV
characteristics display a high value of curvature coefficient leading to high voltage
sensitivity when applied in millimeter wave detector applications These two parameters
are vital in the design of millimeter wave detectors and especially those operating at zero
bias
Subsequently RF measurement up to 40GHz of uniformity study for both within
wafer and wafer to wafer variance were undertaken An average uniformity below 7
was obtained for within wafer study on large device area ( 15times15 microm2 to 100times100 microm
2)
while for small device area ( 4times4 microm2 to 10times10 microm
2) a smaller 3 uniformity variance
was achieved in average However for wafer to wafer study the variant uniformity was
quite high at around 30 on average for relatively large device (15x15 microm2 to 30x30
microm2) This was mainly attributed to different dielectric layers used in the process flows
of the sample rather than fundamental MBE control of the AlAs barrier thickness
174
It was demonstrated in this chapter that careful on-wafer RF measurements of small
size GaAsAlAs ASPAT diodes allow accurate device parameter extraction of both
extrinsic and intrinsic parameters The extrinsic parameters are namely pad capacitance
and inductance with obtained values of 26fF and 47pH respectively These values were
obtained from de-embedding structure fabricated on the same tile as the real devices
The intrinsic parameters such as junction capacitor junction resistor and series
resistance had different values according to device dimensions The smallest zero bias
value of Cj obtained from 4times4 microm2 diodes was 23fF ensuring a high cut-off frequency of
380GHz and hence in the next chapter a 100GHz detector will be presented working at
slightly less than 13 of this cut off frequency
The C-V data extraction confirmed that the fully depleted capacitance started to
happen at around -025V The maximum junction resistance occurs at +025V largely
caused by the depletion region and an additional quantum capacitance effect CQ This
effect is strongly related to the size of a 2DEG which occurs under forward bias (01V to
025V) and can be reduced by having a smaller thickness AlAs barrier
175
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR
DESIGN USING ADS
61 Introduction
The ASPAT diode having features of non-linear IV characteristics at zero voltage
make it useful for signals rectification ie detector and mixer for millimetre-wave
applications Additionally ASPAT diodes have a range of advantages such as large
dynamic range strong temperature insensitivity etc[15]over other rectifier diode This
makes ASPAT an appropriate candidate in RF detection applications Since 1940 the
only two terminals device that has been the workhorse for RF applications is the
Schottky Barrier Diode (SBD)[9] In its earliest form the SBD was built based on a
point-contact device which could not perform at high frequencies It was then developed
to work at higher frequencies by exploitation of epitaxial structures [10] and to date the
SBD remains the mainstay of two terminal devices that are able to work in the
millimetre and submillimetre-wave regions However as discussed in Chapter 4 the
performance of SBD is degraded at extremes of temperatures and these circuits
employing SBDs require temperature compensating circuitry Thus there is additional
complexity associated with technologies and applications related to SBDs
Before this work was carried out no model for the ASPAT diode as detector had
been available or developed especially using the empirical modelling ADS software
When the ASPAT diode was first introduced its function was conceptually explained it
was then built and tested to compare with other microwave detectors at X-band
frequency (95GHz) The comparisons were made in terms of detector parameters ie
sensitivity dynamic range temperature dependence etc[15] These early works lead by
RT Syme et al supplied the basic knowledge to model the ASPAT diode as a zero-bias
detector for mm-wave frequency gt100GHz For the SBD many models and equivalent
circuit approaches have been reported [122 123] The modelling of conventional SBD is
mostly implemented through fitting the S-parameter curves of the model to the
experimental one This approach is also carried out in this research since it is accurate to
predict the performance of the device under test [124]
176
This Chapter aims to introduce low cost reliable and sophisticated detector design
based on ASPAT diodes which is believed to be able to improvereplace SBD in
millimetre-wave applications especially in imaging The focus was on developing and
establishing an appropriate circuit design that suit the new ASPAT diode for such
applications The detector sensitivity as its key parameter ultimately limits the quality
and acquisition time of the detector In the subsequence section the theory of detection
including both direct and heterodyne will be discussed This is followed by definition of
detector characteristics of interest as well as noise consideration Section 65 present the
main focus of this chapter which is the development of 100GHz ASPAT detectors and
their result will be explained in term of all detector characteristic of interest
62 Detection Theory
Any incoming signal such as RF microwave or mm-wave in the form of envelope
function or single wave can be detected by rectification of the signal using a nonlinear
device ie transistor or diode The input and output signal (RF) signals are normally in
the form of amplitude as a function of time Typically the detector output is a low-
frequency signal known as the video signal which has amplitudes that are proportional to
the square of the input RF signalrsquos voltage amplitude
A complete receiver system as shown in Figure 61 below consists of receiver
antenna and a circuit designed to extract the signal and then amplify it The function of
the receiver system is the converse of the function of the transmitter side At the receiver
side the antenna is used to receive the signal it then conveys the signal to the extraction
circuit for detection as the information-bearing part of the signal (using the nonlinear
device as its heart) The signal is finally amplified to avoid any information strength
decay Additionally in a digital system the output signal which had been processed by
the detector circuit has to maintain an optimum input signal conveyed to in-phase and
quadrature (IQ) demodulators The output signal will go through a low pass filter then
to an analogue-to-digital converter (ADC) and thus a digital baseband output signals
will be produced
177
Figure 61 Block diagram represent a complete direct receiver system
There are two types of millimetre wave integrated circuit (MMIC) used for
detection purposes namely direct detectors and heterodyne detectors The direct detector
MMIC is the simplest circuit used for detector applications and has the simplest way of
extracting the RF information Due to its simplicity the direct detection method is
inexpensive and most attractive method used for measuring power in RF Laboratories
and Industries This detection scheme is also sometimes known as video detection[125]
The simplest way of explaining the detection process is that the incoming RF or
microwave signals depicted in Figure 62 below with an appropriate input power (Pin) is
rectified by using a diode and results in a corresponding output voltage (Vout) A detector
IC designed based on diodes is normally able to rectify very low levels of RF power (lt-
40dBm) then produces an output DC voltage that is proportional to the RF power A
rectifier diode can function at zero bias (which is very good for reducing noise) at very
small DC bias (003mA) and relatively high RF impedance which will produce around
600Ω This will affect the capacitance value and a low capacitance is needed to realise a
high detection sensitivity
Figure 62 The detection process of a single wave through a non-linear IV characteristic of a diode
Detector
Speakerdisplay unit Amplifier
Antenna
Vout
Pin
Tuner Amplifier
178
However this type of detector has a drawback which is itrsquos relatively low signal to
noise ratio Thus it will also rectify any incoming electrical noise at all frequencies and
up to the cut-off frequency (fC) The basics lumped components circuit as shown in
Figure 63 is used to build such detector which consists of Source impedance (Zo)
Rectifier diode (ASPAT or Schottky) wire or pad inductance and capacitance and Load
impedance (RL)
Figure 63 Lumped element illustration of microwave detector circuit
Another type of detector is the heterodyne method which mixes incoming RF or
microwave signal (fRF) with another constant signal produced by a secondary circuit
called the Local Oscillator (LO) The LO frequency (fLO) must be slightly higher than fRF
to enhance the RF signal This mixing between fRF and fLO happens in the nonlinear
device as depicted in the Figure 64 This will produce a signal at a different frequency
called the intermediate frequency (fIF) which can then be amplified and detected as
explained in the previous paragraph Theoretically a basic requirement of the mixer is to
have fIF as efficient as possible while practically the minimum conversion efficiency
obtained is around 20 The main reason for using a mixer is due to the fact that
selective amplifiers at RF frequencies are costly and hard to achieve Hence a mixer is a
good technique as it only convert the signal to a lower frequency in which good
selectivity and high gain can be more effortlessly realised[14] A good mixer diode is the
one that can produce a high cut-off frequency and reduce conversion losses (Lc) A
mixer and detector diode with a low driven input power result in reducing overall noise
figure and thus in the ideal case the fIF amplifier also should have a low noise figure for
better performance The advantage of the heterodyne method is that it has a higher
179
sensitivity compared to the direct detection method this is achieved by producing an fIF
which has a lower frequency than the incoming RF signal[14] Obviously a zero-bias
voltage diode is more favourable to be used in mixer and detector applications
Figure 64 The mixing process where the signals are processed by the non-linear I-V characteristic
to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and fRF are applied to the
diode
To have good detection efficiency for both types of detectors the operating
frequency (fO) must be several times smaller than fC In the case of an incoming
maximum modulated signal fM the frequency that can be acquired is in the range of fO
plusmnfM and will normally come with noise The standard method that is used to reduce the
noise is using a filter of bandwidth about 2fM at the centre of fO with the condition that fO
must be smaller than fM (f0lefM) Otherwise it would be difficult to attain However in
most cases fM is smaller than fO and fO is smaller than fC thus this will make the video
impedance (RV) (or nonlinear impedance) very close to the differential resistance of the
diode (at fO) in the equivalent circuit[74]
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis
Theoretically a transfer function measurement is preferable prior to any empirical
modelling since no assumption can be made due to the detector non-linearity
Furthermore measuring voltage output at high frequency can be very low while
measuring the power incident on the detector is hard to achieve where the linearity of
180
the typical power meter is normally less than 3 over its operating range[126]
Therefore the modelling of detector output voltage vs input power (ie transfer
function) can help to determine both nonlinearity correction and appropriate operating
range for the detector itself
The performance of the diode that is often taken into account is the transfer function
(output voltage Vout versus incident power Pin) and the main parameters that is used to
characterise and determine the quality of any detector diode are the voltage sensitivity
(βV) tangential sensitivity (TSS) dynamic range (P1dB) ie under 1 dB roll off power and
variation of output voltage when examined in extreme temperature situation (ΔV(T))
The voltage sensitivity in small signal analysis can use the approach introduced by
Torrey and Whitmer [9] then βV can be expressed as
120573119881(119894119889119890119886119897) =
119877119895119877119871120581
2(119877119881 + 119877119871) (1 +119877119904
119877119895)
2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(61)
Where ω is the angular frequency (2πf) Cj is the junction capacitance of the diode
active region RL is the load resistance RV is the video impedance taken from the
expression of Rj + Rs and κ is the curvature efficiency that give small signal rectifying
action of the ASPAT diode which is given by the second order term and itrsquos expression
is
κ =
11988921198681198891198812frasl
119889119868119889119881frasl
(62)
The curvature coefficient or responsivity (κ) is translated directly from the non-linearity
of the IV characteristics of the ASPAT diode for detector application Both RV and κ are
the parameters that can be extracted directly from diode DC measurement as discussed
in Chapter 5
The voltage sensitivity is actually a quantitative relationship between input
power and detector response Meaning that it is a change in signal output over change in
input power Normally output power is measured in Volts and input signal is measured
in Watts Therefore the unit of responsivity is VW[127 128]
181
TSS is referred to the lowest or minimum signal that the detector could detect it is
determined by the diodersquos βV and total noise available in the system (from the diode and
any amplifiers in the detector circuit) For any diode with fO=10 GHz and low noise of
1MHz bandwidth amplifier the TSS is typically less than -55 dBm[74] The TSS equation
is given by
119879119878119878 =
radic[4119884119870119861119879119861(119865119886 + 119905 minus 1)]
119872
(63)
Where M is a figure of merits and is derived based on the expression M= 120573119881 radic119877119881frasl t
denotes the diode noise temperature Fa is the noise figure B T and Y are the amplifierrsquos
bandwidth temperature and power for signal-to-noise ratio respectively For a low-level
video detector ie lt10GHz the sensitivity mainly depends upon three factors firstly on
RF matching structure secondly on the rectification efficiency output impedance and
noise properties of the diode and finally the input impedance bandwidth and noise
properties of the video amplifier at the detector output The RF matching structure
controls the quantity of overall energy at the active junction for rectification The second
factor controls the reaction of the diode to incident microwave radiation and the last
factor will influence the detector sensitivity in general[109]
In practical the Tss is a direct measure of the signal-to-noise ratio of a detector and
is achieved by varying the amplitude of the input pulse (RF signal) until a point in which
the top of the noise level with no signal applied is at the same level of noise at the
bottom level of RF signal It is commonly measured on an oscilloscope as depicted in
Figure 65 below It is defined as the input power at which a signal to noise ratio of 251
is produced[109]
Figure 65 Measurement of Tangential Sensitivity[108 129]
182
The transfer function in many detector diodes is often divided into three sections
Firstly at low incident power secondly at higher input power and finally at very high
power static (continuous) In the first region the detector diode performs as a square-law
detector in which Vout is proportional to Pin This region normally is used to extract the
dynamic range of the diode detector In the second region Vout is approximately
proportional to Vin and this region is known as the linear regime Finally at higher Pin
still the transfer function or response rolls off and thus Vout ultimately become saturated
This roll-off point where Vout has dropped by 1dB below an extrapolation of the
dependence at low Pin is termed the ldquo1dB roll-off pointrdquo and this value is usually in the
range of -11 to 12 dBm[15] Therefore a dynamic range of the detector diode can be
obtained by taking the interval between TSS and 1dB roll-off point (in dBm)
Finally the temperature dependence of Vout for a detector is normally taken from
two extreme points of the temperature (-40C˚ to +80C˚) and thus can be determined
from
Δ119881(119879) = 10 11989711990011989210 |
119881(1198791)
119881(1198792)|
(64)
This Vout variation between -40C˚ and +80C˚ normally expressed in dB
64 Noise Consideration in a Detector diode
The existence of noise in a system limits the accuracy of device performance and
the precision of measurements In a detector system specifically using a diode the noise
which can reduce the sensitivity of signal encryption is called the Noise Equivalent
Power (NEP) By definition the NEP is a noise power density over the detection
sensitivity and it can be exploited to determine the overall noise performance of a
detector[130 131] In other words NEP is defined as the power from the input source
(Pin) that is required to supply a voltage output (Vout) equal to the root means square
noise at Vout [132] For an ideal lossless match and assuming only Johnson-Nyquist is
present the NEP of a zero-bias detector can be expressed as
119873119864119875119900119901119905 = radic4119896119879119861119877119881120573119900119901119905 (65)
183
Where βopt is responsivity with an optimum match which is given by1 2frasl 119877119895120581 This type
of noise appears when changing voltages across a diode and a noise voltage (Vn)
normally will arise Theoretically the NEP has units of Watts (as it is actually a power)
but it often normalized to 1Hz as it is independent of bandwidth and thus the unit
becomes WHz12
Additionally there are also several noise sources that contribute to Vn in a
semiconductor diode which are Johnson-Nyquist noise Flicker Noise and shot noise
Johnson-Nyquist noise [133 134] appears across any conductor or semiconductor at
thermal equilibrium this is due to the thermal agitation of the carriers or charges It can
be expressed in root mean square voltage as below
119881119869minus119873 = radic4119896119879119861119877119895
(66)
Where Rj is the differential intrinsic resistance B denotes the post-detection bandwidth
T is the device temperature and k is the Boltzmann constant[134]
The second noise that is taken into consideration when dealing with semiconductor
devices is Flicker noise more commonly known as 1f noise It is a group of known and
unknown noise sources that can be observed in the frequency spectrum and normally
display an opposite to the frequency power density curve[135] It comes from a variety
of different causes ie recombination effects at a defect in semiconductor mobility
fluctuation and flow of direct current as well as interface phenomena [136-138] In term
of voltage source Flicker noise can be expressed as[139]
1198811119891 = 119870119891119881119909119891119910 (67)
Where Kf denotes a device-specific constant V is the voltage and f is the frequency The
value of x and y typically used are 2 and -1 respectively This type of noise (1f noise)
will be neglected at frequencies high enough due to the fact that the NEP of the diode is
proportional to the thermal noise and resistance of the diode
Finally the noise that causes time-dependent fluctuation in a flow of electrical
current because of the carrier or electron charge crossing a potential barrier is called shot
noise Shot noise is due to the randomness in the diffusion and recombination of both
majority and minority carriers[140] The equation of shot noise term at random time is
given by[141]
184
119881119878ℎ119900119905 = 2119902119868119861 (68)
Where q is the electron charge I is the current and B is the bandwidth This type of noise
is not affected by changes in temperature or device parameters Therefore the total noise
voltage appearing in the semiconductor is found to be [141]
1198811198992 = 119881119869minus119873
2 + 11988111198912 + 119881119904ℎ119900119905
2 (69)
However a zero-bias device will greatly eliminate both shot and flicker noise
compared to a biased device This has been explained by Equation (66) and Equation
(67) above where both noises are significantly related to the current and voltage Thus
if V and I =0 in the nonappearance of incident power then Vn will also become zero For
a detection process with bias the diode will be self-biased by ΔV which causes both
flicker and shot noise to appear But the shot noise in practical situation is much smaller
and thus normally ignored [142-144] Usually the noise in a zero-bias detector is
estimated by considering the low power limit as good first order estimation in which the
presence of only Johnson-Nyquist noise and ΔV is arbitrarily low [11 145 146]
Additionally it has been reported that the noise in tunnelling type diodes displays very
low or no excess noise in the bias region of the current-voltage characteristic[147 148]
Therefore in general most of the noise specifically in tunnelling type of diode will be
neglected this is a great advantage compared to SBD or transistors
65 Modelling of a 100GHz Zero-biased ASPAT Detector
Once the DC and RF characteristics of the ASPAT diode had been accurately
obtained the next step is to model and design a detector circuit based on S-parameter
measurement results as was explained in the previous chapter The aim is to realise a
detector circuit design which can be operated at millimetre and sub-millimetre wave
regions from an accurate diode model prior to the circuit design A diode detector model
puts experimental observations into context and offers insight into future experiment
results Consequently an electrical model based on lumped element component is vital
for a deeper understanding of how and to what extent a new device like the ASPAT
diode can affect all the key detector parameters that were previously discussed The
prediction of the detector parameters mostly depends upon the ASPAT diode
185
geometrical emitter size and material parameters However for millimetre wave
operating frequency the accuracy of the model is more sensitive not only to diode size
but also to the diode periphery ie substrate as well as coplanar amp transmission line
adopted in the circuit Therefore both extracted intrinsic and parasitic element of such a
device must be taken into account
In this work an ASPAT diode with an emitter size of 4times4microm2 which is the
smallest size that could be fabricated so far was chosen to be exploited for detector
designs The important parameters related to the 4times4microm2 GaAsAlAs ASPAT which
works at 0V is summarize in table 61 below
Table 61 A summary of all the important parameters of the 4x4 microm2 diode
Device Rj(Ω) Rs(Ω) Cj(fF) Cp(fF) κ(V-1) Intrinsic_fcut-off(GHz)
4times4microm2 90K 11 21 15 23 629
The actual measured I-V characteristic is used to model the diode since the library
in the ADS simulation tool does not have an ASPAT diode model or any tunnelling
diode for that matter The procedure of realizing the diode model is by taking the I-V
characteristic obtained from the 4times4microm2 emitter size measurement results and
converting it into a10th
orders polynomial equation via MATLAB software to create a
virtual I-V characteristic Thereafter this equation is then defined as a two terminals
device namely Symbolically-defined Device (SDD1P) ie a component of the non-
linear equation provided by ADS (Figure 66) to represent the ASPAT Figure 67
shows the measured data and 10th
orders polynomial equation fit very well to each other
Hence this new component used to represent the whole ASPAT diode will be used in
this research for MMIC detector and Frequency Multiplier designs The device chosen to
be modelled (4times4microm2) has measured junction capacitance of 21fF (at 0V at 40GHz) The
detector circuit is designed to operate at 100GHz for a safe side due to the extrinsic
calculated fcut-off is around 380GHz Since there are a lot of advantages in using unbiased
detectors compared to biased one this work will discuss the performance of millimetre-
wave detector at zero-bias and their result will be compared to the current performance
of other diodes reported in the literature
186
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted from
MATLAB to realize a virtual GaAsAlAs ASPAT diode
Figure 67 Verification of actual (blue measured) and virtual (red_10th order polynomial) I-V
characteristic of the 4times4 microm2 diode used in this study
To realize the ASPAT detector circuit a simple detector circuit topology as
depicted in Figure 68 was constructed Initial simulation was run to perform a
functionality check of the detector circuit utilizing the Harmonic Balance (HB)
simulation tool embedded in that particular software Such simulation tools will analyse
the detector performances in the frequency-domain as it is mostly beneficial and fully
compatible with microwave and millimetre wave problems The frequency domain is
also suitable for single and multi-tone power excitation The importance of harmonic
balance are described in [149]
-00005
0
00005
0001
00015
0002
00025
0003
-3 -2 -1 0 1 2 3
Cu
rre
nt
(A)
Voltage (V)
ADS
4x4
187
Figure 68 Direct detector circuit topology using an ASPAT diode
Initially the circuit topology that consists of P1_Tone power supply ASPAT
bypass capacitor and load resistance is simulated by setting up a fixed input frequency at
100GHz The ASPAT diode provides a DC output voltage proportional to the input
power strength depending on the absolute values of the DC terms associated with the
nonlinearity of the I-V characteristics The capacitance in the output part is a bypass
capacitor used to prevent millimetre-waves from leaking to the output The load
resistance is large enough to ensure the voltage divider between load impedance and
device impedance gives maximum voltage sensitivity This large load resistance is
achieved by creating an open circuit at the end of detector circuit terminals
Noted that this simulation was run using diode parameters that were extracted from on-
wafer one port S-Parameter measurements as described in chapter 5 To apply them in a
two port application ie detector circuit may or may not provide a very accurate
outcome it however worked adequately in the particular circuit described in this chapter
but may not work in other circuits in general Thus the one port extractions in this work
still provide adequate parameters to build and design specific MMIC detector circuits
but not in general applications
The main reason for these simulations and their results to be used in high frequency
applications is due to the fact that actual RF measurement were done up to 40GHz
Additionally the 100GHz operating frequency was obtained from extrapolation of each
ASPATrsquos component Since the on-wafer measurement that were carried out were
limited to one port characterization applying them to two port network applications may
188
have extra consequences which are unknown Therefore actual MMIC detectors are
needed to be built and test to validate this work
To find out what power the 4times4microm2 ASPAT diode can withstand the input power
is varied from -40dBm to 10dBm via control by the P1_tone As can be seen in Figure
69 the diode starts to saturate when the received input power is about -8 dBm Above
this power limit both output voltage and sensitivity drop dramatically
Figure 69 Output voltage and detector sensitivity over wide range of input power
This diode detector circuit can thus operate adequately at given input powers from -30
dBm to -8 dBm with a sensitivity of 950VW However for the best possible sensitivity
over a range of input frequencies only one optimized input power needs to be chosen
The parameters that directly influence the voltage sensitivity are the curvature
coefficients load resistance and video resistance as can be seen from Equation (61)
Therefore in the following simulation the values RL will be optimized according to the
diodes optimum input power with regards to the highest possible voltage sensitivity
Consequently five values of load resistance were chosen from few ohms to infinity
and with the same applied input power as depicted in Figure 610 For most load
resistors the sensitivity is constant at low input power and drop at the diode saturation
region (-8dBm and greater) However for an RL value of 100KΩ and below the loaded
voltage sensitivity shows a peak near 0dBm input power which corresponds to the
maximum slope of the ASPAT detector transfer function The highest voltage sensitivity
is obtained by using an Open circuit load impedance as shown in the graph The Open
circuit load impedance gives the highest voltage sensitivity due to the voltage divider
189
between source and load impedance therefore RL must be at least 5-10 times larger than
Rj to give a better sensitivity
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load resistance of
the ASPAT detector
Furthermore the value of voltage sensitivity (βV) depends on the junction
resistance of the diode and thus the large value of Rj of the ASPAT diode yields the high
βV observed Rj which was taken from the non-linear measured IV characteristic is a
voltage dependent parameter [142]and is inversely proportional to the forward bias
voltage as depicted in Figure 611 below
Figure 611 Junction resistance as a function of forward voltage
1
10
100
1000
-40 -30 -20 -10 0 10
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Incident Power Pin (dBm)
Infinity
1KΩ
10KΩ
1MΩ
100Ω
100KΩ
0
20
40
60
80
100
0 001 002 003 004 005 006 007 008 009 01
Ju
nct
ion
Res
ista
nce
(k
Ω)
Bias Voltage (V)
190
In fact the expression of (120597119881120597119868frasl ) contribute to the video impedance expression via the
expression RV=Rj+RS (nonlinear resistance) As RS is very small compared to Rj thus it
was ignored when calculating RV Although the large value of Rj will increase the
voltage sensitivity it will also make matching difficult to achieve Therefore there will
be a compromise between the size of the matching circuit and voltage sensitivity to
attain the correct value of Rj Additionally a very high Rj (around ~1MΩ) will also
increase the detectorrsquos noise equivalent power (NEP in Eq(65)) Thus an average value
of RJ typically around 100kΩ is satisfactory[150] By having a large value of RJ one can
benefit from a low input power to drive the diode into the non-linear region and thus the
detector can work at very low RF input power The NEP for GaAsAlAs ASPAT diode
is then calculated based on parameters obtained from this simulation at room
temperature The values are compared to other diode detector available in the literature
as shown in Table 62 below
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode
Device NEP (pWHz12) RJ(KΩ) Frequency(GHz)
ASPAT (4times4 microm2) 188 92 100
Tunnel Diode (08times08 microm2)[150] 370 26 220-330
Zero bias SBD[11] 15 3 150
Sb-Heterojunction Backward Diode[145] 024 32 94
VDI Zero bias SBD[151] 2 18 110
From the Table 62 above the NEP of the ASPAT is calculated based on RF input power
which is required to obtain an output signal-to-noise ratio of unity in a 1Hz at detector
output[142] and also the assumption of only Johnson-Nyquist (thermal noise) is
dominant for small incident power (-25dBm)[152 153] The prediction of NEP for the
ASPAT is comparable to the VDI Zero bias detector since the value of their junction
resistance is much lower than that of the ASPAT Therefore it is very important to
obtain a reasonable value of junction resistance From this it is clear that a trade-off of
high voltage sensitivity and low junction resistance is best to obtain low noise
191
Finally the curvature coefficient at specific operating voltages also influences
the voltage sensitivity of the detector Figure 612 shows the calculated curvature
coefficient of the 4times4microm2 ASPAT diode used in this work
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size of 4times4μm2
The high zero-bias curvature (23V) is reached from the mutual effect of the intra-band
tunnelling in the GaAs-AlAs-GaAs and the highly doped GaAs at the anode and cathode
(Rs amp Rj) This was shown in the numerical simulation in[154] where the combined
effects of the optimum anode AlAs composition increases the curvature coefficients by
thinning the energy tunnelling window (intraband tunnelling process)
Other approaches that can lead to a large curvature is using smaller device area
with minimum series resistance [155] as was also discussed in Section 52 Having a
better curvature coefficient leads to increased voltage sensitivity as seen from Equation
(61) above and βV is also proportional to κ [111] The curvature coefficient calculated
using the above formula is nearly 23V at 1mV peak and high voltage sensitivity can be
achieved by having large value of curvature coefficient But one needs to remember that
this will also decrease with increasing input power because RJ which will also decrease
Therefore for a safe operating region the incident power that can be applied through the
diode is in between -30dBm to -8dBm for a 100GHz operating frequency
In this simulation -25dBm is chosen to simulate the GaAsAlAs ASPTAT diode
detector working at 100GHz input frequency By fixing the P1_Tone to this input power
-5
0
5
10
15
20
25
30
-001 001 003 005 007 009
Cu
rva
ture
Co
effi
cien
t(V
-1)
Voltage (V)
k(4x4 um^2)
192
the frequency is varied from 90GHz to 110GHz and the results are depicted in Figure
613 below
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power
Noticeably the voltage sensitivity of the diode detector decreases linearly with
increasing input frequency At 100GHz a sensitivity of around 540VW is obtained
However the sensitivity in this case is roughly estimated from the Equation (61) above
and will not be sufficiently accurate because of the effect of other key factors such as
reflective power which was not included This parameter must be taken into the account
due the P_1Tone power source which provides a 50 Ω impedance source (Zin) which
does not match the load impedance (ZL) which consists of JωL 1JωC and Z and which
mainly comes from the ASPAT diode itself In order to determine the load impedance at
the diode a typical ohmrsquos law (Z=VI) equation must be used at the input side of the
diode with regards to the applied frequency (100GHz)
As a result the total load impedance obtained from the simulation is 11055-
j69057Ω which is clearly not matched to the 50Ω impedance source The mismatch
between source and load leads the available power from the source to be not fully
delivered to the load and hence there is loss of power leading to a lower detector
sensitivity Therefore actual calculation must take into the account the reflection impact
as expressed in the equation below
193
120573119881(119886119888119905119906119886119897) =
119877119869119877119871120581(1 minus |Γ|2)
2(119877119881 + 119877119871) (1 +119877119904
119877119895)2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(610)
Where the term (1-|Г|2) refers to the normalized power absorption by the ASPAT diode
and Г is the reflection coefficient due to discrepancy between 50Ω input impedance (Zin)
of the input port and the diode Consequently the calculation of reflection coefficient
(eq611) is carried out by using this expression and the result is shown in Figure 614
Γ =
119885119871 minus 119885119894119899
119885119871 + 119885119894119899
(611)
Figure 614 Reflection Coefficient versus operating frequency without matching circuitry
As can be seen in Figure 614 without the matching circuit the S11 is decrease
linearly with frequency but only very slowly This means that most of the RF power
transmitted from the source is reflected back (by that ratio) when it went through the
diode Therefore in order to resolve the mismatch a matching circuit is introduced in
between the source and load of the detector circuit as shown in Figure 615 (red
rectangular) This matching circuit works by transforming the load impedance into an
impedance that is identical to the source or input impedance Note that for any
impedance matching circuit the main purpose is usually to obtain maximum power
transfer to the load however in some cases (ie oscillators) the matching circuit is to
achieve a lower noise figure Hence in a broad sense the introduction of the matching
194
circuit in a detector circuit can be defined as a circuit that convert available impedance
into wanted impedance by obeying the maximum power transfer theorem [156]
Figure 615 Detector circuit with impedance matching circuit placed in between diode and source
There are many type of matching circuit that can be used to achieve both
objectives above such as circuits using lumped element transmission-line-impedance
matching circuit single and double-stub tuners as well as a quarter-wavelength In this
design the technique used to match source and load impedance is the single open and
short stub (in red rectangular) as it is simple convenient and very efficient in ADS
simulation The important parameter that needs to be tuned in both stubs is the electrical
length (E) at any designed frequency ie 100GHz in this case The E tuning is realized
by using the Smith Chart features available in the ADS simulation tools Figure 616
shows the reflection coefficient with matching circuit modelled over a broad frequency
band and it is clearly shown that at the desired operating frequency the reflection is very
low Note that it is difficult to obtain wide frequency band matching
Matching circuit
195
Figure 616 Reflection Coefficient over wide frequency band with matching
The simulation is continued to find the effect of the matching circuit placed in
the detector circuit on the voltage sensitivity The same input power (-25dBm) is applied
to the diode and the voltage sensitivity is plotted against frequency as depicted in Figure
617 Obviously at the desired operating frequency (100GHz) the sensitivity rises up to
a maximum value of 2100VW with this value obtained without any reflection and the
input port being completely matched with the ASPAT diode model used in this work
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band frequency
Once the matching circuit to be used for 100GHz operating frequency was confirmed
further simulations were made by applying a series of low input power to find the
tangential sensitivity (Tss) of the detector diode When determining the Tss it is very
important to include the matching circuit as it will minimize any power losses through
the diode thus a very small input power can be detected
196
Figure 618 Lowest detectable signal at 100GHz operating frequency
The transfer function depicted in Figure 618 shows incident power of -80 dBm
to -50 dBm applied and the lowest detectable signal that can be obtained with 4times4microm2
mesa size ASPAT diode is around 138microV at -68dBm Although a typical value of Tss is
normally not more than ~-55dBm as in ref [74] the lower value obtained in the
simulation is because the device is operated at zero bias operation and does not use any
amplifier therefore the noise and values related to amplifier as in Equation 63 have been
neglected Even though the TSS appeared very low it is most likely very dependant to
the 10th
order polynomial equation embedded into SDD in ADS software Therefore in
near future the TSS value has to be determined in real fabricated MMIC ASPAT detector
As discusses in Section 63 other important parameter that can be extracted from
the diode transfer function is the Dynamic Range of the diode It can be obtained in a
region called square law region which is a region where the Vout of the ASPAT diode is
proportional to the square law of the input power signal From Figure 619 the square
law region is in between -68dBm and -12dBm and the linear region or in this case
saturated region is above -12dBm Taking to the account the roll-off point where Vout
has dropped 1dB below the extrapolation of the dependence at low input power and
therefore the dynamic range of the detector diode can be obtained by taking the interval
between TSS and the 1dB roll-off point (in dBm) which is ~55dBm
197
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of diode operation
The figure of Merit (M) of the detector (ie equation 63) is 2100 (90K) 12
where 2100 is the sensitivity and 90K is the value of RJ at zero bias which is equivalent
to 652 W The M value should be large however in this case due to RJ being very
large it has dropped tremendously when compared to the voltage sensitivity obtained in
this simulation The results obtained indicate a reasonably successful design of the
MMIC detector using the 4times4microm2
emitter size GaAsAlAs ASPAT diode The results
obtained lead to the design of other MMIC detector using the other fabricated diode
sizes (6times6microm2 and 10times10microm
2) A Similar procedure to the one used for the 4times4microm
2
diode was followed The only difference was the use a slight higher input power (-
20dBm) than in the 4times4microm2 design Hence the simulation results obtained are then
compiled and compared as depicted in Figure 620
Saturated
Region
198
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained from the
fabricated ASPAT in this work
The graph plotted for each dimension was taken after matching circuits were included
As can be seen in Figure 620 the highest sensitivity is achieved using the smallest
device size as this has the highest cut off frequency Table 63 below summarises the
performances of the 100GHz ASPAT detectors obtained from the simulation in this
work
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector
Device Tss(dBm) fcut-
off(GHz)
Bv
(VW)
Dynamic range dB(dBm) M(W-12
)
4times4microm2 -68 380 2100 55 65
6times6microm2 -50 151 1445 48 45
10times10microm2 -40 98 247 40 21
From table 63 above it is clear that a lower cut-off frequency will affect the
voltage sensitivity The dynamic range between each ASPAT is different because larger
size area will allow more power to go through the diode as a result of high current that
such a device can handle before reaching the saturation their lowest detectable is higher
Small diode size will detect lowest voltage but cannot handle high power On the other
hand a large diode size is able to receive high power however can only offer lower
voltage output Therefore there is a trade-off between small diode size and receiving
input power which will directly affect Tss and 1dB roll off Once again all the
100
1000
10000
90 95 100 105 110
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Frequency (GHz)
10times10microm^2
6times6microm^2
4times4microm^2
199
parameters obtained in this simulation are just estimation from the 10th
order polynomial
equation thus real ASPAT detector has to be fabricated for verification
The best device performance among all GaAsAlAs ASPAT diodes was obtained
with the 4times4microm2 mesa area size diode which was compared to other exiting millimetre
wave detector diode available in the literature Since the 100GHz is located in the W-
band spectrum frequency therefore the comparison will be performed in this frequency
band but with low input power The parameters for the-state-of-the-art zero bias
detectors are gathered in Table 64 below
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero bias detector
at W-band (75GHz-110GHz)
Device Size(microm2) Tss(dBm) βv (VW) Pin (dBm) f (GHz)
GaAsAlAs ASPAT 4times4 -68 2100 -25 100
GaAs SBD HSCH-
9161[157]
- -49 2200 94
HBD[158] 15x15 2540 -20 95
Planar SBD[159] - -68 2100 -25 100
Note that the ASPAT diode retains its favourable temperature stable characteristics
which are not the case for all the diodes used for comparison in Table 64
66 Conclusions
In this chapter all theory regarding RF detection using diodes ie parameters of
interest noise consideration etc have been discussed The aim to design and develop a
low cost reliable and sophisticated zero bias 100GHz detector circuit was achieved
through exploitation of a 4times4microm2 GaAsAlAs ASPAT diode The design was performed
with the aid of Keysight ADS modelling software utilizing harmonic balance simulation
The effect of load resistance junction resistor to the detector voltage sensitivity was also
discussed in details The 90KΩ Rj value and open circuit load resistance was chosen for
high sensitivity
200
A step by step design of a W-band ASPAT detector was presented The effect of
matching circuit was discussed in detail and where an unmatched sensitivity of 843VW
is obtained which then increases to 2100VW after matching Through RF
characterization simulation a detection at 100GHz (W-band) was successfully achieved
with a relatively large device mesa area (4times4microm2) at an input power of -25dBm
(8microWatt) leading to a 2100VW voltage sensitivity a -68dBm TSS and 55dBm dynamic
range All these values are comparable to others fabricated diodes in the literature
The zero bias ASPAT detectors based on the GaAsAlAs material system in this
work are still at an early stage of development a lot of work is still required to realize
high yielding integrated millimeter and sub-millimeter wave (MMIC) detector circuits
However as this work is on-going at Manchester it is expected that fabricated ASPAT
MMICs with even higher voltage sensitivity will be fabricated in the near future through
collaborating bodies involved in this research especially the University of Cambridge
and ICS Limited
201
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING
GAASALAS ASPAT DIODES
71 Introduction
Originally the key application for the ASPAT diode was for use as microwave and
millimetre wave detectors[18] This is due to the fact that such diode demonstrates
strong non-linearity low noise and high cut-off frequency features as described in the
previous chapters However these features are not only beneficial for detection purposes
but also allow them to be used and designed as microwave and millimetre wave sources
The only way to generateenhance continuous wave (CW) power using a non-linear
device is through frequency multiplication techniques It is known that the frequency
multiplier is the alternative approach (to 3 terminal transistors) using non-linear devices
that are used to generate high frequency low phase noise signals Any high quality low
frequency signal that goes through a frequency multiplier circuit can be generated to any
desired high output frequency[160] Therefore the main objective of this chapter is to
demonstrate the feasibility of the ASPAT diode as a compact source of microwave and
millimeter-wave receiver for imaging applications[161]
The study of the ASPAT diode as a power source begins with a brief explanation
of the importance of a frequency source and the lack of compact device and technologies
at high-frequency signals The state-of-the-art for frequency multiplier will also be
discussed In the next section (Section 74) the fundamentals of the frequency multiplier
architecture ie the principle of operation and appropriate devices will be presented
Since this is the first attempt at using GaAsAlAs ASPAT diodes a simple multiplier
circuit design and topology was built This will be discussed in detail in the subsequent
sections where simulation results are discussed The focus of the discussion will be to
demonstrate the possibility of a GaAsAlAs ASPAT diode functioning as a frequency
multiplier and comparison with other state-of-the-art varistor mode frequency
multipliers
202
72 Motivation and Background
Typically continuous wave (CW) sources generating below 100 GHz can be
obtained through oscillators amplifiers and pin diode comb generator Below 10THz
the sources can be made from RTD IMPATT diodes and Gunn oscillators and above 10
THz it is commonly done by photonic mixing quantum cascade laser (QCL) and gas
lasers [162] Both types of sources and their performance are plotted in Figure 71
However these conventional ways of generating millimetre and sub-millimetre waves
have their own limitations ie high cost complexity and sometimes requirement for
cryonic cooling The most effective way to tackle the limitations of conventional mm-
wave and THz sources is by implementing frequency multiplication technique using
solid state nonlinear diodes [163-165] such as SBD and ASPAT diodes
Figure 71 performance of state-of the-art millimetre wave source [166]
Twenty years ago there were only two types of diodes (SBD and P-N junction
diodes) often used for frequency multiplication To date besides the SBD there are
many types of diode that have been used as frequency multipliers These include the
high electron mobility varactor (HEMV) single barrier varactor (SBV) [167] and hetero-
structure barrier varactor (HBV) (270GHz with 90mW input power and Conversion
Efficiency of 72)[168 169] Other variants that have developed to enhance the
frequency multiplier performance of the classic SBD [170] include the Barrier-intrinsic-
203
n+ (BIN)diode and Barrier N-layer N+ (BNN) diode [171] Other diodes for use in such
applications are the planar doped barrier diode (PDB) Resonant tunnelling diode (RTD)
amp it families ie Quantum well diode (QWD) and step recovery diode which is a
modification of the P-N junction diode
Although three terminal devices ie FET GaAs MESFET and HEMT had
shown better performance and are capable of achieving greater efficiency and
bandwidth as well as having additional conversion gain features [160] two terminal
devices (ie varactor diodes) which are passive multiplier are still preferred This is due
to their simplicity and most importantly their ability to generate very little noise Among
these types of device technologies the SBD is preferable as it is mature and has been
shown to be very suitable for high-frequency applications [172 173]
The ASPAT diode is exploited to investigate the possibility and the feasibility of
generating microwave and millimetre-wave power through well-known frequency
multiplication methods The utilisation of the ASPAT in frequency multiplication will
also aid in generating local oscillator sources which are critical components in
heterodyne receivers The ASPAT diode will work in resistive I-V mode (varistor mode)
and has features to work also at zero bias condition thus offering low power handling
than traditional high-efficiency varactor diode since the varactor diode requires a large
reverse bias supply of several tens of volts
73 Frequency Multiplier Architecture the Basics
In principle a frequency multiplier is an electronic circuit that gives an output
frequency that is a multiple integer of its input frequency signal pumped from a local
oscillator as depicted in Figure 72 The ability to generate any desired multiple output
signals is realised by a nonlinear device ie diode or transistor Such devices though
also can give distortion or cause sudden change to the input frequency Additionally
these devices generate multiples of the input frequency (fout) The distortion of the
sinusoidal signal refers to an abruptsudden change versus amplitude or time which thus
generates higher frequency with lower amplitudes of the input signal Usually a
frequency multiplier circuit will include a bandpass filter to select the desired harmonic
204
frequencies and deselect undesired harmonic frequencies especially fundamental
harmonic at the output for further processing
Any non-linear device either in symmetricalantisymmetric current-voltage or
capacitance-voltage can be utilised to realise a frequency multiplier source [168 174]
Figure 73 describes the method where a nonlinear resistance is utilised to convert a
harmonic input signal into periodic output signal containing components at multiples of
the input frequency Both non-linear resistance and reactance characteristics can be
extended into power series methods
Figure 73 Principle of operation for frequency multiplier utilising a non-linear resistance [10]
The operating principle of the frequency multiplier is shown in Figure 73 where
the I-V curve converts a harmonic frequency input into a periodic frequency output
including components at multiples of the input frequency The non-linear I-V
characteristic can be explained in term of a power series at the operating fixed point of
bias voltage (VB) [174]
Frequency
Multiplier Circuit
finput
foutput
= nfinput
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
205
119868(119881119861 + ∆119881) = 1198860 + 1198861∆119881 + 1198862∆1198812 + 1198863∆1198813 helliphellip (71)
For a given input voltage as below
∆119881 = 119881119904 cos120596119878119905 (72)
The input signal harmonics will become
119868(119905) = 1198680 + 1198681 cos120596119904119905 + 1198682 cos 2120596119904119905 + 1198683 cos 3120596119904119905 (73)
Where t and ω are the time and angular frequency respectively based on equation (73)
the output contains both signal source and harmonics Therefore a complete frequency
multiplier circuit has to have non-linear device and filter to allow the selection of any
frequency components needed
731 Types of frequency multipliers
Frequency multipliers can be classified into passive and active multipliers This
classification is based on the ability of the frequency multiplier to yield any conversion
gainlosses The passive multiplier is the one that only produces conversion losses In
other words it can be described as a multiplier that generates an output power level
lower than the excitation input power and it is mostly dominated by passive nonlinear
devices ie Diodes On the other hand the active multipliers refer to a device that would
produce an output signal with a power level that is greater than the input signal power
This conversion of power is termed as conversion gain These types of multipliers attract
much attention as they do not only increase the frequency at the output but also the
signal power
Passive frequency multiplier can be formed by using diodes that are classified as
being of the varistor (non-linear I-V) or varactor (non-linear C-V) type [160 174] The
varistor type will influence the frequency multiplication with a non-linear resistance or
conductance (resistive diodes) and this results in a very large potential bandwidth at the
output but poor conversion efficiency The varactor diode type where the frequency
multiplications are affected by the non-linear capacitance (reactive diode) as their
reactive element typical result is high conversion efficiency A diode that is used in this
206
application must have strong nonlinearity stable electrical characteristic repeatable and
has fast enough response to an applied frequency Therefore multipliers are classified
into Doubler Tripler quintuple and so forth depending on the highest power of output
harmonic signal
In general all varactor type diodes with such characteristics will produce high
power at odd-order harmonic oscillation if any microwave signal is pumped into them
The benefit of having odd-order in multiplier design is that it reduces the complexity of
the overall circuit ie it eliminates even-order idler frequencies [175] The varactor type
diode had been shown by Manley-Rowe to a get maximum 100 conversion efficiency
for generating an ideal harmonic [176] compared to the varistor type where the
maximum efficiency achievable ideally is 1 1198992frasl where n is the multiplication factor
(output harmonics number) [174] In the case of power handling (input excitation power)
for multipliers varactor mode diode required greater power (several milli Watt) than the
varistor mode due to the fact that reverse applied voltages are very large (many tens of
volts) Therefore these types of frequency multipliers may not be suitable for the case of
high input power excitation There no report in the literature of varistor based
multipliers working with high power excitations
74 Parameters of interest for Frequency Multipliers
The simplest way to describe an equivalent circuit for a complete frequency
multiplier is by setting a Source impedance (ZS) at the input side and load impedance
(ZL) at the output side as depicted in Figure 74 below This circuit usually has the same
properties as described in the previous chapter and most of the others two ports
networks However in this case the purpose is different and is the conversion of a sine
wave signal source (Vs) with angular frequency ωs to an output signal with frequency
nωs where n is the multiplication integer or the order of multiplication
207
Figure 74 A standard system for two port frequency multiplier circuit
Referring to Figure 74 above there are few sets of parameters for the frequency
multiplier to be taken out and compared Examples are the conversion loss maximum
input signal power Impedance at source and load Bandwidth multiplication factor or
harmonic amp subharmonic content and noise conversion properties The conversion loss
(CL) is described by the ratio of available power at source (Ps) to the output harmonic
power delivered to load resistance (PL) and is normally expressed in dB It occurs due to
the nature of passive semiconductor diodes and the electronic circuit itself that are lossy
and dissipate energy On the other hand the conversion efficiency (ηn) is a ratio of the
output power at load (PL) to the available power at the input (Ps) This is often expressed
in percentage () The conversion efficiency can be determined as
120578 =
119875119878
119875119871
(74)
while the conversion loss is expressed as[174]
119871119899[119889119861] = 10 log
119875119904
119875119871= 10 log (
|1198811199042|
4 119877119890 |119885119904||1198681198712|119877119890|119885119871|
) (75)
Where Vs is the input voltage and IL is the output current amplitude Besides this the
conversion efficiency is often referred to as the inverted value of the Ln In designing a
frequency multiplier it is crucial to minimise the conversion loss and maximise the
conversion efficiency value
To achieve a perfect multiplier with minimum conversion loss the impedance of
source and load must be at an optimum level This implies that the source impedance
Frequency
Multiplier Z
L
Zout
Z
in
V
Z
SWR Г
208
(Zs) must be very close to the complex conjugate of the multiplier input impedance
(Zin) hence minimum reflection loss will occur at the input side This can be realised by
introducing an impedance matching circuit between the diode and source The power
transfer between the source and the multiplier is quantitatively described by the value of
the multiplier input reflection coefficient (Ѓ) with source Zs assumed to represent a
reference impedance This specification also can be explained in the standing wave ratio
(SWR) Both relationships are described below respectively [174]
Γ =
119885119894119899 minus 119885119904lowast
119885119894119899 + 119885119904
(76)
119878119882119877 =
1 + |Γ|
1 minus |Γ|
(77)
Where the asterisk () represents the complex conjugate of the Zs impedance
On the other hand the situation of the load impedance is different when a standard
or an optimum value is provided by the designer This will either increase the conversion
loss or decrease the output power Thus one has to keep in mind that frequency
multipliers are non-linear devices and power transfer condition both at the input and the
output depend on each other and the input signal level[174]
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler
In this work a similar ASPAT diode (4times4microm2) to that in designing millimetre
wave detector in the previous chapter is used The main objective of designing the
frequency multiplier circuit was first to investigate the performance of the ASPAT
diode as a microwave or millimetre wave signal source A design is deemed successful
when the diode physical parameters are optimised and the suitable impedance matching
network is produced for each desired harmonic as well as maximising the output power
These goals however are hard to achieve when a higher frequency operation is targeted
for use
There are many types of multiplier circuit topologies that can be implemented
using GaAsAlAs ASPAT diode in varistor mode to achieve high order of multiplication
209
Examples are single diode multiplier series or parallel connected diode multiplier anti-
parallel amp anti-series connection diode pair multiplier anti-parallel-series connected
diode multiplier and bridge frequency multiplier as well as nonlinear transmission line
frequency multiplier [174] Before designing a circuit there is one most important
consideration to make Prior to choosing any mentioned circuits to be used for frequency
doubler the design considerations are made based on the capability of ASPAT diode to
receive an optimum amount of input excitation RF power From the discussions in
Chapter 6 the ASPAT diode will reach saturation level (linear regime) at power ~
-10dBm for a device size of 4x4microm2 Once the optimum input power was confirmed the
circuit topology was carefully chosen to balance between the requirements of the
ASPAT to work at high frequencies ie low Rs and Cj amp high diode cut-off frequency
as well as the desired output signal frequency that needs to be produced
To realise the first attempt of an ASPAT diode as a signal source a simple circuit
topology of a frequency doubler was deployed as depicted in Figure 75 below The
frequency doubler circuit consists of a voltage source (can be power source) input
filtering with matching network ASPAT diode output filtering with matching network
and load impedance (ZL)
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode
In order to investigate the doubler performance the Keysight ADS simulation
tool and similar procedure to obtain accurate ASPAT model using a 10th
order
polynomial equation as in Section 65 was used The circuit in Figure 75 is translated
into ADS format as illustrated in Figure 76 Once the circuit was constructed the
analysis was performed using the Harmonics Balance (HB) simulator The circuit
requirements are matched terminations at the input and output frequencies open
Input Filtering
and matching network
Output Filtering
and matching network
Zs
Vs
ZL
Pin
fin
Pout
nfout
210
circuited terminations at the higher harmonics and optimum reactive terminations (an
inductance which resonates with the junction capacitance) at the output frequencies
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool
The circuit in Figure 76 is the simplest way of constructing a frequency doubler
circuit which consists of the signal source (P_1Tone) input matching circuit (Stubs)
filter (Short stub) ASPAT diode low pass filter output matching circuit(Stubs) and ZL
(load resistance) The utilisation of the stubs is an ideal case of simulation since in the
real fabrication stubs are normally formed in large sizes Therefore a proper design such
as using CPW instead of stubs is essential in real fabrication
Again this simulation works for this particular circuit in this chapter as all the diode
parameters were extracted from on-wafer one port S-Parameter measurement described
in chapter 5 To apply them in such two ports applications may not very accurate
however it still provides adequate parameters to build and design particular frequency
multipliers but not in general applications These simulations and results are adequate for
high frequency applications due to the fact that the actual RF measurements on the
diodes were carried out up to 40GHz and the target operating frequency in this multiplier
design does not exceed 40GHz
Since the on-wafer measurement that were carried out were limited to one port
characterization applying them to two port network applications may have extra
consequences which are unknown Therefore actual MMIC frequency multiplier is
needed to be built and test to validate this work
Input Matching
Output Matching
211
To find the optimum output power initial simulation without matching circuit
was performed This simulation was run by varying the input power from -35dBm to
20dBm but fixing the input frequency at 20GHz As can be seen in Figure 77 the lowest
point in the conversion loss (CL) and the highest point of the conversion efficiency (CE)
are obtained from an input power of -1dBm However this amount of input power is too
high for the ASPAT diode The lowest CL at -1dBm may not be accurate since it was
applied without matching Note that it is difficult to achieve a matching between source
impedance and load impedance when varying the input power Therefore a lower input
power of -10dBm is chosen for this frequency doubler operation Figure 77 shows the
Conversion Loss and Conversion Efficiency as a function of the available power of the
given input source
Figure 77 Conversion loss and conversion efficiency as a function of input power
The circuit in Figure 76 works with a -10dBm input power and 20GHz centre
frequency input signal is pumped from the power source (P1_tone) to the ASPAT diode
and distortionabrupt change of input waveform occurs at the fundamental frequency (f0
in this case 20GHz) Such abrupt change produces harmonics and these harmonics can
be classified into desired frequency component by placing two-quarter wavelength (λ4)
stubs (90˚) at both sides of the ASPAT diode At the input side of the diode short circuit
stubs are utilised to permit the f0 tone to reach the ASPAT diode and block the second
harmonics (2f0 in this case 40GHz) back to the input side and pushes it towards the
load resistance On the contrary at the output side of the diode the open circuit stubs are
used to ldquoopen circuitrdquo the 2f0 signals while ldquoshort circuitrdquo the f0 component Thus 2f0
212
signal will not be affected due to the open circuit stubs being half wave (λ2) long The
function of both stubs is basically to isolate the input and output signal from mixing each
other Therefore the design of input and output matching circuit can be achieved easily
The input matching circuit was designed based on the mentioned input frequency
(f0=20GHz) for an available input power (Ps=-10dBm) which is set up at the power
source by using two stubs with the same configuration as used in Chapter 6 Such
configuration is purposely deployed to increase the 50Ω coming from the P1_tone
source impedance to the conjugate thus reducing the reflection coefficient to the
ASPAT diode From the simulation without matching the input impedance to the diode
is 551Ω in magnitude for an available input power of -10dBm
On the output side of the diode output matching circuit is available to transform the 50Ω
port impedance in the optimum load impedance which provides minimum conversion
loss for the ASPAT diode The output matching circuit is designed based on expected
output frequency which is in this case 2f0 =40GHz Other than this optimum
impedance between load impedance and ASPAT will not be achieved thus resulting in
higher conversion loss
To ensure the proposed circuit is valid and suitable for the specific ASPAT diode
mesa size the response of conversion loss and efficiency are plotted as a function of
output frequency from 20GHz to 100GHz The results of both conversions are illustrated
in Figure 78
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
213
As can be seen in Figure 78 the conversion loss is obtained at the lowest point where
the output frequency is needed Meanwhile the conversion efficiency is maximum at the
same output frequency Therefore this indicates that the first attempt of an ASPAT
Doubler frequency source works well However the values obtained for Ln from this
simulation is 28dB which is rather high On the contrary the η achieved in this study is
very low with a value less than 1
Since the ASPAT is in varistor mode with no bias applied the conversion
efficiency is expected to be low due to resistive losses Another factor that may
contribute to lower η is the diode model itself as it is taken from a 10th
order polynomial
equation not from a diode model provided in the ADS software tools Thus some
properties of such tunnelling diode may not be included Hence it is necessary in due
course to fabricate and build such a compact frequency doubler in the future to verify
the simulation results
From the simulation point of view the less than 1 Conversion Efficiency
obtained is still good enough for a first attempt at a frequency doubler which utilises the
new ASPAT tunnelling diode The frequency doubler obtained from this work is suitable
for use in zero bias varistor modes for low power application The varistor mode doubler
performances from this simulation work are gathered and compared to other in the
literature as summarized in Table 71 below where fout is 40GHz η is 015 Ln is 28dB
and Pi is -10dBm
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art multiplier
diode
Device fout (GHz) η() Ln(dB) Pi (dBm)
ASPAT 40 015 28 -10
SBD (Si)[177] 104 2 134 -10
SBD (GaAs)[178] 13 2 137 -16
214
The performance of the 2040GHz is compared to the literature based on their input
power below -8dBm since the ASPAT is only capable of working at low power To the
best of the author knowledge very few diodes operating in varistor mode at low power
excitation can be found in the field of research and industry Therefore this 2040GHz
ASPAT Doubler might a first for tunnel diodes if it can be fabricated and test at Ka band
and above
76 Conclusions
In this chapter another alternative application based on non-linear features of
GaAsAlAs ASPAT has been presented The simulation of a frequency multiplier
(doubler) was carried out utilizing the 4times4microm2 size ASPAT diode The theory and the
ability of the ASPAT diode to operate as a frequency source were explained in detail
A unique varistor mode frequency multiplier circuit topology for the 2040GHz
ASPAT doubler has been demonstrated and briefly discussed The details and step by
step simulation technique utilizing harmonic balance from Keysight ADS has been
presented Even though the conversion efficiency is very small at 015 and large
conversion loss of 28dB there is still space for improvement in term of design ie
different circuit topology optimized input and output matching circuit etc This design
can be a good reference for a doubler operating at very low power but produce high
frequencies in Ka band
215
8 CONCLUSION AND FUTURE WORK
81 Conclusion
The main focus of this research was the development of a new tunneling diode
namely the asymmetrical spacer layer tunnel (ASPAT) diode for process repeatability
manufacturability and reproducibility The broad study undertaken was to improve the
microwave performance technology by introducing a new type of tunneling diode
For years the asymmetrical spacer layer tunnel diode was unable to be manufactured
due to the high sensitivity of the tunneling current to the barrier thickness This changed
dramatically when the MBE method was carefully optimized to precisely control the
growth to sub-monolayer precisions When stability repeatability and reproducibility in
the epitaxial growth was achieved the next step was to qualify the fabrication process of
the diodes themselves thus ensuring high performance device can be delivered to the
market
For this purpose GaAsAlAs ASPAT diodes made of two different types of
substrates were grown The first batch was grown in the Riber V100HU SSMBE and
used doped substrates Samples XMBE307 and XMBE368 were successfully grown
and fabricated from that batch The DC characterization obtained from measurement
proved that this first batch had fully functional reproducible and manufacturable
devices Later a second batch using semi insulating substrates improvement in spacer
layer and doping concentration were grown This set of samples (9 x 2rdquo wafers grown
simultaneously) and denoted as XMBE304 also showed fully functional DC
characteristic and was used for RF characterization and detector integrated circuits
The conventional GaAsAlAs ASPAT diode structures grown on doped
substrates and developed previously in our lab were not suitable for high frequency RF
characterizations Therefore a major contribution of this work was to develop a new
fabrication technique for a new GaAsAlAs ASPAT structure using semi insulating
substrates to achieve repeatability manufacturability and reproducibility in term of
process flow DC characteristics and ultimately RF characteristics Apart from the
enhancement of the epitaxial layer the other important contribution of this research was
216
the optimization of the small 4times4microm2 emitter size by incorporating both vertical and
lateral structure based purely on low cost I-line optical lithography
To obtain a repeatable and manufacturable fabrication process of lateral
GaAsAlAs ASPAT structures the key issue was to solve the over etching of the
effective mesa area when qualifying the Air Bridge technique This issue caused all
semiconductors under the metal contact to be completely lost thus leaving the metal
contact hanging without connection to any bond pad area However the developments of
the Dielectric Bridge technique realized the true performance of the GaAsAlAs ASPAT
diode structures The samplersquos surface cleanliness as well as DC and RF performance
showed significant improvement when using Si3N4 as a dielectric layer Due to the
highly isotropic etching profile and thicker GaAs layer in XMBE304 samples and
although the smallest emitter size designed on the mask was 2times2microm2 only 4times4microm
2 were
reproducible and showed good uniformity in I-V characteristics
Upon successful optimization in the fabrication process flow of the small emitter
size diodes (4times4microm2 6times6microm
2 and 10times10microm
2) a good uniformity of better than 91
was obtained for DC measurement results within a tile containing over 1000 devices
This confirmed that the lateral GaAsAlAs ASPAT diode structure can only be realized
through the Dielectric Bridge technique These devices were further characterized with
S-parameter measurements and their intrinsic and extrinsic parameter values and
junction capacitances series resistances and junction resistances were extracted leading
to intrinsic cut-off frequencies of 600GHz 429GHz and 100GHz for the three device
sizes respectively
Temperature dependence measurements and simulations were also carried out in
order to confirm that the ASPAT diodersquos characteristics were temperature insensitive
showing less than 5 change in current at both extremes of temperatures 77K to 400K
By comparison the SBD I-V characteristics variations with temperature span orders of
magnitude Physical modelling agreed very well with measured data confirming good
and validated models that can also describe temperature effects
For the realization of the integrated ASPAT millimeter wave detector empirical
modelling using ADS simulation tools was carried out This was performed to predict
the detector performance at 100GHz to comply with the initial objective to develop a
217
millimeter wave detector circuit The simulations using the 4times4microm2 diode models led to
a successful 100GHz circuit design able to detect 100GHz incoming frequency with
2100VW voltage sensitivity
The first ever GaAsAlAs ASPAT diode frequency multiplier design was also
attempted A reasonably good result was obtained for a 20 to 40GHz frequency doubler
operating in varistor mode However the conversion efficiency obtained was less than
1 Further research on this is required to improve the efficiency by using other circuit
topology ie using a balun or other Co-planar waveguides Ultimately fabricating and
testing the actual multiplier circuits are essential to validate the simulation data
82 Future Work
This work has provided a foundation for a reproducible and repeatable GaAsAlAs
ASPAT (SI substrate) wafer fabrication process and recommendations for design and
simulation of ASPAT diode MMIC detectors and frequency source has also been
provided However the GaAsAlAs ASPAT diodes still remain immature and there are
many ways to improve its DC and RF performances both experimentally and in
simulations which will directly affect the detection performances
In term of fabrication process smaller size diodes ie submicron level can be
achieved using dry etching technique with proper calibration For wet etch technique the
etched profile still can be improved by thinning the doped layers so that etching time
will be reduced and hence dimensions down to 2times2microm2 or even 15times15microm
2 can be
reproducibly made
For simulations advanced AC and RF modelling utilizing physical device
simulation available software (SILVACO) must be include in future research hence
holistic study can be conducted to improve the understanding of the ASPAT
For MMIC detector and multiplier design it is vital to produce actual MMIC
devices so that the simulation results can be validated Ultimately tested devices with
good performances can be realized and manufactured
218
REFERENCES
1 Laeri F U Simon and M Wark Host-Guest-Systems Based on Nanoporous
Crystals 2006 John Wiley amp Sons
2 Łukasiak L and A Jakubowski History of semiconductors Journal of
Telecommunications and information technology 2010 p 3-9
3 Song H-J and T Nagatsuma Present and future of terahertz communications
IEEE Transactions on Terahertz Science and Technology 2011 1(1) p 256-
263
4 Hu B and M Nuss Imaging with terahertz waves Optics letters 1995 20(16)
p 1716-1718
5 Smith PR DH Auston and MC Nuss Subpicosecond photoconducting
dipole antennas IEEE Journal of Quantum Electronics 1988 24(2) p 255-260
6 Nagatsuma T Terahertz technologies present and future IEICE Electronics
Express 2011 8(14) p 1127-1142
7 Kumar S et al A 18-THz quantum cascade laser operating significantly above
the temperature of [planck][omega]kB Nature Physics 2011 7(2) p 166-171
8 Phillips T and D Woody Millimeter-and submillimeter-wave receivers Annual
Review of Astronomy and Astrophysics 1982 20(1) p 285-321
9 Whitmer HCTaCA Crystal Rectifiers McGraw-Hill book Company
London 1948
10 Young D and J Irvin Millimeter frequency conversion using Au-n-type GaAs
Schottky barrier epitaxial diodes with a novel contacting technique Proceedings
of the Ieee 1965 53(12) p 2130-2131
11 Liu L et al A broadband quasi-optical terahertz detector utilizing a zero bias
Schottky diode IEEE microwave and wireless components letters 2010 20(9) p
504-506
12 Sankaran S Schottky barrier diodes for millimeter wave detection in a foundry
CMOS process IEEE Electron Device Letters 2005 26(7) p 492-494
13 Chattopadhyay G Submillimeter-wave coherent and incoherent sensors for
space applications in Sensors 2008 Springer p 387-414
14 Anand Y and WJ Moroney Microwave mixer and detector diodes
Proceedings of the Ieee 1971 59(8) p 1182-1190
15 Syme RT Microwave Detection Using GaasAlas Tunnel Structures Gec
Journal of Research 1993 11(1) p 12-23
16 Syme RT et al Asymmetric superlattices for microwave detection in Physical
Concepts of Materials for Novel Optoelectronic Device Applications 1991
International Society for Optics and Photonics
17 Missous M MJ Kelly and J Sexton Extremely uniform tunnel barriers for
low-cost device manufacture IEEE Electron Device Letters 2015 36(6) p 543-
545
18 Syme RT et al Novel GaAsAlAs tunnel structures as microwave detectors in
Semiconductors 92 1992 International Society for Optics and Photonics
19 Schwierz F and JJ Liou Semiconductor devices for RF applications evolution
and current status Microelectronics Reliability 2001 41(2) p 145-168
219
20 HayasHi H Development of Compound Semiconductor DevicesmdashIn Search of
Immense Possibilitiesmdash SEI TECHNICAL REVIEW 2011(72) p 5
21 Mead C Schottky barrier gate field effect transistor Proceedings of the Ieee
1966 54(2) p 307-308
22 Hooper W and W Lehrer An epitaxial GaAs field-effect transistor Proceedings
of the Ieee 1967 55(7) p 1237-1238
23 Drangeid K R Sommerhalder and W Walter High-speed gallium-arsenide
Schottky-barrier field-effect transistors Electronics Letters 1970 6(8) p 228-
229
24 Pillarisetty R Academic and industry research progress in germanium
nanodevices Nature 2011 479(7373) p 324-328
25 Oxley TH 50 years development of the microwave mixer for heterodyne
reception IEEE transactions on microwave theory and techniques 2002 50(3)
p 867-876
26 Baca AG and CI Ashby Fabrication of GaAs devices 2005 IET
27 Cho AY and J Arthur Molecular beam epitaxy Progress in solid state
chemistry 1975 10 p 157-191
28 Cho A Growth of IIIndashV semiconductors by molecular beam epitaxy and their
properties Thin Solid Films 1983 100(4) p 291-317
29 Kiehl RA and TG Sollner High speed heterostructure devices 1994
Academic Press
30 Feiginov M et al Resonant-tunnelling-diode oscillators operating at
frequencies above 11 THz Applied Physics Letters 2011 99(23) p 233506
31 Chang LL L Esaki and R Tsu Resonant tunneling in semiconductor double
barriers Applied Physics Letters 1974 24(12) p 593-595
32 Kasjoo SR Novel Electronic Nanodevices Operating in the Terahertz Region
2012
33 Kanaya H et al Structure dependence of oscillation characteristics of
resonant-tunneling-diode terahertz oscillators associated with intrinsic and
extrinsic delay times Japanese Journal of Applied Physics 2015 54(9) p
094103
34 Chattopadhyay G Technology capabilities and performance of low power
terahertz sources IEEE Transactions on Terahertz Science and Technology
2011 1(1) p 33-53
35 Betz A and R Boreiko A practical Schottky mixer for 5 THz in Proceedings of
the 7th International Symposium on Space Terahertz Technology 1996
36 Yu D et al Ultra high-speed 025-spl mum emitter InP-InGaAs SHBTs with
fsub maxof 687 GHz in Electron Devices Meeting 2004 IEDM Technical
Digest IEEE International 2004 IEEE
37 Das MB Optoelectronic detectors and receivers speed and sensitivity limits in
Optoelectronic and Microelectronic Materials Devices 1998 Proceedings 1998
Conference on 1999 IEEE
38 Rodwell MJ et al Submicron scaling of HBTs IEEE Transactions on Electron
Devices 2001 48(11) p 2606-2624
220
39 Bouloukou A and S Missous Novel High-breakdown Low-noise InGaAs-
InA1As Transistors for Radio Astronomy Applications 2006 University of
Manchester
40 Bean J Materials and technologies 1990 John Wiley amp Sons New York p
13
41 Swaminathan V and A Macrander Materials aspects of GaAs and InP based
structures 1991 Prentice-Hall Inc
42 Vurgaftman I J Meyer and L Ram-Mohan Band parameters for IIIndashV
compound semiconductors and their alloys Journal of applied physics 2001
89(11) p 5815-5875
43 Dingle R W Wiegmann and CH Henry Quantum states of confined carriers
in very thin Al x Ga 1minus x As-GaAs-Al x Ga 1minus x As heterostructures Physical
Review Letters 1974 33(14) p 827
44 Sze SM and KK Ng Physics of semiconductor devices 2006 John wiley amp
sons
45 Tyagi MS Introduction to semiconductor materials and devices 2008 John
Wiley amp Sons
46 Schubert E Delta doping of IIIndashV compound semiconductors Fundamentals
and device applications Journal of Vacuum Science amp Technology A Vacuum
Surfaces and Films 1990 8(3) p 2980-2996
47 Rhoderick EH Metal-semiconductor contacts IEE Proceedings I-Solid-State
and Electron Devices 1982 129(1) p 1
48 Piotrowska A A Guivarch and G Pelous Ohmic contacts to IIIndashV compound
semiconductors A review of fabrication techniques Solid-State Electronics
1983 26(3) p 179-197
49 Rideout V A review of the theory and technology for ohmic contacts to group
IIIndashV compound semiconductors Solid-State Electronics 1975 18(6) p 541-
550
50 Baca A et al A survey of ohmic contacts to III-V compound semiconductors
Thin Solid Films 1997 308 p 599-606
51 Higman T et al Structural analysis of AundashNindashGe and AundashAgndashGe alloyed
ohmic contacts on modulation‐doped AlGaAsndashGaAs heterostructures Journal of
applied physics 1986 60(2) p 677-680
52 Chen KJ et al High-performance enhancement-mode InAlAsInGaAs HEMTs
using non-alloyed ohmic contact and Pt-based buried-gate in Indium Phosphide
and Related Materials 1995 Conference Proceedings Seventh International
Conference on 1995 IEEE
53 Berlin L The man behind the microchip Robert Noyce and the invention of
Silicon Valley 2005 Oxford University Press
54 Goodhue W et al Large room‐temperature effects from resonant tunneling
through AlAs barriers Applied Physics Letters 1986 49(17) p 1086-1088
55 Kerr A and Y Anand Schottky diode MM detectors with improved sensitivity
and dynamic range Microwave Journal 1981 24 p 67-71
56 Davies R Simulations of the current-voltage characteristics of semiconductor
tunnel structures Gec Journal of Research 1987 5(2) p 65-75
221
57 Kelly M Tunnel structures and devices over the coming decade Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2291-2293
58 Wilkinson V and M Kelly Manufacturability of quantum semiconductor
devices in High Performance Electron Devices for Microwave and
Optoelectronic Applications 1995 EDMO IEEE 1995 Workshop on 1995
IEEE
59 Wilkinson V M Kelly and M Carr Tunnel devices are not yet
manufacturable Semiconductor Science and Technology 1997 12(1) p 91
60 Eaves L and MJ Kelly The current status of semiconductor tunnelling devices
Philos trans of the Roy soc of London Ser A Math phys and eng sciences
1996 354(1717)
61 Billen K V Wilkinson and M Kelly Manufacturability of heterojunction
tunnel devices further progress Semiconductor Science and Technology 1997
12(7) p 894
62 Kelly M The engineering of quantumndashdot devices Philosophical Transactions
of the Royal Society of London A Mathematical Physical and Engineering
Sciences 2003 361(1803) p 393-401
63 Kelly M New statistical analysis of tunnel diode barriers Semiconductor
Science and Technology 2000 15(1) p 79
64 Hayden R et al Ex situ re-calibration method for low-cost precision epitaxial
growth of heterostructure devices Semiconductor Science and Technology
2002 17(2) p 135
65 Dasmahapatra P et al Thickness control of molecular beam epitaxy grown
layers at the 001ndash01 monolayer level Semiconductor Science and Technology
2012 27(8) p 085007
66 Hayden R M Missous and M Kelly Precision growth for the manufacture of
semiconductor heterostructure devices Semiconductor Science and Technology
2001 16(8) p 676
67 Shao C et al Highly reproducible tunnel currents in MBE-grown
semiconductor multilayers Electronics Letters 2012 48(13) p 792-794
68 Abdullah MR et al GaAsAlAs tunnelling structure Temperature dependence
of ASPAT detectors in Millimeter Waves and THz Technology Workshop
(UCMMT) 2015 8th UK Europe China 2015 IEEE
69 Ariffin KZ et al Asymmetric Spacer Layer Tunnel In0 18Ga0 82AsAlAs
(ASPAT) Diode using double quantum wells for dual functions Detection and
oscillation in Millimeter Waves and THz Technology Workshop (UCMMT)
2015 8th UK Europe China 2015 IEEE
70 Liboff RL Introductory quantum mechanics 2003 Addison-Wesley
71 Esaki L Discovery of the tunnel diode IEEE Transactions on Electron Devices
1976 23(7) p 644-647
72 Landau LD LEM Quantum Mechanics Non-relativistic Theory Pergamon 3
73 Landau LD et al Quantum Mechanics Non‐Relativistic Theory Vol 3 of
Course of Theoretical Physics 1958 AIP
222
74 Syme R Tunnelling devices as microwave mixers and detectors Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2351-2364
75 Syme R et al Tunnel diode with asymmetric spacer layers for use as
microwave detector Electronics Letters 1991 27(23) p 2192-2194
76 Brown E W Goodhue and T Sollner Fundamental oscillations up to 200 GHz
in resonant tunneling diodes and new estimates of their maximum oscillation
frequency from stationary‐state tunneling theory Journal of applied physics
1988 64(3) p 1519-1529
77 Reddy M Schottky-collector resonant tunnel diodes for sub-millimeter-wave
applications 1997 University of California Santa Barbara
78 Cox R and H Strack Ohmic contacts for GaAs devices Solid-State Electronics
1967 10(12) p 1213IN71215-1214IN81218
79 Valdes LB Resistivity measurements on germanium for transistors
Proceedings of the IRE 1954 42(2) p 420-427
80 Schroder DK Semiconductor material and device characterization 2006 John
Wiley amp Sons
81 Klootwijk J and C Timmering Merits and Limitations of Circular TLM
structures for contact resistance determination for novel 111-V HBTs Proc
fEEE 2004
82 Marlow GS and MB Das The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance Solid-State
Electronics 1982 25(2) p 91-94
83 Murrmann H and D Widmann Current crowding on metal contacts to planar
devices IEEE Transactions on Electron Devices 1969 16(12) p 1022-1024
84 Berger H Models for contacts to planar devices Solid-State Electronics 1972
15(2) p 145-158
85 Reeves G and H Harrison Obtaining the specific contact resistance from
transmission line model measurements IEEE Electron Device Letters 1982
3(5) p 111-113
86 Shur MS GaAs devices and circuits 2013 Springer Science amp Business
Media
87 Popescu D and B Odbert The Advantages Of Remote Labs In Engineering
Education Educatorrsquos Corner-Agilent Technologies-application note 2011 p
11
88 DataSheet Karl Suss- PM5 Probe System Datasheet 2013
89 Keysight IC-CAP Device Modeling Software 2016 Available from
httpwwwkeysightcomenpc-1297149ic-cap-device-modeling-software-
measurement-control-and-parameter-extractioncc=USamplc=eng
90 DataSheet Anritsu 37369A Vector Network Analyzer Datasheet 2016 Available
from httpwwwtestequipmenthqcomdatasheetsANRITSU-37397D-
Datasheetpdf
91 Packard H HP 4142B Modular DC SourceManual Operation Manual 1992
Available from httpcpliteratureagilentcomlitwebpdf04142-90010pdf
223
92 Microtech C Cascade Microtech- Wincal High Performence RF calaibration
Software (Official Website) 2016 Available from
httpswwwcascademicrotechcom
93 Singh J Electronic and optoelectronic properties of semiconductor structures
2007 Cambridge University Press
94 Whyte W Cleanroom design 1999 Wiley Online Library
95 Vieu C et al Electron beam lithography resolution limits and applications
Applied Surface Science 2000 164(1) p 111-117
96 La Fontaine B Lasers and Moorersquos law SPIE Professional October 2010 p
20
97 Madou MJ Fundamentals of microfabrication the science of miniaturization
2002 CRC press
98 Serway R Physics for Scientists and Engineers 1996 Saunders Publ
Philadelphia
99 Jalali B and S Pearton InP HBTs growth processing and applications 1995
Artech House Publishers
100 Shih YC et al Effects of interfacial microstructure on uniformity and thermal
stability of AuNiGe ohmic contact to n‐type GaAs Journal of applied physics
1987 62(2) p 582-590
101 Zawawi M Advanced In0 8Ga0 2AsAlAs Resonant Tunneling Diodes
forApplications in Integrated mm-waves MMIC Oscillators 2015
102 Zawawi MAM et al Fabrication of Submicrometer InGaAsAlAs Resonant
Tunneling Diode Using a Trilayer Soft Reflow Technique With Excellent
Scalability IEEE Transactions on Electron Devices 2014 61(7) p 2338-2342
103 Silvaco I ATLAS Users Manual Device Simulation Software 2010 Santa
Clara CA
104 Kyono C et al Dependence of apparent barrier height on barrier thickness for
perpendicular transport in AlAsGaAs single‐barrier structures grown by
molecular beam epitaxy Applied Physics Letters 1989 54(6) p 549-551
105 Yang K JR East and GI Haddad Numerical modeling of abrupt
heterojunctions using a thermionic-field emission boundary condition Solid-
State Electronics 1993 36(3) p 321-330
106 Varshni YP Temperature dependence of the energy gap in semiconductors
Physica 1967 34(1) p 149-154
107 Handbook LLM Precision DC Current Voltage and Resistance
Measurements Keithley Instruments Inc[online] 6th revision Ohio 2004
108 Lipsky SE Microwave passive direction finding 2004 SciTech Publishing
109 Howell CM and SJ Parisi Principles Applications and Selection of Receiving
Diodes MACOM Semiconductor Products Division Application note AG314
110 Schulman J D Chow and D Jang InGaAs zero bias backward diodes for
millimeter wave direct detection IEEE Electron Device Letters 2001 22(5) p
200-202
111 Zhang Z et al Sub-Micron Area Heterojunction Backward Diode Millimeter-
Wave Detectors With 018$ rm pWHz^12 $ Noise Equivalent Power IEEE
microwave and wireless components letters 2011 21(5) p 267-269
224
112 Jin N et al High sensitivity Si-based backward diodes for zero-biased square-
law detection and the effect of post-growth annealing on performance IEEE
Electron Device Letters 2005 26(8) p 575-578
113 Shashkin VI et al Millimeter-wave detectors based on antenna-coupled low-
barrier Schottky diodes International journal of infrared and millimeter waves
2007 28(11) p 945-952
114 Zhao P et al GaN Heterostructure Barrier Diodes Exploiting Polarization-
Induced $delta $-Doping IEEE Electron Device Letters 2014 35(6) p 615-
617
115 Pozar DM Microwave engineering 2009 John Wiley amp Sons
116 Koolen M J Geelen and M Versleijen An improved de-embedding technique
for on-wafer high-frequency characterization in Bipolar Circuits and
Technology Meeting 1991 Proceedings of the 1991 1991 IEEE
117 Cao M et al RF characteristics uniformity of GaAsAlAs tunnel diodes in
Infrared Millimeter and Terahertz waves (IRMMW-THz) 2016 41st
International Conference on 2016 IEEE
118 Gao J RF and microwave modeling and measurement techniques for field effect
transistors 2010 SciTec
119 Ren T et al A 340-400 GHz Zero-Biased Waveguide Detector Using an Self-
Consistent Method to Extract the Parameters of Schottky Barrier Diode Applied
Computational Electromagnetics Society Journal 2015 30(12)
120 Fobelets K et al High‐frequency capacitances in resonant interband tunneling
diodes Applied Physics Letters 1994 64(19) p 2523-2525
121 Diebold S et al Modeling and Simulation of Terahertz Resonant Tunneling
Diode-Based Circuits IEEE Transactions on Terahertz Science and Technology
2016 6(5) p 716-723
122 Yong Z et al Design of a 220 GHz frequency tripler based on EM model of
Schottky diodes JOURNAL OF INFRARED AND MILLIMETER WAVES
2014 33(4) p 405-411
123 Louhi JT and AV Raisanen On the modeling and optimization of Schottky
varactor frequency multipliers at submillimeter wavelengths IEEE transactions
on microwave theory and techniques 1995 43(4) p 922-926
124 Guo J Z Zhang and C Qian Modeling of commercial millimeter wave
Schottky diodes in Microwave and Millimeter Wave Technology (ICMMT) 2016
IEEE International Conference on 2016 IEEE
125 Schneider M Metal-semiconductor junctions as frequency converters Infrared
and Millimeter Waves 1982 6 p 209
126 Muth C et al Advanced technology microwave sounder on NPOESS and NPP
in Geoscience and Remote Sensing Symposium 2004 IGARSS04 Proceedings
2004 IEEE International 2004 IEEE
127 Putley E Thermal detectors in Optical and Infrared Detectors 1977 Springer
p 71-100
128 Martin DH Spectroscopic techniques for far infra-red submillimetre and
millimetre waves in Spectroscopic Techniques for Far Infra-red Submillimetre
and Millimetre Waves 1967
225
129 Lucas W Tangential sensitivity of a detector video system with RF
preamplification in Proceedings of the Institution of Electrical Engineers 1966
IET
130 Balocco C et al Low-frequency noise of unipolar nanorectifiers Applied
Physics Letters 2011 99(11) p 113511
131 Benford D T Hunter and TG Phillips Noise equivalent power of background
limited thermal detectors at submillimeter wavelengths International journal of
infrared and millimeter waves 1998 19(7) p 931-938
132 Papoušek D Vibration-rotational Spectroscopy and Molecular Dynamics
Advances in Quantum Chemical and Spectroscopical Studies of Molecular
Structures and Dynamics Vol 9 1997 World Scientific
133 Nyquist H Thermal agitation of electric charge in conductors Physical review
1928 32(1) p 110
134 Turner CS Johnson-Nyquist Noise url httpwww claysturner
comdspJohnson-NyquistNoise pdf(Letzter Abruf Juli 2012)
135 Voss RF 1f (flicker) noise A brief review in 33rd Annual Symposium on
Frequency Control 1979 1979 IEEE
136 McWhorter AL 1f noise and related surface effects in germanium 1955
137 Hooge FN 1ƒ noise is no surface effect Physics letters A 1969 29(3) p 139-
140
138 Van der Ziel A Noise Sources characterization measurement Prentice-Hall
Information and System Sciences Series Englewood Cliffs Prentice-Hall 1970
1970
139 Hooge F 1f noise sources IEEE Transactions on Electron Devices 1994
41(11) p 1926-1935
140 Der Ziel A Theory of shot noise in junction diodes and junction transistors
Proceedings of the IRE 1955 43(11) p 1639-1646
141 Schottky W Small-shot effect and flicker effect Physical review 1926 28(1)
p 74
142 Cowley A and H Sorensen Quantitative comparison of solid-state microwave
detectors IEEE transactions on microwave theory and techniques 1966 14(12)
p 588-602
143 Schulman J et al 1$f $ Noise of Sb-Heterostructure Diodes for Pre-Amplified
Detection IEEE microwave and wireless components letters 2007 17(5) p
355-357
144 Lynch JJ et al Passive millimeter-wave imaging module with preamplified
zero-bias detection IEEE transactions on microwave theory and techniques
2008 56(7) p 1592-1600
145 Su N et al Sb-heterostructure millimeter-wave detectors with reduced
capacitance and noise equivalent power IEEE Electron Device Letters 2008
29(6) p 536-539
146 Westlund A Self-Switching Diodes for Zero-Bias Terahertz Detection 2015
Chalmers University of Technology
147 Yajima T and L Esaki Excess noise in narrow germanium pn junctions
Journal of the physical society of Japan 1958 13(11) p 1281-1287
226
148 Sommers H Tunnel diodes as high-frequency devices Proceedings of the IRE
1959 47(7) p 1201-1206
149 Miraftab V and A Abdipour Harmonic balance analysis of a microwave
balanced power amplifier in Electrical and Computer Engineering 2001
Canadian Conference on 2001 IEEE
150 Patrashin M et al GaAsSbInAlAsInGaAs Tunnel Diodes for Millimeter Wave
Detection in 220ndash330-GHz Band IEEE Transactions on Electron Devices 2015
62(3) p 1068-1071
151 Hesler JL and TW Crowe Responsivity and noise measurements of zero-bias
Schottky diode detectors Proc ISSTT 2007 p 89-92
152 Su N et al Temperature dependence of high frequency and noise performance
of Sb-heterostructure millimeter-wave detectors IEEE Electron Device Letters
2007 28(5) p 336-339
153 Lynch J et al Unamplified direct detection sensor for passive millimeter wave
imaging in Proc of SPIE Vol 2006
154 ZHANG Z et al A physics-based tunneling model for Sb-heterostructure
backward tunnel diode millimeter-wave detectors International Journal of High
Speed Electronics and Systems 2011 20(03) p 589-596
155 Bahl IJ and P Bhartia Microwave solid state circuit design 2003 John Wiley
amp Sons
156 Yeom K-W Microwave Circuit Design A Practical Approach Using ADS
2015 Prentice Hall Press
157 Xie L et al A W-band detector with high tangential signal sensitivity and
voltage sensitivity in Microwave and Millimeter Wave Technology (ICMMT)
2010 International Conference on 2010 IEEE
158 Fay P et al High-performance antimonide-based heterostructure backward
diodes for millimeter-wave detection IEEE Electron Device Letters 2002
23(10) p 585-587
159 Hrobak M et al Planar zero bias Schottky diode detector operating in the E-
and W-band in Microwave Conference (EuMC) 2013 European 2013 IEEE
160 Maas SA Nonlinear microwave and RF circuits 2003 Artech House
161 Appleby R and RN Anderton Millimeter-wave and submillimeter-wave
imaging for security and surveillance Proceedings of the Ieee 2007 95(8) p
1683-1690
162 Crowe TW et al Opening the terahertz window with integrated diode circuits
IEEE Journal of Solid-State Circuits 2005 40(10) p 2104-2110
163 Raisanen AV Frequency multipliers for millimeter and submillimeter
wavelengths Proceedings of the Ieee 1992 80(11) p 1842-1852
164 Erickson NR Diode frequency multipliers for terahertz local-oscillator
applications in Astronomical Telescopes amp Instrumentation 1998 International
Society for Optics and Photonics
165 Mehdi I et al Terahertz local oscillator sources performance and capabilities
in Astronomical Telescopes and Instrumentation 2003 International Society for
Optics and Photonics
166 Tonouchi M Cutting-edge terahertz technology Nature photonics 2007 1(2)
p 97-105
227
167 Nilsen SM et al Single barrier varactors for submillimeter wave power
generation IEEE transactions on microwave theory and techniques 1993 41(4)
p 572-580
168 Xiao Q et al A 270-GHz tuner-less heterostructure barrier varactor frequency
tripler IEEE microwave and wireless components letters 2007 17(4) p 241-
243
169 David T et al Monolithic integrated circuits incorporating InP-based
heterostructure barrier varactors IEEE microwave and wireless components
letters 2002 12(8) p 281-283
170 Lieneweg U B Hancock and J Maserjian Barrier-intrinsic-N+(BIN) diodes
for near-millimeter wave generation in Conference Digest for the Twelft
International Conference on Infrared and Millimeter Waves 1987
171 Lieneweg U et al Modeling of planar varactor frequency multiplier devices
with blocking barriers IEEE transactions on microwave theory and techniques
1992 40(5) p 839-845
172 Chattopadhyay G et al An all-solid-state broad-band frequency multiplier
chain at 1500 GHz IEEE transactions on microwave theory and techniques
2004 52(5) p 1538-1547
173 Maestrini A et al A 17-19 THz local oscillator source IEEE microwave and
wireless components letters 2004 14(6) p 253-255
174 Faber MT J Chramiec and ME Adamski Microwave and millimeter-wave
diode frequency multipliers 1995 Artech House Publishers
175 Frerking MA and JR East Novel heterojunction varactors Proceedings of the
Ieee 1992 80(11) p 1853-1860
176 Penfield P and RP Rafuse Varactor applications 1962
177 Palazzi V et al Low-power frequency doubler in cellulose-based materials for
harmonic RFID applications IEEE microwave and wireless components letters
2014 24(12) p 896-898
178 Presas SM Microwave frequency doubler integrated with miniaturized planar
antennas 2008
228
APPENDICES
Appendix I Doped substrate process details
Mask Stage Process Stage Process step Process detail Equipment
Mask 1 (Mesa
Etch)
Sample clean NMP 10 min 80˚C Beaker
Acetone 5 min Beaker
Isopropanol (IPA) 5 min Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist S1805 - Program 4 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
1 min 09mW iline
(Compensation error set to 1)
MA4 Mask
aligner
Develop MIF 319 for 1 min Beaker
Post Exposure
Bake Oven or Bake 120C for 15
minutes Hotplate
Etch Etch Cal Cal Sample - etch for 2 minutes Beaker
Etch
H3PO4H2O2H2O 3150
time is determined by the etch cal Beaker
Resist Strip Acetone - 5 min and IPA - 5 min Beaker
Mask2 (Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3 Beaker
Acetone ultrasonic for 5 Min Power 3 Beaker
Isopropanol (IPA) ultrasonic for 5 Min Power 3 Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist AznLoF - 2um grade - Program 6 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
55 seconds 09mW i-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 326 for 1 mins Beaker
Clean O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
Surface De-oxide HCLH2O 11 40 sec Beaker
Metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Anneal 420˚C 2min Furnace
229
TLM
Measurement ICCAP
Measurement
Bench
Mask 3
(BottomBacks
ide Contact)
Sample clean Acetone Optional Beaker
Isopropanol (IPA) Optional Beaker
Apply Resist Prebake
Bake for 5mins 150C to dry
the sample Hotplate
Resist (top side) S1813 - Program 6 Laurell Spinner
Soft bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Exposure
10 seconds 09mW I-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 319 for 2 mins Beaker
De-scum O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
De-oxidise
Surface De-oxide
HCLH2O 11 40
sec Beaker
metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Clean Water 3min Beaker
TLM
Measurement ICCAP
230
Appendix II Four Mask step Process Flow
Mask Stage Process Stage Process step Process detail
Mask1 Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3
Acetone ultrasonic for 5 Min Power 3
Isopropanol (IPA) ultrasonic for 5 Min Power 3
Apply Resist Prebake Bake for 5mins 150C
1st Resist AznLoF - 2um grade - Program 6
Hot Plate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 55 seconds 09mW iline (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 1 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
Mask 2 (Mesa
Etch)
Sample clean NMP Optional
Acetone Optional
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C
1st Resist S1805 - Program 4
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 1 min 09mW i-line (Compensation error set
to 1)
Develop MIF 319 for 1 min
Post Exposure Bake Oven or Bake 120C for 15 minutes
Etch Etch Cal Cal Sample - etch for 2 minutes
Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Measure TLM
Resist Strip Acetone - 5 min and IPA - 5 min
Mask 3(Isolation) Sample clean Acetone Optional
Isopropanol (IPA) Optional
231
Apply Resist Prebake Bake for 5mins 150C
Resist S1828 - Program 4
Hot Plate 115C for 1 mins
Photolithography Mask Align mask to wafer
Expose 9 mins 09mW iline (Compensation error set
to 1)
Develop MF 319 3 mins
Post Bake Oven Bake 120C for 15mins
Etch Etch Cal Refer to Etch Cal instr tab
Sub-collector Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Resist Strip Acetone 5mins + IPA 5 mins in ultrasonic bath
power 1
inspection Microscope
Sample clean Acetone Optional
Mask 4 (Bottom
Contact)
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C 1st
Resist AznLoF - 2um grade - Program 6
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 10 seconds 09mW i-line (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 2 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide
HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
232
Appendix III Epitaxial Layer XMBE277
TABLE I The epitaxial structure for sample XMBE277
Layer Thickness (nm) Doping Concentration (cm-3)
n+- In053Ga047As 45 200 x 1019
n- In053Ga047As 25 300 x 1018
In053Ga047As 20 undoped
AlAs 13 undoped
In08Ga02As 45 undoped
AlAs 13 undoped
In053Ga047As 20 undoped
n- In053Ga047As 25 300 x 1018
n+- In053Ga047As 400 100 x 1019
Semi-insulating InP
233
Appendix IV SilVaco (Atlas) Simulation Code
go atlas
---------------------------------------------------------
Structure parameter definition (Constants) values in um
---------------------------------------------------------
Thicknesses
set t_contact1=0
set t_ohmic1=03
set t_emitter=004
set t_spacer1=0005
set t_barrier=000283
set t_spacer2=02
set t_collector=004
set t_ohmic2=045
Doping concentrations
set d_ohmic1=4e18
set d_emitter=2e17
set d_collector=2e17
set d_ohmic2=4e18
set d_gap=2
set d_mesa=4
set d_device=10
set d_etch=008
Layers
set I=$t_contact1
set A=$I+$t_ohmic1
set B=$A+$t_emitter
set C=$B+$t_spacer1
set D=$C+$t_barrier
set E=$D+$t_spacer2
set F=$E+$t_collector
set G=$F+$t_ohmic2
-------------------------------------
Mesh generator
-------------------------------------
mesh diagflip width=45
xmesh location=0 s=1
xmesh location=1 s=1
xmesh location=2 s=1
xmesh location=4 s=1
xmesh location=5 s=1
xmesh location=6 s=1
xmesh location=7 s=1
xmesh location=8 s=1
xmesh location=$d_mesa s=1
xmesh location=$d_mesa+$d_gap s=1
xmesh location=$d_device s=1
Ohmic1
ymesh l=0000 s=005
ymesh l=$I s=005
234
ymesh l=$A s=0005
ymesh l=$B s=0005
ymesh l=$C s=00005
ymesh l=$D s=00005
ymesh l=$E s=0009
ymesh l=$F s=0005
ymesh l=$G s=0005
-----------------------------------
SECTION 2 Regions Structure definition
-----------------------------------
region num=1 name=contact1 material=Gold ymin=0 ymax=$I
region num=2 name=ohmic1 material=GaAs ymin=$I ymax=$A
region num=3 name=emitter material=GaAs ymin=$A ymax=$B
region num=4 name=spacer1 material=GaAs ymin=$B ymax=$C
region num=5 name=barrier material=AlAs ymin=$C ymax=$D xmin=0 xmax=$d_mesa
calcstrain qtregion=1
region num=6 name=spacer2 material=GaAs ymin=$D ymax=$E
region num=7 name=collector material=GaAs ymin=$E ymax=$F
region num=8 name=ohmic2 material=GaAs ymin=$F ymax=$G
region num=9
name=etch material=Air ymin=0 ymax=$F+$d_etch xmin=$d_mesa xmax=$d
_device
---------------------------------
Electrodes
---------------------------------
electrode num=1 name=anode xmin=0 xmax=$d_mesa ymin=0 ymax
=$I material=Gold
electrode num=2 name=cathode xmin=$d_mesa+$d_gap xmax=$d_device ymin=$F+
$d_etch ymax=$F+$d_etch material=Gold
--------------------------------
Doping
--------------------------------
doping uniform ntype conc=$d_ohmic1 Region=2 ymin=$I ymax=$A
doping uniform ntype conc=$d_emitter Region=3 ymin=$A ymax=$B
doping uniform ntype conc=$d_collector Region=7 ymin=$E ymax=$F
doping uniform ntype conc=$d_ohmic2 Region=8 ymin=$F ymax=$G
--------------------------
Contacts
--------------------------
interface sc region=1
interface ss region=2
interface ss region=3
interface si region=4
interface si region=5
interface ss region=6
interface ss region=7
interface sc ymin=$F ymax=$F xmin=$d_mesa+$d_gap xmax=$d_device
interface tunnel region=5 dytunnel=0001
contact name=cathode
contact name=anode
235
------------------------------------------
SECTION 3 Material amp Models Definitions
------------------------------------------
material material=AlAs
permittivity=10 eg300=28 mc=004 affinity=305 nc300=4e19 nimin=1e1
material material=GaAs permittivity=139 eg300=14 mc=0067
affinity=407 nc300=09e17 nimin=1e6
BAND DIAGRAM
output tquantum bandparam qfn qfp valband conband charge polarcharge flowlines
STRUCTURE GRAPHIC
solve init
save outf=XMBE304+real2str
tonyplot XMBE304+real2str
------------------------------------------
SECTION 4 ANALYSIS
------------------------------------------
trap acceptor structure=top elevel=03 density=48e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$A ymax=$C xmin=0 xmax=$d_mesa
trap acceptor structure=BOTTOM elevel=035 density=47e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$E ymax=$F xmin=0 xmax=$d_mesa
models sisel sisnlderivs qtregion=1 print
method climit=1e-4 itlimit=50 maxtraps=20
DC ANALYSIS
log outf=XMBE304log
solve init
solve vanode=0 name=anode vstep=001 vfinal=15
save outf=XMBE304str
log off
tonyplot XMBE304str
tonyplot XMBE304log
3
263 ASPAT Electrical Parameters 61
27 Characterization of Ohmic Contacts 68
271 Transmission Line Measurement (TLM) 69
28 Basic Characterization Techniques and procedures 72
281 Measuring tools and apparatuses 72
282 Measurement steps using a VNA 75
283 Measurement Practice and Flowchart 76
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES 79
31 Introduction 79
32 Epitaxial Layer Growth Techniques 80
321 Molecular Beam Epitaxy (MBE) 80
33 Basic Principles of Common Fabrication techniques 81
331 Sample cleaning 81
332 Photolithography 82
333 Etching Process 86
334 Sputtering (dielectric deposition) 88
335 Metallization Process Lift-off and Annealing 88
34 GaAsAlAs ASPAT Process Optimization 92
341 ASPAT Devices used in Fabrication 93
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability 95
343 Fabrication process of GaAsAlAs ASPAT diode toward High
frequency Applications 117
35 Conclusions 125
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT DIODE USING
SILVACO 126
41 Introduction 126
42 SILVACO modelling Tools 127
43 SILVACO Implementation GaAs AlAs ASPAT Modelling 130
44 Simulation Result and Analysis 132
45 Structure Analysis of ASPAT Diode 135
451 Dependencies of current on AlAs Barrier thickness 135
452 Dependence of current on Spacer I length l1 137
4
453 Dependence of current on Spacer II length l2 138
46 Temperature Dependent Simulation 140
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes 142
48 Conclusions 147
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES 148
51 Introduction 148
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes 149
53 RF Test Fixture Theory and Experiment 153
531 On-Wafer Measurement and Small Signal One-Port Characterizations
154
54 Device Calibration 155
541 Open and Short De-Embedding Technique 155
55 S-Parameter Measurement Result and Analysis 157
551 Diode to diode uniformity 158
552 Wafer to wafer uniformity 160
553 Small devices RF measurements 161
56 Extracting RF models of ASPAT at Zero Bias Voltage 164
561 Extraction of ASPAT parasitic element 165
562 Extraction of ASPAT intrinsic elements 168
563 Capacitances -Voltage (C-V) Extraction 172
57 Conclusions 173
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR DESIGN USING
ADS 175
61 Introduction 175
62 Detection Theory 176
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis 179
64 Noise Consideration in a Detector diode 182
65 Modelling of a 100GHz Zero-biased ASPAT Detector 184
66 Conclusions 199
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING GAASALAS
ASPAT DIODES 201
71 Introduction 201
5
72 Motivation and Background 202
73 Frequency Multiplier Architecture the Basics 203
731 Types of frequency multipliers 205
74 Parameters of interest for Frequency Multipliers 206
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler 208
76 Conclusions 214
8 CONCLUSION AND FUTURE WORK 215
81 Conclusion 215
82 Future Work 217
REFERENCES 218
APPENDICES 228
Word count including footnotes and endnotes 61500(approximately)
6
LIST OF TABLES
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials
structure grown on GaAs Substrates by MBE 23
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314
grown on a GaAs substrate by MBE 24
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP
substrate 24
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary
compound semiconductors a room temperature [41 42] 38
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work 56
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and
Ammonia on GaAs and InGaAs materials 87
Table 32 Epitaxial layer of Doped substrate samples 93
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm 94
Table 34 Generic fabrication steps established by Dr Md Adzhar [101] 97
Table 35 Standard process flow for Air-Bridge design fabrication 101
Table 36 Standard fabrication process flow for Dielectric-Bridge design 107
Table 37 New arrangement of the mask number and step in Second Run 110
Table 38 New arrangement for the Third run using Dielectric-Bridge mask 113
Table 39 The outcome of the spreading resistance before and after using LOR
technique 115
Table 310 DC and RF characteristics for XMBE304 118
Table 311 3rd
Gen Mask process step 119
Table 312 Standard deviation at two different voltages 124
Table 41 The parameter values used in this simulation 134
Table 42 The calculated values of bandgap at different temperatures 140
Table 43 The calculated effective masses for each temperature used in this simulation
141
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104) 145
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics
in this work 153
Table 52 Device to device uniformity check for large ASPAT diode 159
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at
four different frequencies[117] 159
7
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B 161
Table 55 Comparison between calculated (fully Depleted) and extracted (different
biases) values from equivalent circuit parameters for different ASPAT mesa sizes at zero
bias voltage 170
Table 61 A summary of all the important parameters of the 4x4 microm2 diode 185
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode 190
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector 198
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero
bias detector at W-band (75GHz-110GHz) 199
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art
multiplier diode 213
8
LIST OF FIGURES
Figure 21 III-V compound semiconductors mobility and band gap[24] 31 Figure 22 illustration of Homojunctions band structure material before (left) and after
(right) equilibrium 34 Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium 35
Figure 24 Lattice Matching for both materials when aL=aS 37 Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40] 37 Figure 26 Lattice mismatched material 39
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and
(b) tensile strain [1] 40 Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg
GaAs (a) Structure (b) energy band diagram and (c) Conduction band diagram when
AlGaAs is n-doped[43] 41 Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact 43
Figure 210 Energy band diagram of Schottky contact on n-type material under (a)
reverse and (b) forward bias 45 Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping
concentration ND (a) Low (b) Intermediate and (c) high 47 Figure 212 Classical view of whether an electron is can surmount a barrier or not
Quantum mechanical view allows an electron to tunnel through a barrier The probability
(blue) is related to the barrier thickness 51
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave
function[70] 52
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in
this study 55 Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27] 57
Figure 216 Conduction band diagram showing band bending and 2DEG formation at
the L1 spacer 60 Figure 217 I-V characteristics of a fabricated ASPAT diode 63 Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
63 Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b
and h are not drawn to scale 65 Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304)
The dimensions are not drawn to scale 67 Figure 221 A simple TLM structure with effective length and sheet resistance
underneath 69 Figure 222 Top view of TLM ladder structure use in this work 71 Figure 223 Typical plot of resistance versus TLM spacing 71
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM 73
9
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
75 Figure 226 Actual VNA system that was used for RF characterization 75 Figure 227 Block diagram of the ASPAT measurement step 77
Figure 31 3D illustration of Optical lithography process used in this research 85 Figure 32 Actual picture of thermal evaporator used in this study 89 Figure 33 Single layer lift-off process using negative photoresist 91 Figure 34 Current-Voltage characteristic of sample XMBE368 used in this study at
two different locations on the wafer tile 96
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2
diode dimensions designed in the 1st Gen Mask 96
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates 100 Figure 37 The layout of 1
st design of Dielectric Bridge (green circle) mask design for
100 times 100microm2 emitter size with option for doped substrate processing 100
Figure 38 Dry Etching for the first run in this study 102 Figure 39 Severe undercut of 2times2 microm
2 and 6times6 microm
2 devices 103
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet
etched 104 Figure 311 SEM Images of the GaAs sample 104
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in
this study 105
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
105
Figure 314 SEM images for InP and InGaAs taken from [56] 105 Figure 315 Short circuit behaviour on one of the fabricated device in this run 106
Figure 316 The surface of the sample after final processing 108 Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2
2500 microm2 900 microm2 400 microm2 225 microm2 100 microm2 and 36 microm2 109
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm
Tolerance 110
Figure 319 After lift-off processing 111 Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
112
Figure 321 side view of lateral ASPAT structure 113
Figure 322 The measured size of the emitter area and the length D (blue color marked)
114 Figure 323 Summary of LOR technique steps 115 Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
116
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and
alignment mark structures used in this study 118 Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-
insulating substrate device type used in this study 121 Figure 327 Example finished process device with bond pad using 3
rd Gen mask 121
Figure 328 XMBE304 TLM measurement for the top contact after annealing 122
10
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing 122 Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 4times4microm2 mesa size 123
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 6times6microm2 mesa size 124
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 10times10microm2 mesa size 124
Figure 41 SILVACO Atlas simulation process flow 128 Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the
diode multilayer heterostructures on the right 131 Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor 131 Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure
(b) the energy band diagram of the ASPAT diode structure when under three different
biases 132 Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm
2) and
(4times4microm2) using SILVACO Atlas simulator for structure device XMBE304 showing
excellent agreement between simulated and experimental data 134
Figure 46 IV characteristics of the dependencies of current on AlAs barrier 136 Figure 47 Example of analysis at -1 and 1V to the current 136 Figure 48 I-V characteristic of the dependencies current to Spacer I layer 137
Figure 49 Current changes with layer thickness l1 138 Figure 410 IV characteristic of the dependencies current to Spacer 1 layer 139
Figure 411Current change with layer thickness l2 139
Figure 412 Measurement and simulation comparison result as a function of temperature
range from 100K to 398K 142 Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample
XMBE304 143
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT
Diode [3] 144
Figure 415 Log Current vs voltage as a function of temperature for SBD sample
XMBE104 145
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and
SBD 146
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2
6x6um2 and 10x10um
2 Note the good scalability 149
Figure 52 Junction resistance versus voltage 151
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT
high sensitivity near zero bias detection 152
Figure 54 One port S-parameter measurements 155
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use
for RF calibration and measurements (Note Images are not to scale) 156
11
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices
from 15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check 158
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero
bias 158
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B)
to qualify the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2
device sizes (Real and Imaginary) Note blue colour is XMBE304A and red colour is
XMBE304B 160
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and
4times4microm2
(Real and Imaginary) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm
2 diodes respectively 162
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and
4times4 microm2 (Smith Chart) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm2 diodes respectively 162
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding
equivalent circuit model 164
Figure 512 The S-parameter Touchstone file is used to read the measured files 165
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure 166
Figure 514 Equivalent circuit model for short de-embedded structure 166
Figure 515 Smith chart representative S-parameter measurement for short (left) and
open (right) CPW The blue lines represent simulated data and the red is measured data
167
Figure 516 Equivalent circuit of the ASPAT diode 169
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 (Real and Imaginary) results for various small device designs 169
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 results (Smith Chart) for various small device designs 170
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled
capacitance vs Voltage) 172
Figure 61 Block diagram represent a complete direct receiver system 177
Figure 62 The detection process of a single wave through a non-linear IV characteristic
of a diode 177
Figure 63 Lumped element illustration of microwave detector circuit 178
Figure 64 The mixing process where the signals are processed by the non-linear I-V
characteristic to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and
fRF are applied to the diode 179
Figure 65 Measurement of Tangential Sensitivity[108 129] 181
12
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted
from MATLAB to realize a virtual GaAsAlAs ASPAT diode 186
Figure 67 Verification of actual (blue measured) and virtual (red_10th order
polynomial) I-V characteristic of the 4times4 microm2 diode used in this study 186
Figure 68 Direct detector circuit topology using an ASPAT diode 187
Figure 69 Output voltage and detector sensitivity over wide range of input power 188
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load
resistance of the ASPAT detector 189
Figure 611 Junction resistance as a function of forward voltage 189
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size
of 4times4μm2 191
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power 192
Figure 614 Reflection Coefficient versus operating frequency without matching
circuitry 193
Figure 615 Detector circuit with impedance matching circuit placed in between diode
and source 194
Figure 616 Reflection Coefficient over wide frequency band with matching 195
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band
frequency 195
Figure 618 Lowest detectable signal at 100GHz operating frequency 196
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of
diode operation 197
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained
from the fabricated ASPAT in this work 198
Figure 71 performance of state-of the-art millimetre wave source [166] 202
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
204
Figure 73 Principle of operation for frequency multiplier utilising a non-linear
resistance [10] 204
Figure 74 A standard system for two port frequency multiplier circuit 207
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode 209
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool 210
Figure 77 Conversion loss and conversion efficiency as a function of input power 211
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
212
13
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS
PUBLICATIONS
1 MRR Abdullah Y K Wang J Sexton M Missous and M J Kelly ldquoGaAsAlAs
Tunnelling Structure Temperature Dependence of ASPAT Detectorsrdquo 8th UK-Europe-
China Workshop on mm-waves and THz Technologies 2015 Cardiff University IEEE
proceedings DOI 101109UCMMT20157460591
2 Yuekun Wang Mohd Rashid Redza Abdullah James Sexton and M Missous
ldquoInGaAs-AlAs asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo 8th
UK-Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings DOI 101109UCMMT20157460589
3 K N Zainul Ariffin S G Muttlak M Abdullah M R R Abdullah Y Wang and M
Missous ldquoAsymmetric Spacer Layer Tunnel In018Ga082AsAlAs (ASPAT) Diode using
Double Quantum Wells for Dual Functions Detection and Oscillationrdquo 8th UK-
Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings Doi 101109UCMMT20157460599
4 K N Zainul Ariffin M R R Abdullah Y K Wang S G Muttlak O S
Abdulwahid J Sexton MJ Kelly and M Missous ldquoAsymmetric Spacer Layer Tunnel
Diode (ASPAT) Quantum Structure Design Linked to Current-Voltage Characteristics
A Physical Simulation Studyrdquo UK-China Millimetre Waves and Terahertz Technology
Workshop September 2017 Submitted 14 July 2017 Conference held on 11th -13th
September 2017 DOI 101109UCMMT20178068358
5 K N Zainul Ariffin Y Wang M R R Abdullah S G Muttlak Omar S
Abdulwahid J Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoInvestigations of
Asymmetric Spacer Tunnel Layer (ASPAT) Diode for High-Frequency Applicationsrdquo
DOI 101109TED20172777803
6 Omar S Abdulwahid S G Muttlak M R R Abdullah K N Zainul Ariffin J
Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoA 100GHz Zero-Biased
Quantum Tunnelling ASPAT Detectorrdquo Submitted to IEEE TED on DEC 2016 under
correctionamendment Pending fabrication data
14
CONFERENCE PRESENTATIONS
1 Mohd Rashid Redza Abdullah J Sexton Kawa Ian MJKelly and M Missousldquo
G2040GHz Frequency Doubler Varistor Mode using ASPAT diodesrdquo UK
Semiconductors 2017 2017 University of Sheffield Oral presentation
2 M R R Abdullah YueKun Wang J Sexton Kawa Ian and M Missousldquo
Microwave Performance of GaAsAlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diodesrdquo UK Semiconductors 2016 2016 University of Sheffield Oral presentation
3 M R R Abdullah J Sexton and M Missousldquo GaAsAlAs Tunnelling Structures
THz RTD oscillators and ASPAT detectorsrdquo UK Semiconductors 2015 2015
University of Sheffield Oral presentation
4 Yuekun Wang Mohd Rashid Redza Abdullah and M MissousldquoInGaAs-AlAs
asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo UK
Semiconductors 2015 2015 University of Sheffield Oral presentation
5 Mohd Rashid Redza Abdullah and M Missousldquo GaAsAlAs Tunnelling
Structure Temperature Dependence of ASPAT Detectorsrdquo PGR Conference2016
2016 University of Manchester Poster presentation
6 YueKun Wang KNZainul Ariffin Mohd Rashid Redza Abdullah J Sexton
Kawa Ian and M Missous ldquoPhysical Modelling and Experimental Studies of
InGaAsAlAs Asymmetric spacer Layer Tunnel Diodesrdquo UK Semiconductors 2016
2016 University of Sheffield Oral presentation
7 K N Zainul Ariffin S G Muttlak M R R Abdullah Y Wang Omar S
Abdulwahid M Missous ldquoExperimental and Physical Modelling of Temperature
Dependence of a Double Quantum Well In018Ga082AsAlAs ASPAT Dioderdquo UK
Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral Presentation
8 Omar S Abdulwahid Mohd Rashid Redza Abdullah S G Muttlak K N Zainul
Ariffin Mohamed Missous ldquoTunnelling Barrier Diode for Millimetre Wave
Mixingrdquo UK Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral
Presentation
9 M Abdullah K N Zainul Ariffin MRR Abdullah J Sexton M Missous and
MJ Kelly ldquoA Novel In18Ga82As-AlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diode with Double Quantum Wells for Microwave Detectionrdquo UK Semiconductor
Conference 2015 Sheffield 1 ndash 2 July 2015 Oral Presentation
15
ABSTRACT
Thesis Title GaAsAlAs ASPAT Diodes for Millimetre and Sub-Millimetre Wave
Applications
Institute School of Electrical and Electronic Engineering the University of Manchester
Candidate Mohd Rashid Redza bin Abdullah
Degree Doctor of Philosophy (PhD)
Date 3 October 2017
The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in
the early 90s as an alternative to the Schottky barrier diode (SBD) technology for
microwave detector applications due to its highly stable temperature characteristics The
ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a
thin barrier which enables RF detection at zero bias from microwaves up to
submillimetre wave frequencies In this work two heavily doped GaAs contact layer on
top and bottom layers adjacent to lightly doped GaAs intermediate layers enclose
undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that
acts as a tunnel barrier The ultimate ambition of this work was to develop a MMIC
detector as well as a frequency source based on optimized ASPAT diodes for millimetre
wave (100GHz) applications The effect of material parameter and dimensions on the
ASPAT source performances was described using an empirical model for the first time
Since this is a new device keys challenges in this work were to improve DC and
RF characteristic as well as to develop a repeatable reproducible and ultimately
manufacturable fabrication process flow This was investigated using two approaches
namely air-bridge and dielectric-bridge fabrication process flows Through this work it
was found that the GaAsAlAs heterostructures ASPAT diode are more amenable to the
dielectric-bridge technique as large-scale fabrication of mesa area up to 4times4microm2 with
device yields exceeding 80 routinely produced The fabrication of the ASPAT using i-
line optical lithography which has the capability to reduce emitter area to 4times4microm2 to
lower down the device capacitance for millimetre wave application has been made
feasible in this work The former challenge was extensively studied through materials
and structural characterisations by a SILVACO physical modelling and confirmed by
comparison with experimental data The I-V characteristic of the fabricated ASPAT
demonstrated outstanding scalability demonstrating robust processing A fair
comparison has been made between ASPAT and SBD fabricated in-house indicating
ASPAT is extremely stable to the temperature The RF characterisations were carried out
with the aid of Keysight ADS software
The DC characteristic from fabricated GaAsAlAs ASPAT diodes were absorbed
into an ADS simulation tool and utilized to demonstrate the performance of MMIC
100GHz detector as well as 20GHz40GHz signal generators Zero bias ASPAT with
mesa area of 4times4microm2 with video resistance of 90KΩ junction capacitance of 23fF and
curvature coefficient of 23V-1
has demonstrated detector voltage sensitivity above
2000VW while the signal source conversion loss and conversion efficiency are 28dB
and 03 respectively An estimate noise equivalent power (NEP) for this particular
device is 188pWHz12
16
DECLARATION AND COPYRIGHT STATEMENT
No portion of the work referred to in the dissertation has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning
COPYRIGHT STATEMENT
i The author of this thesis (including any appendices andor schedules to this thesis) owns
certain copyright or related rights in it (the ldquoCopyrightrdquo) and he has given The University of
Manchester certain rights to use such Copyright including for administrative purposes
ii Copies of this thesis either in full or in extracts and whether in hard or electronic copy
may be made only in accordance with the Copyright Designs and Patents Act 1988 (as
amended) and regulations issued under it or where appropriate in accordance with licensing
agreements which the University has from time to time This page must form part of any
such copies made
iii The ownership of certain Copyright patents designs trademarks and other intellectual
property (the ldquoIntellectual Propertyrdquo) and any reproductions of copyright works in the thesis
for example graphs and tables (ldquoReproductionsrdquo) which may be described in this thesis
may not be owned by the author and may be owned by third parties Such Intellectual
Property and Reproductions cannot and must not be made available for use without the prior
written permission of the owner(s) of the relevant Intellectual Property andor
Reproductions
iv Further information on the conditions under which disclosure publication and
commercialisation of this thesis the Copyright and any Intellectual Property andor
Reproductions described in it may take place is available in the University IP Policy
(httpdocumentsmanchesteracukDocuInfoaspxDocID=487) in any relevant Thesis
restriction declarations deposited in the University Library The University Libraryrsquos
regulations (httpwwwmanchesteracuklibraryaboutusregulations) and in The
Universityrsquos policy on Presentation of Theses
17
ACKNOWLEDGEMENTS
First and foremost all gratefulness and praise is to Allah swt for everything in my
life He is the one and the only one who granted me knowledge health patience and
ability to complete this thesis as well as colouring the whole journey of my PhD
I give my deepest and sincere gratitude to my PhD supervisor Professor Mohamed
Missous for his time support patience and guidance throughout the journey of this PhD
studies His encouragements valuable advice precious ideas and a wealth of knowledge
amp experiences have had a direct inspiration on this research Special thanks also to our
experimental officer Dr James Sexton for not only sharing his knowledge advice and
semiconductor fabrication skills but also his effort in maintaining our clean room
facilities to a great level My gratitude also extends to Mr Mallachi McGowan for his
help and assist in the lab-related issue
I am also obligated to Prof MJ Kelly from University of Cambridge and Dr Kawa
Ian from ICS limited for their measurement of the ASPAT samples on realizing the RF
characteristics This collaboration effort can hopefully last longer in designing and
implementing the ASPAT MMIC detectors
My deepest appreciation also goes to my PhD colleagues Khairul Nabilah Saad
GMuttlak Omar AbdulWahid and Yuekun Wang for their support as well as working
together with me to realize this exciting project directly and indirectly A sincere
thankfulness similarly to my seniors Dr Md Adzhar Zawawi and Dr Fauzi Packeer for
their support during the first and second year of my research For other friends and staff
members under Prof Missous and Dr M Migliorato I will always remember the strong
bond and friendship we made
I am really fortunate that I been blessed with my motherrsquos care who always make doarsquo
for my success every day during my studies As for my beloved wife Dr Nik Maryam
Anisah Nik Mursquotasim who had always encouraged me supported me and gave me
patience through all the hardship in this journey thank you very much
Finally I also would like to thank and acknowledge my sponsor Majlis Amanah
Rakyat (MARA) for financially supporting me during this studies I am greatly indebted
with your kind support which was vital to my study
18
DEDICATION
This thesis dedicated to
My respected and beloved parentshellip
My loving wife dearest siblings and in-lawshellip
19
1 INTRODUCTION
11 Background
It is an undeniable fact that semiconductors have changed the world much further
than anything people could have predicted in the last 60 or 70 years ie after the lsquocats
whisker and vacuum tube eras This field of research has been expanding from year to
year starting from the discovery of the first semiconductor (silver sulfide) in 1833 by
Michael Faraday [1 2] and it still remains very active to the present Semiconductors
have a large range of applications and are not just limited to use in communications they
can be found everywhere in other applications from Earth to space The widespread
usage and sheer number of applications have led to it growing very quickly and
contributing greatly to the growth of World Economics Over time the successful
development of semiconductor growth techniques such as Molecular Beam Epitaxy
(MBE) has enabled researchers to tailor and precisely control the semiconductor
material for new electronic devices with extra functionalities This has led to the
development of advanced devices such as high electron mobility transistors (HEMTs)
and Heterojunction bipolar transistors (HBTs) for use in wireless communication
technology Given this development today electronic devices such as computers
handheld smartphone tablets etc are no longer perceived as luxury and attractive items
but rather have become crucial in everyday life Such devices provide the means to allow
for people to remain connected to each other via the sending and receiving of
information electronically The huge demand for such types of devices has resulted in
competition in both the electronic market and technologies which only goes on to
advance the semiconductor industry
Nowadays the demand for electronic devices characterised by high speed high
efficiency ultra-low power and low manufacturing cost has increased exponentially To
fulfil this growth in demand high data rate systems are required in other words the
system must work at a higher frequency for both the transmitter and receiver The
frequency of interest for advanced wireless communication is in the Millimetre and sub-
20
millimetre wave region which is around 30-300GHz and 300 - 3000GHz respectively
The second frequency region is also sometime known as the terahertz (THz)
electromagnetic region This band lies between the microwave and infrared frequency
bands From the first time it was revealed in the late 80s[3-5] the THz region has gained
a lot of international attention due to its unique properties and since then the motivation
to develop these devices has increased significantly To date the THz frequencies region
has shown its ability to fulfil various applications such as high-resolution imaging in
medical security and surveillance field atmospheric monitoring and environment radio
astronomy as well as compact range radars[3] to name a few
However despite these developments not much effort has been made in exploring
alternative compact THz devices As a result electronic THz devices are still in the state
of immaturity as compared to microwave and photonics devices This is due to their high
cost and absence of compact amp solid-state THz sources (oscillators) and receivers
(detectors) that are capable of operating at both room and extreme temperatures[6 7] A
great deal of work still continues to fill up the lsquoTHz gaprsquo (between 300GHz and 3THz)
used for the most important part of a communication system namely the front-end
receiver or first stage Such a system is responsible for receiving detecting and
processing the received signal to be translated into useful information Furthermore THz
receivers systems still require the best-integrated components such as source mixer and
detector to reach their complete competencies[8] The detector which remains the
critical part of the receiver system requires devices or components that are able to fulfil
the THz gap requirement Studies conducted over a number of years have found out that
the key element in improving THz detection relies upon the use of passive devices ie
diodes Based on these findings many types of diode ie tunnelling diode point-contact
diode and Schottky barrier diode (SBD) have been proposed for detection applications
Amongst microwave and millimetre wave detector diode devices the Schottky
Barrier Diode (SBD) is the dominant detector that has been used since the 1940s[9] The
reason for this dominance is the ease of fabrication of a SBD (by either a point-contact
or evaporated semiconductor-metal structure) and its ability to produce a non-linear
current-voltage (I-V) characteristic which is necessary for rectifyingdetecting diodes [9
10] SBDs also have high cut-off frequency good dynamic range and are low cost To
21
date the SBD has been able to detect signals up to 100GHz [11] 1THz[12] and as high
as 10 THz[13] However the current transport mechanism in a SBD relies on thermionic
emission and therefore is strongly dependent on temperature and means that using them
in extreme conditions ie military and automotive applications is complex The SBD
also suffers from high noise figure[14] and is susceptible to burnout at a modest pulse
power level this will limit the use of ultra-high frequencies and low power signal
applications Other diodes that share the same characteristics are Planar Doped Barrier
(PDB) Germanium Backward Diode (GBD) ie a type of Esaki tunnel diode These
diodes are well known and are reliably used as millimetre wave detectors However it
still proves inefficient to substitute the SDB with any of the previously mentioned
diodes This is due to some drawbacks such as strong temperature dependence limited
dynamic range fabrication complications and hence poor reproducibility (ie GBD) and
other circuit complexities
Hence there is strong compulsion to study examine and produce new detector
diode structures that are able to solve the mentioned diodes limitations and which have
high sensitivity larger dynamic range low noise strong independence to temperature as
well as being able to work efficiently in the high-frequency band and at zero bias The
advantages of working at zero-bias relates very much to the need for a system with less
power consumption so that the device (ie mobile communication) is able to run off
small batteries for a reasonable length of time eliminating extra biasing circuit as well as
noise Therefore a new tunnelling device namely the Asymmetrical Spacer Layer
Tunnel diode (ASPAT) developed by RT Syme [15 16] and refined by Missous et
al[17] has been examined in this work The ASPAT which is in essence a
Semiconductor-insulator-semiconductor structure relies on tunnelling through a barrier
to provide current compared to conventional thermionic emission in SBDs The ASPAT
diode has many advantages a zero bias turn-on voltage very weak sensitivity to changes
in temperature (due to tunnelling) very low noise large dynamic range high resistance
to pulse burn-out [18] and as demonstrated recently can be reproducibly
manufactured[17] The growing interest in THz frequencies nowadays makes the
ASPAT an excellent choice to fulfil all requirements for ultra-high speed applications
22
ie communication (mobile computer networking) radar (military equipment) scalar
analyser and built-in test equipment
In this work an ASPAT diode based on group III-V elements of the periodic table
comprising compound semiconductors of large band gap material Aluminium Arsenide
(AlAs) sandwiched between two lower bandgap Gallium Arsenide (GaAs) are used and
intensively examined The AlAs semiconductor which is ten-monolayer thick has
almost the same lattice constant as GaAs but has a larger bandgap Consequently in the
conduction band a thin barrier of the AlAs is formed from the arrangement of such
structure The structure is made up of GaAs and AlAs both materials are grown on
GaAs substrate using Solid Source Molecular Beam Epitaxy (SSMBE) Therefore in
this study the ASPAT diode will be referred to as ldquoGaAsAlAs ASPATrdquo diode The
conventional GaAsAlAs ASPAT diode has been developed and successfully fabricated
in two different stages This work was the first carried out using facilities provided by
the University of Manchester The first stage of the work was to qualify the
reproducibility and repeatability of growth and fabrication technique which is mostly
performed on larger emitteranode size The second was to develop conventional
ASPAT diodes that can perform at Millimetre and sub-millimetre wave frequencies and
which are comprised of small emitter area
Prior to this work full physical modelling using SILVACO design software was
undertaken to generate models and to fully characterise and identify the fundamental
physical phenomenon of multi-junction ASPAT diode Therefore insight into and
performance based on diode structure and electron movement can be understood and
predicted which lead to the crucial idea in helping and advising iterations to epitaxial
growth as well as diode fabrication The verification of the physical models must be set
as a priority goal by comparing the results of statistically fabricated measured data The
advantage of physical modelling is that it can help reduce materials resources cost and
fabrication time
Further research into the field has led to the development of two other types of
ASPAT diodes that are used to compare with the conventional GaAsAlAs ASPAT
diode Their configuration involved the use of a more advanced semiconductor
technology which comprises InGaAsAlAs materials and GaAsAlAs with InGaAs
23
quantum wells The latter was a novel ASPAT diode and the former is identified as
advanced ASPAT diode However these two advanced ASPAT diodes have not been
extensively studied in this thesis as they will be covered by other co-workers at
Manchester Hence due to these some important parameters are compared to the
conventional one as it is the main focus of this work In the case of temperature
dependent studies the DC characteristic of conventional ASPAT is compared to in-
house fabrication AuGaAs SBD All the ASPATs epitaxial layer materials structures are
shown in the following tables
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials structure grown
on GaAs Substrates by MBE
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE304 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~400 ~50
Spacer1 GaAs NID 50 50 50
Barrier AlAs NID 28 28 28
Spacer 2 GaAs NID 1000 2000 1000
Buffer GaAs(Si) 4times1017
50 400 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~4500 ~3500
Substrate GaAs (Si) 50000 50000 50000
Note that sample XMBE368 and XMBE304 are grown on doped GaAs
substrates Sample XMBE368 was grown un-rotated to study the effect of barrier
thickness variation
24
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314 grown on a
GaAs substrate by MBE
XMBE314
Layer Material Doping (119836119846minus120785) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018
3000 142
Emitter GaAs (Si) 1times1017
400 142
Spacer GaAs Undoped 50 142
Quantum Well In18Ga82As Undoped 60 116
Barrier AlAs Undoped 28 283
Quantum Well In18Ga82As Undoped 60 116
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017
400 142
Ohmic Layer GaAs (Si) 4times1018
4500 142
Substrate GaAs
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP substrate
XMBE326
Layer Material Doping (cm-3
) Thickness (Aring) Bandgap (eV)
Top Ohmic1 In053Ga047As(Si) 5times1019
3000 075
Buffer 1 In053Ga047As(Si) 1times1017
350 075
Spacer1 In053Ga047As NID 50 073
Barrier AlAs NID 283 283
Spacer 2 In053Ga047As NID 2000 075
Buffer In053Ga047As(Si) 1times1017
350 075
Bottom Ohmic In053Ga047As(Si) 15times1019
4200 075
Substrate InP (Si) NID 620000
From the above tables it can be noted that XMBE307 is the first batch that was grown
in-house using a Riber V100HU MBE machine followed by XMBE368 XMBE 304
XMBE314 and finally XMBE326 The two earlier batches were grown on n+
substrate hence their fabrication process flow is simpler On the other hand the three
other batches were grown on semi insulating substrate thus requiring the development
of new repeatable reproducible and robust process flow which will be covered in this
thesis
25
In general the fabrication of the ASPAT diode is based on top-down processes this
is because the ASPAT is a vertical structure device and the junction capacitance of the
ASPAT is directly associated with the size of the anodeemitter area Further to these
the capacitance directly influences the diode cut-off frequency Therefore the simplest
way to reduce the capacitance is by reducing the lateral area of the device of the ASPAT
structure since it can be represented by a parallel plate capacitor where the capacitance
is inversely proportional to the area of the device In order to achieve high cut-off
frequencies minimising capacitance via small dimensions ie sub-micrometre level is
essential However this will also increase the series resistance of the diode As a result
the cut-off frequency will be degraded Thus there is a trade-off between small
dimension of device and high cut-off frequency to be achieved
Finally successful growth and fabrication for small area GaAsAlAs ASPAT diode
in this work has led to carefully extracted RF characteristics This becomes a stepping
stone to designing a millimetre wave integrated circuit (MMIC) detector using empirical
modelling in Keysight ADS tools Therefore a predicted performance for a 4times4 um2
fabricated ASPAT is that can operate at 100GHz ASPAT as a zero-bias detector with a
voltage sensitivity of over 2000VW Additionally the design of a millimetre wave
source using similar ASPAT diodes was also carried out The performance of a 2040
GHz doubler using GaAsAlAs ASPAT in varistor mode is demonstrated for the first
time with a conversion loss of 33dB and conversion efficiency of ~ 02
26
12 Aims and objectives
The aim of this study is to further improve the performance of microwave and
millimetre wave technology by incorporating the Asymmetrical Spacer Layer Tunnel
Diode (ASPAT) for ultimate operation near THz frequencies by designing a range of
low power high-speed devices enhancing the methods of Simulation layout and
materials amp structural characterisations with fabrication process optimization using the
facilities available at the University of Manchester
There are three main objectives in this research firstly to streamline the physical
device design and modelling using the GaAsAlAsGaAs materials systems in order to
produce a zero bias detector which is basically a rectifier of a microwave signal by
using the SILVACO Atlas simulation tools
Secondly to achieve reproducibility and manufacturability of the fabrication
process for new type of GaAsAlAs ASPAT structure (lateral structure) hence small size
ASPAT emitter by improving the device processing technique and maximising the
capability limit of the conventional i-line optical lithography that is available in Prof
Missousrsquos group laboratory
Thirdly to optimise DC parameters through electrical properties investigation as a
stepping stone to the next objective that is to characterise the RF performance of the
GaAsAlAs ASPAT detector circuit The detection properties of microwave and
millimetre wave diode will also be investigated with different ASPAT diode size at
100GHz Further to these the properties of microwave signal source will also be
developed by way of utilizing the non-linearity feature of the diode Therefore this new
type of tunnelling diode can be applied to both applications of signal detection and
signal source in the microwave and millimetre wave ranges
27
13 Outline of this Thesis
This thesis is organized into eight chapters The first chapter discusses the
contextual information that motivates the undertaking of the study An overview of the
work which includes the details of the studied samples the aim and objectives of the
whole research project are also outlined in this chapter
Chapter 2 deals with the literature review of the basic principles and concepts of
the group III-V compound semiconductors The historical background of such
semiconductors which is essential to the development of ternary structures etc and the
advancement of semiconductor materials engineering is presented The types of existing
tunneling diode as well as conventional microwave diodes are also discussed and
compared The fundamentals of ASPAT diode which includes structural parameters and
its operation are then explained in detail Finally discussions of the ASPAT key DC
characteristics which are important for detection purposes are presented
Chapter 3 focusses on the development of the experimental techniques which can
be divided into two stages In the first stage the development is towards repeatability
reproducibility and manufacturability of the ASPAT grown in-house by MBE and
fabricated by conventional i-line optical lithography The second stage involves
optimisation and fine tuning such fabrication method for GaAsAlAs ASPAT samples
that can operate at high frequency ie 100GHz detector For both stages of the
fabrication process all techniques including mask design generic and special process
flow are presented The chapter ends with discussions on issues related to sample
processing and improvements that are proposed to solve these issues
Chapter 4 dwells on the modelling of the GaAsAlAs ASPAT using the SILVACO
simulation package The discussions are expected to offer a better understanding or
insight into each layer that forms the ASPAT diode structure The chapter begins with
discussions of the operation of the SILVACO Atlas tool A validation of physical
modelling is essential and presented according to the fabricated mesa sizes of the diode
28
Thereafter towards the end of the chapter the analyses of the relationship between
device current-voltage (I-V) characteristics the structural parameter including various
temperatures dependent simulations with a comparison to an in-house fabricated SBD
are offered
Chapter 5 presents relevant DC results based on optimized fabrication process and
RF characterization which enable obtaining an intrinsic and extrinsic element of the
GaAsAlAs ASPAT diode The discussions also highlight the analysis of DC zero bias
equivalent circuit and de-embedding extraction using ADS The chapter ends with
discussions on the RF reproducibility performance which includes the performance as
well for millimeter-wave and sub-millimeter wave applications
Chapter 6 discusses the main applications of ASPAT diodes The chapter begins
with discussions on detection theory followed by the parameters of interest and ends
with circuit design as well as the performance of a 100GHz detector The circuit design
was conducted using Keysight ADS software via harmonics balance simulation tool The
performance in term of sensitivity depending on measured ASPAT emitter size is
demonstrated Finally a comparison with conventional Schottky diode is presented
towards the end of the chapter
Chapter 7 discusses a secondary application that can be applied to the ASPAT by
utilizing the nonlinearity feature of the diode to create a signal source namely a 20 to
40GHz frequency doubler in varistor mode The doubler performance of ASPAT will be
explored through circuit design constructed via Keysight ADS simulation software Each
key parameter is highlighted and discussed in detail
The final chapter of this thesis that is Chapter 8 discusses the conclusions of the
study with emphasis on the overall key research findings The chapter also highlights
suggestions for further research in this particular field of study
29
2 LITERATURE REVIEW
21 Introduction
Since 1940s the development in the technology of semiconductor electronics has
been expanding and now has led to the establishment one of the most astonishing
industries of the 3rd
-millennium era Leading this advancement is the integrated circuit
(IC) or chip which was driven mostly by silicon (Si) Overtime the IC has undergone
substantial revolution in term of power economics size and efficient energy
consumption Currently it covers every aspect of human life ie from desktop personal
computers in the office and house to the compact smartphone in the pocket and from a
gigantic satellite in space to small satellite navigation in cars In other words
semiconductor technology is crucial to human life Without developments in
semiconductor materials engineering and shrinking of device size such accomplishment
may not have been realised today Therefore this chapter presents a macro view of the
development in compound semiconductor technology especially in radio frequency (RF)
towards Millimetre and submillimetre wave applications with regard to the improvement
of material and device structures
The essentials of group III-V compound semiconductor will be emphasised for its
points of interest and application in this field (RF technology) This chapter comprises
five main sections The first section is an overview of the semiconductor history with
concentration on its advantages and applications in the RF field while the second and
third discuss the effects of III-V compounds when the interface occurs between
semiconductor-semiconductor and semiconductor-metal respectively which leads to a
basic understanding of hetero-structures device as well as contacts namely Schottky and
Ohmic The fourth section is predominantly concerned with high-speed devices ie
diodes and materials in this field which leads to the exploitation of the main researchrsquos
device Then the following section describes in detail the background works basic
principle and intrinsic amp extrinsic parameters of the Asymmetric spacer Tunnel Diode
(ASPAT) Finally the basic way of characterising the device will also include giving an
overview of how the device is measured and what parameters are needed
30
22 Historical review of III-V Compound Semiconductor for RF applications
The beginning of commercial electronic devices was marked with the first point-
contact semiconductor transistor developed in 1947 by William Shockley at Bell
Laboratories in New Jersey Shockley developed a device based on a Germanium
Bipolar Junction Transistor (Ge BJT) structure [19] with operating frequency above 1
GHz Since then and until early 1950s the development of Ge BJT was fast and it
became foremost in the market of semiconductor technology However the emergence
of Silicon (Si) challenged Ge in the market in the 1960s Si has the upper hand primarily
because it has better electron transport and low manufacturing costs compared to Ge
[19] By the 1970s almost all RF transistors were based on Si BJT Additionally the
development of Si which forms a new material from the formation of native oxide
namely Silicon Dioxide (SiO2) led to the invention of the Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) [19] The future of digital electronic industries has
been ldquobrightrdquo ever since the MOSFET was ldquobornrdquo as it has become a fundamental
building block component in complex microprocessors and flash memories Despite this
development the exploitation of Si at RF frequencies did not last long since Si is not an
optimum semiconductor for RF electronic devices The emergence of GaAs has
improved RF applications for high-speed transistors
Ge and Si which are categorised as single element semiconductor are the earliest
materials used to build the first transistor devices These devices played a crucial role
towards the development of more advanced material such as GaAs of the compound
semiconductor type[20] A compound semiconductor is a semiconductor formed by the
ionic bond of different types of semiconductor material most widely known as the group
III-V compound semiconductors The main reason for the progression of the III-V
compound semiconductors is due to their better electron mobility compared to the single
element semiconductors The term ldquomobilityrdquo in the semiconductor industry refers to the
easiness of movement of charges in many directions inside a crystal In fact it is
determined by the access resistances values with saturated velocity under certain values
of electric fields (bias) the higher the electric field the faster is the carrier movement in
the crystal Figure 21 shows the electron mobility and band gap for the most common
31
group III-V compound semiconductors Besides higher mobility III-V compound
semiconductors also have light-emission capability and are suitable for bandgap-
engineering techniques
The work on III-V compound semiconductors mainly on GaAs FETs led to a new
change for the whole RF electronics industry For example in 1966 the first GaAs
MESFET was invented[21] and achieved a maximum operating frequency of operation
of 3GHz [22] Three years later the frequency increased to 30GHz [23]
Figure 21 III-V compound semiconductors mobility and band gap[24]
With better features in terms of having a higher electron mobility compared to Si
electronic devices based on III-V materials developed rapidly This attracted attention in
many aspects especially in military radar application electronic warfare system missile
guidance control electronic for smart warfare system and secure communication To be
specific those demands were fulfilled through the application of microwave mixer and
detectors [25] which were achieved based on Schottky barrier diodes and FETs
However these applications remained largely as niche markets for use only in military
and exotic scientific projects until 1980 In addition to the microwave industry two
important diodes that played a large role in very high-frequency power source namely
the Gunn diode and the Impact Avalanche and Transit Time (IMPATT) diode which
were discovered in the 1960s[26]
100
1000
10000
100000
0 05 1 15
Bu
lk M
ob
ility
(cm
2 V
-1 s
-1
BandGap (eV)
InS
b
InA
s
Ge
Ga
Sb
In
GaA
s
Si
GaA
s
InP
32
Furthermore the invention of Molecular Beam Epitaxy (MBE) growth technique at
the beginning of 1970s has enhanced the full potential of the III-V compound
semiconductors[27] This technique has led to the formation of a new class of materials
and heterojunction device with high-quality interfaces and accurate control of the
thickness during growth[28] The advancement of material engineering that tailored the
III-V compound semiconductor with MBE effect has been beneficial for both three-
terminal and two-terminal devices As a result of this more advanced devices in both
electronics and optics were developed such as quantum well (QW) laser Resonant
tunnelling diode (RTD) high electron mobility transistor (HEMT) and many more[29]
The aim was to achieve high-speed devices transporting data at high data rates and
robust devices These devices promised an excellent option to conventional transistor
(three terminal devices) in high-frequency systems especially in the terahertz (THz) or
Millimetre and sub-millimetre wave regions [30]
One of the promising diodes that received a lot of attention is the resonant
tunnelling diode (RTD) which was first described in 1974 by Chang [31] This device
which consists of a double barrier and one quantum well is the classical tunnelling diode
Due to its good symmetrical non-linearity in its current- voltage characteristic it can be
exploited for signal generation and detection However the main focus of RTD to date
has been in the generation of continuous wave (CW) ultra-high frequency and to a lesser
extent in detection Therefore other tunnelling based diodes were developed specifically
for detection purposes which are the main foci of this work The PDB and ASPAT
diodes are the workhorse candidates for detection purposes Most of these are built based
on group III-V compound semiconductors [32]
Unlike the Very Large Scale Integration (VLSI) market ie CMOS for personal
computer (PCs) the RF electronic device for civilian application reached the consumer
market only in the late 1980s through satellite television with operating frequencies
around 12GHz [19] Since then many RF application have been deployed on the mass
market depending on their operating frequency such as 09GHz ndash 25GHz for wireless
communication 20GHz to 30GHz for satellite communication 77GHz for car radar
systems and above 90GHz for different sensor applications Utilising GaAs as the main
material RF devices have become the key underpinning components for modern
33
communication systems As a result in 1998 the volume production of mobile phones
was greater than that of PCs for the first time in history Presently production is being
made for devices like smartphones cellular phones mobile internet access and new
communication services and tablets
The development of the RF field is never ending More and more improvements are
being made especially through the design and fabrication of oscillators and detectors
which are mainly built based on group III-V compound semiconductors When RF
devices were used by the military (in the 1970s to 1980s) cost was not a concern
However after getting into civil application market (ie in the 1990s) the most frequent
issues highlighted were performance and cost[19]
The ability to generate or receive high operating frequencies with high power large
bandwidth and high sensitivity is an indicator for a good performance of RF devices
(depending on specific applications) For example the highest room temperature based
oscillator of up to 186 THz was achieved in thin well AlAs-InGaAs RTD by Professor
Masahiro Asada from Tokyo Institute of Technology [33] An excellent review on THz
sources can be found in [34] For ultra-high frequency detector and mixer applications
the two terminals RF device that is mostly used is the SBD In 1996 the highest cut off
frequency achieved by a mixer utilizing the SBD was about 5THz[35] and this has kept
increasing ever since The factor that motivates the development of THz devices is the
requirement to have a compact coherent source in the THz range Undoubtedly in the
future there will be very exciting times for enthusiasts of terahertz sources and receiver
as new generations of compact broadband and tuneable solid source device based on
advanced compound semiconductor are developed
23 The Concept of Heterostructures
A III-V compound semiconductor is mostly grown on a single semiconductor
substrate forming a layer called epitaxial heterojunction layer It is a starting point and
the key feature that brings the idea of realising the most advanced semiconductor
devices currently being developed and manufactured by combining several epitaxial
semiconductors [36-38] Heterojunctions have the capability of manipulating carrier
transport ie electron and holes transport in crystal separately unlike homojunctions
34
This has resulted in the successful development of new devices for high-speed and high-
frequency applications as well as optical sources and detectors [37] This section will
discuss lattice matched material pseudomorphic material hetero-junction band
discontinuities and quantum wells
231 Homojunctions Heterojunctions and Band Discontinuities
The term homo-junction refers to the interface between identical semiconductor
materials that have different polarity ie p-type or n-type but similar in energy gap This
phenomenon is usually applied in forming p-n junction diodes and can be understood by
referring to Figure 22 below
Figure 22 illustration of Homojunctions band structure material before (left) and after (right)
equilibrium
The materials A and B which have similar bandgap (Eg) and different dopant
types ie p-type and n-type will have their Fermi levels (Ef) closer to the valence band
(EV) and conduction band (EC) respectively before ldquothermal equilibriumrdquo Once
equilibrium is achieved Ef of both p-type and n-type will be aligned causing band
bending of EC and EV As a result a built-in electric field is introduced (via diffusion of
carriers) for both holes and electrons and forcing them to move in one direction
On the contrary a heterojunction occurs when the interface between two
semiconductor materials with different bandgap energy are brought together (ie large
energy band gap material combined with a low band gap one eg wide band gap AlAs
and narrow bandgap GaAs) This results in a steep band bending which leads to the
formation of energy band discontinuities at the junction as shown in Figure 23 In a
semiconductor heterojunction the most important parameter is the band gap energy
EC
EV
Ef
Eg
p-type E
g
n-type
EC
EV
Ef
Material A
p-type
n-type
Material B Material A Material B
35
associated with each material in the structure where the degree of discontinuity can be
utilised in varying the carriers transport properties as well as the quality of the junction
depending on the interest of the designer This leads to flexibility in tailoring device
characteristics leading to vastly improved performance of the device
Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium
Based on Figure 23 above Material A indicated with blue line is a large band
gap energy material and Material B highlighted with the red line is a low band gap
material EV represents the valence band EC the conduction band and Ef is the Fermi
level of the materials Alternatively the two materials band discontinuities are denoted
by ΔEC for the conduction band and ΔEV for the valence band χ and Eg represent the
electron affinity and band gap energy respectively
At some point where by the Fermi energy of both semiconductor materials are levelled
the structure would have reached its thermal equilibrium The band gap of materials A
and B have a discontinuity at the interface (ΔEg) of these two materials In general this
is given by
120549119864119892 = 119864119892119860 minus 119864119892
119861 (21)
Furthermore when thermal equilibrium is achieved ΔEg is then divided between
conduction band and valence band discontinuities (ΔEC and ΔEV respectively) at the
material A and B junction interfaces Their relationships can be expressed as
EC
A
EV
A
Ef
A
Eg
A
Material A Material B
χA
χ
B
ΔEC
ΔEV
Ef
B
E
g
B
EC
B
EV
B
EV
A
χA
ΔE
C
ΔEV
EC
A
Ef
EC
B
EV
B
χB
Material A Material B
Vacuum
Level Vacuum
Level
36
∆119864119862 = 120594119860 minus 120594119861 (22)
∆119864119881 = (119864119892119861 minus 119864119892
119860) minus (120594119860 minus 120594119861) (23)
∆119864119892 = 119864119892119860 minus 119864119892
119861 = ∆119864119862 + ∆119864119881 (24)
However these relationships which were introduced by Anderson can only offer an
approximation In practice the results are always different since dislocation and
interface strain occur at the junction Therefore precise control during epitaxial growth is
always required and growth technologies such as MBE are employed In due course the
band gap discontinuity can be further exploited by using different types of material
combination Examples are GaAsAl052Ga048As and In053Ga047As In052Al048As [39]
232 Lattice-Matched and Pseudomorphic Materials
As discussed earlier a heterojunction happens when any two different
semiconductor materials that have different bandgap are joined together At the atomic
level both materials often differ in lattice constant The easiest way to explain this is by
setting the formation of heterojunction which can be separated into two types lattice
matched and lattice mismatched (pseudomorphic)
2321 Lattice Matched Systems
To create discontinuities for use as a high-performance device the combination of
semiconductor materials is essential Selecting the appropriate materials that have
similar or very close lattice constants to combine is crucial to avoid disruption at the
atomic level heterojunction interface Figure 24 shows that the lattice constant of a
material A ie substrate (aS) and material B ie deposited over layer (aL) are identical
or very close and their surface atoms are perfectly matched This scenario is known as
lattice matching
37
Figure 24 Lattice Matching for both materials when aL=aS
As can be seen in Figure 25 while there are restricted binary materials available to
form good heterojunction interfaces it is possible to combine semiconductor materials in
binary ternary and quaternary forms to allow the formation of a variety of lattice-
matched heterojunction interfaces The examples of materials that have successfully
been alloyed are In053Ga047As In052Al048AsInP and GaAsAlxGa(1-x)As (x=0 to 1)
Even though the materials system hetero-junction of these materials has close lattice
constant value their band-gap will experience an abrupt variation
Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40]
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
38
The existence of binary ternary and quaternary semiconductors formed by alloying
semiconductors has expanded the opportunity for heterojunction formation in devices
The alloy semiconductor which is produced by the combinations of two semiconductors
A and B has a lattice constant that obeys Vegardrsquos Law as follows
119886(119886119897119897119900119910) = 119909119886119860 + (1 minus 119909)119886(119861) (25)
For the alloy the band gap normally follows the virtual crystal approximation
119864119892(119886119897119897119900119910) = 119909119864119892(119860) + (1 minus 119909)119864119892(119861) (26)
Table 21 shows the list of the semiconductor alloy band gap and lattice constant for
common binary and ternary for group III-V compound semiconductors[41]
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary compound
semiconductors a room temperature [41 42]
Alloy Lattice constant a(Aring) Band gap EgeV)
AlAs 5661 2239
AlSb 6136 1581
GaAs 5653 1424
GaN 3189 34
InAs 6058 0417
InP 5869 1344
Al052Ga048As 5657 2072
In053Ga047As 5868 0773
In052Al048As 5852 1543
39
2322 Pseudo-morphic Materials
The other scenario is when two different materials with different lattice constants
are brought into contact The observation can be made at the atomic level where the
atom will try to match each other as shown in Figure 26 below
Figure 26 Lattice mismatched material
In fact for both situations (ie lattice matched and lattice mismatched) the atom of
the material at the hetero-interface will change their position to maintain the geometry of
the lattice Due to distortion at this atomic level a strain is then induced at the hetero-
interface In order to form a good hetero-junction interface the strain must not exceed a
certain specific critical value which will cause crystal dislocations to occur The result of
crystal dislocation is generally bad as it will affect the carriers which will be
concentrated in the defect area thus degrading the carriersrsquo mobility This then makes
the overall function or performance of the device to become poor
Nowadays the Molecular Beam Epitaxial (MBE) technique is able to grow epitaxial
layers of mismatched semiconductor layers profile ie mismatched in their lattice
constant (aLneaS) The growth method works when the grown epitaxial layer assumes the
lattice parameters of the layer it is deposited on Nonetheless the layers must be kept
within a certain limit and the deposited layer must be thin enough to avoid defect or
dislocation formations This new layer known as a ldquopseudomorphicrdquo material will alter
its original crystal structure and physical properties
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
40
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and (b) tensile
strain [1]
Figure 27 shows material A in which the pseudomorphic materials can be related to
two situations compressive and tensile strain The compressive strain occurs when the
deposited layer has a larger lattice constant than the substrate (aL gtaS) while tensile strain
happens when the deposited layer has a smaller lattice constant than the substrate
(aLltaS) These leads to aL either to compress or stretch to fit aS respectively Note that
the pseudomorphic layers can only be grown to a certain critical thickness hc From
Figure 27 the strain between the substrate and the deposited epitaxial layer is given by
휀 =119886119871 minus 119886119878
119886119878 (27)
Where Ɛ is strain between two layers aL is lattice constant of the deposited layer and
aS is lattice constant of the substrate layer The concern in deposition of the over layer is
to avoid dislocation occurring at the interface if there is too much strain at the junction
The strain is naturally influenced by the thickness of the deposited layer and thus the
thickness of growth must be controlled below the critical thickness hc which is
expresses as
(b)
41
ℎ119888 =119886119904
2Ɛ
(28)
Moreover one needs to appreciate that even though the crystal structure and their
physical properties change the total energy within the unit cell is maintained This is
possible by distortion of the deposited layer in the direction perpendicular to the growth
direction while leading to lattice matching in the lateral plane Example of lattice
matched materials is GaAsAlAs and pseudomorphic material is In08Ga02AsInP
233 Quantum well and 2DEG
A typical application of heterojunction interface is one in which utilises ΔEC and ΔEV to
form barriers for electrons and holes One example of barriers that confines these
carriers is known as a Quantum Well (QW) A QW is a layered semiconductor usually
very thin ie about ~ 100 Aring thicknesses in which many quantum mechanical effects can
occur It is formed by a thin layer of a low bandgap energy semiconductor material eg
GaAs sandwiched between two similar large bandgap energy semiconductors eg AlAs
or AlGaAs The growth technique to achieve thin layers of QW is usually MBE The
benefit of this method is that it allows the formation of heterojunction with very thin
epitaxial layer
Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg GaAs (a)
Structure (b) energy band diagram and (c) Conduction band diagram when AlGaAs is n-doped[43]
42
The thickness of the layer that can be achieved can be as thin as the electron mean free
path (De Broglie wavelength) which is around 100 Aring to 300 Aring [44] The expression for
the De Broglie wavelength is given by
120582 = ℎ120588frasl (29)
Here h and ρ are Planckrsquos constant and momentum of the electron respectively Figure
28(b) illustrates a quantum well formation in abrupt semiconductor interfaces It can be
observed that the heterojunction boundary will experience discontinuities at the edges of
the conduction band and valence band with a quantum well generated for the carriers
(both electron and holes) The quantised energy sub-bands in the quantum well structure
in Figure 28(b) can be determined from [43]
119864 = 119864119899 + (
ℏ2
2119898lowast) (119896119909
2 + 1198961199102)
(210)
Where 119864119899 = (ℏ21205872
2119898lowast ) (119899
119871)2
and n is the energy level index that can be n=1 2 3hellip
The dopants in a semiconductor with large band gap layers may supply the
carrier to the quantum well and this occurs when the base or bottom of the quantum well
is lower than the Fermi Level and hence the high energy donors will go down to the
well therefore creating a Two-Dimensional Electron Gas (2DEG) In the 2DEG the
electrons and holes move freely in the quantum well in the plane perpendicular to the
growth direction however they are not capable of moving in the crystal growth
direction (confinement direction)[45 46] The 2DEG phenomena can be seen in Figure
28(c)
24 Metal-Semiconductor Contact
A semiconductor device is incomplete if there is no connection between the
semiconductors and the outside world A metal which is usually gold (Au) or gold
germanium (AuGe) is diffused into the semiconductor to allow for electrical connection
from the outside world to the semiconductor and vice versa The metal-semiconductor
contact can be either a Schottky contact or an Ohmic contact The Schottky contact is a
43
rectifying contact while the Ohmic contact is a contact that provides a low resistance
path between semiconductor and metal
241 Schottky Contact
The Schottky contact is basically a metal contact to the gate to enter a region or
channel in a transistor Figure 29 shows a schematic band diagram of a metal-
semiconductor contact before and after contact (Schottky-Mott concept)[47]
Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact
In Figure 29 the work function of the metal is represented by qm while the
semiconductor work function is qS The qχ is the energy difference of an electron
between the vacuum level and conduction band edge ie known as the electron affinity
and qVn is the difference between the conduction band and Fermi level in the
semiconductor EV EC Ef is the valence band energy conduction band energy and the
Fermi level respectively
The metal and semiconductor are brought together as showed in Figure 29(a)
both materials are at steady state However when the metal and semiconductors are in
contact as illustrated in Figure 29(b) the electrons that flow from the conduction band
in the semiconductor into the lower energy state of the metal will cause the Fermi level
to be aligned in thermal equilibrium Due to this process the positive charge donor is
trapped in the semiconductor interface hence forming a depletion region Xdep
Thereafter the upward bending of the energy in the semiconductor takes place On the
qχ(s)
Eg(s)
Vacuum Level
EV
EF(m)
E
F
EC
qϕ(m)
qϕ(s)
Metal Semiconductor
qVn
qϕB
qϕ(s)
qVbi
X
qχ(s)
Eg(s)
Vacuum Level
EV
EF
EC
qϕ(m)
Metal Semiconductor
Xdep
(a) (b)
44
other hand the negative charge (electron) will be accumulated within a narrow region in
the metal interface The existence of two different charges at the metal-semiconductor
boundary generates an electric field This leads to a potential barrier qB as seen by
electrons in the metal moving into the semiconductor and a built-in potential qVbi as
seen by electrons in the semiconductor trying to move into the metal
The built-in potential qVbi is defined as follows
119902119881119887119894 = 119902empty119861 minus 119902119881119899 (211)
The barrier height empty119861 in the ideal case is specified by the dissimilarity between a metal
work function empty119898 and electron affinity of the semiconductor
119902empty119861 = 119902empty119898 minus 119902120594 (212)
Referring to Eq (212) above the barrier height empty119861 rises linearly with the metalrsquos work
function empty119898 Nevertheless this is only in theory as the presence of localised surface
stated at the edges causes empty119861 to become unresponsive to the metal work function
Consequently Eq(211) is then reordered to match the difference in metal and
semiconductor work function Thus the new equation becomes
119902119881119887119894
= 119902(120601119898 minus 120601119904) (213)
A Schottky contact appears when a metal-semiconductor contact has a large
barrier height (B ge kT) and low doping concentration in the semiconductor (ND le NC) In
the case when the metal-semiconductor contact is under some bias eg reverse bias the
semiconductor will react to a positive bias according to the metal by a voltage V=-VR
This condition will affect the built-in potential and leads to increase from Vbi to
(Vbi+VR) thus increasing the barrier height empty119861 in the semiconductor as well
Consequently electrons are less able to flow from the semiconductor and cross into the
metal Therefore the current flow will be very small This phenomena is shown in
Figure 210(a)
45
Figure 210 Energy band diagram of Schottky contact on n-type material under (a) reverse and (b)
forward bias
As can be seen from Figure 210(b) when a forward bias is applied the semiconductor
is biased negatively with respect to the metal by a voltage V=Vf This will result in a
reduction in built-in potential from Vbi to Vbi-Vf The electrons in the semiconductor will
lower the barrier height and a lot of electrons will escape into the metal causing a large
current to flow Thus a large current flow in the forward direction compared to the
reverse direction Essentially this is the origin why the Schottky contact is named a
rectifying contact [48 49] For the metal side both forward and reverse biases applied
do not affect the barrier high empty119861 because there is no voltage drop there
In this system the electron and holes are transported by a phenomenon called
Thermionic Emission (TE) which happens when the semiconductor layer is lightly
doped Nd lt 1x1017119888119898minus3 The electron will only be thermionically emitted into the metal
when the energy is higher than the potential barrier[50] There is another phenomenon
called Thermionic Field Emission (TFE) which happens when the potential barrier
thickness is very thin (thin enough) to allow the electron to tunnel through the barrier
This will be discussed in the next section as this phenomenon leads to the formation of
an ohmic contact
(a) (b)
46
242 Ohmic Contact
Basically an ohmic contactrsquos purpose is to provide a low resistance path from
the semiconductor to the outside world It is different to a Schottky contact as it is a non-
rectifying contact and does not control the current flow the I-V characteristic of an
ohmic contact is linear in both forward and reverse directions (equality in current flow)
The ohmic contact also has a small voltage drop across it compared to the voltage drop
across the device
If a metal and semiconductor are bought together unavoidably a Schottky
contact will be formed Therefore to create an ohmic contact some techniques to reduce
barrier height and width of the depletion region must be used ie increase Nd In carrier
transport theory there are three mechanisms of carrier transport across the barrier
Firstly the Thermionic Emission (TE) which happens when the carries are excited to
overcome the barrier when the thermal energy is present Secondly the Thermionic
Field Emission (TFE) occurs when the electronholes have enough energy to tunnel
through an adequately thin barrier and some has overcome the low barrier at the top
Finally the Field Emission (FE) which results when carriers can tunnel through the
entire barrier The FE is the most favoured mechanism in the ohmic contact approach
[51]
From the three mechanisms above the current can be determined by the following
equations
1) Current in Thermionic emission (Figure 211(a))
exp (empty119861)
119896119879
(214)
2) Current in Thermionic field emission (Figure 211(b))
exp [
(empty119861)
11986400119888119900119905ℎ11986400
119896119879
] (215)
3) Current in Field Emission (Figure 211(c))
exp (empty119861)
11986400
(216)
47
Where k is the Boltzmann constant T is the temperature 11986400 is the tunnelling parameter
and is related to the doping concentration radic119873119863 The barrier height is denoted by empty119861
Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping concentration
ND (a) Low (b) Intermediate and (c) high
Figure 211 shows that the carrier transport mechanism is varied by the doping
concentration (ND) As can be seen from Figure 211(c) the doping concentration here is
the highest and influences the depletion region width Xdep to become smaller Therefore
Field Emission (FE) becomes dominant This FE method is the favourite method for
ohmic contact formation [51] and will be utilised in the fabrication carried out in this
work
In fabricating practical devices the ohmic contact is often split into two types
alloyed and Non-Alloyed The difference between the two is that the alloyed type is used
when the semiconductor is doped with a low doping concentration ie less than
1x1018119888119898minus3 while the Non-Alloyed is designed for heavily doped semiconductors with
more than1 times 1019119888119898minus3 doping
The alloyed ohmic contact requires thermal annealing to have a good performance
for electron transport In multi-layer metals one of the metals has the role of donor or
acceptor which is used to increase the doping concentration of the semiconductor If a
temperature anneals eg 420˚ Celsius is applied the metal will diffuse into the
semiconductor and carry the dopant into the semiconductor Therefore a heavily doped
region will be formed and the depletion width becomes narrow establishing the ohmic
contact The key example of this is the usage of the Gold-Germanium-Nickel (Au-Ge-
Ni) alloy where the Ge is the n-type dopant [52] which diffuses into the semiconductor
(a) (b) (c)
48
and perform atom replacement in the semiconductor ie in GaAs it replaces Ga On the
other hand the Non-Alloyed does not require any thermal annealing as it already has a
very high doping concentration and will automatically reduce the depletion region width
The Non-Alloyed ohmic contact has some advantages such as reproducible contact
reduced processing time and good uniformity [53]
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work
In this section some historical background of the Asymmetrical Spacer-layer
Tunnel (ASPAT) diode is given Since this is the first thesis reporting about this new
device it is worth to mention some historical background about this tunnelling diode
The ASPAT was first proposed by a group of scientists from General Electrical
Company (GEC) in 1990[16] The works led by Richard T Syme and assisted by
Michael JKelly Angus Condie and Ian Dale initiated the idea of launching a new type
of tunnel diode The idea managed to attract the interest of many parties following the
development of resonant tunnelling diode (RTD) which earlier had shown a promising
weak temperature dependence [54] However the interest in RTD is mainly limited to
microwavesub-millimetre wave generation For THz detection the requirement is to
have a significantly asymmetric IV characteristic Given this the ASPAT which has
only a single energy barrier and most importantly weak temperature dependence and
large dynamic range would be a promising candidate for this application
The development of ASPAT is a kind of reverse engineering since it was built
purposely to replace the earliest receiver diode especially the Schottky Barrier Diode
(SBD) which has strong dependence on operating temperature [55] From the time when
it was first revealed a lot of works have been done to realise this most sophisticated
tunnel diode The first attempt which was reported in [56] was meant to gather some
insights into the device by using the well-known Schrodinger and Poissonrsquos equations
for simulation The second attempt on the other hand was directed to physically grow
and fabricate the device Here the real problem occurs At the first stage of qualifying
this device it was found not to be manufacturable Since then a new tunnel diode
structure based on GaAsAlAs materials system was built by both MBE and MOCVD
Its microwave performance was then tested at 94GHz [18] The same paper also
49
reported performance comparisons between ASPAT and another microwave diode ie
Germanium Backward Diode (GBD) PDB and SBD
Work on these devices stopped due to the inability to commercialise the ASPAT
and other tunnel based devices [57-60] The problems associated with low-cost
manufacture of tunnel diodes are due to firstly the thickness of the AlAs barrier layer
the dependence of tunnelling probability (electron) through a single barrier is
exponential and varies by a factor of more than 350 for one monolayer change in the
AlAs barrier thickness[61] The tunnelling of the electron through a barrier is
proportional to the current through a barrier as a function of a bias across the AlAs
barrier[62] Secondly the bandgap which is predominantly happens to be a ternary alloy
with relative composition ie AlxGa1-xAs Here the x can vary the bandgap in the
semiconductor layer For the ASPAT a 1 change in x results in a 30 change in the
current[62] To design an ASPAT for microwave and THz applications the designer
often allows at most plusmn10 variation of the absolute current through a specific diode at a
pre-identified bias This implies that within a wafer the uniformity that the ASPAT must
achieve is less than plusmn01 monolayers while between wafer to wafer the reproducibility
in barrier thickness in average must be identically controlled[63] This explains why at
the qualification stage of investigating ASPAT there was a need to focus on
GaAsAlAs-based material to diminish further errors because of the change in x This
type of work on ASPATs has been carried out by other co-workers at Manchester and
Cambridge
Thereafter the work then focused on repeatability and manufacturability tests
These result in many attempts being carried but failed with unacceptable between wafer
to wafer reproducibility [61 64] The development of reproducibility and repeatability of
the ASPAT was pursued for over 10 years until precise control of the growth of the
thickness AlAs layer was finally achieved using MBE[65] [66 67] This achievement is
confirmed by a current density produced which varied by less than plusmn30 indicating that
the reproducibility of AlAs barrier of the order of plusmn 02 monolayers A final step to
achieve the level control for the ASPATrsquos AlAs barrier thickness was carried out and
resulted in a 1 standard deviation of the IV characteristics for both within a wafer and
different wafer (2 inches wafer size)[17] In the early stage of this work some
50
repeatability and manufacturability test was also carried out Once this vital step is
accomplished further investigation on the ASPAT was made most recently and which
will be covered in this thesis ie temperature independence[68] and new ASPAT
types[69] characterisation to achieve smaller device RF measurement and development
of THz detectors The material systems that have been investigated so far are
GaAsAlAs and InGaAsAlAs both in the ManchesterCambridge group
Recently the ASPAT was commercialised by Linwave Technology as a wideband
zero-bias detector diode This was done in April 2016 Although it is now on the market
the ASPAT remains immature in term of research and development A lot of work is still
required to enhance the device ie working at the sub-millimetre wave using ternary
material etc
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics
The basic building block of the ASPAT diode is based on heterojunction of three
multilayer semiconductor structures which have two different band gaps The structure
comprises a thin layer of wider-gap semiconductor sandwiched between two
semiconductors with narrower-gap forming a tunnel barrier The basic principle of the
ASPAT device is based on the exploitation of quantum mechanics theory using
heterojunctions interface According to quantum mechanics theory moving particles
(electrons) with less energy than the barrier height have a probability of appearing on the
other side of the barrier by a tunneling through it This can be achieved in conditions
where the barrier must be very thin (~ 10 monolayer ) This is in contrast to classical
physics where a particle must have kinetic energy at least slightly greater than the
potential barrier height in order to overcome the barrier otherwise the probability of the
particle to appear on the side of the barrier is zero
Since the ASPAT diode operation is based on tunnelling through a barrier one
needs to know that the tunnelling mechanisms can be classified into two types[44]
intraband and interband The latter is described as tunnelling that occurs from
conduction band to valence band (electron) and valence band to conduction band (holes)
This normally happens in bipolar device ie p-n junction diode which has n-type and p-
type doped regions On the other hand intraband refers to tunnelling which occurs when
51
electron tunnel from the conduction band of a semiconductor to the conduction band of
its neighbouring semiconductor The same thing happens to the holes in the valence
band The device with this type of tunnelling is normally a unipolar device which is
either p-type or n-type doped The ASPAT diode can be considered as a device that is
based on intraband tunnelling mechanism Therefore the focus will be entirely based on
its principles
261 Principle of Quantum Tunneling
Generally all tunneling diodes obey the concept of quantum mechanical
tunneling Quantum mechanical tunneling is a phenomenon where a particle is able to go
through an energy barrier higher than the kinetic energy of the particle and if it is thin
enough compared to the de Broglie electron wavelength (λ) If the electron wave is
greater than the barrier the probability of the wave to occur at both side of the barrier is
higher
Figure 212 Classical view of whether an electron is can surmount a barrier or not Quantum
mechanical view allows an electron to tunnel through a barrier The probability (blue) is related to
the barrier thickness
For the case of classical physics (Figure 212(a)) the particles can be confined by
energy barriers of a semiconductor if their kinetic energy is less than the barrier energy
The particles thus require higher kinetic to escape to other states this phenomenon is
called thermal emission In quantum mechanics (Figure 212(b)) the particle is
described in two ways as a wave and as a particle If the particle moves like a wave it
will carry all the waversquos properties Therefore it will not brusquely end up at the
En
erg
y
(a) Classical view (b) Quantum mechanical view
En
erg
y
En
erg
y
52
boundary of the energy barrier Hence when the particles collide with the barrier
(incidence) there will be a probability of penetrating the barrier if the barrier is thin
enough and has a finite height For thicker barrier the probability of a wave that can be
found on the other side of the barrier is very small However the possibility of the
electron wave to appear on the other side of the barrier is increased by thinning the
barrier The potential barrier of semiconductor material technology can be determined by
using Homojunctions structures with different doping profile This will result in a
difference in band alignment and multilayer heterojunction structure (different
semiconductors have different band gap) which includes semiconductors insulators and
conductors (metals)
The easiest way to explain the phenomenon is by considering a potential barrier
Epot(x) with barrier height E0 energy bigger than the total energy E as shown in Figure
213 the potential energy occurs in a finite space between 0ltxlta and is 0 outside
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave function[70]
The electron outside the region of the potential barrier (xlt0 and xgta) is free to
move The effective mass of the electron is different inside and outside of the barrier in
real tunneling devices when implemented using semiconductor heterostructures The
quantum mechanical equations predict the wave nature of matter which states that matter
unveils wavelike properties under some conditions and particle-like properties under
other conditions The wavelike properties as described by the Schrodinger Formula of
E0 Transmitted Ψ = 119862119890minus119894119896119909
Incident Ψ = 119860119890119894119896119909
Reflected Ψ = 119861119890minus119894119896119909 Ψ = 119863119890minus119894119896119909
0 a
E
x
V(x
)
53
quantum mechanics represent a particle penetrating through a potential barrier most
likely as an evanescent wave coupling of electromagnetic waves[44]
To start the calculation of the tunnelling probability the Schrodinger equation is given
by
119894ℏ
120597
120597119905Ψ(119903 119905) = ΨΗ(r t)
(217)
Where ℏ is Planckrsquos constant (662606957 times 10119890minus341198982119896119892119904
2120587frasl ) Ψ(119903 119905)is the wave
function at position r and time t Η is the Hamiltonian operator given by
Η = minus
ℏ2
2119898nabla2 + 119881(119903 119905)
(218)
Where 119881(119903 119905)is the potential energy which is dependent on space and time 119881(119903 119905) is
considered zero for a particle traveling in free space without any potentials The plane
wave with vector r and t is given by
Ψ(119903 119905) = 119890119894(119896119903minus120596119905) (219)
This equation satisfies Eq (217) above under the condition where the particle is
travelling in free space without potential k is the wave vector which is equivalent
to2120587120582frasl and the angular frequency 120596 is 2120587 multiplied by the frequency
In the case of tunneling through a potential barrier the method of separation of
variables is used to simplify the problem as in the equation below
Ψ(119903 119905) = 119877(119903)119879(119905) (220)
It is assumed that the problem above is divided into time-dependent and time-
independent parts 119877(119903) is the spatial component and 119879(119905) is the time-based component
of the wave function The time dependent problem as shown above in the Schroumldinger
Equation (1) can easily be solved by filling up all the finite parameters The solution of
54
the time-independent part gives the tunneling probability For the one-dimensional (1D)
time-independent Schroumldinger equation[44]
119864120595(119909) = minus
ℏ2
2119898
1198892
1198891199092120595(119909) + 119881(119909)120595(119909)
(221)
E is the total energy and 120595(119909)is the spatial component of the wave function along the x
axis The combination to the wave function is given by
120595(119903 119905) = 120595(119903)119890minus(
119894119864119905ℏ
)
(222)
The time-independent plane wave solution of 120595 = 119890119894119896119909 satisfies the equation (221) for
any constant potential V0 in space Plugging in the wave solution yields the condition
that
119896 = radic2119898lowast(119864 minus 1198810)
ℏ2
(223)
Referring to Figure 213 also the barrier with exact rectangular shape with height E0 and
width W the solution of the wave functions and tunneling probability can be extracted
by using the below equation [44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2= [1 +
11986402 sin ℎ2 (119896119882)
4119864(1198640 minus 119864)]minus1 asymp
16119864(1198640 minus 119864)
11986402 exp(minus2radic
2119898lowast(1198640 minus 119864)
ℎ2119882)
(224)
For more complex barrier shape Wentzel-Kramers-Brillouin has simplified the
Schrodinger equation for tunneling probability of carrier which becomes[44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2asymp 119890minus2int |119896(119886)|119889119886
1198860 asymp 119890
minus2int radic2119898lowast
ℎ2 [119880(119886)minus119864]1198891198861198860
(225)
55
This means that the incident electron has a finite probability T of tunneling
through the potential barrier and this leads to the concept of tunneling probability as well
as a tunnelling current Therefore this becomes the basis of tunneling phenomena and
thus all devices which are related to tunneling can be modelled and analysed based on
this basic example The tunneling phenomenon is a majority-carrier effect and the
tunneling time is set by the quantum transition probability per unit time (which is on the
order of picoseconds) rather than the transit time concept [44 71] This enables the
tunneling devices to work at a much higher switching speed They can also be used in
high-frequency applications such as microwave circuit and high-speed oscillators
262 ASPAT Structural Parameters of GaAsAlAs materials System
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in this study
Conduction band profile
56
The core materials that make up the ASPAT diode in this work is based on
heterostructure of group III-V compound semiconductors Such materials are chosen due
their mature excellent properties and their band gap which can be tailored to fit the
desired design as well as to improve the carrier mobility In this work the primary layers
that form an ASPAT diode are very thin pure Aluminium Arsenic (AlAs) of thickness
ten monolayers buried in between dissimilar thickness of pure Gallium Arsenic (GaAs)
layers as can be seen in the red circle in Figure 214 above These two GaAs layers are
known as spacer layer which normally have a ratio of 401 or 201 in thickness The
asymmetrical spacers layer and the thin barrier in such arrangement lead to an
asymmetric current-voltage characteristics as proposed firstly by Syme and Kelly[15]
To examine and investigate this GaAsAlAs ASPAT structure in term of electrical and
RF characteristics the device have been grown according to Table 22 below
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work
Material Doping (cmminus3) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018 3000 142
Emitter GaAs (Si) 1times1017 400 142
Spacer GaAs Undoped 50 142
Barrier AlAs Undoped 28 283
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017 400 142
Ohmic Layer GaAs (Si) 4times1018 4500 142
Substrate GaAs - 650 microm 142
The arrangement of the multi-layers that form a lattice matched GaAsAlAs ASPAT
diode can be transformed into band structure profile view for easy understanding The
conduction band profile at equilibrium is as sketched in Figure 214 As can be seen in
the Figure 214 the ASPAT diode is generally a heterojunction multilayer structure
tunnelling diode
57
Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27]
The generic structure of ASPAT diode which is shown in Figure 215 above with a
schematic band structure comprises the following (starting from the top)
(1) A thick layer of heavily doped n++
about 4e+18cm-3
of GaAs with a thickness of
approximately 300nm
(2) An intermediate layer of lightly doped n-type about 1e+17cm-3
of GaAs with
thickness of approximately 40nm
(3) A spacer layer not intentionally doped (NID) GaAs with thickness of approximately
5nm
(4) An ultra-thin layer of NID AlAs with thickness of approximately 28nm
(5) A spacer layer of NID GaAs with thickness of approximately 200nm
(6) An intermediate layer of lightly doped n+ ~1e+17
GaAs with thickness of
approximately 40nm
(7) A thick layer of heavily doped n+ about 4e+18 of GaAs with a thickness of
approximately 750nm
Each layer has its own role For instance layer (1) and (7) are used as ohmic
contacts via connection to a AuGeNiAu metal stack This explains why they are
purposely heavily doped (gt 1018
cm-3
) for better low resistance ohmic contacts Two
intermediate layers (layers 2 and 6) are used to prevent the carrier in the contact layers
from diffusing into the undoped layers The two unequal length spacer layers with ratio
58
1198971 1198972 of about 401 are used as voltage arms to yield an asymmetric current-voltage
characteristic The asymmetry means that after a positive bias is applied from the long
spacer region an accumulation layer is formed and it is deeper than that formed by the
negative bias The thin layer positioned in the middle (Layer 4) is the tunneling barrier
The performance of a single barrier ASPAT diode can be optimised depending on
the applications by appropriate selection of the material system so that the band gap and
barrier height of such material can be modified Furthermore the mobility of electron
and doping concentration of the contacts region can be tuned The parameters to tune
during the growth for instant growth interrupt time and growth temperature will also
affect the performance of this diode The key layers that will affect the performance are
the barrier thickness and the two spacer layers enclosing it The study has shown that a
one monolayer change in thickness results in 300 change in in tunneling current for a
fixed voltage point[65]
The following discussions account for the effect of the main structure of the ASPAT
which is related to their performance
2621 Barrier Thickness and height
The probability of an electron tunnelling through a barrier depends exponentially on
the width and height of the barrier as well as the energy that is incident on the barrier[72
73] All these will affect the I-V characteristic of the ASPAT diode The tunnel current is
obtained by summing over all incidents electrons energies with tunnelling probabilities
through the barrier The tunnelling varies approximately as[74]
119879 prop 119890minus120581119889 (226)
Where d is the barrier thickness and κ is defined by the expression below
120581 =
radic2119898lowast(1198810 minus 119864)2
ℏfrasl
(227)
From textbook the tunnelling probability is given by
119879(119864) = 412058121198702
[(1205812 + 1198702)2119904119894119899ℎ2119870119897 + 412058121198702]frasl (228)
Where K is expressed as
59
119870 = radic2119898lowast119864
ℏfrasl (229)
Where ℏ represents the reduced Planckrsquos constant (h2π) E and m are the electron
energy and effective mass respectively Thus by inputting appropriate value into these
equations one finds that reducing the barrier thickness by one monolayer increases the
tunnelling probability by a factor of nearly three for every electron that tunnels through
the barrier As a result the current will also increase Further it indicates that the
tunnelling strongly depends upon barrier thickness and height By contrast the current
does not strongly depend on temperature
2622 Spacer Thickness
The reason for having two dissimilar undoped spacer lengths is mainly to avoid
diffusion of dopant to the barrier and subsequent layers during growth but in the case of
the ASPAT diode the spacer can also act as a voltage arm Varying the thick spacer
layer (1198971) results in the reverse current decreasing as the layer thickness increases and
varying the thin spacer layer (1198972) will affect the forward current which increases as the
thickness reduces To obtain appropriate asymmetrical I-V characteristics one needs to
maintain an adequate ratio between these two spacer thicknesses While a too thin
1198971 results in high leakage current at reverse bias a too thick 1198972 results in low forward
current One also needs to keep it thick enough to prevent carrier diffusion
These two spacers must be kept undoped or very low doped to allow the electron
moving in the electron mean free path region as it is clear from ionised donors Under
large forward bias an accumulation layer is formed between the spacer and barrier
segment and it is more noticeable compared to the accumulation layer that is formed if a
negative bias is applied
60
Figure 216 Conduction band diagram showing band bending and 2DEG formation at the L1
spacer
Consequently a triangular well is formed which creates an emitter 2D electron gas
(2DEG) population The electrons in this 2DEG occupy the quasi-bound states which
mean high excitation energy thus allowing the electron to tunnel through the barrier as
depicted in Figure 216
In term of RF performance it is important to highlight that a thicker spacer layer
will affect the depletion region which gets wider and thus will reduce the junction
capacitance of the device as per the following expression
119862 = 휀0휀119903
119860
119889
(230)
Where A is the area of the device d is the thickness of the main device structure which
consists of spacers barrier and well layers 휀0 is the permittivity of free space and the
relative permittivity of the spacer material is denoted by εr However the intrinsic delay
time will also increase and hence degrade the device high frequency performance
Therefore optimisation through spacer thickness requires trade-off between reducing
leakage current at reverse bias and degrading device junction capacitance
GaAs
GaAs
AlAs
2DEG
Γ
X
61
263 ASPAT Electrical Parameters
The classical approach in determining the current flow through an ASPAT diode is
by solving the Schrodinger and Poison equations Prior work had been done by Syme et
al in 1991 Due to the fact that AlAs barrier is very thin tunnelling is assumed to occur
at the Gamma valley ie AlAs bandgap= 283eV (rather than X valley)[18 75] and only
from accumulation layer (2DEG)[59] Here the DC characteristic of the ASPAT diode
can be calculated by solving Schroumldinger equation with the position vector represented
by z (in this case) Thus the equation is expressed as
minus
ћ2
2nabla
1
119898lowast(119911)nabla120569 + |119890|120593(119911)120569 = 119864120569(119911)
(231)
Supposing the current is uniform across x and y planes then this can be simplified to one
dimension Therefore the 1 D Schroumldinger equations becomes
minusћ2
2119898lowast
1198892
1198891199112120595 + |119890|(120595 minus ∆120595) = 119864119911120595
(232)
Where
120595 =
120569
exp (119894119896119911119911)
(233)
where ∆120595 is the correction term which reduces the effective barrier height The
Schroumldinger equation is solved using different values for Ez thus the quantum
mechanical current density in the z-direction is now expressed as[15]
119895119911 =
minus|119890|ћ
2119898lowast(120595lowast
119889120595
119889119911minus 120595
119889120595lowast
119889119911 )
(234)
It is different for a heavily doped contact which can describe as below the envelope
functions in the left and right contacts respectively can be described by plane wave
120595119897 = exp(119894119896119897119911) + 119877 exp(minus119894119896119897119911) (235)
120595119903 = 119879119890119909119901[119894119896119903(119911 minus 120580119873)] (236)
62
In this case the left contact covers the region zlt0 while the right contact covers the
regions zgt 120580119873 Equations (35 and 36) are then inserted into Eq (34) to form the
following expression
119895119911 =
|119890|ћ1198961
119898lowast(1 minus |119877|2) =
|119890|ћ1198961
119898lowast|119879|2
(237)
Where R (Ez) and T (Ez) are the complex reflection and transmission coefficients
respectively and they are solved by using the transfer matrix method This method has
been described in reference [56] The next step is to integrate the current in the z-
direction 119895119911 for all possible Ez values Thus the expression for the current density
becomes
119895119911 =|119890|119898lowast119896119861119879
2120587ћ2int(1 minus |119877|2)
infin
0
119897119899 |1 + exp (
119864119891 minus 119864119911
119896119861119879)
1 + exp (119864119891 minus 119881|119890| minus 119864119911
119896119861119879
|
(238)
The equations above are used to calculate the current density approximation from
the ASPAT main structure (two spacer layers and one barrier) only and based on
intraband tunnelling from the conduction band profile For real fabricated structure the
calculation must take into account both intrinsic and extrinsic elements of the diode
While the latter is mostly related to the pad and probe that is used to extract the I-V
characteristic the first element mostly comes from the epitaxial layer of the ASPAT
diode itself The ASPAT I-V characteristic is shown in Figure 217 which clearly
indicates nonlinear characteristics and thus can be used for detection applications
63
Figure 217 I-V characteristics of a fabricated ASPAT diode
2631 Intrinsic Elements of the ASPAT diode
In order to extract the intrinsic electrical characteristic of the ASPAT diode a
generic structure as shown in Figure 218 is essential Two main sources of contribution
to the electrical characteristics are the interfaces of each layer and properties of the
materials themselves
Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
64
The electrical current flowing from the top contact to the bottom contact will go
through each epitaxial layer producing a close loop Each junction interface limits the
current flow and sum up the total resistance resulting in what is known as the diode
series resistance (Rs) In the ASPAT main structure there is a junction capacitance (Cj)
due to the undoped regions surrounded by heavily doped contacts thus acting as a
parallel plate capacitor The fully depleted capacitance (Cj) of the diode can be
expressed as in Eq (230)
2632 Series resistance of the ASPAT diode
The total series resistance (Rs) of an ASPAT diode can be calculated based on the
finished fabricated diode structure In general Rs depends on three contributors namely
the non-uniformities in the contact metallization the un-depleted epitaxial layer (total
thickness) on both side of the heterostructures and the resistance caused by the
spreading current from the Mesa into the much wider second contact layer ie doped
substrate or 2nd
ohmic layer[76] In fact the contribution toward building up the total Rs
solely depends on how the structure is designed In this work two types of structures
were deployed namely lateral structures and vertical structures These will be described
in the next subsection
For both types of structures the series resistance (Rs) of the ASPAT diode consists
of aspecific Ohmic contact resistance (ρcA) contact epitaxial layer resistance (Repi-
Layers) and spreading resistance (Rspr)[33 77] where Rspr is influenced by the type of
structure The specific contact resistance is obtained from Transmission Line
Measurements (TLM) of the sample The theory of the TLM will be discussed in detail
in the next section The expression for the specific contact resistance is
120588119888 = 119877119888119871119879119908sinh119889
119871119879frasl
cosh 119889119871119879
frasl
(239)
Here Rc is the contact resistance LT is the transfer length (effective length) w is the
contact pad width and d is the length of the contact pad
65
Repi-Layer is the sum of all doped layers that sandwich the main ASPAT device For
each doped layer the resistance is given by
119877119890119901119894minus119897119886119910119890119903 = 120588
119871
119860
(240)
Where ρ is the resistivity which is given by 120588 = 1
120583119899119902119873119863 L is the epitaxial layer thickness
in cm A is the device area (emitter size) micron denotes the mobility of the electron q is the
electron charge and ND is the donor concentration The spreading resistance depends on
the structure design of the device This will be elaborated in detail in the following
section
26321 Vertical structure (doped Substrate)
The XMBE307 structures were grown on n+ GaAs substrate to provide the
simplest fabrication process The cross section of the finished single diode can be seen in
Figure 219 below
Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b and h are not
drawn to scale
66
At low frequency and in a mesa that is etched into a doped substrate material the
spreading resistance can be approximated by[76]
119877119904119901119903 =120588119904
2119889
(241)
Where ρs is the substrate resistivity and d is the ASPAT diode mesa length
However the spreading resistance is increased at high enough frequencies as the skin
depth (δ) in the substrate is much lower than the effective mesa length (d) of the diode
A new spreading resistance is then calculated also based on the assumption that the skin
depth is much lower than the chip thickness (h) but much larger than the mesa length
Thus the spreading resistance at high frequency is given by
119877119904119901119903(119891) =
120588119904
120587120575[05 ln (
119887
119889) +
ℎ
119887]
(242)
Where the skin depth (δ) is taken from standard planar formula and can be expressed as
120575 = [
2120588
(120583120596)]
12frasl
(243)
Where micro is the permeability and ω is the angular frequency During DC measurement
this type of structure requires having good suction on the stage for a good contact
However for small die (15mm times15mm) the suction sometimes is not strong enough to
provide a very good adhesion to the sample Therefore another type of ASPAT diode is
deployed which is based on the lateral structure by utilising semi-insulating substrate
and both contacts are connected to probes
67
26322 Lateral structure (Semi-insulating Substrate)
Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304) The dimensions
are not drawn to scale
In order to obtain accurate measurement results so as to avoid contact errors to the
substrate between stage and Device Under Test (DUT) a lateral structure as shown in
Figure 220 above is deployed This type of design offers many advantages ie it
provides a path for on-wafer RF measurement However the proper design has to take
into account the increase in RS due to improper attention to the spreading resistance
This spreading resistance is different from the vertical structure that was discussed
above In this case it is mainly caused by a gap at the bottom contact The gap in the
horizontal direction between epitaxial layer and metal at bottom contact is denoted as D
gap in in Figure 220 Therefore Rspr for the lateral design can be expressed as [77]
119877119904119901119903 =
1
120587120590119889119866119886119860119904ln (
119886
119886119898119890119904119886)
(244)
Where σ is the conductivity between two coaxial half-cylindrical electrodes with inner
(amesa) and outer (a) rectangular length or bottom ohmic layer which is given by (σ =1
ρ) a d and amesa are the length and thickness indicated in Figure 220 above Noticeably
68
the D gap will have direct effect on the outer length (a) of the device which is also
proportional to Rspr For high-frequency operation where the skin depth is less than
d(GaAs) σ becomes
120590(120596) =
120590(0)
[1 + (120596120591119903119890119897)2]
(245)
Where τrel =microme and micro m as well as e are the mobility effective mass and electron
charge respectively It is recommended that for high-frequency applications the device
series resistance must be as low as possible
Hence for both type of structure the ASPAT series resistance is calculated based on
all the above-stated resistances and these are set by
119877119904 =120588119862
119860+ 119877119890119901119894minus119897119886119910119890119903119904 + 119877119904119901119903
(246)
The total RS can be decreased by increasing the emitter area of the diode However a
large device will not able to reach millimetre and submillimeter wave region (THz) as
the capacitance will also increase (Eq 230) Therefore both parameters will have a
trade-off between them to be able to work at ultra-high frequencies
27 Characterization of Ohmic Contacts
The semiconductor Ohmic contact can be characterised using techniques that will
be described in the following section First is the Cox-Strack technique which is
specially designed to characterise bulk type semiconductor (thick) contact resistance on
two opposite sides The detailed description of this technique can be found in [78]
Second is a technique called Four Point Probe This technique was developed in 1954 by
Valdes etel [79] to characterise semiconductor resistivity It can also be used to
characterise the contact resistance for planar type devices As this research does not
cover this method the details of the measurement can be referred to [80] Finally the
most common method which is also extensively used in this research is the standard
Transmission Line Measurement (TLM) The details of this method will be explained in
the next section There are simplified versions of the TLM method which require just
one lithography step but are nevertheless very powerful in characterising and optimising
the contact resistance known as Circular Transmission Line Measurement (CTLM)[81
69
82] However in this research this is not to be covered as the standard TLM is already
adequate for planar type devices
271 Transmission Line Measurement (TLM)
The formation of metal and semiconductor interfaces will create a contact that
becomes very important for the characterisations of any fabricated device Additionally
it enables the quality of certain process flow to be determined This interface must be
evaluated by a technique known as the Transmission Line Measurement (TLM) TLM
which was first introduced by Murrmann and Widmand [83] in 1969 underwent some
refinements by Berger [84] in 1971 The theory of the TLM can be described by
constructing a TLM structure which comprises a set of metals contact pads placed in
series on a highly doped semiconductor layer as depicted in Figure 221 The structure is
designed like a series of the islands to permit current flow in parallel to the contact pads
[80] which is a direction defined by etched patterns Each contact metal pad behaves
like a MESA which has a thickness (t) and width (W) The distance between each metal
contact pads is defined by d1 the gap between two neighbouring contact pads which are
beneath each contact pad is defined as effective length LT This will allow current flow
in and out of the subsequent neighbouring metal pad The resistance elements that will
be extracted are RA and RB which sit under the contact and in between two metal pads
These two elements represent the sheet resistance under the metal contact pad area and a
sheet resistance of the material between two metal pads
Figure 221 A simple TLM structure with effective length and sheet resistance underneath
t L
T
LT
RA R
A R
B
dn
Probe Probe
Metal Pad
GaAs
MESA
70
The basic relationship of resistance R with respect to the size of the metal contact
or in the standard transmission line can be expressed as [44]
119877 = 120588
119871
119860= 120588
119871
119905 times 119882=
120588
119905times
119871
119882= 119877119904ℎ
119871
119882
(247)
Where ρ is the materialrsquos resistivity L is the length t is the thickness W is the width
Rsh is the sheet resistance and A is the cross-sectional area of the transmission line The
unit for ρ and Rsh are Ωm and Ωm2 respectively
The total resistance RT of this structure can be taken from the sum of the two
neighbouring padrsquos resistance RA and RB In order to relate with Eq (247) above this
RT will be substituted into Eq(247) to become
119877119879 = 2119877119860 + 119877119861 = 2119877119904ℎ119860
119871119879
119882+ 119877119904ℎ119861
119889119899
119882
(248)
As suggested in [85] RshA and RshB are assumed to be identical Therefore Eq(248)
can be reorganised into specific contact resistance RC and semiconductor sheet
resistance Rsh above as 119877119862 = 119877119904ℎ119860119871119879
119882 the new equation is then
119877119879 = 2119877119862 + 119877119904ℎ119861
119889119899
119882
(249)
The common practice throughout this research is to design a TLM structure that
has a ladder structure consisting of 10 metal pads with each one measuring to a size of
100microm width and 50microm length and the space between the first and second metal pad
5microm The gap is increased after the second metal pad by a further 5microm until ten metal
pads are completed produce a separation between the ninth and tenth pad of 45microm The
TLM ladder structure as depicted in Figure 222 is supplied by a constant current of
1mA at the very left and right metal contacts by two probes This allows the extraction
of RC (Ωmm) and Rsh (Ω) instantly from such structure The potential difference
between the two adjacent metal pads is measured by another two probes and the reading
of a voltmeter is recorded The total resistance is obtained by using Ohm law where
voltage is divided by current (VI) Another voltage reading is taken for the next two
neighbouring metal pads until the largest gap is reached The readings of (conversion
71
VI) which result in the corresponding resistance RT are then plotted against spacing and
the result can be seen in the graph in Figure 223
Figure 222 Top view of TLM ladder structure use in this work
Additionally in the measurement the voltmeter used in work has a very high resistance
Otherwise there will be leakage of current occurring through the probes and cables
Therefore the parasitic resistance of the cable or connector and the probe contact can be
ignored The key parameters that can be extracted from the graph will be discussed in
the next paragraph
Figure 223 Typical plot of resistance versus TLM spacing
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50Res
ista
nce
Rn (
Oh
ms)
TLM Spacing dn (um)
LT
d1 d
2 d
3 d
n
I (1mA)
V
V
LT
ME
SA
Su
bst
rate
72
The straight-line graph plotted in Figure 223 can be referred to Eq (249) and
this must be done by assuming the sheet resistance Rsh of the material is constant If the
straight line of the graph is extended up to initial gap (d=0) the intercept on the y-axis
provides the 2RC value To extract the 2LT further extrapolation is made until the
interception at RT = 0 is reached Therefore an important parameter which is the specific
contact resistance ρC can be found from this expression[85 86]
120588119888 = 119877119862119871119879119882sinh
119897119871119879
cosh119897
119871119879
(250)
Where l represents the total conductive semiconductor thickness The final part that can
be extracted from the graph is the slope of the line This is obtained by dividing the sheet
resistance with the width of the metal pad ie represented by expression (119877119904ℎ
119882frasl )
28 Basic Characterization Techniques and procedures
281 Measuring tools and apparatuses
The success of every experiment is determined by the backend results that are
obtained from the measurements It is important to choose an appropriate instrument
which will provide the required data for a valid and detail analysis Thus this section
will give a brief explanation of the measuring instruments and methods that were
exploited in this research The measurement apparatus systems that are available and
have been utilised in completing this thesis are ldquoset of DCrdquo and ldquoSet of RFrdquo
measurements The DC set measurement consists of room temperature and variable
temperature system This system is built to perform process monitoring during device
fabrication and it comprises of five main components
The fundamental component in the ldquoDCrsquos set toolrdquo is the Agilent B1500A
Parameter Analyser [87] used to provide fixed currentbias during testing The other
component is a Karl Suss PM5 Cascade Prober [88] which is used to receive fixed
currentvoltage and to supply its to the semiconductor contact via probe tip The PM5
Prober has at least four probe arms and each of them is fitted with ldquoneedlerdquo called probe
73
tip The size of the tip that is normally used here is 2microm and in some cases the tip size
of 1microm is also utilised The currentbias supplied to the sample must go through the two
of Source Measurement Units (SMU) namely SMU1 and SMU2 to ensure no mismatch
occurs between parameter analyser and diode All the testing are controlled using a
software called Integrated Circuit Characterization and Analysis Program (IC-CAP
2009) brought from Keysight Technologies[89] The software is installed on a standard
Personal Computer (PC) and the PC is connected to a General Purpose Bus Interface
(GPIB) to link with the B1500A Parameter Analyser This system can be organised
based on the purpose of measurements ie IV characteristics TLM Schottky Diode
and transistor as it is very flexible to change the configuration For examples
Transmission Line Measurement (TLM) configuration requires the addition of a digital
multi-meter and four-point probe tip while diode measurement just needs two point
probe tip without a digital multi-meter Figure 224 illustrates the measurement system
for a set of DC to test the TLM structure
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM
On the other hand the set of RF measurement consists of five block elements
configuration in the system namely the Vector Network Analyser (VNA) DC
sourcemonitor Cascade Microtech Prober SMU and Control PC via GPIB The RF set
Agilent B1500A
Parameter analyser
DUT
(TLM Diode
Capacitance)
Karl Suss
PM5 Cascade
Prober
PC
(MS windows 2000)
Digital Multi-meter
ICCAP 2014 Provide current
source
Measure and read the
voltage Stage and Probe
Signal
Current Source
SMU1 SMU2
General purpose bus interface
74
performs RF characterisation after the device fabrication is completed This system can
also perform DC characterisation as its basic instrument has this function too The VNA
machine used in this research is the Anritsu 37369A [90] which can perform the
Scattering Parameter (S-Parameter) measurement with a frequency range of 40MHz to
40GHz The DC sourceMonitor utilised in this experiment is the HP 4142B Modular
DC SourceMonitor [91] Both of these sub-systems are controlled by a standard PC
which exploits GPIB port to link them During operation the HP 4142B is connected to
the VNA by an internal bridge network and two SMUs to the Cascade Microtech Prober
which is then connected to the bond pads of the device It is identical to the set of DC
measurement where the SMU setting and data assembly are accomplished by IC-CAP
software package therefore the data that was obtained before and after completing the
fabrication can be compared This will enhance the validation of the data
However the stage and probes in both sets of measurement are different The
Cascade Microtech Prober has only two probe arms with each arm fitted with a 3-
fingers probe tip in the arrangement of Ground-Signal-Ground (GSG) as shown in
Figure 225 Each finger (pitch) is separated by 100microm thus to fit in with the pitch and
to reduce the mismatch in resistance the bond pad design must follow this separation
between each contact The GSG is configured by connecting the outer pads (Collector)
to the Ground probe tip while the inner pads (Emitter) are attached to the Signal probe
tip where the RF signal is sent and received through it Figure 226 shows the actual set-
up for RF measurement used in this research
75
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
Figure 226 Actual VNA system that was used for RF characterization
282 Measurement steps using a VNA
The RF measurement steps can be summarised in the following
- Step 1 Select or find the suitable VNA depending on applications
PC
(MS windows 2000)
ICCAP 2014
VNA
Anristru 32379A
40MHz to
40GHz
HP4142B
Modular DC
source
DC Bias Source
Cascade
Microtech
Probe Station
One 50microm pitch G-
S-G probe tips
Ground
SMU1
Cathode
Gen
eral
purp
ose
bus
inte
rfac
e
Lo
w P
ow
er H
igh P
ow
er
Cathode
Anode
SMU2
Ground
Ground
Signal
76
There are few factors that need to be well-thought-out before starting to use a VNA
especially for S-parameter measurements The factors are the availability of the VNA in
term of operational frequency and measurement port types air-filled metallic waveguide
or on-wafer Not all VNA can have an operational frequency for banded measurement
ie W-band Ku-band etc All these may require external signal sources to extend the
operational frequency
- Step 2 Properly setting up the VNA
The VNA can be set up depending on its application and the goal of measurement for an
instant number of point requires a desired frequency span IF bandwidth and the supplied
power level This very important to ensure the desired measurements are correct and
appropriate
- Step 3 Appropriate calibration system
In order to have a valid calibration appropriate calibration method has to be chosen
depending on the applications This will determine the accuracy and standards of
calibration As for on-wafer calibrations the de-embedding is normally used while for
the off-wafer the SOLR technique is more suitable to employ
- Step 4 Validation or verification of the calibration results
It is vital to validate the calibration results to ensure that the system has been properly
calibrated
- Step 5 Proper measurement
Proper alignment positioning and touching from probes tip to DUT is necessary to
guarantee a good repeatability and reproducibility of measurement results Normally
when positioning the probe an alignment marker is used as an aid By doing this similar
travel distance for the probes can be achieved The measuring plane will also be equally
well-defined
283 Measurement Practice and Flowchart
Essentially the device characterisation is performed in two stages ie during
fabrication as a process monitoring and after completion for data collection and
analysis Figure 227 shows the block diagram of a flow chart for testing a 15mm times
15mm wafer processing performance In the wafer processing after reaching the top and
77
bottom contactrsquos step the sample can be examined by measuring the TLM structure
according to the TLM procedure The measurement is conducted by exploiting a set of
DC measurement apparatus as mentioned above analogous to the TLM ladder structure
on the wafer surface Based on the TLM results the presence of any process issue during
the fabrication can be identified by examining the parameter such as contact resistance
and sheet resistance Thus a decision can be made either to proceed or to terminate the
fabrication should any issue is found early on As a result no materials will be wasted
further When a dielectric layer is involved Capacitance Dielectric measurement can be
tested This practise can be used to obtain the quality of the dielectric layer To connect
between a diode effective area and probe a bridge is requires It can be attached to the
diode emitter (to determine the diode size) to a bond pad for probe tip to touch This
bridge can either be left hanging in air or sticking to the isolated dielectric layer For the
GaAsAlAs material system the latter technique is preferable since it avoids issues with
the air-bridge which will be discussed in detail in Chapter 3 The opening area (via) for
metal connection can be checked by measuring the resistance on a special design pad
after a plasma dry etching step
Figure 227 Block diagram of the ASPAT measurement step
The next stage of characterising the device is the on-wafer diode measurement
which takes place after completion of all processing (including bond padsco-planar
pads) The work is carried out using the above set for RF measurement and employed
Ohmic Contact
Opening Via
TLM
Qualified
Device
Bad device
Dielectric
capacitance
Bonding pad DC and RF
Good
Good Good
Fail
Fail
Fail
78
purposely to access the DC and RF performance of each diode where the current-voltage
(I-V) characteristic and S-Parameter results are obtained In fact DC measurements are
first performed using a set of DC measurement and a rough IV characteristic can be
obtained to ensure the diode is working properly Usually the yield of any fabricated
device on 15mm times 15mm wafer in this research is between 70 to 90 In this research
the outcomes that will be discussed in the subsequent chapters are in term of the average
of measured values Thus it is very important to have a meaningful data to compare with
physical modelling and simulation in the future The diode IV characteristics are studied
by applying different DC bias at the emitter to collector terminals to extract its keys
parameters ie turn on voltage (supposedly zero bias) non-linear characteristic Rj RS
Cj etc
The device that has been measured by DC and having produced a valid result
will be marked for the next investigation ie the S-Parameter measurement This
measurement is executed using a similar system but with different probe types The
three fingers probe type is used and the device frequency response is measured via the
one-port network from the VNA The important parameters extracted from this
measurement are usually S11 (depending on how many ports are measured) Although
working devices are selected to measure accordingly there is a need to ensure the VNA
RF cable and probe tips are calibrated so that only valid data without errors will be
obtained A calibration technique called SHORT-OPEN-LOAD (SOL) is performed
prior to each daily measurement by exploiting a calibration sample with WinCal
software (Cascade Microtech)[92]
To avoid confusion it is worth mentioning that this technique used to calibrate
the device structure is different from what is used in SOL calibration to the equipment
Furthermore the de-embedding calibration is made on-wafer with the same substrate of
the actual device whereas the SOL is performed on a special calibration substrate
Normally the de-embedding results are not constantly automated with the VNA
equipment However the measurement is done separately starting with the special DUT
substrate then followed by the OPEN and SHORT de-embedding structures
79
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES
31 Introduction
This chapter presents in detail the general fabrication techniques for a generic and
development work of micron scale ASPAT diodes The discussions will focus on the
semiconductor growth technique used in this work ie MBE and the fabrication process
steps which include sample cleaning photolithography etching and contact
metallization These techniques are ample to build and deliver commercially marketable
fabricated structure Hence all photolithography techniques used to complete this
project are based on conventional i-line optical lithography which is adaptable to
industry and commercial purposes
The fabrication process in this work can be fragmented into two major works
firstly the fabrication towards reproducibility repeatability and manufacturability in
term of device structure process flow and DC amp RF characteristics This work will
involve relatively larger emitter area which varies from 15times15microm2 to 100times100microm
2 The
larger area provides for ease and fast fabrication as well as DCamp RF measurements
Once repeatability and reproducibility of the process flow and performance is confirmed
the second part of this work which is concerned with applications in millimetre and sub-
millimetre-wave then took place In this work small emitter designs varying from
2times2microm2 up to 10times10microm
2 were considered with appropriate measurement pads The
successful fabrication of smaller diode geometries in the second part of the programme
naturally leads to a further investigations to understand its epitaxial layer structure and
extracting intrinsic components ie junction resistance junction capacitance and series
resistance which will determine the device performance in high-frequency applications
The I-V characteristic is obtained from DC measurement which is usually performed at
room temperature Its results are then compiled and compared with advanced simulation
It is worth mentioning that all samples that are investigated in this project are grown by
means of MBE and the activities related to the epitaxial layer growth using MBE in the
University of Manchester were done by the Materials Growth Team (Prof Missous) and
the authors has no responsibility for this particular task
80
32 Epitaxial Layer Growth Techniques
Before discussing the principle of the common lithography technique it is
important to discuss the wafer growth technique as it comes first before the fabrication
The growth technique that is extensively used in this study as well contributing a lot in
the electronic semiconductor industry is Molecular Beam Epitaxy (MBE) The following
section will discuss the basic operating principle of solid source MBE
321 Molecular Beam Epitaxy (MBE)
The MBE technique was developed in the early 1970s [27] and is purposely used for
growing high purity epitaxial layers of compound semiconductors Such sophisticated
growth technique provides significant functionality ie precise control of the thickness
(to one atomic layer) and contributes to the growth of various types of complex
semiconductor multilayers high quality and advanced materials This level of control is
vital for an assortment of heterostructures devices that are being utilized as part of the
development of the advanced electronics devices especially for the ASPAT diode which
require 01ML control over the AlAs barrier to attain acceptable variability in device
characteristics Additionally the accurate doping profile and excellent junction
abruptness also can be achieved by using this technique
Practically the MBE system used in this work is a solid source MBE which
utilises beams produced by heating up various sources The sources can be Si Al Ga
As and other group III-V compound semiconductors When the crucibles which contain
the sources are heated atoms or molecules of the various elements are evaporated and
travel in straight lines paths like beams directed toward a target (heated and rotating
substrate surface) The condition of the vacuum during evaporation is ultra-high vacuum
(UHV) ~10-11
torr in order to have high quality crystals The substrate is heated and
rotated to provide good growth uniformity over large areas ( up to 4times4rdquo wafers) [93]
The growth rate in typical MBE growth is ~1ML second and can be controlled
by the source temperature in the crucible The abruptness at the heterojunctions interface
and switching of the growth compositions can be obtained by precise control of shutters
that are placed in front of the crucibles Therefore an abrupt junction at GaAs and AlAs
81
interface can be formed to realize the barrier in the ASPAT diode In order to monitor
the quality of the growing crystal and measure the layer by layer growth mode
Reflection High Energy Electron diffraction (RHEED) technique is utilised This
technique works based on the diffraction of electrons from the crystal surface [93]
Additionally given that the ASPAT current density is very sensitive to the barrier
thickness a study has been made using different growth techniques namely MBE and
Metal-Organic Chemical Vapour Deposition (MOCVD)[59] From this investigation it
was concluded that the percentage local variability of current density produced by MBE
grown diodes is better than those grown by MOCVD Thus in this study to get benefit
from its performance all wafers are MBE grown
33 Basic Principles of Common Fabrication techniques
This section covers the generic fabrication process which underpins
reproducibility repeatability and process optimisations for high-frequency applications
331 Sample cleaning
Essentially semiconductor processing requires a ldquoclean environmentrdquo to produce
devices The clean environment is classified according to how many ldquounwantedrdquo
particles are present in a cubic meter There are four categories of clean room available
in the industry Class 10 Class 100 Class 1000 and Class 10000 [94]
The fabrication of all ASPAT diodes in this project was performed in a clean
room environment of Class 1000 equipped with laminar air flow and filter system to
give Class 100 or better during processing Although the sample was processed in a
highly controlled particle environment there is still a high chance for a sample to get
contaminated when handled by a human Besides this the source of particle which
contributes to the contamination can be from the apparatuses and processing equipment
used in the laboratory themselves Thus the process of cleaning the sample wafer
surface before the start of each step is vital
Generally in a clean room the standard solutions that are used to clean a sample are
N-Methyl Pyrrolidone (NMP) Acetone Propan-3-ol (Iso-Propane-ol) (IPA) and
82
deionized (DI) water The sample which is cut up into 15times15mm2 size tiles is cleaned
based on the following procedures
1 Hot NMP- The sample is dipped into the solution at 80˚C for 10 minutes This
solution acts as an organic type of nature pollutants removal
2 DI water- acts as NMP remover The sample is then washed by flowing DI water
throughout the samplersquos surface
3 Acetone- to ensure any remaining NMP is completely removed from the sample
The sample is dipped into Acetone for 5 minutes in a low power ultrasonic bath
at ambient temperature
4 IPA- is used to remove the Acetone from the samplersquos surface The sample is
then dipped into the IPA for 5 minutes in a low power ultrasonic bath at room
temperature The use of low power for the ultrasonic bath is to avoid the sample
cracking or breaking
5 Once done the sample is then blow-dried using nitrogen (N2) gun to remove any
moisture coming from the IPA Fortunately it is easy to remove the IPA
completely from the sample surface given its higher rate of evaporation
Once all these steps are accomplished a visual inspection using a high magnification
optical microscope is conducted to ensure the sample surface is clean The cleanliness of
the sample is determined by the (lack) of particles or other spots (liquid mark) that can
sometime be observed during the inspection Obviously the lower the number is the
better the sample is as it is impossible to totally remove dirt especially marks
Sometimes it is hard to remove the particles in one go There is always a need to repeat
each cleaning step for a few times However this will not affect the sample in term of
electrical performance as the cleaning solutions used are non-destructive
332 Photolithography
Lithography or sometimes called pattern transfer is the most important step in
realizing microelectronic devices The designed geometry and dimensions on a quartz
glass plate called a ldquophoto-maskrdquo must be done prior to the fabrication process While
the photo mask can be designed by using various software tools in this work the design
83
is done via the Advance Design System (ADS) by Keysight The details of the design
which includes three different mask designs will be covered in Section 34 The mask
consists of the desired patterns (master) that can be printed onto solid materialrsquos surface
by means of an electrochemically sensitive polymer (photoresist) using
photolithography In fact this type of optical lithography technique can be performed
with and without a mask due to its simplicity It is also easy and cheaper compared to
other techniques such as x-ray lithography or Electron-beam lithography (EBL)
Although the latter is expensive it is still worth to have since it provides a higher
resolution which is preferable when developing sub-micrometre technology
processing[95] The special feature about EBL is that it does not need a mask to pattern
samples but can be produced by the movement of an electron beam point source and
hence writing the patterns directly on the surface
The ultra-violet (UV) based light sources are more popular among researchers
and development workers because they are cheaper and have modest resolution Usually
photolithography operates at wavelengths (λ) from 193 nm to 436nm The source that
provides the UV light is a Mercury (Hg) arc lamp which uses narrowband filters to select
single emission lines First is the i-line at λ= 365nm then the h-line which is of lower
resolution and has λ of 405nm and thirdly the g-line with a λ= 436nm[96] The
conventional optical lithography used in this research uses the ldquoi-linerdquo at a wavelength of
365nm For shorter wavelengths than these excimer laser or krypton fluoride laser with
a λ= 248nm and argon-Fluoride with a λ = 193nm are also used in the industry The
higher power levels enable higher productivity (throughput) while narrower spectral
widths reduce chromatic aberration provide better resolution and larger depth-of-focus
In this research all the fabrication process are done by utilizing a conventional optical
lithography (i-line) using a Karl Suss MA4 mask aligner Before starting any UV
exposure it is important to check the UV light intensity as it will affect the resolution
and thus desired device dimensions Therefore every corner that is exposed to the UV
light is calibrated to be at 09mWatt power exposure
The complete set of photolithography components consists of photoresist
(photosensitive polymer) photo-mask (chromium) which is used to block the UV to
form a pattern mask-aligner and developer (chemical solutions) Standard fabrication
84
process usually practiced at the University of Manchester starts with sample cleaning as
mentioned earlier Then the sample needs to go through heat treatment to remove all the
moisture with a temperature set to be 150˚C and bake for 5-10 minutes After having
cooled down the samplersquos surface is coated with a thin layer of photoresist via a
technique called spin-coating using a Laurell CZ-650 series spinner The spinning speed
is set depending on the type of resist ie 3000rpm for negative photoresist and 5000rpm
for positive photoresist The rotating speed of the spinner does not have much effect on
the coated photoresist thickness but will have consequence on the uniformity distribution
over the sample surface The coated thickness photoresist however depends on the
concentration of the specific photoresist Once spin-coated is done another short heat
treatment (1 minute) is required to ensure the resist is hard enough to contact a
photomask and to remove any excess solvent The temperature is set on the hot plate to
about 115˚C and 110˚C for positive and negative photoresists respectively
The important segments contained in the photoresist are a polymer (base resin)
a sensitizer and a casting solvent [97] The polymer will react by changing its structure
when exposed to the radiation While sensitizers will govern the reaction of the
photochemical in the polymeric phase the casting solvent will permit the spin-coated
application on the wafer surface The photoresist consists of positive and negative
photoresist both of which were used in this research Their basic difference is with
respect to the area that is exposed by UV light ie whether it will remain on the
semiconductor surface or will be removed In the case of a positive resist the exposed
area will be removed by the developer and the covered area will remain In other words
whatever is displayed on the photomask goes onto the sample surface On the other
hand for the negative photoresist the area that is covered from UV exposure will be
dissolved by the developer Figure 31 shows a 3D picture of both processes used in this
research
85
Figure 31 3D illustration of Optical lithography process used in this research
To obtain the desired pattern on the surface after UV exposure for a certain
duration the sample is required to go through a development procedure by using a
developer The developer is used to expel the dissolvable part of the photoresist after
being exposed to UV The usefulness of the developer depends on the photoresist ie
MF319 developer is specifically for positive photoresist while MIF326 is suitable for
negative photoresist Both types of developers will not harm the devices as they are a
kind of metal free ion solution Thus no free ion will change the characteristic of the
device The common practice in the clean room at the University of Manchester is to use
positive photoresist namely Shipley Microposit S1800 supplied by The Dow Chemical
and negative resist AZnLOF2020 (AZ2microm) which is supplied by MicroChem For the
S1800 series the thickness of the photoresist is determined by the last two digits ie
13microm thick for S1813 and 05microm thick for S1805 Both positive photoresists are used
Resist
GaAs
Dielectric
Photo Mask
Negative Resist Positive Resist
After Etching
86
mostly as protective area during wet chemical etching and as sacrificial dielectric layer if
higher temperature is applied ie 190˚C On the contrary AZ2microm which normally has a
thickness of 2microm is useful for patterning small dimension which leaves small gaparea
for the metallization process to fill It has good aspect ratio and useful in single layer lift-
off (post metallization process) In fact this type of resist can be thinned by diluting into
an Edge Bead Removal (EBR) solution and smaller device feature size can be obtained
The final dimension of certain devices (mesa size) is governed by the exposure
time the distance between photomask and samplersquos surface and the development time
The appropriate UV exposure time is required to avoid over-exposure which will cause
the spreading of light into the purportedly dark-field area[98] However the effect of the
exposure time differs between the photoresist types smaller opening area than the mask
pattern for negative resist and larger opening area for positive resist[45] The gap
between the photomask and wafer surface must be reduced as much as possible to avoid
the UV light going through the unwanted area To obtain a good gap value an applied
pressure from stage to the mask is required The normal pressure used in this research is
between 04 to 1 Pascal depending on the type of photoresist (negative and positive) as
well as its thickness Lastly the development time also influences the dimension of the
device Appropriate development time is required because ie over-development will
cause the polymerized photoresist to etch laterally resulting in bad patterned geometries
On the other hand under-development will cause non-uniformity in the surface after wet
chemical etching (positive resist) as well as causing lift-off problem (negative resist)
333 Etching Process
The etching process is a process of removing unwanted semiconductor layers to
define device geometry and isolate each individual device in one sample There are two
types of etching technique used in this research ie wet chemical etching and plasma
dry etching The wet chemical etching is based on Orthophosphoric(H3PO4) solution
which is a selective etchant to materials like GaAs InGaAs and AlAs The selective
etchant is referred to a solution that can etch away a specific semiconductor with a
specific etch rate The etch rate depends on the mixture ratio and concentration of the
solutions ie the higher the concentration the higher the etching rate In practice the
87
temperature humidity and epitaxial layer doping level also have an impact on the etch
rate Hence to minimize variation in the etch rate both temperature and humidity in the
clean room are constantly monitored and regulated Ambient temperature between 18degC
to 19degC is usually suitable while humidity is kept within 30 to 40 The advantage of
the wet chemical etching is that it is inexpensive controllable and with high throughput
highly selective and simple The mixture solution that is used in this work is
Orthophosphoric (H3PO4) Hydrogen Peroxide (H2O2) and Di-ionised water (H2O) with
ratios of 3150 3110 and 212 The ratio of 3150 provides an etch rate of about
600Aminute and is good to define the area and opening the under-cut in air bridges for
InGaAs samples[99] The 3110 ratio results with highly anisotropic shape but is easy to
control as the etch rate is about 1500Aminute for GaAs material system However the
212 etchant solution will provide extremely anisotropic etch rate of about
1000Asecond and is quite difficult to control For GaAsAlAs ASPAT diode it can still
be controlled since the thickness that needs to be removed is about 7000A (refer to
section 342 for details on the fabrication of ASPAT) Table 31 summarizes the etch
rate with different ratios and different selective materials Common to all the ratios
mentioned above are the isotropic side walls with lateral and vertical etch rate of 11
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and Ammonia on GaAs
and InGaAs materials
Material Etchant Ratio Etch Rate (Aringminute)
GaAs H3PO4H2O2H2O 3150 600
GaAs H3PO4H2O2H2O 3110 1500
GaAs H3PO4H2O2H2O 212 60000
GaAs NH4OHH2O2H2O 118 2000~3500
InGaAs H3PO4H2O2H2O 3150 850
The plasma dry etch is purposely run to obtain extremely high anisotropic etch
profile vertically and horizontally It can be done via mask with positive photoresist and
self-align mask which is metal contact as a mesa protector The precursors that are used
to etch away GaAs InGaAs and AlAs layer in this technique are Methane and
Hydrogen (CH4+H2) On the other hand Carbon Tetrafluoromethane (CF4) and H2 is
88
used in removing Si3N4 The etch rate is determined by how much power is applied to
the plasma to hit the sample surface the pressure inside the chamber and amount of the
precursor In this research plasma Technology is used for dry etching This machine
which is a conventional OXFORD INSTRUMENTS 1990 machine can produce an etch
rate on average of 100Aminute for an RF power of 100mWatt
334 Sputtering (dielectric deposition)
In this work a Kurt JLesker PVD 75 is used to deposit Si3N4 layer on the sample
surface The deposition rate depends on the RF power that is applied To avoid surface
damage on the sample surface a sacrificial layer formed by SiO is deposited using the
Bio-Rad Thermal evaporator before transferring to the PVD 75 to start deposition with a
low (75Watt) RF power Once the deposition time reaches 30 minutes the power is
increased up to 200Watt As a result good uniformity of the dielectric layer is obtained
335 Metallization Process Lift-off and Annealing
The metallization process is a process in which metal contacts on semiconductor
devices are created The purpose of this process is to make a proper interconnection
between the semiconductor devices to other parts of the circuit elements In other words
it is to connect the semiconductor device to the outside world This process will allow
the device to be examined electrically so that all electrical characteristics can be obtained
ie resistance I-V curve capacitance conductance etc The metal scheme used in this
process depends on the semiconductor material In the case of GaAsAlAs ASPAT
diode Gold-Germanium (AuGe) Nickel (Ni) and Gold (Au) are used However in the
case of InGaAsAlAs ASPAT diode the metal scheme used is Titanium (Ti) and Au
The technique used in this process is resistive thermal evaporation
The metallization process starts by cleaning all the metallic sources and boats
ie tungsten boat Au Ni and Ti metals by using Trichloroethylene Acetone and IPA
consecutively for 5 minutes each in a high power ultrasonic bath This step is very
important to reduce the risk of contamination during thermal evaporation Once done all
the metallic materials are dried using a high-pressure nitrogen gun and then dipped in
89
Hydrochloric acid (HCL) solution for 2 minutes to de-oxidize the metals so that it has
minimal effect on the series resistance of the ASPAT diode
Two types of thermal evaporators were used extensively in this study both
Edwards Auto 306 (one denoted as Junior Auto 306) The latter is used to deposit alloy
type of metals while the former is used for the non-alloyed type of metals In the case of
GaAsAlAs ASPAT alloy type metals are used while for InGaAsAlAs non-alloyed
metals are used The cleaned metals are then loaded in the thermal evaporators and
placed on a resistive tungsten boat Each metal is placed on its specific tungsten boat to
avoid unnecessary mixture during the evaporation
Figure 32 Actual picture of thermal evaporator used in this study
Prior to loading the sample into the evaporator a standard fabrication process for
ASPAT diodes takes place by patterning the samples with AZ2microm negative photoresist
At the end of this step an opening area is created for the metal contact to be filled and
connected to the ohmic contact of the semiconductor The sample is also deoxidised
using a mixture of HCL and water in the ratio of 11 prior to evaporation This has to be
done in a very short time in order to avoid re-development of the native oxide layer
Inside the chamber the sample is securely placed on a chuck upside down facing the
filled tungsten boat The distance between the sample and metallic source boat is about
90
40 cm Figure 32 illustrates the actual thermal evaporation system used in this study
The thermal evaporator chamber is pumped down to reach a minimum pressure below
1times10-5
mbar before vaporizing the metal It is important that the mean free path between
metal amp sample is created and each vaporized metal stick firmly on the samplersquos surface
The normal practice in this study is to keep the vacuum pressure under 1 times10-6
bar so
that better device performance can be obtained The amount of current required to melt
down the metal is between 4 Amps to 6 Amp This amount of current is forced through
the tungsten boat and generates very high heat melting down the metallic source and
vaporizing it towards the sample surface The deposition rate for each metal can be
monitored by using a built-in film thickness monitoring (FTM) on the thermal
evaporator which proportionally depends on the amount of materials deposited The
GaAsAlAs sample is started with deposit of 55nm AuGe 13nm Ni and 500nm of Au
The reason of depositing AuGe first is due to the fact that the ohmic layer of the
ASPAT only can only be doped with a maximum doping of 4 times1018
cm-3
which is not
high enough for good conductivity Thus here Ge atoms will diffuse into the GaAs and
replaces Ga atoms during annealing process leading to higher doping levels (gt1 times1019
cm-3
) and hence improved conductivity
3351 Lift-off
The use of AZ2microm allows for the exact patterning of metals without the need for etching
using a single layer lift-off technique The negative photoresist also provides an undercut
profile which will create disjointedness between the desired metal pattern (on the
semiconductor) and undesired metal (on photoresist) The process of getting rid of the
unwanted metal from a sample surface is called lift-off The process starts once the
evaporation process is accomplished The sample is soaked into 80˚C N-Methyl-2-
Pyrrolidone (NMP) solution for usually 20 minutes (fast lift-off process) In most
instances the sample is in NMP for more than 12 hours in ambient temperature (slow
lift-off process) as the NMP solution is not destructive to the sample In this solution
the negative resist will be softened and the metal part which sticks on it will also be
eliminated from the sample As depicted in Figure 33 the lift-off process for a single
device shows the usual photoresist undercut profile observed To ensure that NMP
91
residues on the sample surface are completely removed DI water is used to rinse the
sample which is then blown dry with a nitrogen gun
Figure 33 Single layer lift-off process using negative photoresist
3352 Annealing
The alloyed (AuGeNiAu) metal stack requires a thermal treatment called annealing to
improve the ohmic contact between metal and semiconductor The sample which has
deposited top and bottom contacts is loaded into an annealing furnace at a temperature of
420˚C for 2 minutes In the case of GaAs during thermal annealing Ge atoms penetrates
into the GaAs crystal for approximately 70nm-250nm depending on evaporated
thickness of the metal layers annealing temperature as well as time [100] In this work
the total metal thickness evaporated for each contact layer is around 500nm This
thermal annealing treatment will also melt down the Au if it is too thick and is subjected
to too long a heat treatment Therefore it is not advisable to do annealing after the
sample is coated with bond pad metals as it can result in short circuited devices
sometimes
Az2micro Negative
photoresist profile
after UV exposure
and development
Evaporation to
form metal layer
(AuGe Ni Au)
Desired metal
contact
Metallisation
process
Lift-off undesired metal
92
34 GaAsAlAs ASPAT Process Optimization
As mentioned earlier this section present details two major process flows of the
fabrication process for the ASPAT diodes which utilised three stages of development of
photomasks design namely a ldquoFirst generation mask designrdquo (1st Gen) a ldquoSecond
Generation mask (2nd
Gen)rdquo and a ldquoThird Generation mask (3rd
Gen)rdquo design The 1st
and 2nd
generations mask designs are the designs that were produced in the first stage of
this work to develop the fabrication process know-how and to get familiarized with the
actual fabrication techniques in the cleanroom The difference between the 1st Gen and
2nd
Gen masks is in term of the development towards realizing Air Bridges and
Dielectric Bridges which were mostly covered by the 2nd
Gen mask design The
analyses in term of reproducibility repeatability and manufacturability for process
control and current-voltage characteristic as well as ultimately RF measurement are
obtained on relatively large size devices via these two mask designs The large area
emitter dimensions range in size from 15times15 microm2 to 100times100microm
2
The 3rd
Gen mask design was designed based on the optimization of the 2nd
Gen
mask which was to realize ASPAT diodes that are able to work at very high operating
frequencies Therefore in such design the ASPAT devices have to have a minimal
amount of capacitance and low series resistance this is can be achieved by shrinking the
emitter size of the diode to the smallest area possible as well as optimising the
fabrication process ton reduce parasitics The smallest fabricated devices designed on the
new mask has an 2times2 microm2 MESA area which also includes Ground Signal Ground bond
pads for both device and de-embedding structures (open and Short) for RF
measurements
Before the commencement of any fabrications and designing any layouts on eg
Si GaAs InP etc the epitaxial layer must be grown first to a desired design In the
University of Manchester the epitaxial layer structures are grown using one of the two
Molecular Beam Epitaxy (MBE) machines which are either the RIBER V90H or the
V100HU system Both systems are managed by Professor Missous Epitaxial wafers or
sample grown by each system are identified by a prefix and numbers that are prefix
VMBE for the V90H system and XMBE for the V100 system The epitaxial layers are
93
grown on four-inch wafer diameter The maximum diameter that can be grown on using
the V100H is 8 inches but generally single 4rdquo or 4x4rdquo wafers are used The wafers are
then diced and cut using a diamond scriber into 15mm times 15mm tiles for easy handling
and fabrication in the D12 cleanroom lab in the University of Manchester
In this section the structures fabrication and performance of the various ASPAT
diodes for both repeatability and high frequency applications will be discussed further
The ASPAT is manufactured on wafer sample XMBE304 which is a GaAsAlAsGaAs
lattice matched to a GaAs semi insulating substrate is the main focus The ground works
on this ASPAT such as the initial design and fabrication process flow optimization had
been conducted by fellow PhD colleagues in the group led by Professor Missous at the
University of Manchester
341 ASPAT Devices used in Fabrication
3411 XMBE368 and XMBE307
Table 32 Epitaxial layer of Doped substrate samples
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~50
Spacer1 GaAs NID 50 50
Barrier AlAs NID 28 28
Spacer 2 GaAs NID 1000 1000
Buffer GaAs(Si) 4times1017
50 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~3500
Substrate GaAs (Si) Doped 50000 50000
These two samples were the first batch of diode structures used in this work and
were grown using the RIBER V100 MBE machine A great deal of work was expanded
to ensure that it is able to produce appropriate non-linear I-V characteristics The work
carried out including finding suitable fabrication process steps mask designs process
control limitations ie etching rates etc The results obtained from processing these
94
samples mostly on large area anode and cathode sizes and their analysis included both
growth profiles and fabrication process flows These samples were grown on doped
GaAs substrates As such the finished diodes were vertical structures and the fabrication
process has marked differences compared to undoped substrate samples While
XMBE368 had similar epitaxial layer profile to XMBE307 during growth the AlAs
layer was set to be stagnant (ie no-rotation of the substrate during growth) to
investigate the effects of slight variations in barrier thickness
3412 XMBE304
The next sets of samples were all grown on semi-insulating GaAs substrates
Table 33 details the epitaxial layer profile of sample XMBE304 the main work horse
of this research work The growth of this structure was performed on a multi-wafer
platen and consisted of 9 x 2rdquo wafers (from XMBE304A to XMBE304I)
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm
Epitaxial layer Material Doping(cm-3
) Thickness(Aring)
Emitter GaAs(Si) 4e+18
3000
Emitter 2 GaAs(Si) 1e+17
400
Spacer GaAs NID 50
Barrier AlAs NID 28
Spacer 2 GaAs NID 2000
Collector GaAs(Si) 1e+17
400
Collector 2 GaAs(Si) 4e+18
4500
Substrate GaAs(SI) Semi-Insulating
For a typical ASPAT structure the emitter is essentially highly doped to
4times10+18
cm-3
to provide accumulation of electron in the emitter contact region It was
purposely highly doped to also achieve low ohmic contact with the metal The spacers
are used to avoid diffusion of dopants to the subsequent layers The ASPAT structure as
mentioned earlier has a single AlAs barrier with a very small thickness sandwiched
between two different length GaAs spacer layers
Batch XMBE304 is the main focus in these studies All activities required for
repeatability reproducibility process flow and devices as well as qualifying new or
95
optimization fabrication technique for small devices and RF performance which were
then used for high frequency were based on the set of wafers grow in this batch
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability
As the new wafer structures have to be tested and evaluated to gauge the
performance of the ASPAT diodes their uniformity also needs to be tested so as to
ensure it exhibited fully functional diode with zero bias detection in minimal variation in
IV characteristics between diodes As described previously 4rdquo wafers are always diced
up into 15mm times15 mm size for ease of handling in the cleanroom and for masks cost
purposes
3421 Doped n+ Substrate Wafers
For wafers grown on n+ substrates (XMBE368 and XMBE307) a two-level mask
set is sufficient to complete the fabrication process In this case the devices are designed
with mesa structures and top metal contact on the upper surface of the wafer and a
bottom contact on the backside of the wafer One mask plate is used for defining the
mesa structure (wet etch) and the other mask plate is used for defining the metal pad
Since the mesa is relatively large (30times30microm2
to 100times100microm2) there is no requirement to
define bond pads for measurement purposes A prior RTD mask designed by fellow
colleague Dr Md Adzhar for his PhD work was used for processing the ASPAT diodes
as well in the first instance The detail fabrication process is summarized in appendix I
for the doped substrate wafers Figure 34 shows typical IV characteristics for 30x30microm2
emitter size diodes obtained from sample XMBE368
96
The I-V measurement was taken from two different tiles (15mm times15 mm) located
on top and bottom of a 4rdquo XMBE368 wafer The location 1 marked as a blue line in
figure 34 refers to a device on a tile taken from the top of the 4rdquo wafer while location
2 (red) refers to a device on a tile taken from the bottom of 4rdquo wafer At 07V the
separation difference in current is ~228 for both tiles This shows that the device in
tile 1 is less resistive than the sample in tile 2 implying that the AlAs layer for tile
located on the top corner of the wafer is thinner and thus allows more electrons to tunnel
through it at a given bias
3422 First Generation Mask Design (1st Gen)
-0015
0005
0025
0045
0065
0085
-15 -1 -05 0 05 1 15
I C
urr
en
t (A
mp
)
V Voltage (Volt)
Current vs Voltage (XMBE368_1) for 30x30microm2
MidLeft2
MidRight3
Figure 34 Current-Voltage characteristic of sample XMBE368 used
in this study at two different locations on the wafer tile
(a) (b) (c)
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2 diode dimensions
designed in the 1st Gen Mask
Location 2
Location 1
97
The fabrication of the GaAsAlAs ASPAT conducted in this 1st Gen mask is
followed the established generic process flow for InGaAs material which was done by
former co-worker Dr Md Adzhar Md Zawawi[101] The generic process flow is fairly
simple consisting of four mask steps as shown in Table 34 below The fabrication
process starts with the sample being cleaned in a NMP solution at a temperature of 80˚C
with Acetone and Propan-2-ol (IPA) The purpose of cleaning using NMP and Acetone
is to remove any organic material The IPA is used to remove Acetone residues
Table 34 Generic fabrication steps established by Dr Md Adzhar [101]
Step number Process
1 Top Contact
2 Mesa Etch
3 Isolation
4 Bottom Contact
In the 1st Gen mask the first step in fabricating the GaAsAlAs ASPAT diodes is
to use the first mask to define the emitter contact area The emitter has three different
sizes 100times100microm2 30times30microm
2 and 15times15microm
2 The lithography technique uses the
negative photo-resists AZ2micron with 55 second UV-photolithography to pattern the
top contact Then it is developed using MC319 developer to clear and define the
exposed area for the metals to stick to The sample is then subjected to plasma etching to
remove all organic residues and contaminants Then it is dipped into a mixture of
diluted Hydrochloric acid and water HCL H2O with a concentration of 11 for de-
oxidation This must be done in a short time right before the evaporation in order to
ensure good contact between metal and semiconductor surface with very low oxide
formation in between The ASPAT device performance depends on this step as contact
to the channel is by means of current flowing through the anode to the cathode terminals
In our lab the approach taken to achieve the Ohmic contact is by evaporation of Gold
Germanium (AuGe) Nickel (Ni) and Gold (Au) metals layers on top of the cap layer
Subsequently the metal is defined via a lift-off process using NMP
98
The next critical step is to define the MESA or island The mesa etch mask is
designed with two options with 05 microm or 10 microm tolerance The different mesa
tolerances are introduced to act as a safeguard for the emitter from producing excessive
undercut caused by lateral etching This step is to isolate and eliminate the unwanted
GaAs which will electrically link the active layers as many devices will be fabricated at
the same time on the same wafer tile (15mm times 15mm size) The lithography process in
this step uses positive resist and is developed using MC326 developer This step is
achieved using a wet etch process where a non-selective etchants mixture of
H3PO4H2O2H2O etches down the epitaxial layers until it slightly exceeds the AlAs
barrier with an etch rate of about 600Aring to 900Aring per minute The outcome of the MESA
or island step is the formation MESA active layers which are surrounded by inactive
layers of semi-insulating substrate (when using semi-insulating substrates)
The isolation mask is a step that is basically the same as the MESA etch step
eg using similar etchants mixture same lithography process but a different mask This
step is used to etch down until the GaAs substrate is reached which means that the
etching time is longer than that in the MESA etching step The purpose of this step is to
fully isolate the device from other neighboring devices hence ensuring no electrical
connection exists between each device within one sample Since these ASPAT diodes
employ an air bridge structure of size 1times5 microm the two minutes mesa etches will
simultaneously provide an initial undercut through lateral etching for the air bridge
formation
Based on the results so far obtained using the first-generation mask which
provided large mesa areas the current voltage characteristics of the ASPAT as far as the
non-linear zero bias is concerned did work very well However there was a need to
reduce the ASPAT mesa area down to very small dimensions to achieve mm-wave or
THz detection frequencies It is certainly a general rule for semiconductor device which
operate at very high frequency to have extremely small lateral dimension which
minimises the capacitance within the ASPAT device Furthermore for wider adoption of
the technology it is also important to develop a simple reproducible and low-cost
fabrication method for ASPAT diodes Details of this fabrication process are attached in
appendix II
99
3423 Second Generation (2nd
Gen) mask (ASPAT-GSG)
This work intended to enhance the 1st Gen-Large Area ASPAT photomask by
adding many features including 2 times 2microm2 mesa areas ground-signal-ground (GSG) bond
pads to enable RF measurement and three options device processing eg Air Bridge
Dielectric Bridge for semi-insulating doped substrate and dry etch-mesa Other reasons
for designing this mask was also to qualify process steps when deploying thin (1microm
width) bridge to connect small mesa area ASPAT diodes to the co-planar GSG bond pad
for DC and ultimately RF measurements
The mask was designed to fulfil the basic rules of fabricating various types of
tunnelling diode for instance RTD and ASPAT The diodes layouts were designed using
the commercial software Advanced Design Software (ADS) from Keysight
Technologies Ltd Once the design was completed it was ready to be sent to Compu-
Graphics Company for printing and patterned on a special chrome coated glass plate
The new 2nd
Gen mask design was termed ASPAT with Ground-Signal-Ground
(ASPAT-GSG) and consisted of two main designs ldquoAir Bridge and Dielectric Bridgerdquo
where each contained eight diodes with different emitter sizes (100times100μm2 50times50μm
2
30times30μm2 20times20μm
2 15times15μm
2 10times10μm
2 6times6μm
2 and 2times2μm
2) The Air Bridge
design is comprised of Design 1 (doped substrate) and Design 2 (undoped substrate)
This can be selected by changing the order of each individual layer of the mask steps
The same options are applied for Dielectric Bridge design which included processing for
doped and undoped substrates The details of the masks will be explained in the
following paragraph
(1) Air Bridge
Design 1 Contains five steps or layers mask of size 15mm times 15mm
suitable for air-bridge for undoped semi-insulating substrate
Design 2 Consist of seven layers steps mask of 15mm times 15mm size
There are 413 die chips in about 6mm times 6mm sizes in this design Figure 36 shows both
type of design for Air Bridge mask processing
(i) Mask 1- Top Contact
(ii) Mask 2- MESA
100
(iii) Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5- Collector Bond pad with GSG
(vi) Mask 2A-Dielectric
(vii) Mask 6A-Collector Bond Pad with GSG
(2) Dielectric Bridge
Design 1 Consists of seven identical steplayers masks with lateral
lengths of 15mm times 15mm each suitable for fabrication on semi-insulating
substrate
Design 2 Also has seven steps layers masked with dimension of 15mm
times15mm each suitable for doped substrate processing
There are 357 die chips in this type of mask design with an estimated size of 6mm times
6mm separately The smallest emitter size that is connected with a dielectric as the
bridge is 6times6microm2 The smallest 2times2microm
2 diodes was designed with the air-bridge
connected to the emitter bond pad due to the difficulties of opening viascavity for less
than 2 microm2 devices Figure 37 show both options for Dielectric Bridge mask processing
(i) Mask 1- Top Contact
(ii)Mask 2- MESA
(iii)Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5-GSG bond pad
(vi) Mask 6- Via Dielectric
(vii) Mask 7- Dielectric Bridge
(vii)Mask 5A- Via Dielectric
(ix) Mask 6A-GSG bond Pad
(x) Dielectric Bridge
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates
Figure 37 The layout of 1st design of Dielectric Bridge (green circle) mask design for 100 times
100microm2 emitter size with option for doped substrate processing
101
34231 Fabrication Process of the Air-Bridge Design
The fabrication using 1st Gen mask as mentioned in Section 3422 is less
complex however the fabrication process for Air-Bridge mask design contains a few
additional steps which are to add bond pads for the Ground-Signal-Ground radio
frequency (RF) layouts If the sample is on a doped substrate another layer needs to be
added leading to a total of six steps all together
Table 35 Standard process flow for Air-Bridge design fabrication
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa EtchDielectric
3 3 Isolation
4
5
4
5
Bottom Contact
Bond Pad
In this work the samples that have been processed so far are XMBE304
XMBE314 (GaAsAlAs base material system) and XMBE326 (InGaAsAlAs base
material system) All of them are built up on semi-insulating substrate thus the normal
process flow was followed Step 1 to step 4 follow exactly the same route as the 1st Gen-
ASPAT Large Area mask formerly discussed in Section 3422 This process is then
continued by spin coating AZ2microm on the surface Mask 5 is used to pattern the bond
pads The metallisation scheme used for bond pads is TiAu and the thickness must be at
least 1 micrometre thick This is to minimise series resistance at the pads and ensure a
robust surface is created when used for DC and RF measurements
342311 Air-Bridge Process Optimization
Since the Air Bridge design approach is focused more on developing air-bridges
which have a width of 1 microm and as the smallest device is 2 times2 microm2 the negative resist
(Az2microm) which was used in the 1st Gen design type was changed to Az1microm After spin
coating an Edge Bead Remover (EBR) is required to remove the beads at the edge of the
sample this is to ensure no gap is created between samples and mask when ldquohard-
102
contactrdquo is applied during the photolithography step The use of Az1microm and EBR are
critical to enable the fabrication of small air-bridges and emitter sizes
The exposure time during the photolithography technique also needs to be
increased to achieve a 1microm size air bridge A longer time than normal is required thus
95 seconds is used for exposure under UV light Once finished appropriate
development time must be applied to ensure the line for the air bridge is perfectly
opened for the metal to fill up To get impeccable result in this step both combination of
exposure and development have to be tuned naturally leading to trade off in both Too
long exposure and developing time will break the bridge whereas for too short exposure
time and developing the air bridge will not open
There are two types of etching method used in this fabrication wet
(H3PO4H2O2H2O) and dry (NH4H2) etching Both have their own advantages and
disadvantages Wet etching is faster than dry etching However the etching profile is
highly isotropic and causes serious undercut The smaller devices which have
dimensional sizes of 6times6microm2 and below will ldquoshrinkrdquo the effective area under the top
contact metal Even though dry etching can have highly anisotropic etching profile
which can prevent excessive undercuts it requires a lot of time for etching the
semiconductor layers The NH4 and H2 plasma that are used in this technique do not only
etch the GaAs and AlAs layers but also etch the metal contact at the same rate as the
semiconductors Thus the metal area must be covered with a photoresist or thicker metal
(~1microm) must be used to counter this issue Figure 38 shows that the emitter bond pad
which is not covered by the resist will eventually be etched away by the dry etching
Figure 38 Dry Etching for the first run in this study
As mentioned in section 333 the advantage of H3PO4H2O2H2O wet etching is
that it can be made using two solutions fast and slow The fast solution is based on a
concentration ratio of 212 while the slow solution is based on a 3150 mixture The
103
212 fast solution will produce good anisotropic etch profile but is tricky to control due
to the rather high etch rate of 1000Aring per second Both fast and slow wet etching
solutions being carried out in this experiment are replicated from successful recipes that
were developed by other co-worker from Prof Missousrsquos group
342312 Issue of Over Etch under Top Metal (Wet Etching for Air-Bridge
Design)
The first run using the solutions mentioned above started with the deposited
metal as a top contact (Top contact must be defined first to make a bridge) then Mesa
etching to remove ~7000Aring GaAs using the fast etch solution The next process to be
followed was to employ the slow etch solution to etch down the epitaxial layer to the
substrate Doing this ensured that air-bridge was open and the devices isolated
individually Unfortunately unexpected results were observed where large undercuts
still appeared for both 2times2 microm2 and 6times6microm
2 devices Figure 39 shows severe undercut
under the big device that can clearly be seen in the digital scope Most probably this
problem occurs due to excessive time used for the wet etching (10 seconds for fast
solution and 10 minutes for the slow etch solution)
Figure 39 Severe undercut of 2times2 microm2 and 6times6 microm
2 devices
The second run was employed to reduce the wet etching time in total thus dry
etching was needed As discussed above CH4 and H2 are used to etch away the GaAs
and AlAs semiconductor material while O2 is used to remove polymer residues To
reduce redundant generated polymer during dry etching the process must be separated
into several goes (runs) In this run at the mesa etch step the metal area is covered by
S1805 resist and then the plasma etches down until the heavily doped Ohmic layer is
reached For the isolation step the slow wet etching solution is used to ensure the
semiconductor under the bridge is removed The etching time is still long ie over 5
Zoomed Zoomed
104
minutes Hence this will still generate appreciable undercuts Although this run
managed to reduce the wet etching time it still did not solve the undercut Figure 310
shows undercuts under the effective mesa area still occurring in this run
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet etched
Further investigation has been made to find the root cause of this issue Scanning
Electron Microscopy (SEM) picture were taken to see deep into the completed devices to
investigate what is actually happening Figure 311 shows clearly that the semiconductor
under the bridge and effective area under the 2times2 microm2 device went missing The same
goes to for the large device where about half the size of the designed effective area under
to metal was also unintentionally removed by the solution
Figure 311 SEM Images of the GaAs sample
Since this work was also run together with an InGaAs based sample
(XMBE326) new knowledge regarding etching profile was acquired The lesson learnt
from this run is that the wet etch profile of the Gallium Arsenic (GaAs) material is
totally different from that of InGaAs Figure 312 shows the cross section of GaAs and
InGaAs materials after wet etching The evidences of these issues are also indicated by
the SEM images in Figure 313 and Figure 314 This more or less explained the reason
why the semiconductor under the top metal contact is always missing when wet
chemical etching is applied
Zoomed Zoomed
105
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in this study
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
Figure 314 SEM images for InP and InGaAs taken from [56]
Furthermore previous work done by co-worker Dr Md Adzhar Md Zawawi has
optimised the process for RTD samples based on InGaAs and InAlAs heterojuction
semiconductor materials In this work Dr Zawawi found out that achieving submicron
dimensions is possible when using the soft reflow technique on InGaAs[102] However
it does not apply to GaAs when using the same technique There are few reasons to
106
believe that the work that was carried out by the previous student is not repeatable to the
XMBE304 GaAsAlAs material The main reason is due to the much thicker Ohmic
layers used in the GaAs of ASPAT structures which requires longer etch time The
sample that was used in the previous submicron work namely XMBE277 (RTD) [101]
and corresponding epitaxial layer structure is attached in appendix III The thickness
needed to be removed for the MESA step is 1421Aring compared to XMBE304 (ASPAT)
which is ~6900Aring
The fabrication results shown from the Air-Bridge design does not seem
favourable to the GaAsAlAs heterojunction sample These include unreproducible IV
characteristics and excessive undercut under the metal Therefore the GaAsAlAs
ASPAT sample cannot be processed using this type of mask (Air-Bridge approach) The
fabrication efforts were then moved to the Dielectric Bridge design described below
342313 DC measurement
Fully functional ASPAT I-V characteristics were not obtainable in this run due to
severe damages caused by the undercuts that happened underneath the top metal contact
As can be seen from Figure 315 the behaviour of the current response suggests a very
leaky diode This confirms that the air bridge approach does not work with the
GaAsAlAs ASPAT diode
Figure 315 Short circuit behaviour on one of the fabricated device in this run
-0015
-001
-0005
0
0005
001
0015
002
0025
003
0035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
mp
)
Voltage (Volt)
30x30BP
107
34232 Fabrication Process of the Dielectric-Bridge Design
Since the Air-Bridge design was not successful an alternative Dielectric-bridge
process flow was then designed to solve this issue The first run in this Dielectric-bridge
process was performed to ensure that when the fabrication was completed it was able to
produce the correct and reproducible ASPAT current-voltage characteristics The
process flow in this run is to follow the initial design which identifies the steps according
to the mask number Step 1 to step 4 in the process are exactly the same as in the 1st Gen
mask design Step 5 which is the bond pad process is then continued with spin coating
the AZ2microm After exposure and development a TiAu metal scheme with a minimum
thickness of approximately 1 microm is deposited
Table 36 Standard fabrication process flow for Dielectric-Bridge design
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa Etch
3 3 Isolation
4
5
6
7
4
5
6
7
Bottom Contact
Bond Pad
Via Etch
Bridge
Step 6 is quite complicated compared to the other steps where the introduction of
S1805 resist is used as a dielectric layer to prevent short circuit between top and bottom
contacts This includes opening the smallest via (holes within the dielectric layer) of 2times2
microm2 and 6times6 microm
2 emitter sizes This step started by spin-coating the S1805 resist and
was then followed by baking it at 150˚C for 30 minutes The longer baking time is to
ensure it is hard enough to be deployed as a dielectric layer Once the S1805 had
hardened as dielectric layer the sample was then spin-coated again with S1813 (thicker
resist) on the dielectric layer to act as a mask for vias opening (to cover the dielectric
layer from via etching damages) After the S813 was developed O2 plasma etches was
108
applied to remove the S1805 that covered the top metal and bond pads The hole on the
metal was then exposed This required only two minutersquos plasma etches time
As soon as the holes were created within the dielectric layer a quick clean to
remove S1813 was performed using Acetone and IPA This has to be fast enough to
remove the S1813 without removing the S1805 dielectric layer Mask 7 then defined the
area for the metal that will fill up into the open vias This metal connected the top
contact metal of the device to the bond pad (GSG pad) The same metal scheme as
mentioned in Section 3422 was used as the bond pad
The fabrication using the dielectric bridge approach in the 2nd
Gen mask design
appeared to work successfully when initial I-V characteristics were taken and it also
showed that the ASPAT diode was fully functional However using hardened S1805 as
a dielectric layer is not a good practise for manufacturing device since there were left
over residue on the sample surface as depicted in Figure 316 This residue comes from
the non-uniformity of S1805 resit that was formed during heat treatment Therefore the
next run was to avoid using S1805 but replacing it with a standard dielectric layer based
on Silicon nitrite (Si3N4)
Figure 316 The surface of the sample after final processing
342321 DC measurements
Given that the process of qualifying mask steps for GaAsAlAs ASPAT diodes
looked promising using the dielectric bridge approaches initial I-V characteristics
measurements were carried out for XMBE304A Figure 317 shows that the I-V
characteristics are comparable to those of the other runs ie in the 1st Gen mask
Noticeably the IV characteristic (Figure 317) between each device size does not scale
109
on a single line This is attributed to the unintentional variation in the size of the emitter
during wet etching within each sample
Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2 2500 microm2 900
microm2 400 microm2 225 microm2 100 microm2 and 36 microm2
The current densities shown in Figure 317 are calculated based on a reduced
effective area of the devices by a factor of 08 This assumption is made as actual area
(without metal) is un-measurable Theoretically devices with small areas will have
higher resistances compared to larger devices However the opposite occurred in these
devices This problem is still under investigation It could be due to the spreading
resistance producing different values according to device sizes (smaller devices have
longer D while bigger devices have shorter D)
34233 Dielectric-Bridge Process Optimization (Si3N4)
Due to poor surface roughness of the sample when using S1805 as dielectric
layer this run was employed to improve the surface quality by using Si3N4 In order to
get the actual size of the emitter the processing needed to start by defining the
semiconductor area using either top contact mask or mesa etch mask and not to deposit
the metal first Smaller effective area will be obtained if the top contact mask is used to
define the area compared to the MESA mask since there are 05 microm and 1 microm tolerances
designed in the MESA mask
-000001
0
000001
000002
000003
000004
000005
-2 -1 0 1 2
Cu
rren
t D
en
sity
(A
mp
microm
2 )
Voltage (Volt)
Current Density vs Voltage
density36
density100
density225
density400
density900
density2500
density10000
110
Table 37 New arrangement of the mask number and step in Second Run
Mask Number Step number Process
3 1 Isolation
22A 2 Mesa Etch
4 3 Bottom Contact
6
1
7
5
4
5
6
7
Via Etch
Top Contact
Bridge
Bond Pad
The fabrication was initiated by isolating each device using Mask 3 to define
them individually Then MESA mask (Mask 2) was used to cover the area from wet
etching optical measurement were used to obtain the actual size of the emitter without
metal Figure 318 shows the process results after H3P04H2O2H2O etching for a ratio of
3150
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm Tolerance
Although the mask was designed with smaller size of 6times6microm2 using the slow etchant
solution the effective emitter size can still shrink to ~3times3 microm2 and ~2times2 microm
2 as can be
seen in Figure 318 The next step was to define the bottom contact using a metal scheme
that is suitable for GaAs ohmic layer ie AuGeNiAu After lift-off the samples were
then cleaned and spin-coated with AZ2microm Then the area was defined by using Mask 6
allowing the exposed area to be filled by Si3N4 which is the dielectric layer used in the
second run However a tricky issue happened here as the Si3N4 was difficult to lift-off
especially on the smallest emitter area in this mask In this run the lift-off process was
successfully done after three days Step five which uses Mask 1 was to define the top
111
contact The same metal scheme will fill up the tiny holes within the dielectric layer to
attach on the emitter semiconductor Figure 319 below shows an optical image of a
6times6microm2
device after the top contact lift-off process Once lifted-off annealing took place
to ensure Ge diffuse into the GaAs contact layer to lower the resistance
Figure 319 After lift-off processing
Step six uses Mask 7 to define the area of metal connection between active areas
to the bond pad In this step and step seven a different metal scheme from the top and
bottom contact was used to connect metal to metal Here a TiAu scheme was used The
final step (step 7) was to define the bond pad area In this context mask 5 is used The
bond pad requires thicker metal thickness to reduce the series resistance and to increase
the robustness of the metal surface when probed with needles during measurements
This second run of 2nd
Gen mask dielectric approach went well with better samplersquos
surface when using Si3N4 as the dielectric layer compared to the previous run using
S1805 Once the bond pad were defined for each device as done in previous run the
preliminary current-voltage characteristics of the Si3N4 run were obtained This is
described in the next section
342331 DC measurements
As mentioned in the previous section the Si3N4 run started with a defined emitter
area This allows actual ASPAT dimension to be measured thus the current density
versus voltage that are plotted in the following figures are based on actual measured
sizes
112
Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
Although the actual area of each device is obtainable from measurement the current
density of this sample does not scale well either Figure 320 show the current density is
not scalable from 03V to 1V This probably happened due to the same issue related to
the spreading resistance for each diode varying To investigate this issue new runs were
required with intention of reducing Rsprd and were expected to lead to more scalable
devices Therefore a study of reducing the spreading resistance (Rsprd ) due to
contribution of the large D-gap was carried out using the 2nd
Gen mask with the Si3N4
dielectric bridge approach The following section discusses in detail the steps used in
reducing the gap between the top and bottom contact for the GaAsAlAs ASPAT diode
34234 Dielectric-Bridge (Si3N4) Process Optimization by varying the D-Gap
The series resistance as discussed in detail in Section 26322 is generally due to
the total contribution of specific contact resistance in particular the diode size the sum
of all doped layer resistances that sandwich the main ASPAT layer and the spreading
resistance which comes from the lateral structure diode design[33] Thus in order to
acquire better performance at high frequency these contributors must be controlled One
parameter that can be controlled through this fabrication process is to reduce the
spreading resistance by controlling the separation between top and bottom contact ie
the D-gap as indicated in Figure 321
-000001
0
000001
000002
000003
000004
000005
-1 -05 0 05 1
Cu
rren
t D
ensi
ty
(Am
pm
2)
Voltage (Volt)
Current Density vs Voltage
D36
D100
D225
D400
D900
D2500
D10000
113
Figure 321 side view of lateral ASPAT structure
Without designing a new mask at this stage the same 2nd
Gen Dielectric-Bridge
mask was used but the process flows did not follow the sequence order of mask
numbers The reason for deciding not to design a new mask to reduce the D-Gap was
because the fabrication process flow had not yet confirmed it repeatability and
reproducibility Thus the available photo mask at that moment was fully utilised
Furthermore the feature of the 2nd
Gen mask that included the mesa tolerance can be
exploited in this study Hence the initial idea was to reduce the length of D by using the
tolerance that was designed in with Mask 2 (MESA etch mask)
Table 38 New arrangement for the Third run using Dielectric-Bridge mask
Mask Number Step number Process
1 1 Mesa Etch
3 2 Isolation
3
2
3
4
Bottom Contact
Mesa Cover
6
1
7
5
5
6
7
8
Via Etch
Top Contact
Bridge
Bond Pad
The process therefore was initiated by cleaning the sample and was then
followed by spin-coating it with S1805 to cover the emitter contact and define the actual
D-gap
114
size of the diode This first step used Mask 1 with wet chemical etching using the slow
solution (H3P04H2O2H2O etch with a ratio of 3150) Once the resist was striped
optical measurements were performed to obtain the effective area of the emitter Figure
322 below shows the smallest emitter area obtained after etching
Figure 322 The measured size of the emitter area and the length D (blue color marked)
Step two was to isolate the devices individually by using Mask 3 This was
performed using the fast etch solution (H3P04H2O2H2O etch with ratio of 212) This
took about 10 seconds to remove about 10000Aring of material
Step three which involved two masks was the most complicated in this process
Firstly Mask 3 was used to define the bottom contact by covering the sample with
AZ2microm and then the sample was hard- baked at 190 ˚C for 4- 5 minutes to ensure it had
totally dried before applying Polydimethylglutarimide (PMGI) The PMGI type used in
this process is Lift-off Resist (LOR) SF11 After spin-coating the SF11 at 7000RPM for
45 seconds it was post-baked at 190 ˚C for 4 minutes This was done to ensure that the
LOR SF11 was hard enough for the S1805 to stick on it This was followed by spin-
coating S1805 at 4000RPM for 30 seconds and exposing it under i-line UV for 20
seconds and developed using Micro Dev mix with DI water (11 ratio) for one minute
When the correct shape of S1805 was formed the sample was exposed under flood UV
for 15 minutes The SF11 was developed with 101A developer for 1 minute Figure 323
below summarizes the whole process in step three The step three processes concluded
by depositing the bottom contact with alloyed metal scheme and once lift-off had taken
place the next step continues as usual
115
Figure 323 Summary of LOR technique steps
Step four as well as the subsequent steps were completed in this run by copying
from the previous run (ie second run) which was to deposit the Si3N4 as the dielectric
layer and so on All the devices that underwent fabrication using this technique were
measured under optical microscope MC60 assisted by the Walsall software tool in the
lab From the measured value obtained it was expected that reducing the length of D in
this technique would improve the spreading resistance by up to 70 from the original
2nd
Gen mask design Table 39 summarizes the calculation of original spreading
resistance and improvement using this technique The calculation method and equation
are taken from Section 26322
Table 39 The outcome of the spreading resistance before and after using LOR technique
Device Size(microm2) D-original(microm) RSprd(Ω) D-new(microm) RSprd(Ω)
100x100 4 056 163 023
50x50 14 327 194 054
30x30 19 602 163 097
20x20 21 832 212 135
15x15 22 1007 202 18
10x10 24 1293 205 252
6x6 25 1643 230 418
116
Technically from the experiment in this run it was observed that the development time
also controlled the final length of D longer development time produced shorter D
lengths while shorter time yielded larger D gap lengths Therefore in this run the
development time was kept constant because of the desired D length from the mesa
tolerance in general is only ~2microm
342341 DC measurement
As usual when wafer processing was completed early DC measurement took
place to check the diodes performance Each diode size was measured and compiled
into one graph as shown in Figure 324 It is clear that the performance was better than
that in the previous run in term of scalability and current conductivity
Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
To compare the current conductivity from this run and the previous run current
density at 05V was measured for both 2nd
and 3rd
runs Assuming the contact resistances
(TLM) for both runs were constant for 50times50microm2 device size the improvement of
current in the 3rd
run is about 92 This showed that such approach to reduce the D-gap
-500E-06
000E+00
500E-06
100E-05
150E-05
200E-05
-2 -15 -1 -05 0 05 1 15 2Cu
rre
nt
De
nsi
ty (
Amicro
m2)
Voltage (Volt)
Den_100microm2
Den_225microm2
Den_400microm2
Den_900microm2
Den_2500microm2
Den_10000microm2
Den2_36microm2
117
was successful in this run A new mask design was ready to take the challenge for
processing toward millimetre and sub-millimetre wave application
343 Fabrication process of GaAsAlAs ASPAT diode toward High frequency
Applications
So far the information that can be gathered from previous processing is that the
optimum process flow is achieved through dielectric approach design The effort in
reducing the series resistance by lowering its biggest contribution was attained through
lowering the D-Gap in the structure Once everything had been optimized ie the
process flow series resistance junction capacitance etc it was time to develop a new
mask design which only focused on the development of small ASPAT devices for use in
the millimetre and sub-millimetre wave regions
3431 Third Generation (3rd
Gen) mask design
The 3rd
Gen mask design was developed by taking into the account every aspect
of parameters that can contribute to the device by means of robust devices that are able
to function properly at ultra-high frequency The device cut-off frequency is given by
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(31)
Here RS is the series resistance and Cj is the junction capacitance To obtain high cut-off
frequencies Rs and Cj must be kept as low as possible From the fabrication point of
view two parameters that can be directly and easily controlled are the device area (A)
and the D-gap (which contributes to Rs)
Therefore calculations were made to find the best option Table 310 shows the
calculated value of capacitance (eq230 in page 44) and cut-off frequencies (eq31
above) for the ASPAT diodes studied These two equations extract the cut-off frequency
of the ASPAT assuming no external effects and for fully depleted devices The
XMBE304 ASPAT sample is expected to be suitable for millimetre wave applications
if small devices are successfully made In real devices sub-millimetrewave operation
can be hard to achieve due to increased series resistance and other process related
parasitics
118
Table 310 DC and RF characteristics for XMBE304
Device Size (microm2) Fully depleted
Capacitance(fF)
Calculated Series
Resistance (Ω)
Fully depleted Cut-Off
Frequency(GHz)
10000 5490 04 72
900 490 15 216
36 198 7 1148
16 879 11 1646
4 22 29 2500
Therefore in the 3rd
Gen mask design the smallest device that can possibly be obtained
in the GaAs based material fabricated using i-line lithography which is available at the
University of Manchester is 2times2microm2 and the gap between top and bottom is 15microm at
least The connecting bridge technique applied only utilised dielectric bridge method for
GSG features Figure 325 shows the layout of actual 3rd
Gen mask used in this study
There are 344 die chips on this type of mask design It also includes the Ground-signal
ground pad with 50um pitch for each chip and six de-embedding test structures as well
as eight TLM structures
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and alignment mark
structures used in this study
119
This mask is designed generally from optimizations from 2nd
Gen Mask which
deploys a dielectric bridge for connection between the devices to the bond pads
Consequently the processing steps are not being much different but mostly follow what
is shown in Table 311 below The difference only applies to the much smaller mesa
size Other features included in this mask are de-embedding structures for RF
measurements via-hole test structure TLM structures and parallel plate capacitance test
structures
Table 311 3rd
Gen Mask process step
Mask Number Step number Process
1 1 Mesa Etch
2 2 Isolation
3
4
3
4
Bottom Contact
Mesa Cover
5
6
7
5
6
7
Via Etch
Top Contact
Bond Pad
The high frequency fabrication process flow is summarized in the following section
which shows illustrations in three dimensional and cross sectional (Figure 326) views
for easy understanding
34311 Step by Step Processing
0 Wafer preparation
Cleaning using NMP and DI
water or
Acetone and IPA
120
1 Mesa Etch
2 Isolation
3 Bottom Contact
4 Mesa Cover (Dielectric Deposition)
5 Via Etch
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 3110
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 212
Metal deposition with metal
scheme AuGeNiAu for
~500nm thick
Dielectric deposition 500nm
thick Si3N4
Via etch to open holes for metal
contact using reactive ion
etching using CF4
121
6 Top Contact
7 Bridge and Bond Pad
Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-insulating
substrate device type used in this study
Figure 327 Example finished process device with bond pad using 3rd
Gen mask
3432 TLM measurements
Transmission Line model (TLM) measurements for this run were carried out
after annealing (ie at 420˚C for 2 minutes) for process control monitoring by extracting
contact resistance (Rc) values These values are a measure of the quality of ohmic metal
contacts for a given process As discussed in Chapter 2 the TLM technique used four-
Metal deposition with metal
scheme AuGeNiAu for ~500nm
thickness and thermal annealing
420˚C for 2 minutes
Metal deposition with metal
scheme TiAu (1microm thick)
122
point measurement on TLM test structures located around the 15times15mm2 tiles as shown
in Figure 222 (in page 55) Normally five TLM structures are measured across the tile
for both top and bottom contacts Figures 328 and 329 display graphical TLM results
for top and bottom contact respectively As can be seen both graphs exhibit excellent
uniformity
Figure 328 XMBE304 TLM measurement for the top contact after annealing
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing
Based on the graphs above for the top metal contact the average contact
resistance (RC) value using the metal scheme of AuGeNiAu is found to be ~005Ωmicrom
and the sheet resistance (RSH) is 22Ω However for the bottom contact the average
value for contact resistance is 012Ωmicrom and sheet resistance obtained is 26Ω Both
values are in a very good agreement with the known doping of both ohmic contact
0
2
4
6
8
10
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins top contact
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins bottom contact
y = 02157x + 01053
123
layers Therefore the specific contact resistance (Eq 250) that contributes to the total
series resistance can be calculated and the value obtained is 15Ωmicrom2 and 54Ωmicrom
2 for
top and bottom TLM structures respectively
3433 DC characteristic measurements
Again once the wafer processing is completed room temperature DC
characteristics are taken using an HP 414B or HP500B parameter analyser and its actual
setup is as described in Chapter 2 This initial measurement was to ensure the
functionality of the diodes For this run using the 3rd
Gen mask the I-V measurements
for mesa active area of 4times4microm2 6times6 microm
2 and 10times10 microm
2 were taken and are depicted in
Figure 330 Figure 331 and Figure 332 respectively Nine diodes were measured for
each three device sizes to check their uniformity Thus the average current and standard
deviation are taken at two voltage steps of 1V and 15V Table 312 summarizes the
standard deviation for each measured data obtained from this final run
Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
4times4microm2 mesa size
-00005
0
00005
0001
00015
0002
00025
0003
00035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C01_4um_1P_SI
C22_4um_1P_SI
C40_4um_1P_SI
W01_4um_1P_SI
W22_4um_1P_SI
W40_4um_1P_SI
AI01_4um_1P_SI
AI22_4um_1P_SI
AI40_4um_1P_SI
124
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
6times6microm2 mesa size
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature
for 10times10microm2 mesa size
Table 312 Standard deviation at two different voltages
Device size (um2) Standard Deviation 1V () Standard Deviation 15V ()
4times4 14 14
6times6 65 72
10times10 44 39
Noticeably the standard deviation of the device increases for the smaller size
devices This trend happened probably because the active mesa area is not uniform
causing different series resistances Since the smallest mesa active area which achieved
-0001
0
0001
0002
0003
0004
0005
0006
0007
0008
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C02_6um_1P_SI
C23_6um_1P_SI
C41_6um_1P_SI
W02_6um_1P_SI
W23_6um_1P_SI
W41_6um_1P_SI
AI02_6um_1P_SI
AI23_6um_1P_SI
AI41_6um_1P_SI
-0005
0
0005
001
0015
002
0025
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C03_10um_1P_SI
C24_10um_1P_SI
C42_10um_1P_SI
W03_10um_1P_SI
W24_10um_1P_SI
W42_10um_1P_SI
AI03_10um_1P_SI
AI24_10um_1P_SI
AI42_10um_1P_SI
125
a good I-V characteristic is 4times4microm2
in this run these devices were used for the next step
of characterisation which is the S-parameter measurement to extract their behaviour at
different frequencies
35 Conclusions
In this chapter basic fabrication techniques of GaAsAlAs ASPAT on both doped
and semi insulating substrates using standard I-line lithography as well as step by step
descriptions to achieve reproducibility in the process fabrication flow has been
demonstrated with relevant initial measured results Two major outcomes have been
demonstrated firstly related to repeatability reproducibility and manufacturability
mostly done on large device areas (15times15microm2 to 100times100 microm
2) Secondly a successful
process flow for small emitter size devices (2times2 microm2 to 10times10 microm
2) has been
developed
Subsequently two types of designs during process optimization were developed
namely Air-Bridge and Dielectric-Bridge approaches The latter approach seems
favourable for GaAsAlAs materials but was only successful when reducing the series
resistance of the device This problem was addressed by optimising the D-gap between
top and bottom contact which resulted in good scalability of each ASPAT dimensions
improving current conductivity by 92 and achieving a reproducible process On the
other hand in the former approach issues were encountered with over etching underneath
the diode effective area and thus it was hard to achieve reproducible devices
Repeatability reproducibility and manufacturability fabrication processes based on
dielectric bridge method were successfully developed This new process provides a
highly efficient and economical solution for the fabrication of GaAsAlAs ASPAT
diode Emitter sizes down to 4times4 microm2 dimensions are routinely and reproducibly
achieved in this process Series resistance which is an important parameter in
determining high frequency application are greatly reduced by changing the gap between
top and bottom contact
With all the new improvements implemented the possibility of the proposed Dielectric
Bridge method fabrication process was successfully applied for the fabrication of
ASPAT diodes
126
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT
DIODE USING SILVACO
41 Introduction
Fabricating any device or circuit requires a lot of time resources cost etc
especially elements related to the production of semiconductor devices Furthermore in
realising such a device a clean room is required Hence fabrication and processing in
wafer fab need full attention to get it done with a higher rate of success reproducibility
and manufacturability One solution that can be highlighted which will be able to reduce
all the resources that are mentioned above is by using computer simulation approaches
or to be precise physical modelling For epitaxial layer based devices physical
modelling is a good choice as it would give a better understanding and insight into each
layer and how electrical characteristics are derived A software that is most suitable for
epitaxial layer physically modelled is SILVACO This software is a very comprehensive
tool to simulate epitaxial based devices and to predict their behaviour Such software
covers many aspects starting from the first principles of physic epitaxial layer
definition as well as device layout thus making it the most powerful virtual wafer fab
tool in the market
In this chapter the SILVACO packages are discussed The discussions include the
method of defining a new material defining models and constructing the AC or DC
supply to obtain the output characteristics of the virtual device Apart from these the
focus will also be on the ASPAT diode modelling simulation and analyses of the results
which will include the ASPAT structure suitable models and DC current-voltage
characteristics The dependencies of individual structure on the I-V curves will also be
highlighted Finally the discussion of results and analyses involving a range of
operational temperatures dependency as well as from comparison made to conventional
SBD used in this study will be examined
127
42 SILVACO modelling Tools
SILVACO is a modelling software introduced in 1984 by Dr Ivan Pesic It is
purposely created for electronicsrsquo devices physical modelling and characterization This
software company has become the major supplier for most of the Electronic Design
Automation (EDA) for circuit simulation amp design of analogue Mixed-Signal and RF
circuit market This Technology Computer Aided Design (TCAD) software can predict
the simulated device performances starting from first principles It has a package which
can provide Virtual Wafer Fabrication (VWF) simulation to the device designer and
which has the capability to perform two or three dimensional physical device modelling
by using the ATLAS simulator [103] SILVACO allows all parameters such as
electrical thermal and optical characteristics of a device to be simulated under desired
bias conditions It offers cost effectiveness as well as quick prediction of results for
many semiconductor devices compared to real experiments Some hands-on experiment
may not always perform hence SILVACO can be used as an alternative
The core of SILVACO is Atlas itself which provides a platform to perform DC AC
and transient analysis for such dimensional device structure regardless of the
heterojunction material type ie binary ternary quaternary etc As the brain of
SILVACO Atlas which receives input command files containing instruction text for
execution from a runtime environment known as Decbuild will process the instruction
text and display progression error and warning via Runtime Output All the calculations
of the resultsoutcomes of the simulation are plotted via a tool called TonyPlot which is a
tool to visualise the output Figure 41 below shows how precisely the physical
modelling takes place the process of building the structure how its parameters and
variables are defined how an appropriate model statement is selected how performance
is analysed and lastly how the outcomes are displayed
128
Figure 41 SILVACO Atlas simulation process flow
As can be seen in Figure 41 the structure specification statement is used to define
any desired structure by setting the command in Deckbuid of the following parameters
a) Mesh where the structure can be defined either in 2D or 3D Cartesian grids The
unit of the coordinates used is in microns and the spacing parameters which
define the netting size can be used to improve the accuracy of the analysis at any
given position The density of netting size in this statement determines the
processing time
b) Region where the multi-layers in a structure are defined and this statement has
to outline each layer that represents a separated region independently The mesh
must be assigned to a region and the sequence of the region is arranged from low
to high
-Mesh -Region -Electrode
-Contact -Material
Structure Specification
-Model -Interface
Model Specification
Method
Numerical Method
-Log -Solve -Load -Save
Solution Specification
-Tony Plot
Display Results
129
c) Electrode are used to define the location of bias point for a designed structure
when performing the electrical analysis In this work or for the case of a diode
two electrodes are allocated as an anode and a cathode In a vertical device the
latter electrode is placed at the bottom of the device while the anode is at the top
d) Doping this statement refers to doping concentration injected into the desired
region and it normally depends on the material types
e) Materials since SILVACO was developed specifically for Silicon-based devices
default parameters are set up for Silicon properties However the use of
materials statement allows SILVACO to run for different material ie GaAs
InGaAs etc In order to make it work this parameter is defined first and then
followed by the material name and its properties such as bandgap permittivity
conductionamp valence band discontinuities mobility etc
The most crucial part is to determine whether the simulated structure of a particular
device is correct or incorrect This is done by properly choosing the specific model
statement The Specific model statement is employed to express the physic equations
that are used during the device analysis The models statement depends solely on the
structure definition Examples are device structure with double barrier use Non-
equilibrium Green function (NEGF) model and single barrier uses Semiconductor-
insulator-Semiconductor (SIS) model for effective and accurate analysis process For the
case of a single barrier in SILVACO there are many model statements that can be used
for such analysis Therefore it is recommended to check model by model in order to
ensure that all the needed parameters are defined in the material statements and results
produced are valid
SILVACO is able to calculate such models by using different numerical methods
which means semiconductor device problematic is computed to make successive
solutions by random discretisation There are three different numerical methods that are
regularly used by SILVACO to perform its calculations which are Newton Gummel and
Block Basically this is solved by using a non-linear iteration procedure which begins
from an initial guess and which then uses an iterative process to find the predicted
solution The detail of these can be found in reference [103]
130
In order to turn on the problem solution the solution specification is defined This
include log solve save and load statement All these work together to provide data for
analysis by other functions The log statement is a file type that saves in memory and can
be loaded by Atlas Any solved device will be stored in the log file Therefore it is
necessary to define the LOG before SOLVE statement and close it after the calculations
While the save statement is used to store all data point to a node in the output file the
load statement is utilised to recall all the saved data to be read by Atlas
Finally all these files can be displayed or plotted on TonyPlot it is recommended to
make SET files at plotting point for a better visualisation The plotted or displayed files
in TonyPlot can be manipulated for scaling graphs overlaying different curves and most
importantly to export the data to other files formats
43 SILVACO Implementation GaAs AlAs ASPAT Modelling
The structures play an important role in determining the terminal output
characteristics Therefore to start simulating the ASPAT device the first thing that must
be specified is its structure As mentioned earlier in Section 3412 the ASPAT diode is
a top down multilayer structure This structure which is adopted from that of Section
3412 will be used as a basis to perform the ASPAT simulation Figure 42 shows the
structure of the ASPAT in this real simulation which is exactly the same as been
discussed in Section 26322 The ASPAT diode consists of two heavily doped (up to
5x1018119888119898minus3) GaAs contact layers on top and bottom slices adjacent to lightly doped (up
to 3x1017119888119898minus3) GaAs intermediate layers In between these layers is a sandwiched
structure consisting of two different lengths of undoped GaAs spacer layers and a thin
layer of AlAs that act as a tunnel barrier In this work the simulation result will be
compared with the fabricated measurement result depending on the size of the diode
The actual device that will be used to validate the simulation is the main device used in
this study (XMBE304) which is based on a lattice matched GaAsAlAs grown on a
semi-insulating substrate Therefore the design structures that are proposed in the
fabrication are compatible with the fabricated devices and are based on lateral structures
as can be seen in Figure 42
131
Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the diode
multilayer heterostructures on the right
In the consequent simulations a key observation regarding the AlAsGaAs
heterojunction is that there are two types of tunnelling processes direct tunnelling and
indirect tunnelling Figure 43 shows the Energy-Momentum (Ek) diagram depicting the
three valleys for the AlAs conduction band namely L Γ and X points In normal
circumstances the transition of electrons happens to the X-point which is the lowest
energy in the conduction band In the case of very thin barrier the tunnelling process
occurs at the Γ point in both AlAs and GaAs materials which is the direct tunnelling
process[18] It has been reported that in the case of an ASPAT diode tunnelling which
occurs at the Γ point will be the dominant component in the tunnelling current
Therefore the actual band gap will be different from the one at the X-point which is
which 216eV[15] By contrast the energy band gap at the Γ-point is around
283eV[104] Thus this simulation uses this band gap value
Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor
216eV
Γ
X
E
K
L
AlAs
CB
VB
283e
132
The simulation code as attached in Appendix IV and the output of the simulation with all
the input mentioned above are shown in Figure 44 (a) and Figure 44 (b) Figure 44 (a)
is the band diagram at equilibrium and Figure 44 (b) is the band diagram when a bias is
applied
Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure (b) the
energy band diagram of the ASPAT diode structure when under three different biases
44 Simulation Result and Analysis
Basically the SILVACOrsquos Atlas simulation package is used to calculate the I-V
characteristics from multilayers structures In the case of GaAsAlAs heterojunctions all
details of the structure as shown in Figure 44 above are calculated based on solving the
Schrodinger time-independent equation in each layer taking into account the variation of
effective mass and conduction band offset between GaAs and AlAs
For thermionic emission and tunnelling mechanism across an abrupt heterojunction
interface the general method used in SILVACO is taken from K Y Yang work [105]
The tunnelling current of the ASPAT diode uses the equation below[74]
119869 = sum2119898lowast119864119894(1 minus 119877)119896119879
1205872ħ3
119873
119894=1ln [
1 + exp (119864119865 minus 119864119894
119896119879)
1 + exp (119864119865 minus 119881 minus 119864119894
119896119879)]
(41)
Where m is the electron effective mass E denotes the energy of the electron R is the
total resistance k represent Boltzmann constant ħ is the reduced Planck constant EF is
the fermi level V is applied voltage and Ei is the electron energy perpendicular to the
-2
-15
-1
-05
0
05
1
15
1
82
16
3
24
4
32
5
40
6
48
7
56
8
64
9
73
0
81
1
89
2
97
3
Ene
rgy(
eV
)
Thickness (microm)
VB
CB
133
barrier The important parameters that enable SILVACO Atlas to perform correct
calculations and analysis are the choice of appropriate models The suitable model that is
available for evaluating the GaAsAlAs ASPAT is based on the Semiconductor-
insulator-semiconductor (SIS) model
Thus in this run Non-local Quantum Barrier Tunnelling Model (SISEL and
SISHO) are utilized specifically semiconductor-insulator-semiconductor mode This
model enables the tunnelling current between two semiconducting regions separated by a
quantum barrier to be calculated [103] It is assumed that the charge tunnels across the
whole barrier with the source or sinks at the interface with the semiconductor regions
Under the Non-Local Quantum Barrier tunnelling model another model that can be used
is semiconductor-semiconductor-semiconductor (SS) tunnelling model if the materials
are specified By correctly inserting all parameters with the right model an excellent DC
IV characteristic match between simulation and measurement can be produced as shown
in Figure 45
441 DC Current-Voltage Characteristic
In this simulation the current at each bias step and each mesh point can be set up by the
user however the detailed calculation such as formula usage methodology and
approach that is adopted by SILVACO Atlas is unknown As mentioned above in order
to produce the energy band diagram of the ASPAT the DC characteristic of the structure
can be solved by using the Schroumldinger and Poisson equation self-consistently
To ensure that these simulations are valid one fabrication was performed on an
ASPAT diode sample XMBE304 For this sample the structure parameters are the
same as has been set in this simulation The result of the measurement and simulation
are then compared Figure 45 shows that the simulation result is in excellent agreement
with the measured data for this sample
134
Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm2) and (4times4microm
2)
using SILVACO Atlas simulator for structure device XMBE304 showing excellent agreement
between simulated and experimental data
These fitted results were performed on both a large 100times100microm2 device and the
smallest obtainable from fabrication (4times4microm2) which was to be used for the repeatability
amp reproducibility studies as well as for high-frequency applications study respectively at
room temperature In order to get a good fit a few parameters had been modified in the
SILVACO software via the Deck-built tool for example energy band effective masses
and bandgap discontinuity of GaAs spacer and AlAs barrier (The mentioned parameters
values are summarized in Table 41) The percentages of bandgap discontinuity in
SILVACO using the ALIGN parameter is given by[103]
119860119897119894119892119899 =
Δ119864119862
Δ119864119862 + Δ119864119881
(42)
Where ΔEc and ΔEv are the conduction band discontinuity and valence band
discontinuity respectively The m0 in the tables denotes the electron rest mass Once all
agreement between measurement and simulation has been met the simulation is then
carried out with structure analysis at room temperature and different temperatures
simulation
Table 41 The parameter values used in this simulation
Material Bandgap(eV) ΔEg(eV) Effective mass(kg)
GaAs 1424 03 0067m0
AlAs 2835 071 0126m0
-00002
0
00002
00004
00006
00008
0001
00012
-2 -1 0 1 2
Cu
rre
nt
I (A
mp
)
Voltage V (Volt)
Current vs Voltage
Measurment
Simulation
135
45 Structure Analysis of ASPAT Diode
Once the device structure was modelled and having successfully produced a
precise band diagram as well as validated the simulation results with experimental I-V
characteristics the next step is to further analyse the relationship between basic device
structure and its I-V characteristics This approach is used to predict what would happen
to the DC output if some of the parameters were varied especially with regards to the
AlAs barrier thickness In the subsequence simulations the thickness of each main
ASPAT (unequal spacers and barrier) layer will be studied independently as a variable in
order to determine how each parameter affects the I-V characteristic in both magnitude
and curvature The analysis will also include manufacturing tolerance where the
structure parameter which will result in a 10 difference in their I-V characteristics is
examined[59 75] This will provide an overview of how precisely to manufacture each
layer of the device The following simulation is based on the XMBE304 structure with
emitter size of 4x4microm2
451 Dependencies of current on AlAs Barrier thickness
Since the AlAs barrier is what limits the transportation of electron flow and
hence the current (which depends exponentially on the tunnelling barrier thickness)
therefore the first analysis to run on the simulation is the variation on barrier thickness
In the simulation the barrier thickness is measured in term of the monolayer Generally
one monolayer can be calculated by dividing the lattice constant of the material by two
In the case of AlAs one monolayer is calculated as follows
119900119899119890 119898119900119899119900119897119886119910119890119903(1119872119871) =
119860119897119860119904 119897119886119905119905119894119888119890 119898119886119905119888ℎ119890119889 (5666Å)
2
(43)
= 283Å
The nominal value of the AlAs barrier thickness for sample XMBE304 is 283nm
ie ten monolayers In the first simulation test the current change due to the barrier
thickness variation from 9ML to 11ML was examined first followed by the amount of
barrier thickness change that would produce a 10 change in current The simulation is
setup by fixing all other parameters and varying the AlAs barrier thickness as mentioned
136
above with a step of 02ML In order to determine what fraction of a ML would yield a
10 difference in the current the barrier thickness is slightly changed to fit the curve for
both 5 above and 5 below the original curve
Figure 46 IV characteristics of the dependencies of current on AlAs barrier
The current-voltage characteristics of the ASPAT diode do change dramatically with
barrier thickness in forward bias but not that much in reverse bias (Figure 46) The
current decreases as the barrier thickness increases For a 1ML change in layer thickness
(from 9ML to 11ML) the current changes by over ~300 at 05V
Figure 47 Example of analysis at -1 and 1V to the current
-00002
0
00002
00004
00006
00008
0001
00012
00014
-15 -1 -05 0 05 1 15
Cu
rre
nt
(A)
Voltage(V)
9ML
92ML
94ML
96ML
98ML
10ML
102ML
104ML
106ML
108ML
11ML
973E-06
0
0000005
000001
0000015
000002
0000025
000003
0000035
85 95 105 115
Cu
rren
t a
t 1V
B
ias
(Am
p)
Barrier Thickness (ML)
Current change with tunnel barrier thickness
Forward Current
5
-5
137
From the simulation result shown in Figure 46 a 9945ML barrier thickness will
give a 5 higher current and a 10056ML barrier will give a 5 lower current (Figure
47) Therefore in total 01 ML difference yields 10 current difference These indicate
that in order to control the current within 10 barrier thickness difference the growth
precision in the barrier must be precise to better than 01ML Extensive studies have
also shown that the I-V characteristic of a GaAsAlAsGaAs diode is very sensitive to
the thickness of AlAs barrier This work has been reported elsewhere[17]
452 Dependence of current on Spacer I length l1
For the longer spacer length (l1) five different values are chosen from 01microm to
03microm The lengths are changed in the order of 005microm Therefore the arrangement of
length is as follows l1=01microm l1=015microm l1=02microm l1=0 25microm and l1=03microm
respectively The results are plotted from -15V to 15V anode voltage in Figure 48 The
I-V characteristic of the ASPAT diode does not change much with the length in the
forward bias region but in the reverse bias region the current decreases as the layer
thickness increases Here the l1 layer acts as a voltage arm and a small size device
cannot sustain big changes in spacer length Changing the length at the forward region
will also change the energy states on the anode side as well changing the states
distribution on the cathode side in reverse bias
Figure 48 I-V characteristic of the dependencies current to Spacer I layer
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=01
L=015
L=02
L=025
L=03
138
By fixing the current at -1V and 1V the current and the layer thickness relationship is
illustrated in Figure 49
Figure 49 Current changes with layer thickness l1
It is noticeable that there is a dramatic change in reverse current from 01 microm to
05 microm layer thicknesses However the forward current only falls slightly from 01microm to
015microm and is stable afterwards Hence for a small size device a large change in spacer
layer at the cathode will allow more current to pass
453 Dependence of current on Spacer II length l2
Finally is the variation in the spacer II Similar to spacer I above five values are
chosen for the shorter undoped GaAs layer length l2 the thickness is varied from
00025microm to 00075 microm (steps are l2=00025microm l2=000375microm l2=0005microm
l2=000625microm and l2=00075microm respectively The results are plotted from -15V to
15V anode voltage as shown in Figure 410 In this case a slight change in I-V
characteristic in the forward bias can be seen clearly which means the I-V
characteristic depends on the length of the shorter undoped layer Therefore the l2 layer
also acts as another voltage arm due to the asymmetrical length The effect is quite
similar to the spacer l1 but this times the forward current only slight changes The reason
for the small change in current is that the length change is small and it linearly affect the
states distribution
-000002
-0000018
-0000016
-0000014
-0000012
-000001
-0000008
-0000006
-0000004
-0000002
0
0
000005
00001
000015
00002
000025
00003
000035
01 015 02 025 03
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)Reverse Current(-1V)
139
Figure 410 IV characteristic of the dependencies current to Spacer 1 layer
Fixing the current at -1V and 1V the current versus layer thickness relationship is
illustrated in Figure 411
Figure 411Current change with layer thickness l2
The I-V curve depends on the length of the shorter undoped spacer layer quite linearly
The forward current changes in increase to the layer compared to the backward current
The layer thickness l2 should be small as long as it prevents carrier diffusion Therefore
all these three layers must be kept within limit to ensure that the high performance of the
ASPAT diode can be fully utilised
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=75n
L=25n
L=625n
L=5n
L=375n
-2E-07
-18E-07
-16E-07
-14E-07
-12E-07
-1E-07
-8E-08
-6E-08
-4E-08
-2E-08
0
0
00002
00004
00006
00008
0001
00012
0002 0004 0006 0008
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)
Reverse Current(-1V)
140
46 Temperature Dependent Simulation
This section will discuss in detail how changes in operating temperatures influence
the IV characteristics of the ASPAT diode The same codes as in the previous
simulation with fitted results are used for this temperature dependence study but a few
parameters were changed for different temperatures
Theoretically the material parameters that are influenced by the change of
temperature are band gap electron effective mass the density of state (NC NV) light
hole mass heavy hole mass permittivity and electron amp hole mobilities However not
all mentioned parameters will have a large impact on the IV characteristic in the
SILVACO Atlas simulation The most significant factors that give appreciable impact on
the DC output current-voltage were the energy bandgap and the effective mass The
GaAs bandgap as a function of temperature is given by the equation below [106]
119864119892 = 1198641198920 minus
120572 1198791198712
120573 + 119879119871
(44)
Here Eg is the bandgap Eg0 denotes the bandgap at 0K TL is the Temperature α=
Constant (Varshni Parameter) AlAs6e-4 GaAs5405e-4 β= Constant (Varshni
Parameter) AlAs408 and GaAs204 The calculated parameters that are used in this
simulation are shown in Table 42
Table 42 The calculated values of bandgap at different temperatures
Temperature (K) GaAs Eg(eV) AlAs Eg(eV)
77 1506 2903
100 1500 2899
125 149 2893
150 1486 2887
175 1478 2879
200 1470 2871
225 1461 2863
250 1452 2854
275 1443 2844
300 1424 2835
325 1419 2824
350 1414 2814
375 1404 2803
398 1394 2793
141
The effective mass of the materials used in this simulation can be expressed by
119898119899 = 1198980119899 + 11989810 (
119879119871
300119870)
119898119901 = 1198980119901 + 1198981119901 (119879119871
300119870) + 1198982119901 (
119879119871
300119870)2
(45)
Where mn is the effective electron mass mp represents the effective hole mass m1n and
m1p are constant number for the basic GaAs material m0n
for 119898119883119898119871 119886119903119890 119892119894119907119890119899 119887119910 119905ℎ119890 119890119902119906119886119905119894119900119899 (1198981198991199052 lowast 119898119899119897)
13 while m0p is based on the
expression 1198980119901 = (11989811990111989732
+ 119898119901ℎ32
)23 The calculated parameters are shown in Table
43
Table 43 The calculated effective masses for each temperature used in this simulation
Temperatures (K) GaAs Effective Mass (kg) AlAs Effective Mass (kg)
77 00660m0 03790 m0
100 00658 m0 03788 m0
125 00655 m0 03785 m0
150 00652 m0 03782 m0
175 00649 m0 03779 m0
200 00646 m0 03776 m0
225 00643 m0 03773 m0
250 0064 m0 0377 m0
275 00637 m0 03767 m0
300 00634 m0 03764 m0
325 00631 m0 03761 m0
350 00628 m0 03758 m0
375 00625 m0 03755 m0
398 00622 m0 03752 m0
142
Figure 412 Measurement and simulation comparison result as a function of temperature range
from 100K to 398K
Figure 412 above shows excellent agreement between simulation and
measurement results at various temperatures The IV characteristics correspond to a
device of size 100times100microm2 as presented in Chapter 3
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes
As mentioned earlier in chapter one the tunnelling diode has many advantages
over conventional Schottky barrier diodes some of which are a large dynamic range
low power consumption and very weak temperature dependence This section will
discuss the effect of variable temperature applied to the GaAsAlAs ASPAT diode and a
similarly processed TiAu Schottky diode Two samples were fabricated together for
these studies (XMBE304 and XMBE104 representing an ASPAT and a SBD
respectively) The fabrication technique is exactly the same as has been discussed in
Chapter 3 In order to make it fair for direct comparisons as well as easy probing both
diodes were fabricated with the same emitter size (100times100microm2) The DC measurements
at different temperature were carried out using a Lakeshore Cryogenic probe station over
the range of 77K to 398K in 25K step interval
-002
-001
0
001
002
003
004
005
006
-2 -15 -1 -05 0 05 1 15 2
Cu
rren
t I
(Am
p)
Voltage V (Volt)
T=100K_Simu
T=100K_Meas
T=398K_Simu
T=398K_Meas
T=200K_Simu
T=200K_Meas
T=300K_Simu
T=300K_Meas
143
471 GaAsAlAs ASPAT diode vs TiAu SBD
Once fabrication and measurement were completed both DC outputs of the diodes
were characterised and analysed Figure 413 shows a semi-logarithmic plot for
measured current versus voltage as a function of temperature for ASPAT sample
XMBE304 In forwards bias the current changes for different temperatures from 77K
to 398K are less than 5 percent This confirms the very weak temperature dependence of
current transport as it is dominated by tunnelling through the barrier On the other hand
the backward bias shows the current changes at different temperature are slightly bigger
than in forward this due to band bending occurring faster (making the effective barrier
lower) and allowing thermionic emission to significantly contribute to transport of the
current The only other study of temperature dependence for the ASPAT was made by et
el RT Syme[15] but details were not stated in their report
Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample XMBE304
The effective barrier height for the GaAsAlAs ASPAT diode is higher than that of
the SBD (See Figure 414) therefore there is an expectation of more limited thermionic
current flow in the ASPAT than the SBD As mentioned earlier the conventional
Schottky Barrier diode that is used in this study consists of a Gold Titanium and GaAs
(AuTiGaAs) interface which is the baseline for the temperature dependence study
0000001
000001
00001
0001
001
-15 -1 -05 0 05 1 15
Log
Cu
rren
t (A
)
Voltage (V)
T=77K
T=100K
T=125K
T=150K
T=175K
T=200K
T=225K
T=250K
T=275K
T=300K
T=325K
T=350K
T=375K
T=398K
144
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT Diode [3]
The SBD epitaxial layers profile is as shown in Table 44 below Theoretically the SBD
obey thermionic emission transport[44] and its I-V characteristic is given by
119868 = 1198680[exp (
119902119881
119899119896119879) minus 1]
(46)
Where q is the electron charge V is the applied voltage across the diode n denotes the
diode ideality factor k is the Boltzmann Constant T is the absolute temperature in
Kelvin and I0 is the diode saturation current which is given by the expression
1198680 = 119860119860lowast1198792 exp (minus
119902empty1198870
119899119896119879) exp (minus120572120594119890
12120575)
(47)
here A is the area of the diode A denotes the effective Richardson constant Oslashb0 is the
barrier height at zero bias δ represents the thickness of interfacial insulator layer χ
denotes the mean tunnelling barrier and α = radic(4120587
ℎ)(2119898lowast) is a constant value The
ideality factor n is taken from the slope of the SBD current-voltage characteristic and in
this study its value varies from 1 to 2 (depending on temperature) In the case of the
ASPAT diode thermionic emission can also happen if a thicker barrier is used (~ 100Aring
or thicker) as shown by CS Kyono et el [104] who concluded that when a thicker
barrier of AlAs barrier is used the current transport is dominated by thermionic emission
145
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104)
Layer Material Doping(cm-3
) Thickness(Aring) Bandgap (eV)
Schottky GaAs(Si) 500E+15 7500 14
Semiconductor GaAs(Si) 300E+16 7500 14
Semiconductor GaAs(Si) 100E+17 7500 14
Ohmic GaAs(Si) 500E+17 7500 14
Buffer GaAs(Si) 300E+18 7500 14
Substrate GaAs(Si) N+ 3000 14
The fabricated SBD was also measured and its I-V characteristic is plotted as a
function of temperature in Figure 415 Unlike the ASPAT diode the current at forward
bias for the SBD change enormously with temperature from 77K to 398K and at all
biases For the ASPAT diode the slight change in current only started after 08V bias as
the current starts to have some component of thermionic emission over barrier
Figure 415 Log Current vs voltage as a function of temperature for SBD sample XMBE104
In order to see clearly how much the current is changing in forward bias for both
ASPAT and SBDs diode a log current at different voltages versus 1000temperature is
plotted as shown in Figure 416
1E-08
00000001
0000001
000001
00001
0001
001
01
-2 -1 0 1 2
Log
Cu
rren
t (A
)
Voltage (V)
T=398K
T=375K
T=350K
T=325K
T=300K
T=275K
T=250K
T=225K
T=200K
T=175K
T=150K
T=125K
T=100K
T=77K
146
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and SBD
Semi-logarithmic plots of current (at V= 05 06 07 08V) versus inverse
temperature for both SBD and ASPAT are shown in Figure 416 When the temperature
is increased the current also increases in the SBD as a result of thermionic emission
over the barrier for sample XMBE104 This is in contrast to the temperature-
independent tunnelling through the thin AlAs barrier of sample XMBE304 ASPAT
diode where when the temperature is increased the current is almost constant
At low and high temperatures the ASPAT shows excellent temperature
independence with a constant current flow It exhibits a tunnelling current in excess of
values expected by the elastic tunnelling current calculation equation suggested by RT
Syme [16 18] above (Eq 1) using a Oslash value of 105eV (ΓGaAs to Γ AlAs tunnelling) By
contrast for the SBD at low temperature (77K-275K) the changes of currents were very
high and for every 02V there is an exponential change of more than 40 This
temperature dependent study was also reported in[68]
147
48 Conclusions
This chapter demonstrated the establishment of an excellent physical model and
comparison of room temperature I-V characteristics of GaAsAlAs ASPAT diodes for
different emitter sizes their scalability as well as an investigation of their characteristics
at different temperatures from 77K to 398K Simulation are validated on well-
characterized experimental data and excellent fitting which had been achieved in this
work permit the designer to extract all related parameters of heterojunctionmultilayer
ASPAT structures thus creating modification for future growth specification in order to
achieved precise designs
It is clear that the work which had been carried out in this chapter is able to
achieve with adequate accuracy a claim of reverse engineering capability The ability of
the GaAsAlAs ASPAT to act as a zero-bias detector has been analysed and compared
with the SBD It is clear that the temperature stability which is shown by the
GaAsAlAs ASPAT is much better than that of the SBD thus demonstrating that the
tunnelling current is dominant over the thermionic emission in ASPAT diodes
148
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES
51 Introduction
To assist in circuit designs for any type of high-frequency circuits such as
millimetre wave detectors frequency multipliers and mixer circuits which are built
based on non-linear devices (diodes) an equivalent-circuit model for the diode is
required This is among the simplest and most effective method for analysing
semiconductor devices which work at high frequency where the electrical characteristics
measured obtained from the devices are extracted and presented in a circuit consisting of
lumped elements components (resistor inductor capacitor etc) However accurate DC
and RF measurement data is essential to extract the equivalent-circuit elements quickly
and correctly The extracted parameters values from the circuit that are taken into
account usually depends on bias and frequency associated with the device physically
which is also interrelated to the semiconductor material parameters device structure as
well as fabrication process flows
In this work the DC and RF data were derived from DC and S-parameter
measurements respectively These measurements were carried out both in-house and at
the University of Cambridge by a collaborator partner (Prof MJ Kelly) The I-V
characteristics of the diode obtained from DC measurements were measured from -2V to
2V while the S-parameters were carried out over a wide frequency range from 40MHz to
40GHz with eight different biases In this chapter the DC measurements for various
sizes of the diodes with analysis of their IV characteristics will be discussed The one-
port on-wafer ASPAT measurement setup as well as the de-embedding method will
also be explained Thereafter the equivalent circuit models with all lumped element
effect will be discussed This work is carried out with the help of the VNA which
principle has been described in Chapter 2 and Keysight ADS simulation tool All
technical details regarding the equivalent circuit models will be explained together with
the method used for the ASPAT diode evaluation The equivalent circuit model also will
cover the diode intrinsic elements such as Cj Rj and Rs and extrinsic elements ie CP
149
and RP Finally an equivalent circuit model with the small signal characterization of the
fabricated ASPAT diodes will be presented
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes
The recent development of state-of-art for DC measurement apparatus has led to
capabilities for high-level accuracy of measuring voltages to a few nano Volts and
current signals in the femto Amp range[107] This can easily be obtained by exploitation
of proper connections and high-quality cables connecting the equipment to the Device
under Test (DUT) In this work the DC measurements were carried out using an Agilent
B1500A Parameter analyser whose description was covered in Chapter 2
As was discussed in Chapter 3 the GaAsAlAs ASPAT diodes have been
fabricated with different mesa areas between 2times2microm2 to 100times100microm
2 but the smallest
size obtained with good I-Vs was 4times4microm2 In this section the focus will be on how the
extracted data can be expanded further for empirical modelling Figure 51 shows typical
results for measured ASPAT diodes with various dimensions to check for their
uniformity According to our standard procedure the DC measurement has to be
conducted prior to the RF to ensure the diode is in fully working order as this will later
save a lot of time during RF characterization
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2 6x6um
2 and
10x10um2 Note the good scalability
1E-10
1E-09
1E-08
00000001
0000001
000001
00001
0001-2 -1 0 1 2
Cu
rre
nt
De
nsi
ti (
Amicro
m2)
Voltage (V)
4x4microm^2
6x6microm^2
10x10microm^2
150
Figure 51 above demonstrates the IV Characteristics of measured GaAsAlAs
ASPAT diodes (XMBE304) for emitter sizes of 4times4um2 6times6um
2 and 10times10um
2 This
sample was processed using the dielectric bridge technique developed in this work It
can be observed that current per unit area for each dimension fits and scales to each
other The scalability of each diodes measurement is very important to ensure no process
related issues are hampering the devicersquos proper operations This also confirms that the
diodes are completely functional and can be used for the next stage of measurements
The advantage of having an excellent scalability of those diode sizes is that a prediction
of smaller emitter size can be made
This type of IV characteristic shows asymmetric behaviour which results from
the unequal spacer lengths of the device This behaviour is very useful for detection
application as it obeys a square law model The square law predicts that the current is
proportional to the square of the applied bias
119868 = 1198861198812 119908ℎ119890119899 119881 gt 0
119868 = 0 119908ℎ119890119899 119881 lt 0
(51)
To extract the first order effects of ASPAT diodes DC measurements which
result in asymmetric I-V characteristics are analysed The slope of the non-linear region
is used to determine the junction resistance (Rj) which is obtained from the first
derivative of voltage versus current (dVdI) The expression of Rj is given by
119877119895 =
120597119881
120597119868
(52)
In order to understand the relationship between Rj and diode sizes of the ASPAT the IV
characteristic for each diode displayed in Figure 51 is used to extract the Rj This has
been done by using the expression in equation (52) above and their response is plotted
against bias as displayed in Figure 52
151
Figure 52 Junction resistance versus voltage
As can be seen in the Figure 52 above the Rj for each device decreases strongly
when the voltage increases At zero bias the 4times4um2 devices show the highest Rj value
followed by 6times6um2 and 10times10um
2 devices The junction resistance at zero bias obtained
from the 4times4um2 diode is around 86KΩ while reducing by a third for the 6times6um
2 and
10times10um2 diodes with Rj of 27KΩ and 10KΩ respectively A diode with a smaller
forward current under the same applied voltage will exhibit a larger Rj For a good
millimetre wave detector a device with a large value of Rj is desirable since it will
provide high detection sensitivity
The slope at the IV characteristic contributes to an important parameter that is
commonly used by electronic manufacturers to describe diode specification namely the
video impedance (RV) which is also known as the non-linear resistance The RV which is
extracted from the real part of the diode small signal impedance is highly dependent on
the DC bias current and only weakly depends on the series resistance of the diode (RS)
Therefore the video impedance is given by
119877119881 = 119877119895 + 119877119878 (53)
Where RS is the series resistance of the diode whose value is normally very small and
does not contribute much to the whole slope and hence RV is dominated by Rj The RV
changes in behaviour if any DC current is flowing through the diode Practically small
DC current in the range of 1 to 10 microAmp or total zero bias is used to maintain the
appropriate RV value (1-2KΩ to several MΩ) RV will also determine the voltage
-10
10
30
50
70
90
110
130
150
-01 0 01 02 03
Rj(
KΩ
)
Voltage (V)
6x6um^2
10x10um^2
4x4um^2
152
sensitivity of the whole detector circuit This will be explained further in the next
chapter In the case of a detector with an amplifier RV of the diode acts as the RF
impedance which needs to be matched with the video amplifier ( impedance looking into
the diode from the amplifier)[108 109]
The quotient of the second order derivative to the first derivative
((d2IdV
2)dIdV)) when calculated from the whole I-V characteristic translates directly
into a curvature coefficient (k) This is the most commonly used figure-of-merit to
quantify diode nonlinearity at zero bias Figure 53 below shows the variation of k with
bias and more importantly the zero bias rectifying action for device sizes of 4times4 um2
6times6 um2 10times10 um
2 This parameter which represents the small-signal rectifying
action of the diode will affect the performance of the detector (voltage sensitivity)
Detailed discussions on how this parameter effect the detector performance will also be
discussed in the next chapter
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT high sensitivity
near zero bias detection
Figure 53 above shows calculated curvature coefficient of the measured I-V
characteristics from the same diodes shown in Figure 51 The highest k value is
obtained from the diodes with size of 4times4um2 followed by 6times6um
2 then 10times10um
2
The curvature coefficient decreases sharply as the bias increases for each diode This can
be attributed to a significantly increasing number of electrons that tunnel through the
thin barrier which were accumulated in the 2DEG formed in the intrinsic spacer region
-5
0
5
10
15
20
25
30
-001 004 009
Cu
rvat
ure
Co
effi
cien
t(V
-1)
Voltage (V)
k(10x10 um^2)
k(6x6 um^2)
k(4x4 um^2)
153
An ASPAT diode with a smaller size will have a larger Rj with a corresponding smaller
current under the same bias condition and hence will demonstrate a larger k value In
this calculation the curvature coefficient at zero bias obtained from 4times4um2 6times6um
2
and 10times10um2 diode is 23V
-1 17V
-1 and 16V
-1 respectively
A summary of the ASPAT diodes parameters obtained from measured I-V
characteristics that have been translated into first and second order differentials are
gathered in Table 51 below and compared to other diodes in the literature
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics in this work
Sample Rj(Ω) k(1volt)
ASPAT 10times10 microm2 10K 16
ASPAT 6times6 microm2 27K 17
ASPAT 4times4 microm2 86K 23
Ge Backward diode 182K[110] 159[110]
InGaAs Backward diode 154[110] 23[110]
Sb Backward diode 5K[111] 47[111]
Si-Backward diode 135K[112] 31[112]
PDB 15K[8] -
AlGaAs SBD 20-100K[113] 34-38[113]
GaN HBD - 16[114]
From Table 51 above it is clearly that the ASPAT diode has a comparable value of Rj
and k to existing detector diode in the research community and in the commercial
market Based on literature of each diodes stated in the table the key to obtaining a high
value of k at zero bias is to minimize any forward tunnelling current Furthermore the
largest ASPAT diode used here (10times10microm2) has very close performances to that of a
commercial diode ie discrete Ge backward diode (ref[110]) where both Rj and k value
are close to each other
53 RF Test Fixture Theory and Experiment
RF measurements differ from DC measurement as they are more complicated
and it is necessary to comprehend the basic measurement principles to achieve
meaningful data This is obligatory especially for on-wafer RF characterization and
154
analysis to attain precise results Most of the electronics component measurements
which have input and output for instance antenna amplifier cables etc are based on a
two-port network configuration The characteristics which can be extracted from these
components are usually used to define their impact on a more complicated system
The performance of the two-port network can be described by a few parameters
ie scattering (S-Parameter) admittance (Y-Parameter) Impedance (Z-parameter) and
Hybrid (H-Parameter) However the S-parameter approach is favoured for high-
frequency measurements as it is relatively easier to characterize the microwave
performance and is able to convert to other parameters when necessary The advantage
of S-parameters is that they can straightforwardlydirectly convert into other two-port
parameters as mentioned above in term of currents and voltages[115] In fact to obtain
the device capacitance the appropriate S-parameters needs to be transformed into Y-
parameters using specific equations Furthermore the devicersquos cut-off frequency can
also be obtained when S-parameter measurements are performed over a wide frequency
range
531 On-Wafer Measurement and Small Signal One-Port Characterizations
In this work the arrangement of the RF measurement setup is assumed to be a
linear system as small voltage amplitude signals are used this means that the signals
have only a linear effect on the network without any gain compression or attenuation
The assumption is still acceptable even though the typical ASPAT is characterised as
non-linear in nature because it is a passive device which will act linearly at any input
power level
Generally the S-Parameter measurements on a diode can be adequately and
suitably performed using a one port measurement The technique used to characterise the
output is similar to the two ports technique but only incident and reflected waves are
used to characterise the input and output ports of the device Essentially this is because
the ASPAT has only two terminals and it is a passive device like other diodes
Therefore the analysis will revolve around the S11 parameter Figure 54 below show the
S11 is a ratio of reflected wave to the incident wave
155
11987811 =
119877119890119891119897119890119888119905119890119889
119868119899119888119894119889119890119899119905=
1198871
1198861 119908ℎ119890119899 1198862 = 0
(54)
A VNA as described in Chapter 2 is used to measure the ASPAT diodes This
powerful equipment is able to measure S-parameters up to 40 GHz To conduct accurate
S-parameter measurement at the diode the measurement setup must be calibrated prior
to the actual measurements taking place
54 Device Calibration
541 Open and Short De-Embedding Technique
Further calibration to be made involves anything related or attached to the
device The co-planar waveguide (CPW) bond pad and interconnect line that are
attached to the intrinsic diode are the main contributors of the errors also are required to
be calibrated In general the bonds pad could generate a capacitance (parasitic) in
parallel with the intrinsic diode and its contribution depends on the size of the bonds pad
as well as the operating frequency Meanwhile the CPW and interconnect line may
cause a parasitic inductance in series with the diode
The method that is used to get rid of this parasitic is called de-embedding and the
most common technique to realise it is by introducing OPEN-SHORT structure[116]
This method is based on a lumped-elements model Parasitic elements of the diode
De-Embedding Structure
Incident wave
Reflected wave
One-port device
a1
b1
Figure 54 One port S-parameter measurements
156
equivalent circuit correlate directly to the access section of the CPW hence can be
derived from de-embedding structures The aim of the de-embedding technique is to
represent these parasitic elements so that the one-port characteristic of the actual diode
can be determined
The two types of de-embedding structure OPEN and SHORT are conventional
techniques that are widely used in this study The design of all structure must be
identical (in size) to the device to avoid any discrepancy It is very simple to design all
these three structures for example open structures are obtained by eliminating the diode
layout and keeping the bond pad layer only The short structure just adds a bridge and
ensures ground and signal pad are connected to each other Through structures are
realised by disconnecting both ground pad and leaving the signal pad to connect to each
other
To gain more accuracy this external effect must be removed by the implementation of
de-embedding structures on the same tile as the actual device Figure 55 shows the
fabricated de-embedding structures used in this study
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use for RF
calibration and measurements (Note Images are not to scale)
In summary the de-embedding which is used to extract out the parasitic elements
from entire single diode measurement is a very important step as normally on-wafer
measurement requires coplanar waveguide (CPW) to access the diode structure (active
region) The CPW will have some effects which will disturb the accuracy of the device
characteristics
157
55 S-Parameter Measurement Result and Analysis
This section will only present RF measurement results after all VNA setup and
calibration were performed The S-Parameter measurements were carried out on ASPAT
diodes at five different DC biases from -2 to 05 volt with a sweep frequency from
40MHz to 40GHz using a calibrated VNA and the input power was fixed at -30dBm
The measurement procedure as described in Chapter 2 was performed on the device
(on-wafer) equipped with the appropriate bond pads This is important to ensure the
results obtained are valid The reason for using different biases is to find at what voltage
the device capacitance is fully depleted This is also very important in determining the
cut- off frequency of the devices
In this research two phases of the experiment on the S-parameter measurements
were carried out The first phase is to qualify the process flow ie for manufacturability
and repeatability which can be obtained from the consistency of the result The S-
parameter measurements taken on the same wafer dies are repeated several times on
different GaAsAlAs ASPAT diodes There are three different tiles taken from 3
different wafers namely XMBE304A XMBE304B and XMBE304C carried out in
this experiment The repeatability tests are done mostly on the large devices (15times15microm2
up to 100times100 microm2) and the results are analysed based on the reflection coefficient (S11)
on Real and Imaginary measurements
In the second phase the measurement is toward producing devices that can
perform at high-frequencies This can be realised by utilising small emitter size devices
(4times4microm2 6times6 microm
2 and 10times10 microm
2) The measurement results of these devices will be
used to build the equivalent circuit models while both the intrinsic as well as the
parasitics of the device will be evaluated Hence all the values obtained from these S-
parameter measurements will be used to design the device that can be used in
millimetres-wave applications As can be seen in Figure 56 below the extracted S-
parameter measurement results comprise of a reflection coefficient (S11) for real
imaginary and Smith chart for XMBE304A While these measurement results are
extracted at zero bias voltage the other bias voltages will be used to extract the
capacitance This will be described in the final section of this chapter
158
551 Diode to diode uniformity
In order to study within tile uniformity and reproducibility statistics of the RF
performance five devices of different mesa sizes in the same tile (XMBE304A) were
measured at zero bias and represented in term of Real and Imaginary reflection
coefficient (S11) the uniformity check is carried out at three different frequencies step
under 15GHz since the cut-off frequency for these big devices is relatively low at about
~20GHz on average The variation of the reflection coefficient is taken from the
percentage of the (standard deviationmean values) for all five diodes from this run The
following figures show Real and Imaginary S11 of large mesa area ASPAT diode from
15times15microm2 up to 100times100microm
2 which are represented by lines graph in a few different
colours
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices from
15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero bias
159
The variance data extracted from the graph (Real S11) above for each device within-
wafer (device to device) uniformity study is summarize in Table 52 below
Table 52 Device to device uniformity check for large ASPAT diode
Device Size 100times100 microm2 50times50 microm
2 30times30 microm
2 20times20 microm
2 15times15 microm
2
Variation 5GHz 181 115 405 151 145
Variation 10GHz 106 133 522 424 293
Variation 15GHz 119 198 281 76 509
The majority of diodes show that the variations of S11 measurements are below
3 and only a few are below 8 These finding still can be considered as good for
manufacturing control since absolute I-V characteristics reported in [63] is set by
designerrsquos specification to be not more than plusmn10 variation Further extensive RF
measurements were carried out by the research collaboration with the University of
Cambridge on the same GaAsAlAs ASPAT diodes wafer [117] In their study they
focused on 50times50 microm2
mesa size 17 of diodes were chosen to be measured The study of
uniformity of RF characteristic only focused on frequencies below 20GHz The same
approach was used to get the variation of the reflection coefficient for all 17 diodes but
this work was carried at four different frequencies Table 53 shows the zero bias S11
result for four different frequencies and standard deviation of the devices
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at four different
frequencies[117]
Frequency (GHz) 5 10 15 20
Variation () 197 243 26 276
From the results the variations of 50times50 microm2 mesa sizes measured in-house and
at the University of Cambridge are comparable with all variations showing good
uniformity ie recording variations below 3 This indicates that the RF performance
of the GaAs AlAs diode is valid and reproducible and is thus considered as a good
achievement for manufacturing Once the reproducibility and repeatability of the large
devices showed stable results the fabrication process then continued to obtain smaller
emitter size for work at high-frequencies
160
552 Wafer to wafer uniformity
Other RF measurements were conducted on sample XMBE304B which was
fabricated in-house using the same process steps but the only difference from
XMBE304A was the use of SiN3 as dielectric In this run three different mesa sizes
were measured (15times15mmicro2 20times20microm
2 and 30times30 microm
2) and Real and Imaginary S11
plotted against frequency The RF performances of both samples are gathered in one
graph as shown in Figure 58 below
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B) to qualify
the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2 device sizes (Real and
Imaginary) Note blue colour is XMBE304A and red colour is XMBE304B
For this wafer to wafer uniformity study four diodes with three different sizes as
specified previously were measured from sample XMBE304B and four diodes from
previous measurements of XMBE304A The blue line in Figure 58 represent
measurement result of real and imaginary for sample XMBE304A while the red line
161
represents XMBE304B The uniformity data is compared at three different frequencies
and gathered in the table below
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B
Device Size 30times30 microm2 20times20 microm
2 15times15 microm
2
Wafer A vs wafer B variation 5GHz 305 31 1 314
Wafer A vs wafer B Variation 10GHz 352 344 329
Wafer A vs wafer B Variation 15GHz 321 376 359
As can be seen in the Table 54 above the wafer to wafer uniformity is rather
large (30) on average The main reasons being that sample XMBE304A was
processed by utilizing S1805 as a dielectric layer while sample XMBE304B used
Si4N3 Although the process steps are similar for both wafer processing the use of
different dielectric layer will influence the diode parameters especially resistance and
capacitance as the dielectric constant for each materials is different Secondly the wafer
processing is not run concurrently at the same time thus the moisture and temperature in
the clean room might differ for both processing Although the wafer to wafer uniformity
test for this run might not be favourable for manufacturing tolerance at least the use of
different dielectric layer shows some significant result in term of capacitance resistance
effect to the GaAsAlAs ASPAT diode
553 Small devices RF measurements
The first objective of this study was to make smaller size mesa devices ie
1times2microm2 1times3 microm
2 2times2 microm
2 and 3times3 microm
2 However for GaAsAlAs ASPAT type this is
difficult to achieve in practise These issues were discussed in detail in Chapter 3
Hence the smallest emitter size that yields repeatable and reproducible results was
4times4um2 The final measurement which was done on sample XMBE304C focused on
small devices The measurements were done on four devices two with the diode bond
pads sitting on substrate (GaAs SI) and the other two sitting on dielectric layer (Si4N3)
Figure 59 below shows three measured results obtained from sample XMBE304C
using the 3rd
Gen Mask
162
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and 4times4microm
2 (Real and
Imaginary) Note that green red and blue colour represents 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and 4times4 microm2
(Smith Chart) Note that green red and blue colour represents 4times4microm2 6times6mmicro2 and 10times10microm2
diodes respectively
30MHz
40GHz
163
As can be seen in Figure 59 (Real Imaginary) and Figure 510 (Smith Chart) are
obtained from measurement of four diodes in the same tile The diode to diode
uniformity that is sitting on the same platform obtained at 35GHz frequency in this run
on average is ~15 25 and 1 for 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively On the other hand the uniformity between diode to diode sitting on
dielectric and substrate is quite high due to different capacitance value of devices on
average ~7 are attained from three different sizes of diode
From the measurement results above the Real S11 measurement of four different
sizes show the same trend for each frequency At low frequency resistances for each
diode is high as the S11 value is large At intermediate frequency the values drop
tremendously for big devices (30times30 mmicro2 and 20times20 mmicro
2) ie in Figure 57 At high
frequency all diode reach saturation limit as the value are constant Small devices
(4times4mmicro2 6times6mmicro
2 and 10times10microm
2) ie Figure 59 show S11 values that are higher than
those of large devices as smaller emitter diode have larger resistance value
The imaginary S11 value also shows the same trend as for big devices However
for small devices in this run (4times4mmicro2 6times6mmicro
2 and 10times10microm
2) the S11 value keep
dropping toward negative values at increasing frequencies This indicates that bigger
devices with positive value at high frequency are more capacitive than the smaller
devices It is worth mentioned that the capacitance and inductance values for device
sizes of 4times4microm2and 6times6microm
2 come from the CPW layouts and these are dominant while
for device sizes of 15times15 mmicro2 and above the device capacitance itself is dominant
The Smith Chart shows the reflection coefficient (S11) as a function of the
applied frequency (30MHz to 40GHz) All measurements from each mesa size follow
unique impedance circle which is that most of the lines are at the lower right outer ring
This means that the diode capacitance value is frequency dependent For the case of
10times10microm2
devices these impedance circles are mostly toward the outer ring meaning a
higher capacitance than the other two mesa dimensions All the device constantly follow
the outer ring without crossing any real axis at any frequency point meaning that the Cj
is not shorted at the maximum 40GHz measurement frequency (not reached cut-off
frequency) Therefore the entire small GaAsAlAs diodes in this run have capability to
work in the millimetre wave frequencies range
164
56 Extracting RF models of ASPAT at Zero Bias Voltage
The methodology used in the S-Parameters measurement for high-frequency
analysis must ensure that the derivation of the equivalent circuit corresponds to their port
characteristics In other words the component representing the ASPAT in the equivalent
circuit model must have physical significance otherwise the circuit will be meaningless
The fabricated ASPAT diodes as discussed in Chapter 3 have the cross section shown in
Figure 511
There are two main components that can be extracted from the fabricated
ASPAT depicted above ie intrinsic and parasitic The intrinsic refers to the main
structure of the diode itself and are represented by three bias dependent elements
namely Junction Resistance (Rj) Junction Capacitance (Cj) and diode Series Resistance
(Rs) The parasitic is the elements related to the bond pad of the anode and cathode as
well as interconnects They are represented by parasitic inductance (LP) resistance (RP)
and capacitance (CP)
The diode parameter extraction is different from the three terminal devices
(FETs) in the sense that FETs are a kind of direct extraction in which all the elements in
the transistor have linear functions to the port characteristics ie S-parameter Y-
Parameter Z-Parameter and can easily be solved by the matrix calculation method for
those particular parameters[118] The same extraction method cannot be applied to the
diodes because its elements will embroil with each other Therefore only one method is
used to extract the diode element which is optimisation by tuning the initial value toward
the measured S-Parameter values
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding equivalent circuit
model
165
The strategy used to model the ASPAT is based on an initial fitting value of the
lumped elements to the extracted value from measurement on three S-parameter graphs
(real imaginary and Smith chart) for the reflection coefficient (S11) The refinement is
accomplished by optimisation and fine tuning of the values which result in minimum
error between extracted and modelled values Figure 517 (on page 153) shows fitted S-
parameter result for extracted and model numbers with each one fitted in a single line as
an example However to achieve this excellent fitting key prior steps have to be used
de-embedding fitting the intrinsic value and optimisation
561 Extraction of ASPAT parasitic element
Once the S-parameter measurements achieve stability repeatability and
reproducibility for each measurement in term of S11 results as mentioned above the
results of the de-embedding structure which had been measured prior to the device
structure are then extracted to form a well-defined equivalent circuit In order to build
and analyse the equivalent circuit firstly the measured data is imported into the ADS
software prior to any fitting This can be realised via the ldquoStart The Data File Toolrdquo
features provided by this particular software When successfully imported the data is
read by the function S2PMDIF (These files are a natural extension of two-port S-
parameter Touchstone files) as depicted in Figure 512 below
Figure 512 The S-parameter Touchstone file is used to read the measured files
166
For the open and short techniques after de-embedding the equivalent circuit
model which is represented by mainly a capacitor and an inductor is built The open
structure requires resistance and the capacitance values of 20KΩ and 26fF respectively
connected in parallel to be well fitted to the real imaginary and Smith chart (S11) output
On the other hand for the short structure the Real imaginary and Smith chart (S11) have
to satisfy the values of resistance and inductance elements of 1Ω and ~47pH respectively
connected in series These values strongly rely on the bond pad or CPW dimension and
length The Equivalent circuit models and fitted data as well as measurement can be
seen in Figure 513 and Figure 514 below
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure
Figure 514 Equivalent circuit model for short de-embedded structure
To satisfy the equivalent circuit a self-consistence method introduced by
Ren[119] is utilised This approach accurately extracts the CPW capacitance (Cpad) and
inductance (Lpad) as well as intrinsic Junction capacitor (Cj) which is attained from the
one-port S-parameter measurements Therefore the pad capacitance introduced by the
self-consistence method for the open structure can be expressed by
167
119862119875 =
119868119898(11988411119874119901119890119899)
120596
(55)
Lpad which represents the short structure is given by
119871119875 =
1
120596(119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
))
(56)
Here Y is the admittance parameter (Y-parameter) converted from the S-parameter
measurement data and ω is the angular frequency The extracted measurement data
represented in the equivalent circuit fits with the simulated data in three S11 graphs as
can be seen in Figure 515 below From the Smith Chart it can be clearly seen that both
open and short S11 results are on the circumference which means the resistance of the
short structure is very small while in the open it is very large Additionally the
calculated Cpad and Lpad using Equations 55 and 56 above produce results similar to
those obtained in the equivalent circuit model for the open and short structure The
values are ~25fF and ~45pH respectively These data completely verify and validate
both results
Figure 515 Smith chart representative S-parameter measurement for short (left) and open (right)
CPW The blue lines represent simulated data and the red is measured data
Short
Open
168
562 Extraction of ASPAT intrinsic elements
Once the parasitic elements are determined it is easy to build a complete ASPAT
equivalent circuit The ASPAT is not like other tunnelling diode which their equivalent
circuit models widely studied ie RTD [120] IMPATT and PDB The only literature
which reports ASPAT equivalent circuits can be found in [15] and other RT Symersquos
journal paper[16] Fortunately its equivalent circuit model is not much different
compared to other diode video detectors Thus other literature which is based on
Schottky diode equivalent circuit model used for detector application can be referred to
The simplest form of ASPAT equivalent circuit and other video detectors intrinsically
consist of junction capacitance (Cj) series resistance (RS) and junction resistance (Rj)
First and foremost to extract the equivalent circuit one must know the theory behind
each parameter that is developedbuilt as a spine to become a complete element This is
vital to ensure the equivalent circuit is correct In the case of the ASPAT Cj is predicted
from a simple fully depleted parallel plate capacitor approximation which was discussed
previously in Eq (230)[15] Additionally for the S-parameter measurements the Cj can
also be validated by the self-consistence method mentioned earlier and thus can be
expressed by
119862119895 =
[
(1
120596)
1
1
119868119898 (11988411119905119900119905119886119897minus 11988411119874119901119890119899
)+
1
119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
)]
(57)
This approach helps to verify both the fully depleted parallel plate capacitor in S-
parameter measurements The basic component which is responsible for the ASPAT
series resistance RS was discussed in detail in Chapter 2 RS and Cj are key contributors
to the high-frequency operation as expressed by the device cut-off frequency Equation
(58) below
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(58)
The R and C parameters must be kept as low as possible in order to obtain high cut-off
frequencies for millimetre wave applications From the fabrication point of view Cj can
169
be reduced by making as small a diode emitter size as possible while for RS reducing
the D gap is of paramount importance as it dominates the series resistance The ASPAT
contact resistance in the electrodes (contacts between metal and semiconductor) can be
reduced by using high doping in the ohmic layers
The junction resistance (Rj) of the ASPAT is taken from the 1st derivative or
slope of the current-voltage characteristics Normally the value of Rj is very large
(several kilo Ω) compared to Rs The small signals ASPAT equivalent circuit built with
intrinsic and extrinsic components is shown in Figure 516 below while the fitting
results is shown in Figure 517 and Figure 518
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
(Real and Imaginary) results for various small device designs
Rj
Cj
Cpad Rpad
Rs Lpad
Figure 516 Equivalent circuit of the ASPAT diode
170
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
results (Smith Chart) for various small device designs
The equivalent circuit that was built for the ASPAT is taken from sample
XMBE304C with emitter dimensions of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 These
devices are expected to work in the millimetre-wave region and have cut-off frequencies
(intrinsic) of ~650GHz ~200GHz and ~100GHz respectively
Table 55 Comparison between calculated (fully Depleted) and extracted (different biases) values
from equivalent circuit parameters for different ASPAT mesa sizes at zero bias voltage
Parameters 4times4microm2 6times6 microm
2 10times10 microm
2
Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted
0V -05V -1V 0V -05V -1V 0V -05V -1V
Cj(fF) 879 23 7 6 198 55 148 139 549 171 486 46
Cpad(fF) - 15 15 15 - 15 152 152 - 15 15 15
Lpad(pH) - 45 43 42 - 50 473 473 - 51 51 46
Rj(KΩ) - 90 833 522 - 35 392 392 - 12 125 13
Rs(Ω) 99 11 11 11 67 95 8 7 41 95 45 37
fcut-off
Cj(GHz)
1828 629 2066 241
1
1208 192 1344 163
5
710 107 728 935
fcut-off
Cj+Cp(GHz)
- 380 658 688 - 151 663 781 - 98 556 705
171
The focus in this study is purposely to build ASPATs as zero bias detectors that are able
to work in the millimetre and sub-millimetre frequency range therefore all the
parameters which are obtained from equivalent circuit were extracted at zero bias
voltage Theoretically the calculations which are derived from both self-consistence amp
theory can only be solved for fully depleted device capacitance (using a parallel plate
configuration) Hence both extracted and calculated results are compiled in Table 55
Noticeably the calculation can only produce the intrinsic parameters of the
ASPAT for fully depleted capacitance On the other hand both intrinsic and extrinsic
parameters of GaAsAlAs ASPAT are obtainable from extraction and thus help to
determine at what bias the diode is start to deplete The junction and series resistance (Rj
and RS) of each dimensions shown in Table 55 above were achieved by fitting the
elements of the equivalent circuit with the three measured S11 graphs whereas the Cpad
and Lpad were extracted by utilising the self-consistent method from the S-parameter
measurements which is fitting the de-embedding structure Additionally the Cj values
are obtained via fitting the measured S11 data and employing the self-consistence
approach Results obtained from both techniques are identical
At zero bias all extracted junction capacitance from each device sizes are very
different from the calculated one while the extracted series resistance are closer to the
calculation This means that Cj is a highly voltage dependent parameter and Rs is
voltage independent but solely dependent on device structure and material used to
fabricate it The extraction at -05V and -1V shows that the values of junction resistance
is changing for most of the devices which means this parameter also rely on bias voltage
as discussed earlier in Section 52
The cut-off frequency for each calculated devices are near the THz range even
for the 100microm2 emitter area However with the introduction of parasitics elements ie
pad capacitances fcut-off is degraded tremendously Therefore it is important to make sure
all the intrinsic elements have optimum values so that the target operating frequency of
the ASPAT diode can be met Due to this it is advisable to operate the devices at no
more than 13 of fcut-off when designing detector systems
The parameters extraction at -05 and -1V also show that Cj values are closer the
calculated ones which means the ASPAT diode is reaching full depletion
172
563 Capacitances -Voltage (C-V) Extraction
Theoretically the junction capacitance of the ASPAT is calculated from the fully
depleted formula 119862119895 = 휀119900휀119903119860119889 which was also discussed in Equation (230) in Chapter
2 in page 43 Its value depends on the change of voltages to depletion at the emitter
contact[15] and make it one of the voltage dependent parameter for the diode[121]
Therefore the C-V characteristic of the GaAsAlAs must be precisely extracted
In practice the capacitance is difficult to measure due to the very low resistance at zero-
bias However alternatively it can be measured and extracted by applying different
voltage and identifying the point at which there is change which essentially represents
full-depletion Apart from these it can also be extracted from S-parameters measurement
which is then converted to Y-parameters A C-V characteristic of the GaAsAlAs
ASPAT from XMBE304C is extracted and plotted as depicted in Figure 518 below
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled capacitance vs
Voltage)
From the graph shown in Figure 518 the capacitance is extracted at eight
different biases for 4times4 microm2 6times6 microm
2 and 10times10 microm
2 The devicersquos junction
capacitance for each dimension increases and reaches a maximum value at 025V There
are additional quantum capacitance effect which comes from an increase in the negative
charges in the 2DEG region (when band bending happens creating an accumulation
0
50
100
150
200
250
-2 -15 -1 -05 0 05
Cap
acit
ance
(fF
)
Voltage (V)
Cj(4x4microm^2)
Cj(6x6microm^2)
Cj(10x10microm^2)
173
region at the barrier) This charge is imaged by the positive charge in the whole
depletion region Increasing the voltage toward positive values leads to a lowering of
the AlAs barrier and thus allowing thermionic emission to take place after certain bias
values leaving only the depletion capacitance and making the quantum capacitance
negligibly small
In the reverse bias case the device junction capacitance reaches a saturation
(fully depleted capacitance) at a voltage of -025V and remain constant up to -2V If the
reverse bias voltage is increased further the ASPAT may reach breakdown Therefore it
is important to know how far the diode can withstand applied reverse bias to ensure it
can still give full performance
57 Conclusions
In this chapter scalable DC characteristics of GaAsAlAs ASPAT diode derived
from three different emitter sizes of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 was
demonstrated The current density obtained at zero bias is several microAmicrom2 These allow
1st order differential effect to exhibit high value of Junction resistance (Rj) at zero bias
However Rj is highly bias dependent The 2nd
order differential effect on IV
characteristics display a high value of curvature coefficient leading to high voltage
sensitivity when applied in millimeter wave detector applications These two parameters
are vital in the design of millimeter wave detectors and especially those operating at zero
bias
Subsequently RF measurement up to 40GHz of uniformity study for both within
wafer and wafer to wafer variance were undertaken An average uniformity below 7
was obtained for within wafer study on large device area ( 15times15 microm2 to 100times100 microm
2)
while for small device area ( 4times4 microm2 to 10times10 microm
2) a smaller 3 uniformity variance
was achieved in average However for wafer to wafer study the variant uniformity was
quite high at around 30 on average for relatively large device (15x15 microm2 to 30x30
microm2) This was mainly attributed to different dielectric layers used in the process flows
of the sample rather than fundamental MBE control of the AlAs barrier thickness
174
It was demonstrated in this chapter that careful on-wafer RF measurements of small
size GaAsAlAs ASPAT diodes allow accurate device parameter extraction of both
extrinsic and intrinsic parameters The extrinsic parameters are namely pad capacitance
and inductance with obtained values of 26fF and 47pH respectively These values were
obtained from de-embedding structure fabricated on the same tile as the real devices
The intrinsic parameters such as junction capacitor junction resistor and series
resistance had different values according to device dimensions The smallest zero bias
value of Cj obtained from 4times4 microm2 diodes was 23fF ensuring a high cut-off frequency of
380GHz and hence in the next chapter a 100GHz detector will be presented working at
slightly less than 13 of this cut off frequency
The C-V data extraction confirmed that the fully depleted capacitance started to
happen at around -025V The maximum junction resistance occurs at +025V largely
caused by the depletion region and an additional quantum capacitance effect CQ This
effect is strongly related to the size of a 2DEG which occurs under forward bias (01V to
025V) and can be reduced by having a smaller thickness AlAs barrier
175
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR
DESIGN USING ADS
61 Introduction
The ASPAT diode having features of non-linear IV characteristics at zero voltage
make it useful for signals rectification ie detector and mixer for millimetre-wave
applications Additionally ASPAT diodes have a range of advantages such as large
dynamic range strong temperature insensitivity etc[15]over other rectifier diode This
makes ASPAT an appropriate candidate in RF detection applications Since 1940 the
only two terminals device that has been the workhorse for RF applications is the
Schottky Barrier Diode (SBD)[9] In its earliest form the SBD was built based on a
point-contact device which could not perform at high frequencies It was then developed
to work at higher frequencies by exploitation of epitaxial structures [10] and to date the
SBD remains the mainstay of two terminal devices that are able to work in the
millimetre and submillimetre-wave regions However as discussed in Chapter 4 the
performance of SBD is degraded at extremes of temperatures and these circuits
employing SBDs require temperature compensating circuitry Thus there is additional
complexity associated with technologies and applications related to SBDs
Before this work was carried out no model for the ASPAT diode as detector had
been available or developed especially using the empirical modelling ADS software
When the ASPAT diode was first introduced its function was conceptually explained it
was then built and tested to compare with other microwave detectors at X-band
frequency (95GHz) The comparisons were made in terms of detector parameters ie
sensitivity dynamic range temperature dependence etc[15] These early works lead by
RT Syme et al supplied the basic knowledge to model the ASPAT diode as a zero-bias
detector for mm-wave frequency gt100GHz For the SBD many models and equivalent
circuit approaches have been reported [122 123] The modelling of conventional SBD is
mostly implemented through fitting the S-parameter curves of the model to the
experimental one This approach is also carried out in this research since it is accurate to
predict the performance of the device under test [124]
176
This Chapter aims to introduce low cost reliable and sophisticated detector design
based on ASPAT diodes which is believed to be able to improvereplace SBD in
millimetre-wave applications especially in imaging The focus was on developing and
establishing an appropriate circuit design that suit the new ASPAT diode for such
applications The detector sensitivity as its key parameter ultimately limits the quality
and acquisition time of the detector In the subsequence section the theory of detection
including both direct and heterodyne will be discussed This is followed by definition of
detector characteristics of interest as well as noise consideration Section 65 present the
main focus of this chapter which is the development of 100GHz ASPAT detectors and
their result will be explained in term of all detector characteristic of interest
62 Detection Theory
Any incoming signal such as RF microwave or mm-wave in the form of envelope
function or single wave can be detected by rectification of the signal using a nonlinear
device ie transistor or diode The input and output signal (RF) signals are normally in
the form of amplitude as a function of time Typically the detector output is a low-
frequency signal known as the video signal which has amplitudes that are proportional to
the square of the input RF signalrsquos voltage amplitude
A complete receiver system as shown in Figure 61 below consists of receiver
antenna and a circuit designed to extract the signal and then amplify it The function of
the receiver system is the converse of the function of the transmitter side At the receiver
side the antenna is used to receive the signal it then conveys the signal to the extraction
circuit for detection as the information-bearing part of the signal (using the nonlinear
device as its heart) The signal is finally amplified to avoid any information strength
decay Additionally in a digital system the output signal which had been processed by
the detector circuit has to maintain an optimum input signal conveyed to in-phase and
quadrature (IQ) demodulators The output signal will go through a low pass filter then
to an analogue-to-digital converter (ADC) and thus a digital baseband output signals
will be produced
177
Figure 61 Block diagram represent a complete direct receiver system
There are two types of millimetre wave integrated circuit (MMIC) used for
detection purposes namely direct detectors and heterodyne detectors The direct detector
MMIC is the simplest circuit used for detector applications and has the simplest way of
extracting the RF information Due to its simplicity the direct detection method is
inexpensive and most attractive method used for measuring power in RF Laboratories
and Industries This detection scheme is also sometimes known as video detection[125]
The simplest way of explaining the detection process is that the incoming RF or
microwave signals depicted in Figure 62 below with an appropriate input power (Pin) is
rectified by using a diode and results in a corresponding output voltage (Vout) A detector
IC designed based on diodes is normally able to rectify very low levels of RF power (lt-
40dBm) then produces an output DC voltage that is proportional to the RF power A
rectifier diode can function at zero bias (which is very good for reducing noise) at very
small DC bias (003mA) and relatively high RF impedance which will produce around
600Ω This will affect the capacitance value and a low capacitance is needed to realise a
high detection sensitivity
Figure 62 The detection process of a single wave through a non-linear IV characteristic of a diode
Detector
Speakerdisplay unit Amplifier
Antenna
Vout
Pin
Tuner Amplifier
178
However this type of detector has a drawback which is itrsquos relatively low signal to
noise ratio Thus it will also rectify any incoming electrical noise at all frequencies and
up to the cut-off frequency (fC) The basics lumped components circuit as shown in
Figure 63 is used to build such detector which consists of Source impedance (Zo)
Rectifier diode (ASPAT or Schottky) wire or pad inductance and capacitance and Load
impedance (RL)
Figure 63 Lumped element illustration of microwave detector circuit
Another type of detector is the heterodyne method which mixes incoming RF or
microwave signal (fRF) with another constant signal produced by a secondary circuit
called the Local Oscillator (LO) The LO frequency (fLO) must be slightly higher than fRF
to enhance the RF signal This mixing between fRF and fLO happens in the nonlinear
device as depicted in the Figure 64 This will produce a signal at a different frequency
called the intermediate frequency (fIF) which can then be amplified and detected as
explained in the previous paragraph Theoretically a basic requirement of the mixer is to
have fIF as efficient as possible while practically the minimum conversion efficiency
obtained is around 20 The main reason for using a mixer is due to the fact that
selective amplifiers at RF frequencies are costly and hard to achieve Hence a mixer is a
good technique as it only convert the signal to a lower frequency in which good
selectivity and high gain can be more effortlessly realised[14] A good mixer diode is the
one that can produce a high cut-off frequency and reduce conversion losses (Lc) A
mixer and detector diode with a low driven input power result in reducing overall noise
figure and thus in the ideal case the fIF amplifier also should have a low noise figure for
better performance The advantage of the heterodyne method is that it has a higher
179
sensitivity compared to the direct detection method this is achieved by producing an fIF
which has a lower frequency than the incoming RF signal[14] Obviously a zero-bias
voltage diode is more favourable to be used in mixer and detector applications
Figure 64 The mixing process where the signals are processed by the non-linear I-V characteristic
to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and fRF are applied to the
diode
To have good detection efficiency for both types of detectors the operating
frequency (fO) must be several times smaller than fC In the case of an incoming
maximum modulated signal fM the frequency that can be acquired is in the range of fO
plusmnfM and will normally come with noise The standard method that is used to reduce the
noise is using a filter of bandwidth about 2fM at the centre of fO with the condition that fO
must be smaller than fM (f0lefM) Otherwise it would be difficult to attain However in
most cases fM is smaller than fO and fO is smaller than fC thus this will make the video
impedance (RV) (or nonlinear impedance) very close to the differential resistance of the
diode (at fO) in the equivalent circuit[74]
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis
Theoretically a transfer function measurement is preferable prior to any empirical
modelling since no assumption can be made due to the detector non-linearity
Furthermore measuring voltage output at high frequency can be very low while
measuring the power incident on the detector is hard to achieve where the linearity of
180
the typical power meter is normally less than 3 over its operating range[126]
Therefore the modelling of detector output voltage vs input power (ie transfer
function) can help to determine both nonlinearity correction and appropriate operating
range for the detector itself
The performance of the diode that is often taken into account is the transfer function
(output voltage Vout versus incident power Pin) and the main parameters that is used to
characterise and determine the quality of any detector diode are the voltage sensitivity
(βV) tangential sensitivity (TSS) dynamic range (P1dB) ie under 1 dB roll off power and
variation of output voltage when examined in extreme temperature situation (ΔV(T))
The voltage sensitivity in small signal analysis can use the approach introduced by
Torrey and Whitmer [9] then βV can be expressed as
120573119881(119894119889119890119886119897) =
119877119895119877119871120581
2(119877119881 + 119877119871) (1 +119877119904
119877119895)
2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(61)
Where ω is the angular frequency (2πf) Cj is the junction capacitance of the diode
active region RL is the load resistance RV is the video impedance taken from the
expression of Rj + Rs and κ is the curvature efficiency that give small signal rectifying
action of the ASPAT diode which is given by the second order term and itrsquos expression
is
κ =
11988921198681198891198812frasl
119889119868119889119881frasl
(62)
The curvature coefficient or responsivity (κ) is translated directly from the non-linearity
of the IV characteristics of the ASPAT diode for detector application Both RV and κ are
the parameters that can be extracted directly from diode DC measurement as discussed
in Chapter 5
The voltage sensitivity is actually a quantitative relationship between input
power and detector response Meaning that it is a change in signal output over change in
input power Normally output power is measured in Volts and input signal is measured
in Watts Therefore the unit of responsivity is VW[127 128]
181
TSS is referred to the lowest or minimum signal that the detector could detect it is
determined by the diodersquos βV and total noise available in the system (from the diode and
any amplifiers in the detector circuit) For any diode with fO=10 GHz and low noise of
1MHz bandwidth amplifier the TSS is typically less than -55 dBm[74] The TSS equation
is given by
119879119878119878 =
radic[4119884119870119861119879119861(119865119886 + 119905 minus 1)]
119872
(63)
Where M is a figure of merits and is derived based on the expression M= 120573119881 radic119877119881frasl t
denotes the diode noise temperature Fa is the noise figure B T and Y are the amplifierrsquos
bandwidth temperature and power for signal-to-noise ratio respectively For a low-level
video detector ie lt10GHz the sensitivity mainly depends upon three factors firstly on
RF matching structure secondly on the rectification efficiency output impedance and
noise properties of the diode and finally the input impedance bandwidth and noise
properties of the video amplifier at the detector output The RF matching structure
controls the quantity of overall energy at the active junction for rectification The second
factor controls the reaction of the diode to incident microwave radiation and the last
factor will influence the detector sensitivity in general[109]
In practical the Tss is a direct measure of the signal-to-noise ratio of a detector and
is achieved by varying the amplitude of the input pulse (RF signal) until a point in which
the top of the noise level with no signal applied is at the same level of noise at the
bottom level of RF signal It is commonly measured on an oscilloscope as depicted in
Figure 65 below It is defined as the input power at which a signal to noise ratio of 251
is produced[109]
Figure 65 Measurement of Tangential Sensitivity[108 129]
182
The transfer function in many detector diodes is often divided into three sections
Firstly at low incident power secondly at higher input power and finally at very high
power static (continuous) In the first region the detector diode performs as a square-law
detector in which Vout is proportional to Pin This region normally is used to extract the
dynamic range of the diode detector In the second region Vout is approximately
proportional to Vin and this region is known as the linear regime Finally at higher Pin
still the transfer function or response rolls off and thus Vout ultimately become saturated
This roll-off point where Vout has dropped by 1dB below an extrapolation of the
dependence at low Pin is termed the ldquo1dB roll-off pointrdquo and this value is usually in the
range of -11 to 12 dBm[15] Therefore a dynamic range of the detector diode can be
obtained by taking the interval between TSS and 1dB roll-off point (in dBm)
Finally the temperature dependence of Vout for a detector is normally taken from
two extreme points of the temperature (-40C˚ to +80C˚) and thus can be determined
from
Δ119881(119879) = 10 11989711990011989210 |
119881(1198791)
119881(1198792)|
(64)
This Vout variation between -40C˚ and +80C˚ normally expressed in dB
64 Noise Consideration in a Detector diode
The existence of noise in a system limits the accuracy of device performance and
the precision of measurements In a detector system specifically using a diode the noise
which can reduce the sensitivity of signal encryption is called the Noise Equivalent
Power (NEP) By definition the NEP is a noise power density over the detection
sensitivity and it can be exploited to determine the overall noise performance of a
detector[130 131] In other words NEP is defined as the power from the input source
(Pin) that is required to supply a voltage output (Vout) equal to the root means square
noise at Vout [132] For an ideal lossless match and assuming only Johnson-Nyquist is
present the NEP of a zero-bias detector can be expressed as
119873119864119875119900119901119905 = radic4119896119879119861119877119881120573119900119901119905 (65)
183
Where βopt is responsivity with an optimum match which is given by1 2frasl 119877119895120581 This type
of noise appears when changing voltages across a diode and a noise voltage (Vn)
normally will arise Theoretically the NEP has units of Watts (as it is actually a power)
but it often normalized to 1Hz as it is independent of bandwidth and thus the unit
becomes WHz12
Additionally there are also several noise sources that contribute to Vn in a
semiconductor diode which are Johnson-Nyquist noise Flicker Noise and shot noise
Johnson-Nyquist noise [133 134] appears across any conductor or semiconductor at
thermal equilibrium this is due to the thermal agitation of the carriers or charges It can
be expressed in root mean square voltage as below
119881119869minus119873 = radic4119896119879119861119877119895
(66)
Where Rj is the differential intrinsic resistance B denotes the post-detection bandwidth
T is the device temperature and k is the Boltzmann constant[134]
The second noise that is taken into consideration when dealing with semiconductor
devices is Flicker noise more commonly known as 1f noise It is a group of known and
unknown noise sources that can be observed in the frequency spectrum and normally
display an opposite to the frequency power density curve[135] It comes from a variety
of different causes ie recombination effects at a defect in semiconductor mobility
fluctuation and flow of direct current as well as interface phenomena [136-138] In term
of voltage source Flicker noise can be expressed as[139]
1198811119891 = 119870119891119881119909119891119910 (67)
Where Kf denotes a device-specific constant V is the voltage and f is the frequency The
value of x and y typically used are 2 and -1 respectively This type of noise (1f noise)
will be neglected at frequencies high enough due to the fact that the NEP of the diode is
proportional to the thermal noise and resistance of the diode
Finally the noise that causes time-dependent fluctuation in a flow of electrical
current because of the carrier or electron charge crossing a potential barrier is called shot
noise Shot noise is due to the randomness in the diffusion and recombination of both
majority and minority carriers[140] The equation of shot noise term at random time is
given by[141]
184
119881119878ℎ119900119905 = 2119902119868119861 (68)
Where q is the electron charge I is the current and B is the bandwidth This type of noise
is not affected by changes in temperature or device parameters Therefore the total noise
voltage appearing in the semiconductor is found to be [141]
1198811198992 = 119881119869minus119873
2 + 11988111198912 + 119881119904ℎ119900119905
2 (69)
However a zero-bias device will greatly eliminate both shot and flicker noise
compared to a biased device This has been explained by Equation (66) and Equation
(67) above where both noises are significantly related to the current and voltage Thus
if V and I =0 in the nonappearance of incident power then Vn will also become zero For
a detection process with bias the diode will be self-biased by ΔV which causes both
flicker and shot noise to appear But the shot noise in practical situation is much smaller
and thus normally ignored [142-144] Usually the noise in a zero-bias detector is
estimated by considering the low power limit as good first order estimation in which the
presence of only Johnson-Nyquist noise and ΔV is arbitrarily low [11 145 146]
Additionally it has been reported that the noise in tunnelling type diodes displays very
low or no excess noise in the bias region of the current-voltage characteristic[147 148]
Therefore in general most of the noise specifically in tunnelling type of diode will be
neglected this is a great advantage compared to SBD or transistors
65 Modelling of a 100GHz Zero-biased ASPAT Detector
Once the DC and RF characteristics of the ASPAT diode had been accurately
obtained the next step is to model and design a detector circuit based on S-parameter
measurement results as was explained in the previous chapter The aim is to realise a
detector circuit design which can be operated at millimetre and sub-millimetre wave
regions from an accurate diode model prior to the circuit design A diode detector model
puts experimental observations into context and offers insight into future experiment
results Consequently an electrical model based on lumped element component is vital
for a deeper understanding of how and to what extent a new device like the ASPAT
diode can affect all the key detector parameters that were previously discussed The
prediction of the detector parameters mostly depends upon the ASPAT diode
185
geometrical emitter size and material parameters However for millimetre wave
operating frequency the accuracy of the model is more sensitive not only to diode size
but also to the diode periphery ie substrate as well as coplanar amp transmission line
adopted in the circuit Therefore both extracted intrinsic and parasitic element of such a
device must be taken into account
In this work an ASPAT diode with an emitter size of 4times4microm2 which is the
smallest size that could be fabricated so far was chosen to be exploited for detector
designs The important parameters related to the 4times4microm2 GaAsAlAs ASPAT which
works at 0V is summarize in table 61 below
Table 61 A summary of all the important parameters of the 4x4 microm2 diode
Device Rj(Ω) Rs(Ω) Cj(fF) Cp(fF) κ(V-1) Intrinsic_fcut-off(GHz)
4times4microm2 90K 11 21 15 23 629
The actual measured I-V characteristic is used to model the diode since the library
in the ADS simulation tool does not have an ASPAT diode model or any tunnelling
diode for that matter The procedure of realizing the diode model is by taking the I-V
characteristic obtained from the 4times4microm2 emitter size measurement results and
converting it into a10th
orders polynomial equation via MATLAB software to create a
virtual I-V characteristic Thereafter this equation is then defined as a two terminals
device namely Symbolically-defined Device (SDD1P) ie a component of the non-
linear equation provided by ADS (Figure 66) to represent the ASPAT Figure 67
shows the measured data and 10th
orders polynomial equation fit very well to each other
Hence this new component used to represent the whole ASPAT diode will be used in
this research for MMIC detector and Frequency Multiplier designs The device chosen to
be modelled (4times4microm2) has measured junction capacitance of 21fF (at 0V at 40GHz) The
detector circuit is designed to operate at 100GHz for a safe side due to the extrinsic
calculated fcut-off is around 380GHz Since there are a lot of advantages in using unbiased
detectors compared to biased one this work will discuss the performance of millimetre-
wave detector at zero-bias and their result will be compared to the current performance
of other diodes reported in the literature
186
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted from
MATLAB to realize a virtual GaAsAlAs ASPAT diode
Figure 67 Verification of actual (blue measured) and virtual (red_10th order polynomial) I-V
characteristic of the 4times4 microm2 diode used in this study
To realize the ASPAT detector circuit a simple detector circuit topology as
depicted in Figure 68 was constructed Initial simulation was run to perform a
functionality check of the detector circuit utilizing the Harmonic Balance (HB)
simulation tool embedded in that particular software Such simulation tools will analyse
the detector performances in the frequency-domain as it is mostly beneficial and fully
compatible with microwave and millimetre wave problems The frequency domain is
also suitable for single and multi-tone power excitation The importance of harmonic
balance are described in [149]
-00005
0
00005
0001
00015
0002
00025
0003
-3 -2 -1 0 1 2 3
Cu
rre
nt
(A)
Voltage (V)
ADS
4x4
187
Figure 68 Direct detector circuit topology using an ASPAT diode
Initially the circuit topology that consists of P1_Tone power supply ASPAT
bypass capacitor and load resistance is simulated by setting up a fixed input frequency at
100GHz The ASPAT diode provides a DC output voltage proportional to the input
power strength depending on the absolute values of the DC terms associated with the
nonlinearity of the I-V characteristics The capacitance in the output part is a bypass
capacitor used to prevent millimetre-waves from leaking to the output The load
resistance is large enough to ensure the voltage divider between load impedance and
device impedance gives maximum voltage sensitivity This large load resistance is
achieved by creating an open circuit at the end of detector circuit terminals
Noted that this simulation was run using diode parameters that were extracted from on-
wafer one port S-Parameter measurements as described in chapter 5 To apply them in a
two port application ie detector circuit may or may not provide a very accurate
outcome it however worked adequately in the particular circuit described in this chapter
but may not work in other circuits in general Thus the one port extractions in this work
still provide adequate parameters to build and design specific MMIC detector circuits
but not in general applications
The main reason for these simulations and their results to be used in high frequency
applications is due to the fact that actual RF measurement were done up to 40GHz
Additionally the 100GHz operating frequency was obtained from extrapolation of each
ASPATrsquos component Since the on-wafer measurement that were carried out were
limited to one port characterization applying them to two port network applications may
188
have extra consequences which are unknown Therefore actual MMIC detectors are
needed to be built and test to validate this work
To find out what power the 4times4microm2 ASPAT diode can withstand the input power
is varied from -40dBm to 10dBm via control by the P1_tone As can be seen in Figure
69 the diode starts to saturate when the received input power is about -8 dBm Above
this power limit both output voltage and sensitivity drop dramatically
Figure 69 Output voltage and detector sensitivity over wide range of input power
This diode detector circuit can thus operate adequately at given input powers from -30
dBm to -8 dBm with a sensitivity of 950VW However for the best possible sensitivity
over a range of input frequencies only one optimized input power needs to be chosen
The parameters that directly influence the voltage sensitivity are the curvature
coefficients load resistance and video resistance as can be seen from Equation (61)
Therefore in the following simulation the values RL will be optimized according to the
diodes optimum input power with regards to the highest possible voltage sensitivity
Consequently five values of load resistance were chosen from few ohms to infinity
and with the same applied input power as depicted in Figure 610 For most load
resistors the sensitivity is constant at low input power and drop at the diode saturation
region (-8dBm and greater) However for an RL value of 100KΩ and below the loaded
voltage sensitivity shows a peak near 0dBm input power which corresponds to the
maximum slope of the ASPAT detector transfer function The highest voltage sensitivity
is obtained by using an Open circuit load impedance as shown in the graph The Open
circuit load impedance gives the highest voltage sensitivity due to the voltage divider
189
between source and load impedance therefore RL must be at least 5-10 times larger than
Rj to give a better sensitivity
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load resistance of
the ASPAT detector
Furthermore the value of voltage sensitivity (βV) depends on the junction
resistance of the diode and thus the large value of Rj of the ASPAT diode yields the high
βV observed Rj which was taken from the non-linear measured IV characteristic is a
voltage dependent parameter [142]and is inversely proportional to the forward bias
voltage as depicted in Figure 611 below
Figure 611 Junction resistance as a function of forward voltage
1
10
100
1000
-40 -30 -20 -10 0 10
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Incident Power Pin (dBm)
Infinity
1KΩ
10KΩ
1MΩ
100Ω
100KΩ
0
20
40
60
80
100
0 001 002 003 004 005 006 007 008 009 01
Ju
nct
ion
Res
ista
nce
(k
Ω)
Bias Voltage (V)
190
In fact the expression of (120597119881120597119868frasl ) contribute to the video impedance expression via the
expression RV=Rj+RS (nonlinear resistance) As RS is very small compared to Rj thus it
was ignored when calculating RV Although the large value of Rj will increase the
voltage sensitivity it will also make matching difficult to achieve Therefore there will
be a compromise between the size of the matching circuit and voltage sensitivity to
attain the correct value of Rj Additionally a very high Rj (around ~1MΩ) will also
increase the detectorrsquos noise equivalent power (NEP in Eq(65)) Thus an average value
of RJ typically around 100kΩ is satisfactory[150] By having a large value of RJ one can
benefit from a low input power to drive the diode into the non-linear region and thus the
detector can work at very low RF input power The NEP for GaAsAlAs ASPAT diode
is then calculated based on parameters obtained from this simulation at room
temperature The values are compared to other diode detector available in the literature
as shown in Table 62 below
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode
Device NEP (pWHz12) RJ(KΩ) Frequency(GHz)
ASPAT (4times4 microm2) 188 92 100
Tunnel Diode (08times08 microm2)[150] 370 26 220-330
Zero bias SBD[11] 15 3 150
Sb-Heterojunction Backward Diode[145] 024 32 94
VDI Zero bias SBD[151] 2 18 110
From the Table 62 above the NEP of the ASPAT is calculated based on RF input power
which is required to obtain an output signal-to-noise ratio of unity in a 1Hz at detector
output[142] and also the assumption of only Johnson-Nyquist (thermal noise) is
dominant for small incident power (-25dBm)[152 153] The prediction of NEP for the
ASPAT is comparable to the VDI Zero bias detector since the value of their junction
resistance is much lower than that of the ASPAT Therefore it is very important to
obtain a reasonable value of junction resistance From this it is clear that a trade-off of
high voltage sensitivity and low junction resistance is best to obtain low noise
191
Finally the curvature coefficient at specific operating voltages also influences
the voltage sensitivity of the detector Figure 612 shows the calculated curvature
coefficient of the 4times4microm2 ASPAT diode used in this work
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size of 4times4μm2
The high zero-bias curvature (23V) is reached from the mutual effect of the intra-band
tunnelling in the GaAs-AlAs-GaAs and the highly doped GaAs at the anode and cathode
(Rs amp Rj) This was shown in the numerical simulation in[154] where the combined
effects of the optimum anode AlAs composition increases the curvature coefficients by
thinning the energy tunnelling window (intraband tunnelling process)
Other approaches that can lead to a large curvature is using smaller device area
with minimum series resistance [155] as was also discussed in Section 52 Having a
better curvature coefficient leads to increased voltage sensitivity as seen from Equation
(61) above and βV is also proportional to κ [111] The curvature coefficient calculated
using the above formula is nearly 23V at 1mV peak and high voltage sensitivity can be
achieved by having large value of curvature coefficient But one needs to remember that
this will also decrease with increasing input power because RJ which will also decrease
Therefore for a safe operating region the incident power that can be applied through the
diode is in between -30dBm to -8dBm for a 100GHz operating frequency
In this simulation -25dBm is chosen to simulate the GaAsAlAs ASPTAT diode
detector working at 100GHz input frequency By fixing the P1_Tone to this input power
-5
0
5
10
15
20
25
30
-001 001 003 005 007 009
Cu
rva
ture
Co
effi
cien
t(V
-1)
Voltage (V)
k(4x4 um^2)
192
the frequency is varied from 90GHz to 110GHz and the results are depicted in Figure
613 below
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power
Noticeably the voltage sensitivity of the diode detector decreases linearly with
increasing input frequency At 100GHz a sensitivity of around 540VW is obtained
However the sensitivity in this case is roughly estimated from the Equation (61) above
and will not be sufficiently accurate because of the effect of other key factors such as
reflective power which was not included This parameter must be taken into the account
due the P_1Tone power source which provides a 50 Ω impedance source (Zin) which
does not match the load impedance (ZL) which consists of JωL 1JωC and Z and which
mainly comes from the ASPAT diode itself In order to determine the load impedance at
the diode a typical ohmrsquos law (Z=VI) equation must be used at the input side of the
diode with regards to the applied frequency (100GHz)
As a result the total load impedance obtained from the simulation is 11055-
j69057Ω which is clearly not matched to the 50Ω impedance source The mismatch
between source and load leads the available power from the source to be not fully
delivered to the load and hence there is loss of power leading to a lower detector
sensitivity Therefore actual calculation must take into the account the reflection impact
as expressed in the equation below
193
120573119881(119886119888119905119906119886119897) =
119877119869119877119871120581(1 minus |Γ|2)
2(119877119881 + 119877119871) (1 +119877119904
119877119895)2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(610)
Where the term (1-|Г|2) refers to the normalized power absorption by the ASPAT diode
and Г is the reflection coefficient due to discrepancy between 50Ω input impedance (Zin)
of the input port and the diode Consequently the calculation of reflection coefficient
(eq611) is carried out by using this expression and the result is shown in Figure 614
Γ =
119885119871 minus 119885119894119899
119885119871 + 119885119894119899
(611)
Figure 614 Reflection Coefficient versus operating frequency without matching circuitry
As can be seen in Figure 614 without the matching circuit the S11 is decrease
linearly with frequency but only very slowly This means that most of the RF power
transmitted from the source is reflected back (by that ratio) when it went through the
diode Therefore in order to resolve the mismatch a matching circuit is introduced in
between the source and load of the detector circuit as shown in Figure 615 (red
rectangular) This matching circuit works by transforming the load impedance into an
impedance that is identical to the source or input impedance Note that for any
impedance matching circuit the main purpose is usually to obtain maximum power
transfer to the load however in some cases (ie oscillators) the matching circuit is to
achieve a lower noise figure Hence in a broad sense the introduction of the matching
194
circuit in a detector circuit can be defined as a circuit that convert available impedance
into wanted impedance by obeying the maximum power transfer theorem [156]
Figure 615 Detector circuit with impedance matching circuit placed in between diode and source
There are many type of matching circuit that can be used to achieve both
objectives above such as circuits using lumped element transmission-line-impedance
matching circuit single and double-stub tuners as well as a quarter-wavelength In this
design the technique used to match source and load impedance is the single open and
short stub (in red rectangular) as it is simple convenient and very efficient in ADS
simulation The important parameter that needs to be tuned in both stubs is the electrical
length (E) at any designed frequency ie 100GHz in this case The E tuning is realized
by using the Smith Chart features available in the ADS simulation tools Figure 616
shows the reflection coefficient with matching circuit modelled over a broad frequency
band and it is clearly shown that at the desired operating frequency the reflection is very
low Note that it is difficult to obtain wide frequency band matching
Matching circuit
195
Figure 616 Reflection Coefficient over wide frequency band with matching
The simulation is continued to find the effect of the matching circuit placed in
the detector circuit on the voltage sensitivity The same input power (-25dBm) is applied
to the diode and the voltage sensitivity is plotted against frequency as depicted in Figure
617 Obviously at the desired operating frequency (100GHz) the sensitivity rises up to
a maximum value of 2100VW with this value obtained without any reflection and the
input port being completely matched with the ASPAT diode model used in this work
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band frequency
Once the matching circuit to be used for 100GHz operating frequency was confirmed
further simulations were made by applying a series of low input power to find the
tangential sensitivity (Tss) of the detector diode When determining the Tss it is very
important to include the matching circuit as it will minimize any power losses through
the diode thus a very small input power can be detected
196
Figure 618 Lowest detectable signal at 100GHz operating frequency
The transfer function depicted in Figure 618 shows incident power of -80 dBm
to -50 dBm applied and the lowest detectable signal that can be obtained with 4times4microm2
mesa size ASPAT diode is around 138microV at -68dBm Although a typical value of Tss is
normally not more than ~-55dBm as in ref [74] the lower value obtained in the
simulation is because the device is operated at zero bias operation and does not use any
amplifier therefore the noise and values related to amplifier as in Equation 63 have been
neglected Even though the TSS appeared very low it is most likely very dependant to
the 10th
order polynomial equation embedded into SDD in ADS software Therefore in
near future the TSS value has to be determined in real fabricated MMIC ASPAT detector
As discusses in Section 63 other important parameter that can be extracted from
the diode transfer function is the Dynamic Range of the diode It can be obtained in a
region called square law region which is a region where the Vout of the ASPAT diode is
proportional to the square law of the input power signal From Figure 619 the square
law region is in between -68dBm and -12dBm and the linear region or in this case
saturated region is above -12dBm Taking to the account the roll-off point where Vout
has dropped 1dB below the extrapolation of the dependence at low input power and
therefore the dynamic range of the detector diode can be obtained by taking the interval
between TSS and the 1dB roll-off point (in dBm) which is ~55dBm
197
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of diode operation
The figure of Merit (M) of the detector (ie equation 63) is 2100 (90K) 12
where 2100 is the sensitivity and 90K is the value of RJ at zero bias which is equivalent
to 652 W The M value should be large however in this case due to RJ being very
large it has dropped tremendously when compared to the voltage sensitivity obtained in
this simulation The results obtained indicate a reasonably successful design of the
MMIC detector using the 4times4microm2
emitter size GaAsAlAs ASPAT diode The results
obtained lead to the design of other MMIC detector using the other fabricated diode
sizes (6times6microm2 and 10times10microm
2) A Similar procedure to the one used for the 4times4microm
2
diode was followed The only difference was the use a slight higher input power (-
20dBm) than in the 4times4microm2 design Hence the simulation results obtained are then
compiled and compared as depicted in Figure 620
Saturated
Region
198
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained from the
fabricated ASPAT in this work
The graph plotted for each dimension was taken after matching circuits were included
As can be seen in Figure 620 the highest sensitivity is achieved using the smallest
device size as this has the highest cut off frequency Table 63 below summarises the
performances of the 100GHz ASPAT detectors obtained from the simulation in this
work
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector
Device Tss(dBm) fcut-
off(GHz)
Bv
(VW)
Dynamic range dB(dBm) M(W-12
)
4times4microm2 -68 380 2100 55 65
6times6microm2 -50 151 1445 48 45
10times10microm2 -40 98 247 40 21
From table 63 above it is clear that a lower cut-off frequency will affect the
voltage sensitivity The dynamic range between each ASPAT is different because larger
size area will allow more power to go through the diode as a result of high current that
such a device can handle before reaching the saturation their lowest detectable is higher
Small diode size will detect lowest voltage but cannot handle high power On the other
hand a large diode size is able to receive high power however can only offer lower
voltage output Therefore there is a trade-off between small diode size and receiving
input power which will directly affect Tss and 1dB roll off Once again all the
100
1000
10000
90 95 100 105 110
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Frequency (GHz)
10times10microm^2
6times6microm^2
4times4microm^2
199
parameters obtained in this simulation are just estimation from the 10th
order polynomial
equation thus real ASPAT detector has to be fabricated for verification
The best device performance among all GaAsAlAs ASPAT diodes was obtained
with the 4times4microm2 mesa area size diode which was compared to other exiting millimetre
wave detector diode available in the literature Since the 100GHz is located in the W-
band spectrum frequency therefore the comparison will be performed in this frequency
band but with low input power The parameters for the-state-of-the-art zero bias
detectors are gathered in Table 64 below
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero bias detector
at W-band (75GHz-110GHz)
Device Size(microm2) Tss(dBm) βv (VW) Pin (dBm) f (GHz)
GaAsAlAs ASPAT 4times4 -68 2100 -25 100
GaAs SBD HSCH-
9161[157]
- -49 2200 94
HBD[158] 15x15 2540 -20 95
Planar SBD[159] - -68 2100 -25 100
Note that the ASPAT diode retains its favourable temperature stable characteristics
which are not the case for all the diodes used for comparison in Table 64
66 Conclusions
In this chapter all theory regarding RF detection using diodes ie parameters of
interest noise consideration etc have been discussed The aim to design and develop a
low cost reliable and sophisticated zero bias 100GHz detector circuit was achieved
through exploitation of a 4times4microm2 GaAsAlAs ASPAT diode The design was performed
with the aid of Keysight ADS modelling software utilizing harmonic balance simulation
The effect of load resistance junction resistor to the detector voltage sensitivity was also
discussed in details The 90KΩ Rj value and open circuit load resistance was chosen for
high sensitivity
200
A step by step design of a W-band ASPAT detector was presented The effect of
matching circuit was discussed in detail and where an unmatched sensitivity of 843VW
is obtained which then increases to 2100VW after matching Through RF
characterization simulation a detection at 100GHz (W-band) was successfully achieved
with a relatively large device mesa area (4times4microm2) at an input power of -25dBm
(8microWatt) leading to a 2100VW voltage sensitivity a -68dBm TSS and 55dBm dynamic
range All these values are comparable to others fabricated diodes in the literature
The zero bias ASPAT detectors based on the GaAsAlAs material system in this
work are still at an early stage of development a lot of work is still required to realize
high yielding integrated millimeter and sub-millimeter wave (MMIC) detector circuits
However as this work is on-going at Manchester it is expected that fabricated ASPAT
MMICs with even higher voltage sensitivity will be fabricated in the near future through
collaborating bodies involved in this research especially the University of Cambridge
and ICS Limited
201
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING
GAASALAS ASPAT DIODES
71 Introduction
Originally the key application for the ASPAT diode was for use as microwave and
millimetre wave detectors[18] This is due to the fact that such diode demonstrates
strong non-linearity low noise and high cut-off frequency features as described in the
previous chapters However these features are not only beneficial for detection purposes
but also allow them to be used and designed as microwave and millimetre wave sources
The only way to generateenhance continuous wave (CW) power using a non-linear
device is through frequency multiplication techniques It is known that the frequency
multiplier is the alternative approach (to 3 terminal transistors) using non-linear devices
that are used to generate high frequency low phase noise signals Any high quality low
frequency signal that goes through a frequency multiplier circuit can be generated to any
desired high output frequency[160] Therefore the main objective of this chapter is to
demonstrate the feasibility of the ASPAT diode as a compact source of microwave and
millimeter-wave receiver for imaging applications[161]
The study of the ASPAT diode as a power source begins with a brief explanation
of the importance of a frequency source and the lack of compact device and technologies
at high-frequency signals The state-of-the-art for frequency multiplier will also be
discussed In the next section (Section 74) the fundamentals of the frequency multiplier
architecture ie the principle of operation and appropriate devices will be presented
Since this is the first attempt at using GaAsAlAs ASPAT diodes a simple multiplier
circuit design and topology was built This will be discussed in detail in the subsequent
sections where simulation results are discussed The focus of the discussion will be to
demonstrate the possibility of a GaAsAlAs ASPAT diode functioning as a frequency
multiplier and comparison with other state-of-the-art varistor mode frequency
multipliers
202
72 Motivation and Background
Typically continuous wave (CW) sources generating below 100 GHz can be
obtained through oscillators amplifiers and pin diode comb generator Below 10THz
the sources can be made from RTD IMPATT diodes and Gunn oscillators and above 10
THz it is commonly done by photonic mixing quantum cascade laser (QCL) and gas
lasers [162] Both types of sources and their performance are plotted in Figure 71
However these conventional ways of generating millimetre and sub-millimetre waves
have their own limitations ie high cost complexity and sometimes requirement for
cryonic cooling The most effective way to tackle the limitations of conventional mm-
wave and THz sources is by implementing frequency multiplication technique using
solid state nonlinear diodes [163-165] such as SBD and ASPAT diodes
Figure 71 performance of state-of the-art millimetre wave source [166]
Twenty years ago there were only two types of diodes (SBD and P-N junction
diodes) often used for frequency multiplication To date besides the SBD there are
many types of diode that have been used as frequency multipliers These include the
high electron mobility varactor (HEMV) single barrier varactor (SBV) [167] and hetero-
structure barrier varactor (HBV) (270GHz with 90mW input power and Conversion
Efficiency of 72)[168 169] Other variants that have developed to enhance the
frequency multiplier performance of the classic SBD [170] include the Barrier-intrinsic-
203
n+ (BIN)diode and Barrier N-layer N+ (BNN) diode [171] Other diodes for use in such
applications are the planar doped barrier diode (PDB) Resonant tunnelling diode (RTD)
amp it families ie Quantum well diode (QWD) and step recovery diode which is a
modification of the P-N junction diode
Although three terminal devices ie FET GaAs MESFET and HEMT had
shown better performance and are capable of achieving greater efficiency and
bandwidth as well as having additional conversion gain features [160] two terminal
devices (ie varactor diodes) which are passive multiplier are still preferred This is due
to their simplicity and most importantly their ability to generate very little noise Among
these types of device technologies the SBD is preferable as it is mature and has been
shown to be very suitable for high-frequency applications [172 173]
The ASPAT diode is exploited to investigate the possibility and the feasibility of
generating microwave and millimetre-wave power through well-known frequency
multiplication methods The utilisation of the ASPAT in frequency multiplication will
also aid in generating local oscillator sources which are critical components in
heterodyne receivers The ASPAT diode will work in resistive I-V mode (varistor mode)
and has features to work also at zero bias condition thus offering low power handling
than traditional high-efficiency varactor diode since the varactor diode requires a large
reverse bias supply of several tens of volts
73 Frequency Multiplier Architecture the Basics
In principle a frequency multiplier is an electronic circuit that gives an output
frequency that is a multiple integer of its input frequency signal pumped from a local
oscillator as depicted in Figure 72 The ability to generate any desired multiple output
signals is realised by a nonlinear device ie diode or transistor Such devices though
also can give distortion or cause sudden change to the input frequency Additionally
these devices generate multiples of the input frequency (fout) The distortion of the
sinusoidal signal refers to an abruptsudden change versus amplitude or time which thus
generates higher frequency with lower amplitudes of the input signal Usually a
frequency multiplier circuit will include a bandpass filter to select the desired harmonic
204
frequencies and deselect undesired harmonic frequencies especially fundamental
harmonic at the output for further processing
Any non-linear device either in symmetricalantisymmetric current-voltage or
capacitance-voltage can be utilised to realise a frequency multiplier source [168 174]
Figure 73 describes the method where a nonlinear resistance is utilised to convert a
harmonic input signal into periodic output signal containing components at multiples of
the input frequency Both non-linear resistance and reactance characteristics can be
extended into power series methods
Figure 73 Principle of operation for frequency multiplier utilising a non-linear resistance [10]
The operating principle of the frequency multiplier is shown in Figure 73 where
the I-V curve converts a harmonic frequency input into a periodic frequency output
including components at multiples of the input frequency The non-linear I-V
characteristic can be explained in term of a power series at the operating fixed point of
bias voltage (VB) [174]
Frequency
Multiplier Circuit
finput
foutput
= nfinput
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
205
119868(119881119861 + ∆119881) = 1198860 + 1198861∆119881 + 1198862∆1198812 + 1198863∆1198813 helliphellip (71)
For a given input voltage as below
∆119881 = 119881119904 cos120596119878119905 (72)
The input signal harmonics will become
119868(119905) = 1198680 + 1198681 cos120596119904119905 + 1198682 cos 2120596119904119905 + 1198683 cos 3120596119904119905 (73)
Where t and ω are the time and angular frequency respectively based on equation (73)
the output contains both signal source and harmonics Therefore a complete frequency
multiplier circuit has to have non-linear device and filter to allow the selection of any
frequency components needed
731 Types of frequency multipliers
Frequency multipliers can be classified into passive and active multipliers This
classification is based on the ability of the frequency multiplier to yield any conversion
gainlosses The passive multiplier is the one that only produces conversion losses In
other words it can be described as a multiplier that generates an output power level
lower than the excitation input power and it is mostly dominated by passive nonlinear
devices ie Diodes On the other hand the active multipliers refer to a device that would
produce an output signal with a power level that is greater than the input signal power
This conversion of power is termed as conversion gain These types of multipliers attract
much attention as they do not only increase the frequency at the output but also the
signal power
Passive frequency multiplier can be formed by using diodes that are classified as
being of the varistor (non-linear I-V) or varactor (non-linear C-V) type [160 174] The
varistor type will influence the frequency multiplication with a non-linear resistance or
conductance (resistive diodes) and this results in a very large potential bandwidth at the
output but poor conversion efficiency The varactor diode type where the frequency
multiplications are affected by the non-linear capacitance (reactive diode) as their
reactive element typical result is high conversion efficiency A diode that is used in this
206
application must have strong nonlinearity stable electrical characteristic repeatable and
has fast enough response to an applied frequency Therefore multipliers are classified
into Doubler Tripler quintuple and so forth depending on the highest power of output
harmonic signal
In general all varactor type diodes with such characteristics will produce high
power at odd-order harmonic oscillation if any microwave signal is pumped into them
The benefit of having odd-order in multiplier design is that it reduces the complexity of
the overall circuit ie it eliminates even-order idler frequencies [175] The varactor type
diode had been shown by Manley-Rowe to a get maximum 100 conversion efficiency
for generating an ideal harmonic [176] compared to the varistor type where the
maximum efficiency achievable ideally is 1 1198992frasl where n is the multiplication factor
(output harmonics number) [174] In the case of power handling (input excitation power)
for multipliers varactor mode diode required greater power (several milli Watt) than the
varistor mode due to the fact that reverse applied voltages are very large (many tens of
volts) Therefore these types of frequency multipliers may not be suitable for the case of
high input power excitation There no report in the literature of varistor based
multipliers working with high power excitations
74 Parameters of interest for Frequency Multipliers
The simplest way to describe an equivalent circuit for a complete frequency
multiplier is by setting a Source impedance (ZS) at the input side and load impedance
(ZL) at the output side as depicted in Figure 74 below This circuit usually has the same
properties as described in the previous chapter and most of the others two ports
networks However in this case the purpose is different and is the conversion of a sine
wave signal source (Vs) with angular frequency ωs to an output signal with frequency
nωs where n is the multiplication integer or the order of multiplication
207
Figure 74 A standard system for two port frequency multiplier circuit
Referring to Figure 74 above there are few sets of parameters for the frequency
multiplier to be taken out and compared Examples are the conversion loss maximum
input signal power Impedance at source and load Bandwidth multiplication factor or
harmonic amp subharmonic content and noise conversion properties The conversion loss
(CL) is described by the ratio of available power at source (Ps) to the output harmonic
power delivered to load resistance (PL) and is normally expressed in dB It occurs due to
the nature of passive semiconductor diodes and the electronic circuit itself that are lossy
and dissipate energy On the other hand the conversion efficiency (ηn) is a ratio of the
output power at load (PL) to the available power at the input (Ps) This is often expressed
in percentage () The conversion efficiency can be determined as
120578 =
119875119878
119875119871
(74)
while the conversion loss is expressed as[174]
119871119899[119889119861] = 10 log
119875119904
119875119871= 10 log (
|1198811199042|
4 119877119890 |119885119904||1198681198712|119877119890|119885119871|
) (75)
Where Vs is the input voltage and IL is the output current amplitude Besides this the
conversion efficiency is often referred to as the inverted value of the Ln In designing a
frequency multiplier it is crucial to minimise the conversion loss and maximise the
conversion efficiency value
To achieve a perfect multiplier with minimum conversion loss the impedance of
source and load must be at an optimum level This implies that the source impedance
Frequency
Multiplier Z
L
Zout
Z
in
V
Z
SWR Г
208
(Zs) must be very close to the complex conjugate of the multiplier input impedance
(Zin) hence minimum reflection loss will occur at the input side This can be realised by
introducing an impedance matching circuit between the diode and source The power
transfer between the source and the multiplier is quantitatively described by the value of
the multiplier input reflection coefficient (Ѓ) with source Zs assumed to represent a
reference impedance This specification also can be explained in the standing wave ratio
(SWR) Both relationships are described below respectively [174]
Γ =
119885119894119899 minus 119885119904lowast
119885119894119899 + 119885119904
(76)
119878119882119877 =
1 + |Γ|
1 minus |Γ|
(77)
Where the asterisk () represents the complex conjugate of the Zs impedance
On the other hand the situation of the load impedance is different when a standard
or an optimum value is provided by the designer This will either increase the conversion
loss or decrease the output power Thus one has to keep in mind that frequency
multipliers are non-linear devices and power transfer condition both at the input and the
output depend on each other and the input signal level[174]
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler
In this work a similar ASPAT diode (4times4microm2) to that in designing millimetre
wave detector in the previous chapter is used The main objective of designing the
frequency multiplier circuit was first to investigate the performance of the ASPAT
diode as a microwave or millimetre wave signal source A design is deemed successful
when the diode physical parameters are optimised and the suitable impedance matching
network is produced for each desired harmonic as well as maximising the output power
These goals however are hard to achieve when a higher frequency operation is targeted
for use
There are many types of multiplier circuit topologies that can be implemented
using GaAsAlAs ASPAT diode in varistor mode to achieve high order of multiplication
209
Examples are single diode multiplier series or parallel connected diode multiplier anti-
parallel amp anti-series connection diode pair multiplier anti-parallel-series connected
diode multiplier and bridge frequency multiplier as well as nonlinear transmission line
frequency multiplier [174] Before designing a circuit there is one most important
consideration to make Prior to choosing any mentioned circuits to be used for frequency
doubler the design considerations are made based on the capability of ASPAT diode to
receive an optimum amount of input excitation RF power From the discussions in
Chapter 6 the ASPAT diode will reach saturation level (linear regime) at power ~
-10dBm for a device size of 4x4microm2 Once the optimum input power was confirmed the
circuit topology was carefully chosen to balance between the requirements of the
ASPAT to work at high frequencies ie low Rs and Cj amp high diode cut-off frequency
as well as the desired output signal frequency that needs to be produced
To realise the first attempt of an ASPAT diode as a signal source a simple circuit
topology of a frequency doubler was deployed as depicted in Figure 75 below The
frequency doubler circuit consists of a voltage source (can be power source) input
filtering with matching network ASPAT diode output filtering with matching network
and load impedance (ZL)
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode
In order to investigate the doubler performance the Keysight ADS simulation
tool and similar procedure to obtain accurate ASPAT model using a 10th
order
polynomial equation as in Section 65 was used The circuit in Figure 75 is translated
into ADS format as illustrated in Figure 76 Once the circuit was constructed the
analysis was performed using the Harmonics Balance (HB) simulator The circuit
requirements are matched terminations at the input and output frequencies open
Input Filtering
and matching network
Output Filtering
and matching network
Zs
Vs
ZL
Pin
fin
Pout
nfout
210
circuited terminations at the higher harmonics and optimum reactive terminations (an
inductance which resonates with the junction capacitance) at the output frequencies
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool
The circuit in Figure 76 is the simplest way of constructing a frequency doubler
circuit which consists of the signal source (P_1Tone) input matching circuit (Stubs)
filter (Short stub) ASPAT diode low pass filter output matching circuit(Stubs) and ZL
(load resistance) The utilisation of the stubs is an ideal case of simulation since in the
real fabrication stubs are normally formed in large sizes Therefore a proper design such
as using CPW instead of stubs is essential in real fabrication
Again this simulation works for this particular circuit in this chapter as all the diode
parameters were extracted from on-wafer one port S-Parameter measurement described
in chapter 5 To apply them in such two ports applications may not very accurate
however it still provides adequate parameters to build and design particular frequency
multipliers but not in general applications These simulations and results are adequate for
high frequency applications due to the fact that the actual RF measurements on the
diodes were carried out up to 40GHz and the target operating frequency in this multiplier
design does not exceed 40GHz
Since the on-wafer measurement that were carried out were limited to one port
characterization applying them to two port network applications may have extra
consequences which are unknown Therefore actual MMIC frequency multiplier is
needed to be built and test to validate this work
Input Matching
Output Matching
211
To find the optimum output power initial simulation without matching circuit
was performed This simulation was run by varying the input power from -35dBm to
20dBm but fixing the input frequency at 20GHz As can be seen in Figure 77 the lowest
point in the conversion loss (CL) and the highest point of the conversion efficiency (CE)
are obtained from an input power of -1dBm However this amount of input power is too
high for the ASPAT diode The lowest CL at -1dBm may not be accurate since it was
applied without matching Note that it is difficult to achieve a matching between source
impedance and load impedance when varying the input power Therefore a lower input
power of -10dBm is chosen for this frequency doubler operation Figure 77 shows the
Conversion Loss and Conversion Efficiency as a function of the available power of the
given input source
Figure 77 Conversion loss and conversion efficiency as a function of input power
The circuit in Figure 76 works with a -10dBm input power and 20GHz centre
frequency input signal is pumped from the power source (P1_tone) to the ASPAT diode
and distortionabrupt change of input waveform occurs at the fundamental frequency (f0
in this case 20GHz) Such abrupt change produces harmonics and these harmonics can
be classified into desired frequency component by placing two-quarter wavelength (λ4)
stubs (90˚) at both sides of the ASPAT diode At the input side of the diode short circuit
stubs are utilised to permit the f0 tone to reach the ASPAT diode and block the second
harmonics (2f0 in this case 40GHz) back to the input side and pushes it towards the
load resistance On the contrary at the output side of the diode the open circuit stubs are
used to ldquoopen circuitrdquo the 2f0 signals while ldquoshort circuitrdquo the f0 component Thus 2f0
212
signal will not be affected due to the open circuit stubs being half wave (λ2) long The
function of both stubs is basically to isolate the input and output signal from mixing each
other Therefore the design of input and output matching circuit can be achieved easily
The input matching circuit was designed based on the mentioned input frequency
(f0=20GHz) for an available input power (Ps=-10dBm) which is set up at the power
source by using two stubs with the same configuration as used in Chapter 6 Such
configuration is purposely deployed to increase the 50Ω coming from the P1_tone
source impedance to the conjugate thus reducing the reflection coefficient to the
ASPAT diode From the simulation without matching the input impedance to the diode
is 551Ω in magnitude for an available input power of -10dBm
On the output side of the diode output matching circuit is available to transform the 50Ω
port impedance in the optimum load impedance which provides minimum conversion
loss for the ASPAT diode The output matching circuit is designed based on expected
output frequency which is in this case 2f0 =40GHz Other than this optimum
impedance between load impedance and ASPAT will not be achieved thus resulting in
higher conversion loss
To ensure the proposed circuit is valid and suitable for the specific ASPAT diode
mesa size the response of conversion loss and efficiency are plotted as a function of
output frequency from 20GHz to 100GHz The results of both conversions are illustrated
in Figure 78
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
213
As can be seen in Figure 78 the conversion loss is obtained at the lowest point where
the output frequency is needed Meanwhile the conversion efficiency is maximum at the
same output frequency Therefore this indicates that the first attempt of an ASPAT
Doubler frequency source works well However the values obtained for Ln from this
simulation is 28dB which is rather high On the contrary the η achieved in this study is
very low with a value less than 1
Since the ASPAT is in varistor mode with no bias applied the conversion
efficiency is expected to be low due to resistive losses Another factor that may
contribute to lower η is the diode model itself as it is taken from a 10th
order polynomial
equation not from a diode model provided in the ADS software tools Thus some
properties of such tunnelling diode may not be included Hence it is necessary in due
course to fabricate and build such a compact frequency doubler in the future to verify
the simulation results
From the simulation point of view the less than 1 Conversion Efficiency
obtained is still good enough for a first attempt at a frequency doubler which utilises the
new ASPAT tunnelling diode The frequency doubler obtained from this work is suitable
for use in zero bias varistor modes for low power application The varistor mode doubler
performances from this simulation work are gathered and compared to other in the
literature as summarized in Table 71 below where fout is 40GHz η is 015 Ln is 28dB
and Pi is -10dBm
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art multiplier
diode
Device fout (GHz) η() Ln(dB) Pi (dBm)
ASPAT 40 015 28 -10
SBD (Si)[177] 104 2 134 -10
SBD (GaAs)[178] 13 2 137 -16
214
The performance of the 2040GHz is compared to the literature based on their input
power below -8dBm since the ASPAT is only capable of working at low power To the
best of the author knowledge very few diodes operating in varistor mode at low power
excitation can be found in the field of research and industry Therefore this 2040GHz
ASPAT Doubler might a first for tunnel diodes if it can be fabricated and test at Ka band
and above
76 Conclusions
In this chapter another alternative application based on non-linear features of
GaAsAlAs ASPAT has been presented The simulation of a frequency multiplier
(doubler) was carried out utilizing the 4times4microm2 size ASPAT diode The theory and the
ability of the ASPAT diode to operate as a frequency source were explained in detail
A unique varistor mode frequency multiplier circuit topology for the 2040GHz
ASPAT doubler has been demonstrated and briefly discussed The details and step by
step simulation technique utilizing harmonic balance from Keysight ADS has been
presented Even though the conversion efficiency is very small at 015 and large
conversion loss of 28dB there is still space for improvement in term of design ie
different circuit topology optimized input and output matching circuit etc This design
can be a good reference for a doubler operating at very low power but produce high
frequencies in Ka band
215
8 CONCLUSION AND FUTURE WORK
81 Conclusion
The main focus of this research was the development of a new tunneling diode
namely the asymmetrical spacer layer tunnel (ASPAT) diode for process repeatability
manufacturability and reproducibility The broad study undertaken was to improve the
microwave performance technology by introducing a new type of tunneling diode
For years the asymmetrical spacer layer tunnel diode was unable to be manufactured
due to the high sensitivity of the tunneling current to the barrier thickness This changed
dramatically when the MBE method was carefully optimized to precisely control the
growth to sub-monolayer precisions When stability repeatability and reproducibility in
the epitaxial growth was achieved the next step was to qualify the fabrication process of
the diodes themselves thus ensuring high performance device can be delivered to the
market
For this purpose GaAsAlAs ASPAT diodes made of two different types of
substrates were grown The first batch was grown in the Riber V100HU SSMBE and
used doped substrates Samples XMBE307 and XMBE368 were successfully grown
and fabricated from that batch The DC characterization obtained from measurement
proved that this first batch had fully functional reproducible and manufacturable
devices Later a second batch using semi insulating substrates improvement in spacer
layer and doping concentration were grown This set of samples (9 x 2rdquo wafers grown
simultaneously) and denoted as XMBE304 also showed fully functional DC
characteristic and was used for RF characterization and detector integrated circuits
The conventional GaAsAlAs ASPAT diode structures grown on doped
substrates and developed previously in our lab were not suitable for high frequency RF
characterizations Therefore a major contribution of this work was to develop a new
fabrication technique for a new GaAsAlAs ASPAT structure using semi insulating
substrates to achieve repeatability manufacturability and reproducibility in term of
process flow DC characteristics and ultimately RF characteristics Apart from the
enhancement of the epitaxial layer the other important contribution of this research was
216
the optimization of the small 4times4microm2 emitter size by incorporating both vertical and
lateral structure based purely on low cost I-line optical lithography
To obtain a repeatable and manufacturable fabrication process of lateral
GaAsAlAs ASPAT structures the key issue was to solve the over etching of the
effective mesa area when qualifying the Air Bridge technique This issue caused all
semiconductors under the metal contact to be completely lost thus leaving the metal
contact hanging without connection to any bond pad area However the developments of
the Dielectric Bridge technique realized the true performance of the GaAsAlAs ASPAT
diode structures The samplersquos surface cleanliness as well as DC and RF performance
showed significant improvement when using Si3N4 as a dielectric layer Due to the
highly isotropic etching profile and thicker GaAs layer in XMBE304 samples and
although the smallest emitter size designed on the mask was 2times2microm2 only 4times4microm
2 were
reproducible and showed good uniformity in I-V characteristics
Upon successful optimization in the fabrication process flow of the small emitter
size diodes (4times4microm2 6times6microm
2 and 10times10microm
2) a good uniformity of better than 91
was obtained for DC measurement results within a tile containing over 1000 devices
This confirmed that the lateral GaAsAlAs ASPAT diode structure can only be realized
through the Dielectric Bridge technique These devices were further characterized with
S-parameter measurements and their intrinsic and extrinsic parameter values and
junction capacitances series resistances and junction resistances were extracted leading
to intrinsic cut-off frequencies of 600GHz 429GHz and 100GHz for the three device
sizes respectively
Temperature dependence measurements and simulations were also carried out in
order to confirm that the ASPAT diodersquos characteristics were temperature insensitive
showing less than 5 change in current at both extremes of temperatures 77K to 400K
By comparison the SBD I-V characteristics variations with temperature span orders of
magnitude Physical modelling agreed very well with measured data confirming good
and validated models that can also describe temperature effects
For the realization of the integrated ASPAT millimeter wave detector empirical
modelling using ADS simulation tools was carried out This was performed to predict
the detector performance at 100GHz to comply with the initial objective to develop a
217
millimeter wave detector circuit The simulations using the 4times4microm2 diode models led to
a successful 100GHz circuit design able to detect 100GHz incoming frequency with
2100VW voltage sensitivity
The first ever GaAsAlAs ASPAT diode frequency multiplier design was also
attempted A reasonably good result was obtained for a 20 to 40GHz frequency doubler
operating in varistor mode However the conversion efficiency obtained was less than
1 Further research on this is required to improve the efficiency by using other circuit
topology ie using a balun or other Co-planar waveguides Ultimately fabricating and
testing the actual multiplier circuits are essential to validate the simulation data
82 Future Work
This work has provided a foundation for a reproducible and repeatable GaAsAlAs
ASPAT (SI substrate) wafer fabrication process and recommendations for design and
simulation of ASPAT diode MMIC detectors and frequency source has also been
provided However the GaAsAlAs ASPAT diodes still remain immature and there are
many ways to improve its DC and RF performances both experimentally and in
simulations which will directly affect the detection performances
In term of fabrication process smaller size diodes ie submicron level can be
achieved using dry etching technique with proper calibration For wet etch technique the
etched profile still can be improved by thinning the doped layers so that etching time
will be reduced and hence dimensions down to 2times2microm2 or even 15times15microm
2 can be
reproducibly made
For simulations advanced AC and RF modelling utilizing physical device
simulation available software (SILVACO) must be include in future research hence
holistic study can be conducted to improve the understanding of the ASPAT
For MMIC detector and multiplier design it is vital to produce actual MMIC
devices so that the simulation results can be validated Ultimately tested devices with
good performances can be realized and manufactured
218
REFERENCES
1 Laeri F U Simon and M Wark Host-Guest-Systems Based on Nanoporous
Crystals 2006 John Wiley amp Sons
2 Łukasiak L and A Jakubowski History of semiconductors Journal of
Telecommunications and information technology 2010 p 3-9
3 Song H-J and T Nagatsuma Present and future of terahertz communications
IEEE Transactions on Terahertz Science and Technology 2011 1(1) p 256-
263
4 Hu B and M Nuss Imaging with terahertz waves Optics letters 1995 20(16)
p 1716-1718
5 Smith PR DH Auston and MC Nuss Subpicosecond photoconducting
dipole antennas IEEE Journal of Quantum Electronics 1988 24(2) p 255-260
6 Nagatsuma T Terahertz technologies present and future IEICE Electronics
Express 2011 8(14) p 1127-1142
7 Kumar S et al A 18-THz quantum cascade laser operating significantly above
the temperature of [planck][omega]kB Nature Physics 2011 7(2) p 166-171
8 Phillips T and D Woody Millimeter-and submillimeter-wave receivers Annual
Review of Astronomy and Astrophysics 1982 20(1) p 285-321
9 Whitmer HCTaCA Crystal Rectifiers McGraw-Hill book Company
London 1948
10 Young D and J Irvin Millimeter frequency conversion using Au-n-type GaAs
Schottky barrier epitaxial diodes with a novel contacting technique Proceedings
of the Ieee 1965 53(12) p 2130-2131
11 Liu L et al A broadband quasi-optical terahertz detector utilizing a zero bias
Schottky diode IEEE microwave and wireless components letters 2010 20(9) p
504-506
12 Sankaran S Schottky barrier diodes for millimeter wave detection in a foundry
CMOS process IEEE Electron Device Letters 2005 26(7) p 492-494
13 Chattopadhyay G Submillimeter-wave coherent and incoherent sensors for
space applications in Sensors 2008 Springer p 387-414
14 Anand Y and WJ Moroney Microwave mixer and detector diodes
Proceedings of the Ieee 1971 59(8) p 1182-1190
15 Syme RT Microwave Detection Using GaasAlas Tunnel Structures Gec
Journal of Research 1993 11(1) p 12-23
16 Syme RT et al Asymmetric superlattices for microwave detection in Physical
Concepts of Materials for Novel Optoelectronic Device Applications 1991
International Society for Optics and Photonics
17 Missous M MJ Kelly and J Sexton Extremely uniform tunnel barriers for
low-cost device manufacture IEEE Electron Device Letters 2015 36(6) p 543-
545
18 Syme RT et al Novel GaAsAlAs tunnel structures as microwave detectors in
Semiconductors 92 1992 International Society for Optics and Photonics
19 Schwierz F and JJ Liou Semiconductor devices for RF applications evolution
and current status Microelectronics Reliability 2001 41(2) p 145-168
219
20 HayasHi H Development of Compound Semiconductor DevicesmdashIn Search of
Immense Possibilitiesmdash SEI TECHNICAL REVIEW 2011(72) p 5
21 Mead C Schottky barrier gate field effect transistor Proceedings of the Ieee
1966 54(2) p 307-308
22 Hooper W and W Lehrer An epitaxial GaAs field-effect transistor Proceedings
of the Ieee 1967 55(7) p 1237-1238
23 Drangeid K R Sommerhalder and W Walter High-speed gallium-arsenide
Schottky-barrier field-effect transistors Electronics Letters 1970 6(8) p 228-
229
24 Pillarisetty R Academic and industry research progress in germanium
nanodevices Nature 2011 479(7373) p 324-328
25 Oxley TH 50 years development of the microwave mixer for heterodyne
reception IEEE transactions on microwave theory and techniques 2002 50(3)
p 867-876
26 Baca AG and CI Ashby Fabrication of GaAs devices 2005 IET
27 Cho AY and J Arthur Molecular beam epitaxy Progress in solid state
chemistry 1975 10 p 157-191
28 Cho A Growth of IIIndashV semiconductors by molecular beam epitaxy and their
properties Thin Solid Films 1983 100(4) p 291-317
29 Kiehl RA and TG Sollner High speed heterostructure devices 1994
Academic Press
30 Feiginov M et al Resonant-tunnelling-diode oscillators operating at
frequencies above 11 THz Applied Physics Letters 2011 99(23) p 233506
31 Chang LL L Esaki and R Tsu Resonant tunneling in semiconductor double
barriers Applied Physics Letters 1974 24(12) p 593-595
32 Kasjoo SR Novel Electronic Nanodevices Operating in the Terahertz Region
2012
33 Kanaya H et al Structure dependence of oscillation characteristics of
resonant-tunneling-diode terahertz oscillators associated with intrinsic and
extrinsic delay times Japanese Journal of Applied Physics 2015 54(9) p
094103
34 Chattopadhyay G Technology capabilities and performance of low power
terahertz sources IEEE Transactions on Terahertz Science and Technology
2011 1(1) p 33-53
35 Betz A and R Boreiko A practical Schottky mixer for 5 THz in Proceedings of
the 7th International Symposium on Space Terahertz Technology 1996
36 Yu D et al Ultra high-speed 025-spl mum emitter InP-InGaAs SHBTs with
fsub maxof 687 GHz in Electron Devices Meeting 2004 IEDM Technical
Digest IEEE International 2004 IEEE
37 Das MB Optoelectronic detectors and receivers speed and sensitivity limits in
Optoelectronic and Microelectronic Materials Devices 1998 Proceedings 1998
Conference on 1999 IEEE
38 Rodwell MJ et al Submicron scaling of HBTs IEEE Transactions on Electron
Devices 2001 48(11) p 2606-2624
220
39 Bouloukou A and S Missous Novel High-breakdown Low-noise InGaAs-
InA1As Transistors for Radio Astronomy Applications 2006 University of
Manchester
40 Bean J Materials and technologies 1990 John Wiley amp Sons New York p
13
41 Swaminathan V and A Macrander Materials aspects of GaAs and InP based
structures 1991 Prentice-Hall Inc
42 Vurgaftman I J Meyer and L Ram-Mohan Band parameters for IIIndashV
compound semiconductors and their alloys Journal of applied physics 2001
89(11) p 5815-5875
43 Dingle R W Wiegmann and CH Henry Quantum states of confined carriers
in very thin Al x Ga 1minus x As-GaAs-Al x Ga 1minus x As heterostructures Physical
Review Letters 1974 33(14) p 827
44 Sze SM and KK Ng Physics of semiconductor devices 2006 John wiley amp
sons
45 Tyagi MS Introduction to semiconductor materials and devices 2008 John
Wiley amp Sons
46 Schubert E Delta doping of IIIndashV compound semiconductors Fundamentals
and device applications Journal of Vacuum Science amp Technology A Vacuum
Surfaces and Films 1990 8(3) p 2980-2996
47 Rhoderick EH Metal-semiconductor contacts IEE Proceedings I-Solid-State
and Electron Devices 1982 129(1) p 1
48 Piotrowska A A Guivarch and G Pelous Ohmic contacts to IIIndashV compound
semiconductors A review of fabrication techniques Solid-State Electronics
1983 26(3) p 179-197
49 Rideout V A review of the theory and technology for ohmic contacts to group
IIIndashV compound semiconductors Solid-State Electronics 1975 18(6) p 541-
550
50 Baca A et al A survey of ohmic contacts to III-V compound semiconductors
Thin Solid Films 1997 308 p 599-606
51 Higman T et al Structural analysis of AundashNindashGe and AundashAgndashGe alloyed
ohmic contacts on modulation‐doped AlGaAsndashGaAs heterostructures Journal of
applied physics 1986 60(2) p 677-680
52 Chen KJ et al High-performance enhancement-mode InAlAsInGaAs HEMTs
using non-alloyed ohmic contact and Pt-based buried-gate in Indium Phosphide
and Related Materials 1995 Conference Proceedings Seventh International
Conference on 1995 IEEE
53 Berlin L The man behind the microchip Robert Noyce and the invention of
Silicon Valley 2005 Oxford University Press
54 Goodhue W et al Large room‐temperature effects from resonant tunneling
through AlAs barriers Applied Physics Letters 1986 49(17) p 1086-1088
55 Kerr A and Y Anand Schottky diode MM detectors with improved sensitivity
and dynamic range Microwave Journal 1981 24 p 67-71
56 Davies R Simulations of the current-voltage characteristics of semiconductor
tunnel structures Gec Journal of Research 1987 5(2) p 65-75
221
57 Kelly M Tunnel structures and devices over the coming decade Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2291-2293
58 Wilkinson V and M Kelly Manufacturability of quantum semiconductor
devices in High Performance Electron Devices for Microwave and
Optoelectronic Applications 1995 EDMO IEEE 1995 Workshop on 1995
IEEE
59 Wilkinson V M Kelly and M Carr Tunnel devices are not yet
manufacturable Semiconductor Science and Technology 1997 12(1) p 91
60 Eaves L and MJ Kelly The current status of semiconductor tunnelling devices
Philos trans of the Roy soc of London Ser A Math phys and eng sciences
1996 354(1717)
61 Billen K V Wilkinson and M Kelly Manufacturability of heterojunction
tunnel devices further progress Semiconductor Science and Technology 1997
12(7) p 894
62 Kelly M The engineering of quantumndashdot devices Philosophical Transactions
of the Royal Society of London A Mathematical Physical and Engineering
Sciences 2003 361(1803) p 393-401
63 Kelly M New statistical analysis of tunnel diode barriers Semiconductor
Science and Technology 2000 15(1) p 79
64 Hayden R et al Ex situ re-calibration method for low-cost precision epitaxial
growth of heterostructure devices Semiconductor Science and Technology
2002 17(2) p 135
65 Dasmahapatra P et al Thickness control of molecular beam epitaxy grown
layers at the 001ndash01 monolayer level Semiconductor Science and Technology
2012 27(8) p 085007
66 Hayden R M Missous and M Kelly Precision growth for the manufacture of
semiconductor heterostructure devices Semiconductor Science and Technology
2001 16(8) p 676
67 Shao C et al Highly reproducible tunnel currents in MBE-grown
semiconductor multilayers Electronics Letters 2012 48(13) p 792-794
68 Abdullah MR et al GaAsAlAs tunnelling structure Temperature dependence
of ASPAT detectors in Millimeter Waves and THz Technology Workshop
(UCMMT) 2015 8th UK Europe China 2015 IEEE
69 Ariffin KZ et al Asymmetric Spacer Layer Tunnel In0 18Ga0 82AsAlAs
(ASPAT) Diode using double quantum wells for dual functions Detection and
oscillation in Millimeter Waves and THz Technology Workshop (UCMMT)
2015 8th UK Europe China 2015 IEEE
70 Liboff RL Introductory quantum mechanics 2003 Addison-Wesley
71 Esaki L Discovery of the tunnel diode IEEE Transactions on Electron Devices
1976 23(7) p 644-647
72 Landau LD LEM Quantum Mechanics Non-relativistic Theory Pergamon 3
73 Landau LD et al Quantum Mechanics Non‐Relativistic Theory Vol 3 of
Course of Theoretical Physics 1958 AIP
222
74 Syme R Tunnelling devices as microwave mixers and detectors Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2351-2364
75 Syme R et al Tunnel diode with asymmetric spacer layers for use as
microwave detector Electronics Letters 1991 27(23) p 2192-2194
76 Brown E W Goodhue and T Sollner Fundamental oscillations up to 200 GHz
in resonant tunneling diodes and new estimates of their maximum oscillation
frequency from stationary‐state tunneling theory Journal of applied physics
1988 64(3) p 1519-1529
77 Reddy M Schottky-collector resonant tunnel diodes for sub-millimeter-wave
applications 1997 University of California Santa Barbara
78 Cox R and H Strack Ohmic contacts for GaAs devices Solid-State Electronics
1967 10(12) p 1213IN71215-1214IN81218
79 Valdes LB Resistivity measurements on germanium for transistors
Proceedings of the IRE 1954 42(2) p 420-427
80 Schroder DK Semiconductor material and device characterization 2006 John
Wiley amp Sons
81 Klootwijk J and C Timmering Merits and Limitations of Circular TLM
structures for contact resistance determination for novel 111-V HBTs Proc
fEEE 2004
82 Marlow GS and MB Das The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance Solid-State
Electronics 1982 25(2) p 91-94
83 Murrmann H and D Widmann Current crowding on metal contacts to planar
devices IEEE Transactions on Electron Devices 1969 16(12) p 1022-1024
84 Berger H Models for contacts to planar devices Solid-State Electronics 1972
15(2) p 145-158
85 Reeves G and H Harrison Obtaining the specific contact resistance from
transmission line model measurements IEEE Electron Device Letters 1982
3(5) p 111-113
86 Shur MS GaAs devices and circuits 2013 Springer Science amp Business
Media
87 Popescu D and B Odbert The Advantages Of Remote Labs In Engineering
Education Educatorrsquos Corner-Agilent Technologies-application note 2011 p
11
88 DataSheet Karl Suss- PM5 Probe System Datasheet 2013
89 Keysight IC-CAP Device Modeling Software 2016 Available from
httpwwwkeysightcomenpc-1297149ic-cap-device-modeling-software-
measurement-control-and-parameter-extractioncc=USamplc=eng
90 DataSheet Anritsu 37369A Vector Network Analyzer Datasheet 2016 Available
from httpwwwtestequipmenthqcomdatasheetsANRITSU-37397D-
Datasheetpdf
91 Packard H HP 4142B Modular DC SourceManual Operation Manual 1992
Available from httpcpliteratureagilentcomlitwebpdf04142-90010pdf
223
92 Microtech C Cascade Microtech- Wincal High Performence RF calaibration
Software (Official Website) 2016 Available from
httpswwwcascademicrotechcom
93 Singh J Electronic and optoelectronic properties of semiconductor structures
2007 Cambridge University Press
94 Whyte W Cleanroom design 1999 Wiley Online Library
95 Vieu C et al Electron beam lithography resolution limits and applications
Applied Surface Science 2000 164(1) p 111-117
96 La Fontaine B Lasers and Moorersquos law SPIE Professional October 2010 p
20
97 Madou MJ Fundamentals of microfabrication the science of miniaturization
2002 CRC press
98 Serway R Physics for Scientists and Engineers 1996 Saunders Publ
Philadelphia
99 Jalali B and S Pearton InP HBTs growth processing and applications 1995
Artech House Publishers
100 Shih YC et al Effects of interfacial microstructure on uniformity and thermal
stability of AuNiGe ohmic contact to n‐type GaAs Journal of applied physics
1987 62(2) p 582-590
101 Zawawi M Advanced In0 8Ga0 2AsAlAs Resonant Tunneling Diodes
forApplications in Integrated mm-waves MMIC Oscillators 2015
102 Zawawi MAM et al Fabrication of Submicrometer InGaAsAlAs Resonant
Tunneling Diode Using a Trilayer Soft Reflow Technique With Excellent
Scalability IEEE Transactions on Electron Devices 2014 61(7) p 2338-2342
103 Silvaco I ATLAS Users Manual Device Simulation Software 2010 Santa
Clara CA
104 Kyono C et al Dependence of apparent barrier height on barrier thickness for
perpendicular transport in AlAsGaAs single‐barrier structures grown by
molecular beam epitaxy Applied Physics Letters 1989 54(6) p 549-551
105 Yang K JR East and GI Haddad Numerical modeling of abrupt
heterojunctions using a thermionic-field emission boundary condition Solid-
State Electronics 1993 36(3) p 321-330
106 Varshni YP Temperature dependence of the energy gap in semiconductors
Physica 1967 34(1) p 149-154
107 Handbook LLM Precision DC Current Voltage and Resistance
Measurements Keithley Instruments Inc[online] 6th revision Ohio 2004
108 Lipsky SE Microwave passive direction finding 2004 SciTech Publishing
109 Howell CM and SJ Parisi Principles Applications and Selection of Receiving
Diodes MACOM Semiconductor Products Division Application note AG314
110 Schulman J D Chow and D Jang InGaAs zero bias backward diodes for
millimeter wave direct detection IEEE Electron Device Letters 2001 22(5) p
200-202
111 Zhang Z et al Sub-Micron Area Heterojunction Backward Diode Millimeter-
Wave Detectors With 018$ rm pWHz^12 $ Noise Equivalent Power IEEE
microwave and wireless components letters 2011 21(5) p 267-269
224
112 Jin N et al High sensitivity Si-based backward diodes for zero-biased square-
law detection and the effect of post-growth annealing on performance IEEE
Electron Device Letters 2005 26(8) p 575-578
113 Shashkin VI et al Millimeter-wave detectors based on antenna-coupled low-
barrier Schottky diodes International journal of infrared and millimeter waves
2007 28(11) p 945-952
114 Zhao P et al GaN Heterostructure Barrier Diodes Exploiting Polarization-
Induced $delta $-Doping IEEE Electron Device Letters 2014 35(6) p 615-
617
115 Pozar DM Microwave engineering 2009 John Wiley amp Sons
116 Koolen M J Geelen and M Versleijen An improved de-embedding technique
for on-wafer high-frequency characterization in Bipolar Circuits and
Technology Meeting 1991 Proceedings of the 1991 1991 IEEE
117 Cao M et al RF characteristics uniformity of GaAsAlAs tunnel diodes in
Infrared Millimeter and Terahertz waves (IRMMW-THz) 2016 41st
International Conference on 2016 IEEE
118 Gao J RF and microwave modeling and measurement techniques for field effect
transistors 2010 SciTec
119 Ren T et al A 340-400 GHz Zero-Biased Waveguide Detector Using an Self-
Consistent Method to Extract the Parameters of Schottky Barrier Diode Applied
Computational Electromagnetics Society Journal 2015 30(12)
120 Fobelets K et al High‐frequency capacitances in resonant interband tunneling
diodes Applied Physics Letters 1994 64(19) p 2523-2525
121 Diebold S et al Modeling and Simulation of Terahertz Resonant Tunneling
Diode-Based Circuits IEEE Transactions on Terahertz Science and Technology
2016 6(5) p 716-723
122 Yong Z et al Design of a 220 GHz frequency tripler based on EM model of
Schottky diodes JOURNAL OF INFRARED AND MILLIMETER WAVES
2014 33(4) p 405-411
123 Louhi JT and AV Raisanen On the modeling and optimization of Schottky
varactor frequency multipliers at submillimeter wavelengths IEEE transactions
on microwave theory and techniques 1995 43(4) p 922-926
124 Guo J Z Zhang and C Qian Modeling of commercial millimeter wave
Schottky diodes in Microwave and Millimeter Wave Technology (ICMMT) 2016
IEEE International Conference on 2016 IEEE
125 Schneider M Metal-semiconductor junctions as frequency converters Infrared
and Millimeter Waves 1982 6 p 209
126 Muth C et al Advanced technology microwave sounder on NPOESS and NPP
in Geoscience and Remote Sensing Symposium 2004 IGARSS04 Proceedings
2004 IEEE International 2004 IEEE
127 Putley E Thermal detectors in Optical and Infrared Detectors 1977 Springer
p 71-100
128 Martin DH Spectroscopic techniques for far infra-red submillimetre and
millimetre waves in Spectroscopic Techniques for Far Infra-red Submillimetre
and Millimetre Waves 1967
225
129 Lucas W Tangential sensitivity of a detector video system with RF
preamplification in Proceedings of the Institution of Electrical Engineers 1966
IET
130 Balocco C et al Low-frequency noise of unipolar nanorectifiers Applied
Physics Letters 2011 99(11) p 113511
131 Benford D T Hunter and TG Phillips Noise equivalent power of background
limited thermal detectors at submillimeter wavelengths International journal of
infrared and millimeter waves 1998 19(7) p 931-938
132 Papoušek D Vibration-rotational Spectroscopy and Molecular Dynamics
Advances in Quantum Chemical and Spectroscopical Studies of Molecular
Structures and Dynamics Vol 9 1997 World Scientific
133 Nyquist H Thermal agitation of electric charge in conductors Physical review
1928 32(1) p 110
134 Turner CS Johnson-Nyquist Noise url httpwww claysturner
comdspJohnson-NyquistNoise pdf(Letzter Abruf Juli 2012)
135 Voss RF 1f (flicker) noise A brief review in 33rd Annual Symposium on
Frequency Control 1979 1979 IEEE
136 McWhorter AL 1f noise and related surface effects in germanium 1955
137 Hooge FN 1ƒ noise is no surface effect Physics letters A 1969 29(3) p 139-
140
138 Van der Ziel A Noise Sources characterization measurement Prentice-Hall
Information and System Sciences Series Englewood Cliffs Prentice-Hall 1970
1970
139 Hooge F 1f noise sources IEEE Transactions on Electron Devices 1994
41(11) p 1926-1935
140 Der Ziel A Theory of shot noise in junction diodes and junction transistors
Proceedings of the IRE 1955 43(11) p 1639-1646
141 Schottky W Small-shot effect and flicker effect Physical review 1926 28(1)
p 74
142 Cowley A and H Sorensen Quantitative comparison of solid-state microwave
detectors IEEE transactions on microwave theory and techniques 1966 14(12)
p 588-602
143 Schulman J et al 1$f $ Noise of Sb-Heterostructure Diodes for Pre-Amplified
Detection IEEE microwave and wireless components letters 2007 17(5) p
355-357
144 Lynch JJ et al Passive millimeter-wave imaging module with preamplified
zero-bias detection IEEE transactions on microwave theory and techniques
2008 56(7) p 1592-1600
145 Su N et al Sb-heterostructure millimeter-wave detectors with reduced
capacitance and noise equivalent power IEEE Electron Device Letters 2008
29(6) p 536-539
146 Westlund A Self-Switching Diodes for Zero-Bias Terahertz Detection 2015
Chalmers University of Technology
147 Yajima T and L Esaki Excess noise in narrow germanium pn junctions
Journal of the physical society of Japan 1958 13(11) p 1281-1287
226
148 Sommers H Tunnel diodes as high-frequency devices Proceedings of the IRE
1959 47(7) p 1201-1206
149 Miraftab V and A Abdipour Harmonic balance analysis of a microwave
balanced power amplifier in Electrical and Computer Engineering 2001
Canadian Conference on 2001 IEEE
150 Patrashin M et al GaAsSbInAlAsInGaAs Tunnel Diodes for Millimeter Wave
Detection in 220ndash330-GHz Band IEEE Transactions on Electron Devices 2015
62(3) p 1068-1071
151 Hesler JL and TW Crowe Responsivity and noise measurements of zero-bias
Schottky diode detectors Proc ISSTT 2007 p 89-92
152 Su N et al Temperature dependence of high frequency and noise performance
of Sb-heterostructure millimeter-wave detectors IEEE Electron Device Letters
2007 28(5) p 336-339
153 Lynch J et al Unamplified direct detection sensor for passive millimeter wave
imaging in Proc of SPIE Vol 2006
154 ZHANG Z et al A physics-based tunneling model for Sb-heterostructure
backward tunnel diode millimeter-wave detectors International Journal of High
Speed Electronics and Systems 2011 20(03) p 589-596
155 Bahl IJ and P Bhartia Microwave solid state circuit design 2003 John Wiley
amp Sons
156 Yeom K-W Microwave Circuit Design A Practical Approach Using ADS
2015 Prentice Hall Press
157 Xie L et al A W-band detector with high tangential signal sensitivity and
voltage sensitivity in Microwave and Millimeter Wave Technology (ICMMT)
2010 International Conference on 2010 IEEE
158 Fay P et al High-performance antimonide-based heterostructure backward
diodes for millimeter-wave detection IEEE Electron Device Letters 2002
23(10) p 585-587
159 Hrobak M et al Planar zero bias Schottky diode detector operating in the E-
and W-band in Microwave Conference (EuMC) 2013 European 2013 IEEE
160 Maas SA Nonlinear microwave and RF circuits 2003 Artech House
161 Appleby R and RN Anderton Millimeter-wave and submillimeter-wave
imaging for security and surveillance Proceedings of the Ieee 2007 95(8) p
1683-1690
162 Crowe TW et al Opening the terahertz window with integrated diode circuits
IEEE Journal of Solid-State Circuits 2005 40(10) p 2104-2110
163 Raisanen AV Frequency multipliers for millimeter and submillimeter
wavelengths Proceedings of the Ieee 1992 80(11) p 1842-1852
164 Erickson NR Diode frequency multipliers for terahertz local-oscillator
applications in Astronomical Telescopes amp Instrumentation 1998 International
Society for Optics and Photonics
165 Mehdi I et al Terahertz local oscillator sources performance and capabilities
in Astronomical Telescopes and Instrumentation 2003 International Society for
Optics and Photonics
166 Tonouchi M Cutting-edge terahertz technology Nature photonics 2007 1(2)
p 97-105
227
167 Nilsen SM et al Single barrier varactors for submillimeter wave power
generation IEEE transactions on microwave theory and techniques 1993 41(4)
p 572-580
168 Xiao Q et al A 270-GHz tuner-less heterostructure barrier varactor frequency
tripler IEEE microwave and wireless components letters 2007 17(4) p 241-
243
169 David T et al Monolithic integrated circuits incorporating InP-based
heterostructure barrier varactors IEEE microwave and wireless components
letters 2002 12(8) p 281-283
170 Lieneweg U B Hancock and J Maserjian Barrier-intrinsic-N+(BIN) diodes
for near-millimeter wave generation in Conference Digest for the Twelft
International Conference on Infrared and Millimeter Waves 1987
171 Lieneweg U et al Modeling of planar varactor frequency multiplier devices
with blocking barriers IEEE transactions on microwave theory and techniques
1992 40(5) p 839-845
172 Chattopadhyay G et al An all-solid-state broad-band frequency multiplier
chain at 1500 GHz IEEE transactions on microwave theory and techniques
2004 52(5) p 1538-1547
173 Maestrini A et al A 17-19 THz local oscillator source IEEE microwave and
wireless components letters 2004 14(6) p 253-255
174 Faber MT J Chramiec and ME Adamski Microwave and millimeter-wave
diode frequency multipliers 1995 Artech House Publishers
175 Frerking MA and JR East Novel heterojunction varactors Proceedings of the
Ieee 1992 80(11) p 1853-1860
176 Penfield P and RP Rafuse Varactor applications 1962
177 Palazzi V et al Low-power frequency doubler in cellulose-based materials for
harmonic RFID applications IEEE microwave and wireless components letters
2014 24(12) p 896-898
178 Presas SM Microwave frequency doubler integrated with miniaturized planar
antennas 2008
228
APPENDICES
Appendix I Doped substrate process details
Mask Stage Process Stage Process step Process detail Equipment
Mask 1 (Mesa
Etch)
Sample clean NMP 10 min 80˚C Beaker
Acetone 5 min Beaker
Isopropanol (IPA) 5 min Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist S1805 - Program 4 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
1 min 09mW iline
(Compensation error set to 1)
MA4 Mask
aligner
Develop MIF 319 for 1 min Beaker
Post Exposure
Bake Oven or Bake 120C for 15
minutes Hotplate
Etch Etch Cal Cal Sample - etch for 2 minutes Beaker
Etch
H3PO4H2O2H2O 3150
time is determined by the etch cal Beaker
Resist Strip Acetone - 5 min and IPA - 5 min Beaker
Mask2 (Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3 Beaker
Acetone ultrasonic for 5 Min Power 3 Beaker
Isopropanol (IPA) ultrasonic for 5 Min Power 3 Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist AznLoF - 2um grade - Program 6 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
55 seconds 09mW i-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 326 for 1 mins Beaker
Clean O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
Surface De-oxide HCLH2O 11 40 sec Beaker
Metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Anneal 420˚C 2min Furnace
229
TLM
Measurement ICCAP
Measurement
Bench
Mask 3
(BottomBacks
ide Contact)
Sample clean Acetone Optional Beaker
Isopropanol (IPA) Optional Beaker
Apply Resist Prebake
Bake for 5mins 150C to dry
the sample Hotplate
Resist (top side) S1813 - Program 6 Laurell Spinner
Soft bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Exposure
10 seconds 09mW I-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 319 for 2 mins Beaker
De-scum O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
De-oxidise
Surface De-oxide
HCLH2O 11 40
sec Beaker
metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Clean Water 3min Beaker
TLM
Measurement ICCAP
230
Appendix II Four Mask step Process Flow
Mask Stage Process Stage Process step Process detail
Mask1 Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3
Acetone ultrasonic for 5 Min Power 3
Isopropanol (IPA) ultrasonic for 5 Min Power 3
Apply Resist Prebake Bake for 5mins 150C
1st Resist AznLoF - 2um grade - Program 6
Hot Plate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 55 seconds 09mW iline (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 1 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
Mask 2 (Mesa
Etch)
Sample clean NMP Optional
Acetone Optional
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C
1st Resist S1805 - Program 4
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 1 min 09mW i-line (Compensation error set
to 1)
Develop MIF 319 for 1 min
Post Exposure Bake Oven or Bake 120C for 15 minutes
Etch Etch Cal Cal Sample - etch for 2 minutes
Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Measure TLM
Resist Strip Acetone - 5 min and IPA - 5 min
Mask 3(Isolation) Sample clean Acetone Optional
Isopropanol (IPA) Optional
231
Apply Resist Prebake Bake for 5mins 150C
Resist S1828 - Program 4
Hot Plate 115C for 1 mins
Photolithography Mask Align mask to wafer
Expose 9 mins 09mW iline (Compensation error set
to 1)
Develop MF 319 3 mins
Post Bake Oven Bake 120C for 15mins
Etch Etch Cal Refer to Etch Cal instr tab
Sub-collector Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Resist Strip Acetone 5mins + IPA 5 mins in ultrasonic bath
power 1
inspection Microscope
Sample clean Acetone Optional
Mask 4 (Bottom
Contact)
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C 1st
Resist AznLoF - 2um grade - Program 6
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 10 seconds 09mW i-line (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 2 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide
HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
232
Appendix III Epitaxial Layer XMBE277
TABLE I The epitaxial structure for sample XMBE277
Layer Thickness (nm) Doping Concentration (cm-3)
n+- In053Ga047As 45 200 x 1019
n- In053Ga047As 25 300 x 1018
In053Ga047As 20 undoped
AlAs 13 undoped
In08Ga02As 45 undoped
AlAs 13 undoped
In053Ga047As 20 undoped
n- In053Ga047As 25 300 x 1018
n+- In053Ga047As 400 100 x 1019
Semi-insulating InP
233
Appendix IV SilVaco (Atlas) Simulation Code
go atlas
---------------------------------------------------------
Structure parameter definition (Constants) values in um
---------------------------------------------------------
Thicknesses
set t_contact1=0
set t_ohmic1=03
set t_emitter=004
set t_spacer1=0005
set t_barrier=000283
set t_spacer2=02
set t_collector=004
set t_ohmic2=045
Doping concentrations
set d_ohmic1=4e18
set d_emitter=2e17
set d_collector=2e17
set d_ohmic2=4e18
set d_gap=2
set d_mesa=4
set d_device=10
set d_etch=008
Layers
set I=$t_contact1
set A=$I+$t_ohmic1
set B=$A+$t_emitter
set C=$B+$t_spacer1
set D=$C+$t_barrier
set E=$D+$t_spacer2
set F=$E+$t_collector
set G=$F+$t_ohmic2
-------------------------------------
Mesh generator
-------------------------------------
mesh diagflip width=45
xmesh location=0 s=1
xmesh location=1 s=1
xmesh location=2 s=1
xmesh location=4 s=1
xmesh location=5 s=1
xmesh location=6 s=1
xmesh location=7 s=1
xmesh location=8 s=1
xmesh location=$d_mesa s=1
xmesh location=$d_mesa+$d_gap s=1
xmesh location=$d_device s=1
Ohmic1
ymesh l=0000 s=005
ymesh l=$I s=005
234
ymesh l=$A s=0005
ymesh l=$B s=0005
ymesh l=$C s=00005
ymesh l=$D s=00005
ymesh l=$E s=0009
ymesh l=$F s=0005
ymesh l=$G s=0005
-----------------------------------
SECTION 2 Regions Structure definition
-----------------------------------
region num=1 name=contact1 material=Gold ymin=0 ymax=$I
region num=2 name=ohmic1 material=GaAs ymin=$I ymax=$A
region num=3 name=emitter material=GaAs ymin=$A ymax=$B
region num=4 name=spacer1 material=GaAs ymin=$B ymax=$C
region num=5 name=barrier material=AlAs ymin=$C ymax=$D xmin=0 xmax=$d_mesa
calcstrain qtregion=1
region num=6 name=spacer2 material=GaAs ymin=$D ymax=$E
region num=7 name=collector material=GaAs ymin=$E ymax=$F
region num=8 name=ohmic2 material=GaAs ymin=$F ymax=$G
region num=9
name=etch material=Air ymin=0 ymax=$F+$d_etch xmin=$d_mesa xmax=$d
_device
---------------------------------
Electrodes
---------------------------------
electrode num=1 name=anode xmin=0 xmax=$d_mesa ymin=0 ymax
=$I material=Gold
electrode num=2 name=cathode xmin=$d_mesa+$d_gap xmax=$d_device ymin=$F+
$d_etch ymax=$F+$d_etch material=Gold
--------------------------------
Doping
--------------------------------
doping uniform ntype conc=$d_ohmic1 Region=2 ymin=$I ymax=$A
doping uniform ntype conc=$d_emitter Region=3 ymin=$A ymax=$B
doping uniform ntype conc=$d_collector Region=7 ymin=$E ymax=$F
doping uniform ntype conc=$d_ohmic2 Region=8 ymin=$F ymax=$G
--------------------------
Contacts
--------------------------
interface sc region=1
interface ss region=2
interface ss region=3
interface si region=4
interface si region=5
interface ss region=6
interface ss region=7
interface sc ymin=$F ymax=$F xmin=$d_mesa+$d_gap xmax=$d_device
interface tunnel region=5 dytunnel=0001
contact name=cathode
contact name=anode
235
------------------------------------------
SECTION 3 Material amp Models Definitions
------------------------------------------
material material=AlAs
permittivity=10 eg300=28 mc=004 affinity=305 nc300=4e19 nimin=1e1
material material=GaAs permittivity=139 eg300=14 mc=0067
affinity=407 nc300=09e17 nimin=1e6
BAND DIAGRAM
output tquantum bandparam qfn qfp valband conband charge polarcharge flowlines
STRUCTURE GRAPHIC
solve init
save outf=XMBE304+real2str
tonyplot XMBE304+real2str
------------------------------------------
SECTION 4 ANALYSIS
------------------------------------------
trap acceptor structure=top elevel=03 density=48e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$A ymax=$C xmin=0 xmax=$d_mesa
trap acceptor structure=BOTTOM elevel=035 density=47e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$E ymax=$F xmin=0 xmax=$d_mesa
models sisel sisnlderivs qtregion=1 print
method climit=1e-4 itlimit=50 maxtraps=20
DC ANALYSIS
log outf=XMBE304log
solve init
solve vanode=0 name=anode vstep=001 vfinal=15
save outf=XMBE304str
log off
tonyplot XMBE304str
tonyplot XMBE304log
4
453 Dependence of current on Spacer II length l2 138
46 Temperature Dependent Simulation 140
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes 142
48 Conclusions 147
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES 148
51 Introduction 148
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes 149
53 RF Test Fixture Theory and Experiment 153
531 On-Wafer Measurement and Small Signal One-Port Characterizations
154
54 Device Calibration 155
541 Open and Short De-Embedding Technique 155
55 S-Parameter Measurement Result and Analysis 157
551 Diode to diode uniformity 158
552 Wafer to wafer uniformity 160
553 Small devices RF measurements 161
56 Extracting RF models of ASPAT at Zero Bias Voltage 164
561 Extraction of ASPAT parasitic element 165
562 Extraction of ASPAT intrinsic elements 168
563 Capacitances -Voltage (C-V) Extraction 172
57 Conclusions 173
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR DESIGN USING
ADS 175
61 Introduction 175
62 Detection Theory 176
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis 179
64 Noise Consideration in a Detector diode 182
65 Modelling of a 100GHz Zero-biased ASPAT Detector 184
66 Conclusions 199
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING GAASALAS
ASPAT DIODES 201
71 Introduction 201
5
72 Motivation and Background 202
73 Frequency Multiplier Architecture the Basics 203
731 Types of frequency multipliers 205
74 Parameters of interest for Frequency Multipliers 206
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler 208
76 Conclusions 214
8 CONCLUSION AND FUTURE WORK 215
81 Conclusion 215
82 Future Work 217
REFERENCES 218
APPENDICES 228
Word count including footnotes and endnotes 61500(approximately)
6
LIST OF TABLES
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials
structure grown on GaAs Substrates by MBE 23
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314
grown on a GaAs substrate by MBE 24
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP
substrate 24
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary
compound semiconductors a room temperature [41 42] 38
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work 56
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and
Ammonia on GaAs and InGaAs materials 87
Table 32 Epitaxial layer of Doped substrate samples 93
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm 94
Table 34 Generic fabrication steps established by Dr Md Adzhar [101] 97
Table 35 Standard process flow for Air-Bridge design fabrication 101
Table 36 Standard fabrication process flow for Dielectric-Bridge design 107
Table 37 New arrangement of the mask number and step in Second Run 110
Table 38 New arrangement for the Third run using Dielectric-Bridge mask 113
Table 39 The outcome of the spreading resistance before and after using LOR
technique 115
Table 310 DC and RF characteristics for XMBE304 118
Table 311 3rd
Gen Mask process step 119
Table 312 Standard deviation at two different voltages 124
Table 41 The parameter values used in this simulation 134
Table 42 The calculated values of bandgap at different temperatures 140
Table 43 The calculated effective masses for each temperature used in this simulation
141
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104) 145
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics
in this work 153
Table 52 Device to device uniformity check for large ASPAT diode 159
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at
four different frequencies[117] 159
7
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B 161
Table 55 Comparison between calculated (fully Depleted) and extracted (different
biases) values from equivalent circuit parameters for different ASPAT mesa sizes at zero
bias voltage 170
Table 61 A summary of all the important parameters of the 4x4 microm2 diode 185
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode 190
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector 198
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero
bias detector at W-band (75GHz-110GHz) 199
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art
multiplier diode 213
8
LIST OF FIGURES
Figure 21 III-V compound semiconductors mobility and band gap[24] 31 Figure 22 illustration of Homojunctions band structure material before (left) and after
(right) equilibrium 34 Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium 35
Figure 24 Lattice Matching for both materials when aL=aS 37 Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40] 37 Figure 26 Lattice mismatched material 39
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and
(b) tensile strain [1] 40 Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg
GaAs (a) Structure (b) energy band diagram and (c) Conduction band diagram when
AlGaAs is n-doped[43] 41 Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact 43
Figure 210 Energy band diagram of Schottky contact on n-type material under (a)
reverse and (b) forward bias 45 Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping
concentration ND (a) Low (b) Intermediate and (c) high 47 Figure 212 Classical view of whether an electron is can surmount a barrier or not
Quantum mechanical view allows an electron to tunnel through a barrier The probability
(blue) is related to the barrier thickness 51
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave
function[70] 52
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in
this study 55 Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27] 57
Figure 216 Conduction band diagram showing band bending and 2DEG formation at
the L1 spacer 60 Figure 217 I-V characteristics of a fabricated ASPAT diode 63 Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
63 Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b
and h are not drawn to scale 65 Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304)
The dimensions are not drawn to scale 67 Figure 221 A simple TLM structure with effective length and sheet resistance
underneath 69 Figure 222 Top view of TLM ladder structure use in this work 71 Figure 223 Typical plot of resistance versus TLM spacing 71
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM 73
9
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
75 Figure 226 Actual VNA system that was used for RF characterization 75 Figure 227 Block diagram of the ASPAT measurement step 77
Figure 31 3D illustration of Optical lithography process used in this research 85 Figure 32 Actual picture of thermal evaporator used in this study 89 Figure 33 Single layer lift-off process using negative photoresist 91 Figure 34 Current-Voltage characteristic of sample XMBE368 used in this study at
two different locations on the wafer tile 96
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2
diode dimensions designed in the 1st Gen Mask 96
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates 100 Figure 37 The layout of 1
st design of Dielectric Bridge (green circle) mask design for
100 times 100microm2 emitter size with option for doped substrate processing 100
Figure 38 Dry Etching for the first run in this study 102 Figure 39 Severe undercut of 2times2 microm
2 and 6times6 microm
2 devices 103
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet
etched 104 Figure 311 SEM Images of the GaAs sample 104
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in
this study 105
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
105
Figure 314 SEM images for InP and InGaAs taken from [56] 105 Figure 315 Short circuit behaviour on one of the fabricated device in this run 106
Figure 316 The surface of the sample after final processing 108 Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2
2500 microm2 900 microm2 400 microm2 225 microm2 100 microm2 and 36 microm2 109
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm
Tolerance 110
Figure 319 After lift-off processing 111 Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
112
Figure 321 side view of lateral ASPAT structure 113
Figure 322 The measured size of the emitter area and the length D (blue color marked)
114 Figure 323 Summary of LOR technique steps 115 Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
116
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and
alignment mark structures used in this study 118 Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-
insulating substrate device type used in this study 121 Figure 327 Example finished process device with bond pad using 3
rd Gen mask 121
Figure 328 XMBE304 TLM measurement for the top contact after annealing 122
10
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing 122 Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 4times4microm2 mesa size 123
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 6times6microm2 mesa size 124
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 10times10microm2 mesa size 124
Figure 41 SILVACO Atlas simulation process flow 128 Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the
diode multilayer heterostructures on the right 131 Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor 131 Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure
(b) the energy band diagram of the ASPAT diode structure when under three different
biases 132 Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm
2) and
(4times4microm2) using SILVACO Atlas simulator for structure device XMBE304 showing
excellent agreement between simulated and experimental data 134
Figure 46 IV characteristics of the dependencies of current on AlAs barrier 136 Figure 47 Example of analysis at -1 and 1V to the current 136 Figure 48 I-V characteristic of the dependencies current to Spacer I layer 137
Figure 49 Current changes with layer thickness l1 138 Figure 410 IV characteristic of the dependencies current to Spacer 1 layer 139
Figure 411Current change with layer thickness l2 139
Figure 412 Measurement and simulation comparison result as a function of temperature
range from 100K to 398K 142 Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample
XMBE304 143
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT
Diode [3] 144
Figure 415 Log Current vs voltage as a function of temperature for SBD sample
XMBE104 145
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and
SBD 146
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2
6x6um2 and 10x10um
2 Note the good scalability 149
Figure 52 Junction resistance versus voltage 151
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT
high sensitivity near zero bias detection 152
Figure 54 One port S-parameter measurements 155
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use
for RF calibration and measurements (Note Images are not to scale) 156
11
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices
from 15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check 158
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero
bias 158
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B)
to qualify the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2
device sizes (Real and Imaginary) Note blue colour is XMBE304A and red colour is
XMBE304B 160
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and
4times4microm2
(Real and Imaginary) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm
2 diodes respectively 162
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and
4times4 microm2 (Smith Chart) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm2 diodes respectively 162
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding
equivalent circuit model 164
Figure 512 The S-parameter Touchstone file is used to read the measured files 165
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure 166
Figure 514 Equivalent circuit model for short de-embedded structure 166
Figure 515 Smith chart representative S-parameter measurement for short (left) and
open (right) CPW The blue lines represent simulated data and the red is measured data
167
Figure 516 Equivalent circuit of the ASPAT diode 169
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 (Real and Imaginary) results for various small device designs 169
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 results (Smith Chart) for various small device designs 170
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled
capacitance vs Voltage) 172
Figure 61 Block diagram represent a complete direct receiver system 177
Figure 62 The detection process of a single wave through a non-linear IV characteristic
of a diode 177
Figure 63 Lumped element illustration of microwave detector circuit 178
Figure 64 The mixing process where the signals are processed by the non-linear I-V
characteristic to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and
fRF are applied to the diode 179
Figure 65 Measurement of Tangential Sensitivity[108 129] 181
12
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted
from MATLAB to realize a virtual GaAsAlAs ASPAT diode 186
Figure 67 Verification of actual (blue measured) and virtual (red_10th order
polynomial) I-V characteristic of the 4times4 microm2 diode used in this study 186
Figure 68 Direct detector circuit topology using an ASPAT diode 187
Figure 69 Output voltage and detector sensitivity over wide range of input power 188
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load
resistance of the ASPAT detector 189
Figure 611 Junction resistance as a function of forward voltage 189
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size
of 4times4μm2 191
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power 192
Figure 614 Reflection Coefficient versus operating frequency without matching
circuitry 193
Figure 615 Detector circuit with impedance matching circuit placed in between diode
and source 194
Figure 616 Reflection Coefficient over wide frequency band with matching 195
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band
frequency 195
Figure 618 Lowest detectable signal at 100GHz operating frequency 196
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of
diode operation 197
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained
from the fabricated ASPAT in this work 198
Figure 71 performance of state-of the-art millimetre wave source [166] 202
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
204
Figure 73 Principle of operation for frequency multiplier utilising a non-linear
resistance [10] 204
Figure 74 A standard system for two port frequency multiplier circuit 207
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode 209
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool 210
Figure 77 Conversion loss and conversion efficiency as a function of input power 211
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
212
13
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS
PUBLICATIONS
1 MRR Abdullah Y K Wang J Sexton M Missous and M J Kelly ldquoGaAsAlAs
Tunnelling Structure Temperature Dependence of ASPAT Detectorsrdquo 8th UK-Europe-
China Workshop on mm-waves and THz Technologies 2015 Cardiff University IEEE
proceedings DOI 101109UCMMT20157460591
2 Yuekun Wang Mohd Rashid Redza Abdullah James Sexton and M Missous
ldquoInGaAs-AlAs asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo 8th
UK-Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings DOI 101109UCMMT20157460589
3 K N Zainul Ariffin S G Muttlak M Abdullah M R R Abdullah Y Wang and M
Missous ldquoAsymmetric Spacer Layer Tunnel In018Ga082AsAlAs (ASPAT) Diode using
Double Quantum Wells for Dual Functions Detection and Oscillationrdquo 8th UK-
Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings Doi 101109UCMMT20157460599
4 K N Zainul Ariffin M R R Abdullah Y K Wang S G Muttlak O S
Abdulwahid J Sexton MJ Kelly and M Missous ldquoAsymmetric Spacer Layer Tunnel
Diode (ASPAT) Quantum Structure Design Linked to Current-Voltage Characteristics
A Physical Simulation Studyrdquo UK-China Millimetre Waves and Terahertz Technology
Workshop September 2017 Submitted 14 July 2017 Conference held on 11th -13th
September 2017 DOI 101109UCMMT20178068358
5 K N Zainul Ariffin Y Wang M R R Abdullah S G Muttlak Omar S
Abdulwahid J Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoInvestigations of
Asymmetric Spacer Tunnel Layer (ASPAT) Diode for High-Frequency Applicationsrdquo
DOI 101109TED20172777803
6 Omar S Abdulwahid S G Muttlak M R R Abdullah K N Zainul Ariffin J
Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoA 100GHz Zero-Biased
Quantum Tunnelling ASPAT Detectorrdquo Submitted to IEEE TED on DEC 2016 under
correctionamendment Pending fabrication data
14
CONFERENCE PRESENTATIONS
1 Mohd Rashid Redza Abdullah J Sexton Kawa Ian MJKelly and M Missousldquo
G2040GHz Frequency Doubler Varistor Mode using ASPAT diodesrdquo UK
Semiconductors 2017 2017 University of Sheffield Oral presentation
2 M R R Abdullah YueKun Wang J Sexton Kawa Ian and M Missousldquo
Microwave Performance of GaAsAlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diodesrdquo UK Semiconductors 2016 2016 University of Sheffield Oral presentation
3 M R R Abdullah J Sexton and M Missousldquo GaAsAlAs Tunnelling Structures
THz RTD oscillators and ASPAT detectorsrdquo UK Semiconductors 2015 2015
University of Sheffield Oral presentation
4 Yuekun Wang Mohd Rashid Redza Abdullah and M MissousldquoInGaAs-AlAs
asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo UK
Semiconductors 2015 2015 University of Sheffield Oral presentation
5 Mohd Rashid Redza Abdullah and M Missousldquo GaAsAlAs Tunnelling
Structure Temperature Dependence of ASPAT Detectorsrdquo PGR Conference2016
2016 University of Manchester Poster presentation
6 YueKun Wang KNZainul Ariffin Mohd Rashid Redza Abdullah J Sexton
Kawa Ian and M Missous ldquoPhysical Modelling and Experimental Studies of
InGaAsAlAs Asymmetric spacer Layer Tunnel Diodesrdquo UK Semiconductors 2016
2016 University of Sheffield Oral presentation
7 K N Zainul Ariffin S G Muttlak M R R Abdullah Y Wang Omar S
Abdulwahid M Missous ldquoExperimental and Physical Modelling of Temperature
Dependence of a Double Quantum Well In018Ga082AsAlAs ASPAT Dioderdquo UK
Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral Presentation
8 Omar S Abdulwahid Mohd Rashid Redza Abdullah S G Muttlak K N Zainul
Ariffin Mohamed Missous ldquoTunnelling Barrier Diode for Millimetre Wave
Mixingrdquo UK Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral
Presentation
9 M Abdullah K N Zainul Ariffin MRR Abdullah J Sexton M Missous and
MJ Kelly ldquoA Novel In18Ga82As-AlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diode with Double Quantum Wells for Microwave Detectionrdquo UK Semiconductor
Conference 2015 Sheffield 1 ndash 2 July 2015 Oral Presentation
15
ABSTRACT
Thesis Title GaAsAlAs ASPAT Diodes for Millimetre and Sub-Millimetre Wave
Applications
Institute School of Electrical and Electronic Engineering the University of Manchester
Candidate Mohd Rashid Redza bin Abdullah
Degree Doctor of Philosophy (PhD)
Date 3 October 2017
The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in
the early 90s as an alternative to the Schottky barrier diode (SBD) technology for
microwave detector applications due to its highly stable temperature characteristics The
ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a
thin barrier which enables RF detection at zero bias from microwaves up to
submillimetre wave frequencies In this work two heavily doped GaAs contact layer on
top and bottom layers adjacent to lightly doped GaAs intermediate layers enclose
undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that
acts as a tunnel barrier The ultimate ambition of this work was to develop a MMIC
detector as well as a frequency source based on optimized ASPAT diodes for millimetre
wave (100GHz) applications The effect of material parameter and dimensions on the
ASPAT source performances was described using an empirical model for the first time
Since this is a new device keys challenges in this work were to improve DC and
RF characteristic as well as to develop a repeatable reproducible and ultimately
manufacturable fabrication process flow This was investigated using two approaches
namely air-bridge and dielectric-bridge fabrication process flows Through this work it
was found that the GaAsAlAs heterostructures ASPAT diode are more amenable to the
dielectric-bridge technique as large-scale fabrication of mesa area up to 4times4microm2 with
device yields exceeding 80 routinely produced The fabrication of the ASPAT using i-
line optical lithography which has the capability to reduce emitter area to 4times4microm2 to
lower down the device capacitance for millimetre wave application has been made
feasible in this work The former challenge was extensively studied through materials
and structural characterisations by a SILVACO physical modelling and confirmed by
comparison with experimental data The I-V characteristic of the fabricated ASPAT
demonstrated outstanding scalability demonstrating robust processing A fair
comparison has been made between ASPAT and SBD fabricated in-house indicating
ASPAT is extremely stable to the temperature The RF characterisations were carried out
with the aid of Keysight ADS software
The DC characteristic from fabricated GaAsAlAs ASPAT diodes were absorbed
into an ADS simulation tool and utilized to demonstrate the performance of MMIC
100GHz detector as well as 20GHz40GHz signal generators Zero bias ASPAT with
mesa area of 4times4microm2 with video resistance of 90KΩ junction capacitance of 23fF and
curvature coefficient of 23V-1
has demonstrated detector voltage sensitivity above
2000VW while the signal source conversion loss and conversion efficiency are 28dB
and 03 respectively An estimate noise equivalent power (NEP) for this particular
device is 188pWHz12
16
DECLARATION AND COPYRIGHT STATEMENT
No portion of the work referred to in the dissertation has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning
COPYRIGHT STATEMENT
i The author of this thesis (including any appendices andor schedules to this thesis) owns
certain copyright or related rights in it (the ldquoCopyrightrdquo) and he has given The University of
Manchester certain rights to use such Copyright including for administrative purposes
ii Copies of this thesis either in full or in extracts and whether in hard or electronic copy
may be made only in accordance with the Copyright Designs and Patents Act 1988 (as
amended) and regulations issued under it or where appropriate in accordance with licensing
agreements which the University has from time to time This page must form part of any
such copies made
iii The ownership of certain Copyright patents designs trademarks and other intellectual
property (the ldquoIntellectual Propertyrdquo) and any reproductions of copyright works in the thesis
for example graphs and tables (ldquoReproductionsrdquo) which may be described in this thesis
may not be owned by the author and may be owned by third parties Such Intellectual
Property and Reproductions cannot and must not be made available for use without the prior
written permission of the owner(s) of the relevant Intellectual Property andor
Reproductions
iv Further information on the conditions under which disclosure publication and
commercialisation of this thesis the Copyright and any Intellectual Property andor
Reproductions described in it may take place is available in the University IP Policy
(httpdocumentsmanchesteracukDocuInfoaspxDocID=487) in any relevant Thesis
restriction declarations deposited in the University Library The University Libraryrsquos
regulations (httpwwwmanchesteracuklibraryaboutusregulations) and in The
Universityrsquos policy on Presentation of Theses
17
ACKNOWLEDGEMENTS
First and foremost all gratefulness and praise is to Allah swt for everything in my
life He is the one and the only one who granted me knowledge health patience and
ability to complete this thesis as well as colouring the whole journey of my PhD
I give my deepest and sincere gratitude to my PhD supervisor Professor Mohamed
Missous for his time support patience and guidance throughout the journey of this PhD
studies His encouragements valuable advice precious ideas and a wealth of knowledge
amp experiences have had a direct inspiration on this research Special thanks also to our
experimental officer Dr James Sexton for not only sharing his knowledge advice and
semiconductor fabrication skills but also his effort in maintaining our clean room
facilities to a great level My gratitude also extends to Mr Mallachi McGowan for his
help and assist in the lab-related issue
I am also obligated to Prof MJ Kelly from University of Cambridge and Dr Kawa
Ian from ICS limited for their measurement of the ASPAT samples on realizing the RF
characteristics This collaboration effort can hopefully last longer in designing and
implementing the ASPAT MMIC detectors
My deepest appreciation also goes to my PhD colleagues Khairul Nabilah Saad
GMuttlak Omar AbdulWahid and Yuekun Wang for their support as well as working
together with me to realize this exciting project directly and indirectly A sincere
thankfulness similarly to my seniors Dr Md Adzhar Zawawi and Dr Fauzi Packeer for
their support during the first and second year of my research For other friends and staff
members under Prof Missous and Dr M Migliorato I will always remember the strong
bond and friendship we made
I am really fortunate that I been blessed with my motherrsquos care who always make doarsquo
for my success every day during my studies As for my beloved wife Dr Nik Maryam
Anisah Nik Mursquotasim who had always encouraged me supported me and gave me
patience through all the hardship in this journey thank you very much
Finally I also would like to thank and acknowledge my sponsor Majlis Amanah
Rakyat (MARA) for financially supporting me during this studies I am greatly indebted
with your kind support which was vital to my study
18
DEDICATION
This thesis dedicated to
My respected and beloved parentshellip
My loving wife dearest siblings and in-lawshellip
19
1 INTRODUCTION
11 Background
It is an undeniable fact that semiconductors have changed the world much further
than anything people could have predicted in the last 60 or 70 years ie after the lsquocats
whisker and vacuum tube eras This field of research has been expanding from year to
year starting from the discovery of the first semiconductor (silver sulfide) in 1833 by
Michael Faraday [1 2] and it still remains very active to the present Semiconductors
have a large range of applications and are not just limited to use in communications they
can be found everywhere in other applications from Earth to space The widespread
usage and sheer number of applications have led to it growing very quickly and
contributing greatly to the growth of World Economics Over time the successful
development of semiconductor growth techniques such as Molecular Beam Epitaxy
(MBE) has enabled researchers to tailor and precisely control the semiconductor
material for new electronic devices with extra functionalities This has led to the
development of advanced devices such as high electron mobility transistors (HEMTs)
and Heterojunction bipolar transistors (HBTs) for use in wireless communication
technology Given this development today electronic devices such as computers
handheld smartphone tablets etc are no longer perceived as luxury and attractive items
but rather have become crucial in everyday life Such devices provide the means to allow
for people to remain connected to each other via the sending and receiving of
information electronically The huge demand for such types of devices has resulted in
competition in both the electronic market and technologies which only goes on to
advance the semiconductor industry
Nowadays the demand for electronic devices characterised by high speed high
efficiency ultra-low power and low manufacturing cost has increased exponentially To
fulfil this growth in demand high data rate systems are required in other words the
system must work at a higher frequency for both the transmitter and receiver The
frequency of interest for advanced wireless communication is in the Millimetre and sub-
20
millimetre wave region which is around 30-300GHz and 300 - 3000GHz respectively
The second frequency region is also sometime known as the terahertz (THz)
electromagnetic region This band lies between the microwave and infrared frequency
bands From the first time it was revealed in the late 80s[3-5] the THz region has gained
a lot of international attention due to its unique properties and since then the motivation
to develop these devices has increased significantly To date the THz frequencies region
has shown its ability to fulfil various applications such as high-resolution imaging in
medical security and surveillance field atmospheric monitoring and environment radio
astronomy as well as compact range radars[3] to name a few
However despite these developments not much effort has been made in exploring
alternative compact THz devices As a result electronic THz devices are still in the state
of immaturity as compared to microwave and photonics devices This is due to their high
cost and absence of compact amp solid-state THz sources (oscillators) and receivers
(detectors) that are capable of operating at both room and extreme temperatures[6 7] A
great deal of work still continues to fill up the lsquoTHz gaprsquo (between 300GHz and 3THz)
used for the most important part of a communication system namely the front-end
receiver or first stage Such a system is responsible for receiving detecting and
processing the received signal to be translated into useful information Furthermore THz
receivers systems still require the best-integrated components such as source mixer and
detector to reach their complete competencies[8] The detector which remains the
critical part of the receiver system requires devices or components that are able to fulfil
the THz gap requirement Studies conducted over a number of years have found out that
the key element in improving THz detection relies upon the use of passive devices ie
diodes Based on these findings many types of diode ie tunnelling diode point-contact
diode and Schottky barrier diode (SBD) have been proposed for detection applications
Amongst microwave and millimetre wave detector diode devices the Schottky
Barrier Diode (SBD) is the dominant detector that has been used since the 1940s[9] The
reason for this dominance is the ease of fabrication of a SBD (by either a point-contact
or evaporated semiconductor-metal structure) and its ability to produce a non-linear
current-voltage (I-V) characteristic which is necessary for rectifyingdetecting diodes [9
10] SBDs also have high cut-off frequency good dynamic range and are low cost To
21
date the SBD has been able to detect signals up to 100GHz [11] 1THz[12] and as high
as 10 THz[13] However the current transport mechanism in a SBD relies on thermionic
emission and therefore is strongly dependent on temperature and means that using them
in extreme conditions ie military and automotive applications is complex The SBD
also suffers from high noise figure[14] and is susceptible to burnout at a modest pulse
power level this will limit the use of ultra-high frequencies and low power signal
applications Other diodes that share the same characteristics are Planar Doped Barrier
(PDB) Germanium Backward Diode (GBD) ie a type of Esaki tunnel diode These
diodes are well known and are reliably used as millimetre wave detectors However it
still proves inefficient to substitute the SDB with any of the previously mentioned
diodes This is due to some drawbacks such as strong temperature dependence limited
dynamic range fabrication complications and hence poor reproducibility (ie GBD) and
other circuit complexities
Hence there is strong compulsion to study examine and produce new detector
diode structures that are able to solve the mentioned diodes limitations and which have
high sensitivity larger dynamic range low noise strong independence to temperature as
well as being able to work efficiently in the high-frequency band and at zero bias The
advantages of working at zero-bias relates very much to the need for a system with less
power consumption so that the device (ie mobile communication) is able to run off
small batteries for a reasonable length of time eliminating extra biasing circuit as well as
noise Therefore a new tunnelling device namely the Asymmetrical Spacer Layer
Tunnel diode (ASPAT) developed by RT Syme [15 16] and refined by Missous et
al[17] has been examined in this work The ASPAT which is in essence a
Semiconductor-insulator-semiconductor structure relies on tunnelling through a barrier
to provide current compared to conventional thermionic emission in SBDs The ASPAT
diode has many advantages a zero bias turn-on voltage very weak sensitivity to changes
in temperature (due to tunnelling) very low noise large dynamic range high resistance
to pulse burn-out [18] and as demonstrated recently can be reproducibly
manufactured[17] The growing interest in THz frequencies nowadays makes the
ASPAT an excellent choice to fulfil all requirements for ultra-high speed applications
22
ie communication (mobile computer networking) radar (military equipment) scalar
analyser and built-in test equipment
In this work an ASPAT diode based on group III-V elements of the periodic table
comprising compound semiconductors of large band gap material Aluminium Arsenide
(AlAs) sandwiched between two lower bandgap Gallium Arsenide (GaAs) are used and
intensively examined The AlAs semiconductor which is ten-monolayer thick has
almost the same lattice constant as GaAs but has a larger bandgap Consequently in the
conduction band a thin barrier of the AlAs is formed from the arrangement of such
structure The structure is made up of GaAs and AlAs both materials are grown on
GaAs substrate using Solid Source Molecular Beam Epitaxy (SSMBE) Therefore in
this study the ASPAT diode will be referred to as ldquoGaAsAlAs ASPATrdquo diode The
conventional GaAsAlAs ASPAT diode has been developed and successfully fabricated
in two different stages This work was the first carried out using facilities provided by
the University of Manchester The first stage of the work was to qualify the
reproducibility and repeatability of growth and fabrication technique which is mostly
performed on larger emitteranode size The second was to develop conventional
ASPAT diodes that can perform at Millimetre and sub-millimetre wave frequencies and
which are comprised of small emitter area
Prior to this work full physical modelling using SILVACO design software was
undertaken to generate models and to fully characterise and identify the fundamental
physical phenomenon of multi-junction ASPAT diode Therefore insight into and
performance based on diode structure and electron movement can be understood and
predicted which lead to the crucial idea in helping and advising iterations to epitaxial
growth as well as diode fabrication The verification of the physical models must be set
as a priority goal by comparing the results of statistically fabricated measured data The
advantage of physical modelling is that it can help reduce materials resources cost and
fabrication time
Further research into the field has led to the development of two other types of
ASPAT diodes that are used to compare with the conventional GaAsAlAs ASPAT
diode Their configuration involved the use of a more advanced semiconductor
technology which comprises InGaAsAlAs materials and GaAsAlAs with InGaAs
23
quantum wells The latter was a novel ASPAT diode and the former is identified as
advanced ASPAT diode However these two advanced ASPAT diodes have not been
extensively studied in this thesis as they will be covered by other co-workers at
Manchester Hence due to these some important parameters are compared to the
conventional one as it is the main focus of this work In the case of temperature
dependent studies the DC characteristic of conventional ASPAT is compared to in-
house fabrication AuGaAs SBD All the ASPATs epitaxial layer materials structures are
shown in the following tables
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials structure grown
on GaAs Substrates by MBE
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE304 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~400 ~50
Spacer1 GaAs NID 50 50 50
Barrier AlAs NID 28 28 28
Spacer 2 GaAs NID 1000 2000 1000
Buffer GaAs(Si) 4times1017
50 400 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~4500 ~3500
Substrate GaAs (Si) 50000 50000 50000
Note that sample XMBE368 and XMBE304 are grown on doped GaAs
substrates Sample XMBE368 was grown un-rotated to study the effect of barrier
thickness variation
24
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314 grown on a
GaAs substrate by MBE
XMBE314
Layer Material Doping (119836119846minus120785) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018
3000 142
Emitter GaAs (Si) 1times1017
400 142
Spacer GaAs Undoped 50 142
Quantum Well In18Ga82As Undoped 60 116
Barrier AlAs Undoped 28 283
Quantum Well In18Ga82As Undoped 60 116
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017
400 142
Ohmic Layer GaAs (Si) 4times1018
4500 142
Substrate GaAs
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP substrate
XMBE326
Layer Material Doping (cm-3
) Thickness (Aring) Bandgap (eV)
Top Ohmic1 In053Ga047As(Si) 5times1019
3000 075
Buffer 1 In053Ga047As(Si) 1times1017
350 075
Spacer1 In053Ga047As NID 50 073
Barrier AlAs NID 283 283
Spacer 2 In053Ga047As NID 2000 075
Buffer In053Ga047As(Si) 1times1017
350 075
Bottom Ohmic In053Ga047As(Si) 15times1019
4200 075
Substrate InP (Si) NID 620000
From the above tables it can be noted that XMBE307 is the first batch that was grown
in-house using a Riber V100HU MBE machine followed by XMBE368 XMBE 304
XMBE314 and finally XMBE326 The two earlier batches were grown on n+
substrate hence their fabrication process flow is simpler On the other hand the three
other batches were grown on semi insulating substrate thus requiring the development
of new repeatable reproducible and robust process flow which will be covered in this
thesis
25
In general the fabrication of the ASPAT diode is based on top-down processes this
is because the ASPAT is a vertical structure device and the junction capacitance of the
ASPAT is directly associated with the size of the anodeemitter area Further to these
the capacitance directly influences the diode cut-off frequency Therefore the simplest
way to reduce the capacitance is by reducing the lateral area of the device of the ASPAT
structure since it can be represented by a parallel plate capacitor where the capacitance
is inversely proportional to the area of the device In order to achieve high cut-off
frequencies minimising capacitance via small dimensions ie sub-micrometre level is
essential However this will also increase the series resistance of the diode As a result
the cut-off frequency will be degraded Thus there is a trade-off between small
dimension of device and high cut-off frequency to be achieved
Finally successful growth and fabrication for small area GaAsAlAs ASPAT diode
in this work has led to carefully extracted RF characteristics This becomes a stepping
stone to designing a millimetre wave integrated circuit (MMIC) detector using empirical
modelling in Keysight ADS tools Therefore a predicted performance for a 4times4 um2
fabricated ASPAT is that can operate at 100GHz ASPAT as a zero-bias detector with a
voltage sensitivity of over 2000VW Additionally the design of a millimetre wave
source using similar ASPAT diodes was also carried out The performance of a 2040
GHz doubler using GaAsAlAs ASPAT in varistor mode is demonstrated for the first
time with a conversion loss of 33dB and conversion efficiency of ~ 02
26
12 Aims and objectives
The aim of this study is to further improve the performance of microwave and
millimetre wave technology by incorporating the Asymmetrical Spacer Layer Tunnel
Diode (ASPAT) for ultimate operation near THz frequencies by designing a range of
low power high-speed devices enhancing the methods of Simulation layout and
materials amp structural characterisations with fabrication process optimization using the
facilities available at the University of Manchester
There are three main objectives in this research firstly to streamline the physical
device design and modelling using the GaAsAlAsGaAs materials systems in order to
produce a zero bias detector which is basically a rectifier of a microwave signal by
using the SILVACO Atlas simulation tools
Secondly to achieve reproducibility and manufacturability of the fabrication
process for new type of GaAsAlAs ASPAT structure (lateral structure) hence small size
ASPAT emitter by improving the device processing technique and maximising the
capability limit of the conventional i-line optical lithography that is available in Prof
Missousrsquos group laboratory
Thirdly to optimise DC parameters through electrical properties investigation as a
stepping stone to the next objective that is to characterise the RF performance of the
GaAsAlAs ASPAT detector circuit The detection properties of microwave and
millimetre wave diode will also be investigated with different ASPAT diode size at
100GHz Further to these the properties of microwave signal source will also be
developed by way of utilizing the non-linearity feature of the diode Therefore this new
type of tunnelling diode can be applied to both applications of signal detection and
signal source in the microwave and millimetre wave ranges
27
13 Outline of this Thesis
This thesis is organized into eight chapters The first chapter discusses the
contextual information that motivates the undertaking of the study An overview of the
work which includes the details of the studied samples the aim and objectives of the
whole research project are also outlined in this chapter
Chapter 2 deals with the literature review of the basic principles and concepts of
the group III-V compound semiconductors The historical background of such
semiconductors which is essential to the development of ternary structures etc and the
advancement of semiconductor materials engineering is presented The types of existing
tunneling diode as well as conventional microwave diodes are also discussed and
compared The fundamentals of ASPAT diode which includes structural parameters and
its operation are then explained in detail Finally discussions of the ASPAT key DC
characteristics which are important for detection purposes are presented
Chapter 3 focusses on the development of the experimental techniques which can
be divided into two stages In the first stage the development is towards repeatability
reproducibility and manufacturability of the ASPAT grown in-house by MBE and
fabricated by conventional i-line optical lithography The second stage involves
optimisation and fine tuning such fabrication method for GaAsAlAs ASPAT samples
that can operate at high frequency ie 100GHz detector For both stages of the
fabrication process all techniques including mask design generic and special process
flow are presented The chapter ends with discussions on issues related to sample
processing and improvements that are proposed to solve these issues
Chapter 4 dwells on the modelling of the GaAsAlAs ASPAT using the SILVACO
simulation package The discussions are expected to offer a better understanding or
insight into each layer that forms the ASPAT diode structure The chapter begins with
discussions of the operation of the SILVACO Atlas tool A validation of physical
modelling is essential and presented according to the fabricated mesa sizes of the diode
28
Thereafter towards the end of the chapter the analyses of the relationship between
device current-voltage (I-V) characteristics the structural parameter including various
temperatures dependent simulations with a comparison to an in-house fabricated SBD
are offered
Chapter 5 presents relevant DC results based on optimized fabrication process and
RF characterization which enable obtaining an intrinsic and extrinsic element of the
GaAsAlAs ASPAT diode The discussions also highlight the analysis of DC zero bias
equivalent circuit and de-embedding extraction using ADS The chapter ends with
discussions on the RF reproducibility performance which includes the performance as
well for millimeter-wave and sub-millimeter wave applications
Chapter 6 discusses the main applications of ASPAT diodes The chapter begins
with discussions on detection theory followed by the parameters of interest and ends
with circuit design as well as the performance of a 100GHz detector The circuit design
was conducted using Keysight ADS software via harmonics balance simulation tool The
performance in term of sensitivity depending on measured ASPAT emitter size is
demonstrated Finally a comparison with conventional Schottky diode is presented
towards the end of the chapter
Chapter 7 discusses a secondary application that can be applied to the ASPAT by
utilizing the nonlinearity feature of the diode to create a signal source namely a 20 to
40GHz frequency doubler in varistor mode The doubler performance of ASPAT will be
explored through circuit design constructed via Keysight ADS simulation software Each
key parameter is highlighted and discussed in detail
The final chapter of this thesis that is Chapter 8 discusses the conclusions of the
study with emphasis on the overall key research findings The chapter also highlights
suggestions for further research in this particular field of study
29
2 LITERATURE REVIEW
21 Introduction
Since 1940s the development in the technology of semiconductor electronics has
been expanding and now has led to the establishment one of the most astonishing
industries of the 3rd
-millennium era Leading this advancement is the integrated circuit
(IC) or chip which was driven mostly by silicon (Si) Overtime the IC has undergone
substantial revolution in term of power economics size and efficient energy
consumption Currently it covers every aspect of human life ie from desktop personal
computers in the office and house to the compact smartphone in the pocket and from a
gigantic satellite in space to small satellite navigation in cars In other words
semiconductor technology is crucial to human life Without developments in
semiconductor materials engineering and shrinking of device size such accomplishment
may not have been realised today Therefore this chapter presents a macro view of the
development in compound semiconductor technology especially in radio frequency (RF)
towards Millimetre and submillimetre wave applications with regard to the improvement
of material and device structures
The essentials of group III-V compound semiconductor will be emphasised for its
points of interest and application in this field (RF technology) This chapter comprises
five main sections The first section is an overview of the semiconductor history with
concentration on its advantages and applications in the RF field while the second and
third discuss the effects of III-V compounds when the interface occurs between
semiconductor-semiconductor and semiconductor-metal respectively which leads to a
basic understanding of hetero-structures device as well as contacts namely Schottky and
Ohmic The fourth section is predominantly concerned with high-speed devices ie
diodes and materials in this field which leads to the exploitation of the main researchrsquos
device Then the following section describes in detail the background works basic
principle and intrinsic amp extrinsic parameters of the Asymmetric spacer Tunnel Diode
(ASPAT) Finally the basic way of characterising the device will also include giving an
overview of how the device is measured and what parameters are needed
30
22 Historical review of III-V Compound Semiconductor for RF applications
The beginning of commercial electronic devices was marked with the first point-
contact semiconductor transistor developed in 1947 by William Shockley at Bell
Laboratories in New Jersey Shockley developed a device based on a Germanium
Bipolar Junction Transistor (Ge BJT) structure [19] with operating frequency above 1
GHz Since then and until early 1950s the development of Ge BJT was fast and it
became foremost in the market of semiconductor technology However the emergence
of Silicon (Si) challenged Ge in the market in the 1960s Si has the upper hand primarily
because it has better electron transport and low manufacturing costs compared to Ge
[19] By the 1970s almost all RF transistors were based on Si BJT Additionally the
development of Si which forms a new material from the formation of native oxide
namely Silicon Dioxide (SiO2) led to the invention of the Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) [19] The future of digital electronic industries has
been ldquobrightrdquo ever since the MOSFET was ldquobornrdquo as it has become a fundamental
building block component in complex microprocessors and flash memories Despite this
development the exploitation of Si at RF frequencies did not last long since Si is not an
optimum semiconductor for RF electronic devices The emergence of GaAs has
improved RF applications for high-speed transistors
Ge and Si which are categorised as single element semiconductor are the earliest
materials used to build the first transistor devices These devices played a crucial role
towards the development of more advanced material such as GaAs of the compound
semiconductor type[20] A compound semiconductor is a semiconductor formed by the
ionic bond of different types of semiconductor material most widely known as the group
III-V compound semiconductors The main reason for the progression of the III-V
compound semiconductors is due to their better electron mobility compared to the single
element semiconductors The term ldquomobilityrdquo in the semiconductor industry refers to the
easiness of movement of charges in many directions inside a crystal In fact it is
determined by the access resistances values with saturated velocity under certain values
of electric fields (bias) the higher the electric field the faster is the carrier movement in
the crystal Figure 21 shows the electron mobility and band gap for the most common
31
group III-V compound semiconductors Besides higher mobility III-V compound
semiconductors also have light-emission capability and are suitable for bandgap-
engineering techniques
The work on III-V compound semiconductors mainly on GaAs FETs led to a new
change for the whole RF electronics industry For example in 1966 the first GaAs
MESFET was invented[21] and achieved a maximum operating frequency of operation
of 3GHz [22] Three years later the frequency increased to 30GHz [23]
Figure 21 III-V compound semiconductors mobility and band gap[24]
With better features in terms of having a higher electron mobility compared to Si
electronic devices based on III-V materials developed rapidly This attracted attention in
many aspects especially in military radar application electronic warfare system missile
guidance control electronic for smart warfare system and secure communication To be
specific those demands were fulfilled through the application of microwave mixer and
detectors [25] which were achieved based on Schottky barrier diodes and FETs
However these applications remained largely as niche markets for use only in military
and exotic scientific projects until 1980 In addition to the microwave industry two
important diodes that played a large role in very high-frequency power source namely
the Gunn diode and the Impact Avalanche and Transit Time (IMPATT) diode which
were discovered in the 1960s[26]
100
1000
10000
100000
0 05 1 15
Bu
lk M
ob
ility
(cm
2 V
-1 s
-1
BandGap (eV)
InS
b
InA
s
Ge
Ga
Sb
In
GaA
s
Si
GaA
s
InP
32
Furthermore the invention of Molecular Beam Epitaxy (MBE) growth technique at
the beginning of 1970s has enhanced the full potential of the III-V compound
semiconductors[27] This technique has led to the formation of a new class of materials
and heterojunction device with high-quality interfaces and accurate control of the
thickness during growth[28] The advancement of material engineering that tailored the
III-V compound semiconductor with MBE effect has been beneficial for both three-
terminal and two-terminal devices As a result of this more advanced devices in both
electronics and optics were developed such as quantum well (QW) laser Resonant
tunnelling diode (RTD) high electron mobility transistor (HEMT) and many more[29]
The aim was to achieve high-speed devices transporting data at high data rates and
robust devices These devices promised an excellent option to conventional transistor
(three terminal devices) in high-frequency systems especially in the terahertz (THz) or
Millimetre and sub-millimetre wave regions [30]
One of the promising diodes that received a lot of attention is the resonant
tunnelling diode (RTD) which was first described in 1974 by Chang [31] This device
which consists of a double barrier and one quantum well is the classical tunnelling diode
Due to its good symmetrical non-linearity in its current- voltage characteristic it can be
exploited for signal generation and detection However the main focus of RTD to date
has been in the generation of continuous wave (CW) ultra-high frequency and to a lesser
extent in detection Therefore other tunnelling based diodes were developed specifically
for detection purposes which are the main foci of this work The PDB and ASPAT
diodes are the workhorse candidates for detection purposes Most of these are built based
on group III-V compound semiconductors [32]
Unlike the Very Large Scale Integration (VLSI) market ie CMOS for personal
computer (PCs) the RF electronic device for civilian application reached the consumer
market only in the late 1980s through satellite television with operating frequencies
around 12GHz [19] Since then many RF application have been deployed on the mass
market depending on their operating frequency such as 09GHz ndash 25GHz for wireless
communication 20GHz to 30GHz for satellite communication 77GHz for car radar
systems and above 90GHz for different sensor applications Utilising GaAs as the main
material RF devices have become the key underpinning components for modern
33
communication systems As a result in 1998 the volume production of mobile phones
was greater than that of PCs for the first time in history Presently production is being
made for devices like smartphones cellular phones mobile internet access and new
communication services and tablets
The development of the RF field is never ending More and more improvements are
being made especially through the design and fabrication of oscillators and detectors
which are mainly built based on group III-V compound semiconductors When RF
devices were used by the military (in the 1970s to 1980s) cost was not a concern
However after getting into civil application market (ie in the 1990s) the most frequent
issues highlighted were performance and cost[19]
The ability to generate or receive high operating frequencies with high power large
bandwidth and high sensitivity is an indicator for a good performance of RF devices
(depending on specific applications) For example the highest room temperature based
oscillator of up to 186 THz was achieved in thin well AlAs-InGaAs RTD by Professor
Masahiro Asada from Tokyo Institute of Technology [33] An excellent review on THz
sources can be found in [34] For ultra-high frequency detector and mixer applications
the two terminals RF device that is mostly used is the SBD In 1996 the highest cut off
frequency achieved by a mixer utilizing the SBD was about 5THz[35] and this has kept
increasing ever since The factor that motivates the development of THz devices is the
requirement to have a compact coherent source in the THz range Undoubtedly in the
future there will be very exciting times for enthusiasts of terahertz sources and receiver
as new generations of compact broadband and tuneable solid source device based on
advanced compound semiconductor are developed
23 The Concept of Heterostructures
A III-V compound semiconductor is mostly grown on a single semiconductor
substrate forming a layer called epitaxial heterojunction layer It is a starting point and
the key feature that brings the idea of realising the most advanced semiconductor
devices currently being developed and manufactured by combining several epitaxial
semiconductors [36-38] Heterojunctions have the capability of manipulating carrier
transport ie electron and holes transport in crystal separately unlike homojunctions
34
This has resulted in the successful development of new devices for high-speed and high-
frequency applications as well as optical sources and detectors [37] This section will
discuss lattice matched material pseudomorphic material hetero-junction band
discontinuities and quantum wells
231 Homojunctions Heterojunctions and Band Discontinuities
The term homo-junction refers to the interface between identical semiconductor
materials that have different polarity ie p-type or n-type but similar in energy gap This
phenomenon is usually applied in forming p-n junction diodes and can be understood by
referring to Figure 22 below
Figure 22 illustration of Homojunctions band structure material before (left) and after (right)
equilibrium
The materials A and B which have similar bandgap (Eg) and different dopant
types ie p-type and n-type will have their Fermi levels (Ef) closer to the valence band
(EV) and conduction band (EC) respectively before ldquothermal equilibriumrdquo Once
equilibrium is achieved Ef of both p-type and n-type will be aligned causing band
bending of EC and EV As a result a built-in electric field is introduced (via diffusion of
carriers) for both holes and electrons and forcing them to move in one direction
On the contrary a heterojunction occurs when the interface between two
semiconductor materials with different bandgap energy are brought together (ie large
energy band gap material combined with a low band gap one eg wide band gap AlAs
and narrow bandgap GaAs) This results in a steep band bending which leads to the
formation of energy band discontinuities at the junction as shown in Figure 23 In a
semiconductor heterojunction the most important parameter is the band gap energy
EC
EV
Ef
Eg
p-type E
g
n-type
EC
EV
Ef
Material A
p-type
n-type
Material B Material A Material B
35
associated with each material in the structure where the degree of discontinuity can be
utilised in varying the carriers transport properties as well as the quality of the junction
depending on the interest of the designer This leads to flexibility in tailoring device
characteristics leading to vastly improved performance of the device
Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium
Based on Figure 23 above Material A indicated with blue line is a large band
gap energy material and Material B highlighted with the red line is a low band gap
material EV represents the valence band EC the conduction band and Ef is the Fermi
level of the materials Alternatively the two materials band discontinuities are denoted
by ΔEC for the conduction band and ΔEV for the valence band χ and Eg represent the
electron affinity and band gap energy respectively
At some point where by the Fermi energy of both semiconductor materials are levelled
the structure would have reached its thermal equilibrium The band gap of materials A
and B have a discontinuity at the interface (ΔEg) of these two materials In general this
is given by
120549119864119892 = 119864119892119860 minus 119864119892
119861 (21)
Furthermore when thermal equilibrium is achieved ΔEg is then divided between
conduction band and valence band discontinuities (ΔEC and ΔEV respectively) at the
material A and B junction interfaces Their relationships can be expressed as
EC
A
EV
A
Ef
A
Eg
A
Material A Material B
χA
χ
B
ΔEC
ΔEV
Ef
B
E
g
B
EC
B
EV
B
EV
A
χA
ΔE
C
ΔEV
EC
A
Ef
EC
B
EV
B
χB
Material A Material B
Vacuum
Level Vacuum
Level
36
∆119864119862 = 120594119860 minus 120594119861 (22)
∆119864119881 = (119864119892119861 minus 119864119892
119860) minus (120594119860 minus 120594119861) (23)
∆119864119892 = 119864119892119860 minus 119864119892
119861 = ∆119864119862 + ∆119864119881 (24)
However these relationships which were introduced by Anderson can only offer an
approximation In practice the results are always different since dislocation and
interface strain occur at the junction Therefore precise control during epitaxial growth is
always required and growth technologies such as MBE are employed In due course the
band gap discontinuity can be further exploited by using different types of material
combination Examples are GaAsAl052Ga048As and In053Ga047As In052Al048As [39]
232 Lattice-Matched and Pseudomorphic Materials
As discussed earlier a heterojunction happens when any two different
semiconductor materials that have different bandgap are joined together At the atomic
level both materials often differ in lattice constant The easiest way to explain this is by
setting the formation of heterojunction which can be separated into two types lattice
matched and lattice mismatched (pseudomorphic)
2321 Lattice Matched Systems
To create discontinuities for use as a high-performance device the combination of
semiconductor materials is essential Selecting the appropriate materials that have
similar or very close lattice constants to combine is crucial to avoid disruption at the
atomic level heterojunction interface Figure 24 shows that the lattice constant of a
material A ie substrate (aS) and material B ie deposited over layer (aL) are identical
or very close and their surface atoms are perfectly matched This scenario is known as
lattice matching
37
Figure 24 Lattice Matching for both materials when aL=aS
As can be seen in Figure 25 while there are restricted binary materials available to
form good heterojunction interfaces it is possible to combine semiconductor materials in
binary ternary and quaternary forms to allow the formation of a variety of lattice-
matched heterojunction interfaces The examples of materials that have successfully
been alloyed are In053Ga047As In052Al048AsInP and GaAsAlxGa(1-x)As (x=0 to 1)
Even though the materials system hetero-junction of these materials has close lattice
constant value their band-gap will experience an abrupt variation
Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40]
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
38
The existence of binary ternary and quaternary semiconductors formed by alloying
semiconductors has expanded the opportunity for heterojunction formation in devices
The alloy semiconductor which is produced by the combinations of two semiconductors
A and B has a lattice constant that obeys Vegardrsquos Law as follows
119886(119886119897119897119900119910) = 119909119886119860 + (1 minus 119909)119886(119861) (25)
For the alloy the band gap normally follows the virtual crystal approximation
119864119892(119886119897119897119900119910) = 119909119864119892(119860) + (1 minus 119909)119864119892(119861) (26)
Table 21 shows the list of the semiconductor alloy band gap and lattice constant for
common binary and ternary for group III-V compound semiconductors[41]
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary compound
semiconductors a room temperature [41 42]
Alloy Lattice constant a(Aring) Band gap EgeV)
AlAs 5661 2239
AlSb 6136 1581
GaAs 5653 1424
GaN 3189 34
InAs 6058 0417
InP 5869 1344
Al052Ga048As 5657 2072
In053Ga047As 5868 0773
In052Al048As 5852 1543
39
2322 Pseudo-morphic Materials
The other scenario is when two different materials with different lattice constants
are brought into contact The observation can be made at the atomic level where the
atom will try to match each other as shown in Figure 26 below
Figure 26 Lattice mismatched material
In fact for both situations (ie lattice matched and lattice mismatched) the atom of
the material at the hetero-interface will change their position to maintain the geometry of
the lattice Due to distortion at this atomic level a strain is then induced at the hetero-
interface In order to form a good hetero-junction interface the strain must not exceed a
certain specific critical value which will cause crystal dislocations to occur The result of
crystal dislocation is generally bad as it will affect the carriers which will be
concentrated in the defect area thus degrading the carriersrsquo mobility This then makes
the overall function or performance of the device to become poor
Nowadays the Molecular Beam Epitaxial (MBE) technique is able to grow epitaxial
layers of mismatched semiconductor layers profile ie mismatched in their lattice
constant (aLneaS) The growth method works when the grown epitaxial layer assumes the
lattice parameters of the layer it is deposited on Nonetheless the layers must be kept
within a certain limit and the deposited layer must be thin enough to avoid defect or
dislocation formations This new layer known as a ldquopseudomorphicrdquo material will alter
its original crystal structure and physical properties
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
40
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and (b) tensile
strain [1]
Figure 27 shows material A in which the pseudomorphic materials can be related to
two situations compressive and tensile strain The compressive strain occurs when the
deposited layer has a larger lattice constant than the substrate (aL gtaS) while tensile strain
happens when the deposited layer has a smaller lattice constant than the substrate
(aLltaS) These leads to aL either to compress or stretch to fit aS respectively Note that
the pseudomorphic layers can only be grown to a certain critical thickness hc From
Figure 27 the strain between the substrate and the deposited epitaxial layer is given by
휀 =119886119871 minus 119886119878
119886119878 (27)
Where Ɛ is strain between two layers aL is lattice constant of the deposited layer and
aS is lattice constant of the substrate layer The concern in deposition of the over layer is
to avoid dislocation occurring at the interface if there is too much strain at the junction
The strain is naturally influenced by the thickness of the deposited layer and thus the
thickness of growth must be controlled below the critical thickness hc which is
expresses as
(b)
41
ℎ119888 =119886119904
2Ɛ
(28)
Moreover one needs to appreciate that even though the crystal structure and their
physical properties change the total energy within the unit cell is maintained This is
possible by distortion of the deposited layer in the direction perpendicular to the growth
direction while leading to lattice matching in the lateral plane Example of lattice
matched materials is GaAsAlAs and pseudomorphic material is In08Ga02AsInP
233 Quantum well and 2DEG
A typical application of heterojunction interface is one in which utilises ΔEC and ΔEV to
form barriers for electrons and holes One example of barriers that confines these
carriers is known as a Quantum Well (QW) A QW is a layered semiconductor usually
very thin ie about ~ 100 Aring thicknesses in which many quantum mechanical effects can
occur It is formed by a thin layer of a low bandgap energy semiconductor material eg
GaAs sandwiched between two similar large bandgap energy semiconductors eg AlAs
or AlGaAs The growth technique to achieve thin layers of QW is usually MBE The
benefit of this method is that it allows the formation of heterojunction with very thin
epitaxial layer
Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg GaAs (a)
Structure (b) energy band diagram and (c) Conduction band diagram when AlGaAs is n-doped[43]
42
The thickness of the layer that can be achieved can be as thin as the electron mean free
path (De Broglie wavelength) which is around 100 Aring to 300 Aring [44] The expression for
the De Broglie wavelength is given by
120582 = ℎ120588frasl (29)
Here h and ρ are Planckrsquos constant and momentum of the electron respectively Figure
28(b) illustrates a quantum well formation in abrupt semiconductor interfaces It can be
observed that the heterojunction boundary will experience discontinuities at the edges of
the conduction band and valence band with a quantum well generated for the carriers
(both electron and holes) The quantised energy sub-bands in the quantum well structure
in Figure 28(b) can be determined from [43]
119864 = 119864119899 + (
ℏ2
2119898lowast) (119896119909
2 + 1198961199102)
(210)
Where 119864119899 = (ℏ21205872
2119898lowast ) (119899
119871)2
and n is the energy level index that can be n=1 2 3hellip
The dopants in a semiconductor with large band gap layers may supply the
carrier to the quantum well and this occurs when the base or bottom of the quantum well
is lower than the Fermi Level and hence the high energy donors will go down to the
well therefore creating a Two-Dimensional Electron Gas (2DEG) In the 2DEG the
electrons and holes move freely in the quantum well in the plane perpendicular to the
growth direction however they are not capable of moving in the crystal growth
direction (confinement direction)[45 46] The 2DEG phenomena can be seen in Figure
28(c)
24 Metal-Semiconductor Contact
A semiconductor device is incomplete if there is no connection between the
semiconductors and the outside world A metal which is usually gold (Au) or gold
germanium (AuGe) is diffused into the semiconductor to allow for electrical connection
from the outside world to the semiconductor and vice versa The metal-semiconductor
contact can be either a Schottky contact or an Ohmic contact The Schottky contact is a
43
rectifying contact while the Ohmic contact is a contact that provides a low resistance
path between semiconductor and metal
241 Schottky Contact
The Schottky contact is basically a metal contact to the gate to enter a region or
channel in a transistor Figure 29 shows a schematic band diagram of a metal-
semiconductor contact before and after contact (Schottky-Mott concept)[47]
Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact
In Figure 29 the work function of the metal is represented by qm while the
semiconductor work function is qS The qχ is the energy difference of an electron
between the vacuum level and conduction band edge ie known as the electron affinity
and qVn is the difference between the conduction band and Fermi level in the
semiconductor EV EC Ef is the valence band energy conduction band energy and the
Fermi level respectively
The metal and semiconductor are brought together as showed in Figure 29(a)
both materials are at steady state However when the metal and semiconductors are in
contact as illustrated in Figure 29(b) the electrons that flow from the conduction band
in the semiconductor into the lower energy state of the metal will cause the Fermi level
to be aligned in thermal equilibrium Due to this process the positive charge donor is
trapped in the semiconductor interface hence forming a depletion region Xdep
Thereafter the upward bending of the energy in the semiconductor takes place On the
qχ(s)
Eg(s)
Vacuum Level
EV
EF(m)
E
F
EC
qϕ(m)
qϕ(s)
Metal Semiconductor
qVn
qϕB
qϕ(s)
qVbi
X
qχ(s)
Eg(s)
Vacuum Level
EV
EF
EC
qϕ(m)
Metal Semiconductor
Xdep
(a) (b)
44
other hand the negative charge (electron) will be accumulated within a narrow region in
the metal interface The existence of two different charges at the metal-semiconductor
boundary generates an electric field This leads to a potential barrier qB as seen by
electrons in the metal moving into the semiconductor and a built-in potential qVbi as
seen by electrons in the semiconductor trying to move into the metal
The built-in potential qVbi is defined as follows
119902119881119887119894 = 119902empty119861 minus 119902119881119899 (211)
The barrier height empty119861 in the ideal case is specified by the dissimilarity between a metal
work function empty119898 and electron affinity of the semiconductor
119902empty119861 = 119902empty119898 minus 119902120594 (212)
Referring to Eq (212) above the barrier height empty119861 rises linearly with the metalrsquos work
function empty119898 Nevertheless this is only in theory as the presence of localised surface
stated at the edges causes empty119861 to become unresponsive to the metal work function
Consequently Eq(211) is then reordered to match the difference in metal and
semiconductor work function Thus the new equation becomes
119902119881119887119894
= 119902(120601119898 minus 120601119904) (213)
A Schottky contact appears when a metal-semiconductor contact has a large
barrier height (B ge kT) and low doping concentration in the semiconductor (ND le NC) In
the case when the metal-semiconductor contact is under some bias eg reverse bias the
semiconductor will react to a positive bias according to the metal by a voltage V=-VR
This condition will affect the built-in potential and leads to increase from Vbi to
(Vbi+VR) thus increasing the barrier height empty119861 in the semiconductor as well
Consequently electrons are less able to flow from the semiconductor and cross into the
metal Therefore the current flow will be very small This phenomena is shown in
Figure 210(a)
45
Figure 210 Energy band diagram of Schottky contact on n-type material under (a) reverse and (b)
forward bias
As can be seen from Figure 210(b) when a forward bias is applied the semiconductor
is biased negatively with respect to the metal by a voltage V=Vf This will result in a
reduction in built-in potential from Vbi to Vbi-Vf The electrons in the semiconductor will
lower the barrier height and a lot of electrons will escape into the metal causing a large
current to flow Thus a large current flow in the forward direction compared to the
reverse direction Essentially this is the origin why the Schottky contact is named a
rectifying contact [48 49] For the metal side both forward and reverse biases applied
do not affect the barrier high empty119861 because there is no voltage drop there
In this system the electron and holes are transported by a phenomenon called
Thermionic Emission (TE) which happens when the semiconductor layer is lightly
doped Nd lt 1x1017119888119898minus3 The electron will only be thermionically emitted into the metal
when the energy is higher than the potential barrier[50] There is another phenomenon
called Thermionic Field Emission (TFE) which happens when the potential barrier
thickness is very thin (thin enough) to allow the electron to tunnel through the barrier
This will be discussed in the next section as this phenomenon leads to the formation of
an ohmic contact
(a) (b)
46
242 Ohmic Contact
Basically an ohmic contactrsquos purpose is to provide a low resistance path from
the semiconductor to the outside world It is different to a Schottky contact as it is a non-
rectifying contact and does not control the current flow the I-V characteristic of an
ohmic contact is linear in both forward and reverse directions (equality in current flow)
The ohmic contact also has a small voltage drop across it compared to the voltage drop
across the device
If a metal and semiconductor are bought together unavoidably a Schottky
contact will be formed Therefore to create an ohmic contact some techniques to reduce
barrier height and width of the depletion region must be used ie increase Nd In carrier
transport theory there are three mechanisms of carrier transport across the barrier
Firstly the Thermionic Emission (TE) which happens when the carries are excited to
overcome the barrier when the thermal energy is present Secondly the Thermionic
Field Emission (TFE) occurs when the electronholes have enough energy to tunnel
through an adequately thin barrier and some has overcome the low barrier at the top
Finally the Field Emission (FE) which results when carriers can tunnel through the
entire barrier The FE is the most favoured mechanism in the ohmic contact approach
[51]
From the three mechanisms above the current can be determined by the following
equations
1) Current in Thermionic emission (Figure 211(a))
exp (empty119861)
119896119879
(214)
2) Current in Thermionic field emission (Figure 211(b))
exp [
(empty119861)
11986400119888119900119905ℎ11986400
119896119879
] (215)
3) Current in Field Emission (Figure 211(c))
exp (empty119861)
11986400
(216)
47
Where k is the Boltzmann constant T is the temperature 11986400 is the tunnelling parameter
and is related to the doping concentration radic119873119863 The barrier height is denoted by empty119861
Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping concentration
ND (a) Low (b) Intermediate and (c) high
Figure 211 shows that the carrier transport mechanism is varied by the doping
concentration (ND) As can be seen from Figure 211(c) the doping concentration here is
the highest and influences the depletion region width Xdep to become smaller Therefore
Field Emission (FE) becomes dominant This FE method is the favourite method for
ohmic contact formation [51] and will be utilised in the fabrication carried out in this
work
In fabricating practical devices the ohmic contact is often split into two types
alloyed and Non-Alloyed The difference between the two is that the alloyed type is used
when the semiconductor is doped with a low doping concentration ie less than
1x1018119888119898minus3 while the Non-Alloyed is designed for heavily doped semiconductors with
more than1 times 1019119888119898minus3 doping
The alloyed ohmic contact requires thermal annealing to have a good performance
for electron transport In multi-layer metals one of the metals has the role of donor or
acceptor which is used to increase the doping concentration of the semiconductor If a
temperature anneals eg 420˚ Celsius is applied the metal will diffuse into the
semiconductor and carry the dopant into the semiconductor Therefore a heavily doped
region will be formed and the depletion width becomes narrow establishing the ohmic
contact The key example of this is the usage of the Gold-Germanium-Nickel (Au-Ge-
Ni) alloy where the Ge is the n-type dopant [52] which diffuses into the semiconductor
(a) (b) (c)
48
and perform atom replacement in the semiconductor ie in GaAs it replaces Ga On the
other hand the Non-Alloyed does not require any thermal annealing as it already has a
very high doping concentration and will automatically reduce the depletion region width
The Non-Alloyed ohmic contact has some advantages such as reproducible contact
reduced processing time and good uniformity [53]
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work
In this section some historical background of the Asymmetrical Spacer-layer
Tunnel (ASPAT) diode is given Since this is the first thesis reporting about this new
device it is worth to mention some historical background about this tunnelling diode
The ASPAT was first proposed by a group of scientists from General Electrical
Company (GEC) in 1990[16] The works led by Richard T Syme and assisted by
Michael JKelly Angus Condie and Ian Dale initiated the idea of launching a new type
of tunnel diode The idea managed to attract the interest of many parties following the
development of resonant tunnelling diode (RTD) which earlier had shown a promising
weak temperature dependence [54] However the interest in RTD is mainly limited to
microwavesub-millimetre wave generation For THz detection the requirement is to
have a significantly asymmetric IV characteristic Given this the ASPAT which has
only a single energy barrier and most importantly weak temperature dependence and
large dynamic range would be a promising candidate for this application
The development of ASPAT is a kind of reverse engineering since it was built
purposely to replace the earliest receiver diode especially the Schottky Barrier Diode
(SBD) which has strong dependence on operating temperature [55] From the time when
it was first revealed a lot of works have been done to realise this most sophisticated
tunnel diode The first attempt which was reported in [56] was meant to gather some
insights into the device by using the well-known Schrodinger and Poissonrsquos equations
for simulation The second attempt on the other hand was directed to physically grow
and fabricate the device Here the real problem occurs At the first stage of qualifying
this device it was found not to be manufacturable Since then a new tunnel diode
structure based on GaAsAlAs materials system was built by both MBE and MOCVD
Its microwave performance was then tested at 94GHz [18] The same paper also
49
reported performance comparisons between ASPAT and another microwave diode ie
Germanium Backward Diode (GBD) PDB and SBD
Work on these devices stopped due to the inability to commercialise the ASPAT
and other tunnel based devices [57-60] The problems associated with low-cost
manufacture of tunnel diodes are due to firstly the thickness of the AlAs barrier layer
the dependence of tunnelling probability (electron) through a single barrier is
exponential and varies by a factor of more than 350 for one monolayer change in the
AlAs barrier thickness[61] The tunnelling of the electron through a barrier is
proportional to the current through a barrier as a function of a bias across the AlAs
barrier[62] Secondly the bandgap which is predominantly happens to be a ternary alloy
with relative composition ie AlxGa1-xAs Here the x can vary the bandgap in the
semiconductor layer For the ASPAT a 1 change in x results in a 30 change in the
current[62] To design an ASPAT for microwave and THz applications the designer
often allows at most plusmn10 variation of the absolute current through a specific diode at a
pre-identified bias This implies that within a wafer the uniformity that the ASPAT must
achieve is less than plusmn01 monolayers while between wafer to wafer the reproducibility
in barrier thickness in average must be identically controlled[63] This explains why at
the qualification stage of investigating ASPAT there was a need to focus on
GaAsAlAs-based material to diminish further errors because of the change in x This
type of work on ASPATs has been carried out by other co-workers at Manchester and
Cambridge
Thereafter the work then focused on repeatability and manufacturability tests
These result in many attempts being carried but failed with unacceptable between wafer
to wafer reproducibility [61 64] The development of reproducibility and repeatability of
the ASPAT was pursued for over 10 years until precise control of the growth of the
thickness AlAs layer was finally achieved using MBE[65] [66 67] This achievement is
confirmed by a current density produced which varied by less than plusmn30 indicating that
the reproducibility of AlAs barrier of the order of plusmn 02 monolayers A final step to
achieve the level control for the ASPATrsquos AlAs barrier thickness was carried out and
resulted in a 1 standard deviation of the IV characteristics for both within a wafer and
different wafer (2 inches wafer size)[17] In the early stage of this work some
50
repeatability and manufacturability test was also carried out Once this vital step is
accomplished further investigation on the ASPAT was made most recently and which
will be covered in this thesis ie temperature independence[68] and new ASPAT
types[69] characterisation to achieve smaller device RF measurement and development
of THz detectors The material systems that have been investigated so far are
GaAsAlAs and InGaAsAlAs both in the ManchesterCambridge group
Recently the ASPAT was commercialised by Linwave Technology as a wideband
zero-bias detector diode This was done in April 2016 Although it is now on the market
the ASPAT remains immature in term of research and development A lot of work is still
required to enhance the device ie working at the sub-millimetre wave using ternary
material etc
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics
The basic building block of the ASPAT diode is based on heterojunction of three
multilayer semiconductor structures which have two different band gaps The structure
comprises a thin layer of wider-gap semiconductor sandwiched between two
semiconductors with narrower-gap forming a tunnel barrier The basic principle of the
ASPAT device is based on the exploitation of quantum mechanics theory using
heterojunctions interface According to quantum mechanics theory moving particles
(electrons) with less energy than the barrier height have a probability of appearing on the
other side of the barrier by a tunneling through it This can be achieved in conditions
where the barrier must be very thin (~ 10 monolayer ) This is in contrast to classical
physics where a particle must have kinetic energy at least slightly greater than the
potential barrier height in order to overcome the barrier otherwise the probability of the
particle to appear on the side of the barrier is zero
Since the ASPAT diode operation is based on tunnelling through a barrier one
needs to know that the tunnelling mechanisms can be classified into two types[44]
intraband and interband The latter is described as tunnelling that occurs from
conduction band to valence band (electron) and valence band to conduction band (holes)
This normally happens in bipolar device ie p-n junction diode which has n-type and p-
type doped regions On the other hand intraband refers to tunnelling which occurs when
51
electron tunnel from the conduction band of a semiconductor to the conduction band of
its neighbouring semiconductor The same thing happens to the holes in the valence
band The device with this type of tunnelling is normally a unipolar device which is
either p-type or n-type doped The ASPAT diode can be considered as a device that is
based on intraband tunnelling mechanism Therefore the focus will be entirely based on
its principles
261 Principle of Quantum Tunneling
Generally all tunneling diodes obey the concept of quantum mechanical
tunneling Quantum mechanical tunneling is a phenomenon where a particle is able to go
through an energy barrier higher than the kinetic energy of the particle and if it is thin
enough compared to the de Broglie electron wavelength (λ) If the electron wave is
greater than the barrier the probability of the wave to occur at both side of the barrier is
higher
Figure 212 Classical view of whether an electron is can surmount a barrier or not Quantum
mechanical view allows an electron to tunnel through a barrier The probability (blue) is related to
the barrier thickness
For the case of classical physics (Figure 212(a)) the particles can be confined by
energy barriers of a semiconductor if their kinetic energy is less than the barrier energy
The particles thus require higher kinetic to escape to other states this phenomenon is
called thermal emission In quantum mechanics (Figure 212(b)) the particle is
described in two ways as a wave and as a particle If the particle moves like a wave it
will carry all the waversquos properties Therefore it will not brusquely end up at the
En
erg
y
(a) Classical view (b) Quantum mechanical view
En
erg
y
En
erg
y
52
boundary of the energy barrier Hence when the particles collide with the barrier
(incidence) there will be a probability of penetrating the barrier if the barrier is thin
enough and has a finite height For thicker barrier the probability of a wave that can be
found on the other side of the barrier is very small However the possibility of the
electron wave to appear on the other side of the barrier is increased by thinning the
barrier The potential barrier of semiconductor material technology can be determined by
using Homojunctions structures with different doping profile This will result in a
difference in band alignment and multilayer heterojunction structure (different
semiconductors have different band gap) which includes semiconductors insulators and
conductors (metals)
The easiest way to explain the phenomenon is by considering a potential barrier
Epot(x) with barrier height E0 energy bigger than the total energy E as shown in Figure
213 the potential energy occurs in a finite space between 0ltxlta and is 0 outside
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave function[70]
The electron outside the region of the potential barrier (xlt0 and xgta) is free to
move The effective mass of the electron is different inside and outside of the barrier in
real tunneling devices when implemented using semiconductor heterostructures The
quantum mechanical equations predict the wave nature of matter which states that matter
unveils wavelike properties under some conditions and particle-like properties under
other conditions The wavelike properties as described by the Schrodinger Formula of
E0 Transmitted Ψ = 119862119890minus119894119896119909
Incident Ψ = 119860119890119894119896119909
Reflected Ψ = 119861119890minus119894119896119909 Ψ = 119863119890minus119894119896119909
0 a
E
x
V(x
)
53
quantum mechanics represent a particle penetrating through a potential barrier most
likely as an evanescent wave coupling of electromagnetic waves[44]
To start the calculation of the tunnelling probability the Schrodinger equation is given
by
119894ℏ
120597
120597119905Ψ(119903 119905) = ΨΗ(r t)
(217)
Where ℏ is Planckrsquos constant (662606957 times 10119890minus341198982119896119892119904
2120587frasl ) Ψ(119903 119905)is the wave
function at position r and time t Η is the Hamiltonian operator given by
Η = minus
ℏ2
2119898nabla2 + 119881(119903 119905)
(218)
Where 119881(119903 119905)is the potential energy which is dependent on space and time 119881(119903 119905) is
considered zero for a particle traveling in free space without any potentials The plane
wave with vector r and t is given by
Ψ(119903 119905) = 119890119894(119896119903minus120596119905) (219)
This equation satisfies Eq (217) above under the condition where the particle is
travelling in free space without potential k is the wave vector which is equivalent
to2120587120582frasl and the angular frequency 120596 is 2120587 multiplied by the frequency
In the case of tunneling through a potential barrier the method of separation of
variables is used to simplify the problem as in the equation below
Ψ(119903 119905) = 119877(119903)119879(119905) (220)
It is assumed that the problem above is divided into time-dependent and time-
independent parts 119877(119903) is the spatial component and 119879(119905) is the time-based component
of the wave function The time dependent problem as shown above in the Schroumldinger
Equation (1) can easily be solved by filling up all the finite parameters The solution of
54
the time-independent part gives the tunneling probability For the one-dimensional (1D)
time-independent Schroumldinger equation[44]
119864120595(119909) = minus
ℏ2
2119898
1198892
1198891199092120595(119909) + 119881(119909)120595(119909)
(221)
E is the total energy and 120595(119909)is the spatial component of the wave function along the x
axis The combination to the wave function is given by
120595(119903 119905) = 120595(119903)119890minus(
119894119864119905ℏ
)
(222)
The time-independent plane wave solution of 120595 = 119890119894119896119909 satisfies the equation (221) for
any constant potential V0 in space Plugging in the wave solution yields the condition
that
119896 = radic2119898lowast(119864 minus 1198810)
ℏ2
(223)
Referring to Figure 213 also the barrier with exact rectangular shape with height E0 and
width W the solution of the wave functions and tunneling probability can be extracted
by using the below equation [44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2= [1 +
11986402 sin ℎ2 (119896119882)
4119864(1198640 minus 119864)]minus1 asymp
16119864(1198640 minus 119864)
11986402 exp(minus2radic
2119898lowast(1198640 minus 119864)
ℎ2119882)
(224)
For more complex barrier shape Wentzel-Kramers-Brillouin has simplified the
Schrodinger equation for tunneling probability of carrier which becomes[44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2asymp 119890minus2int |119896(119886)|119889119886
1198860 asymp 119890
minus2int radic2119898lowast
ℎ2 [119880(119886)minus119864]1198891198861198860
(225)
55
This means that the incident electron has a finite probability T of tunneling
through the potential barrier and this leads to the concept of tunneling probability as well
as a tunnelling current Therefore this becomes the basis of tunneling phenomena and
thus all devices which are related to tunneling can be modelled and analysed based on
this basic example The tunneling phenomenon is a majority-carrier effect and the
tunneling time is set by the quantum transition probability per unit time (which is on the
order of picoseconds) rather than the transit time concept [44 71] This enables the
tunneling devices to work at a much higher switching speed They can also be used in
high-frequency applications such as microwave circuit and high-speed oscillators
262 ASPAT Structural Parameters of GaAsAlAs materials System
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in this study
Conduction band profile
56
The core materials that make up the ASPAT diode in this work is based on
heterostructure of group III-V compound semiconductors Such materials are chosen due
their mature excellent properties and their band gap which can be tailored to fit the
desired design as well as to improve the carrier mobility In this work the primary layers
that form an ASPAT diode are very thin pure Aluminium Arsenic (AlAs) of thickness
ten monolayers buried in between dissimilar thickness of pure Gallium Arsenic (GaAs)
layers as can be seen in the red circle in Figure 214 above These two GaAs layers are
known as spacer layer which normally have a ratio of 401 or 201 in thickness The
asymmetrical spacers layer and the thin barrier in such arrangement lead to an
asymmetric current-voltage characteristics as proposed firstly by Syme and Kelly[15]
To examine and investigate this GaAsAlAs ASPAT structure in term of electrical and
RF characteristics the device have been grown according to Table 22 below
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work
Material Doping (cmminus3) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018 3000 142
Emitter GaAs (Si) 1times1017 400 142
Spacer GaAs Undoped 50 142
Barrier AlAs Undoped 28 283
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017 400 142
Ohmic Layer GaAs (Si) 4times1018 4500 142
Substrate GaAs - 650 microm 142
The arrangement of the multi-layers that form a lattice matched GaAsAlAs ASPAT
diode can be transformed into band structure profile view for easy understanding The
conduction band profile at equilibrium is as sketched in Figure 214 As can be seen in
the Figure 214 the ASPAT diode is generally a heterojunction multilayer structure
tunnelling diode
57
Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27]
The generic structure of ASPAT diode which is shown in Figure 215 above with a
schematic band structure comprises the following (starting from the top)
(1) A thick layer of heavily doped n++
about 4e+18cm-3
of GaAs with a thickness of
approximately 300nm
(2) An intermediate layer of lightly doped n-type about 1e+17cm-3
of GaAs with
thickness of approximately 40nm
(3) A spacer layer not intentionally doped (NID) GaAs with thickness of approximately
5nm
(4) An ultra-thin layer of NID AlAs with thickness of approximately 28nm
(5) A spacer layer of NID GaAs with thickness of approximately 200nm
(6) An intermediate layer of lightly doped n+ ~1e+17
GaAs with thickness of
approximately 40nm
(7) A thick layer of heavily doped n+ about 4e+18 of GaAs with a thickness of
approximately 750nm
Each layer has its own role For instance layer (1) and (7) are used as ohmic
contacts via connection to a AuGeNiAu metal stack This explains why they are
purposely heavily doped (gt 1018
cm-3
) for better low resistance ohmic contacts Two
intermediate layers (layers 2 and 6) are used to prevent the carrier in the contact layers
from diffusing into the undoped layers The two unequal length spacer layers with ratio
58
1198971 1198972 of about 401 are used as voltage arms to yield an asymmetric current-voltage
characteristic The asymmetry means that after a positive bias is applied from the long
spacer region an accumulation layer is formed and it is deeper than that formed by the
negative bias The thin layer positioned in the middle (Layer 4) is the tunneling barrier
The performance of a single barrier ASPAT diode can be optimised depending on
the applications by appropriate selection of the material system so that the band gap and
barrier height of such material can be modified Furthermore the mobility of electron
and doping concentration of the contacts region can be tuned The parameters to tune
during the growth for instant growth interrupt time and growth temperature will also
affect the performance of this diode The key layers that will affect the performance are
the barrier thickness and the two spacer layers enclosing it The study has shown that a
one monolayer change in thickness results in 300 change in in tunneling current for a
fixed voltage point[65]
The following discussions account for the effect of the main structure of the ASPAT
which is related to their performance
2621 Barrier Thickness and height
The probability of an electron tunnelling through a barrier depends exponentially on
the width and height of the barrier as well as the energy that is incident on the barrier[72
73] All these will affect the I-V characteristic of the ASPAT diode The tunnel current is
obtained by summing over all incidents electrons energies with tunnelling probabilities
through the barrier The tunnelling varies approximately as[74]
119879 prop 119890minus120581119889 (226)
Where d is the barrier thickness and κ is defined by the expression below
120581 =
radic2119898lowast(1198810 minus 119864)2
ℏfrasl
(227)
From textbook the tunnelling probability is given by
119879(119864) = 412058121198702
[(1205812 + 1198702)2119904119894119899ℎ2119870119897 + 412058121198702]frasl (228)
Where K is expressed as
59
119870 = radic2119898lowast119864
ℏfrasl (229)
Where ℏ represents the reduced Planckrsquos constant (h2π) E and m are the electron
energy and effective mass respectively Thus by inputting appropriate value into these
equations one finds that reducing the barrier thickness by one monolayer increases the
tunnelling probability by a factor of nearly three for every electron that tunnels through
the barrier As a result the current will also increase Further it indicates that the
tunnelling strongly depends upon barrier thickness and height By contrast the current
does not strongly depend on temperature
2622 Spacer Thickness
The reason for having two dissimilar undoped spacer lengths is mainly to avoid
diffusion of dopant to the barrier and subsequent layers during growth but in the case of
the ASPAT diode the spacer can also act as a voltage arm Varying the thick spacer
layer (1198971) results in the reverse current decreasing as the layer thickness increases and
varying the thin spacer layer (1198972) will affect the forward current which increases as the
thickness reduces To obtain appropriate asymmetrical I-V characteristics one needs to
maintain an adequate ratio between these two spacer thicknesses While a too thin
1198971 results in high leakage current at reverse bias a too thick 1198972 results in low forward
current One also needs to keep it thick enough to prevent carrier diffusion
These two spacers must be kept undoped or very low doped to allow the electron
moving in the electron mean free path region as it is clear from ionised donors Under
large forward bias an accumulation layer is formed between the spacer and barrier
segment and it is more noticeable compared to the accumulation layer that is formed if a
negative bias is applied
60
Figure 216 Conduction band diagram showing band bending and 2DEG formation at the L1
spacer
Consequently a triangular well is formed which creates an emitter 2D electron gas
(2DEG) population The electrons in this 2DEG occupy the quasi-bound states which
mean high excitation energy thus allowing the electron to tunnel through the barrier as
depicted in Figure 216
In term of RF performance it is important to highlight that a thicker spacer layer
will affect the depletion region which gets wider and thus will reduce the junction
capacitance of the device as per the following expression
119862 = 휀0휀119903
119860
119889
(230)
Where A is the area of the device d is the thickness of the main device structure which
consists of spacers barrier and well layers 휀0 is the permittivity of free space and the
relative permittivity of the spacer material is denoted by εr However the intrinsic delay
time will also increase and hence degrade the device high frequency performance
Therefore optimisation through spacer thickness requires trade-off between reducing
leakage current at reverse bias and degrading device junction capacitance
GaAs
GaAs
AlAs
2DEG
Γ
X
61
263 ASPAT Electrical Parameters
The classical approach in determining the current flow through an ASPAT diode is
by solving the Schrodinger and Poison equations Prior work had been done by Syme et
al in 1991 Due to the fact that AlAs barrier is very thin tunnelling is assumed to occur
at the Gamma valley ie AlAs bandgap= 283eV (rather than X valley)[18 75] and only
from accumulation layer (2DEG)[59] Here the DC characteristic of the ASPAT diode
can be calculated by solving Schroumldinger equation with the position vector represented
by z (in this case) Thus the equation is expressed as
minus
ћ2
2nabla
1
119898lowast(119911)nabla120569 + |119890|120593(119911)120569 = 119864120569(119911)
(231)
Supposing the current is uniform across x and y planes then this can be simplified to one
dimension Therefore the 1 D Schroumldinger equations becomes
minusћ2
2119898lowast
1198892
1198891199112120595 + |119890|(120595 minus ∆120595) = 119864119911120595
(232)
Where
120595 =
120569
exp (119894119896119911119911)
(233)
where ∆120595 is the correction term which reduces the effective barrier height The
Schroumldinger equation is solved using different values for Ez thus the quantum
mechanical current density in the z-direction is now expressed as[15]
119895119911 =
minus|119890|ћ
2119898lowast(120595lowast
119889120595
119889119911minus 120595
119889120595lowast
119889119911 )
(234)
It is different for a heavily doped contact which can describe as below the envelope
functions in the left and right contacts respectively can be described by plane wave
120595119897 = exp(119894119896119897119911) + 119877 exp(minus119894119896119897119911) (235)
120595119903 = 119879119890119909119901[119894119896119903(119911 minus 120580119873)] (236)
62
In this case the left contact covers the region zlt0 while the right contact covers the
regions zgt 120580119873 Equations (35 and 36) are then inserted into Eq (34) to form the
following expression
119895119911 =
|119890|ћ1198961
119898lowast(1 minus |119877|2) =
|119890|ћ1198961
119898lowast|119879|2
(237)
Where R (Ez) and T (Ez) are the complex reflection and transmission coefficients
respectively and they are solved by using the transfer matrix method This method has
been described in reference [56] The next step is to integrate the current in the z-
direction 119895119911 for all possible Ez values Thus the expression for the current density
becomes
119895119911 =|119890|119898lowast119896119861119879
2120587ћ2int(1 minus |119877|2)
infin
0
119897119899 |1 + exp (
119864119891 minus 119864119911
119896119861119879)
1 + exp (119864119891 minus 119881|119890| minus 119864119911
119896119861119879
|
(238)
The equations above are used to calculate the current density approximation from
the ASPAT main structure (two spacer layers and one barrier) only and based on
intraband tunnelling from the conduction band profile For real fabricated structure the
calculation must take into account both intrinsic and extrinsic elements of the diode
While the latter is mostly related to the pad and probe that is used to extract the I-V
characteristic the first element mostly comes from the epitaxial layer of the ASPAT
diode itself The ASPAT I-V characteristic is shown in Figure 217 which clearly
indicates nonlinear characteristics and thus can be used for detection applications
63
Figure 217 I-V characteristics of a fabricated ASPAT diode
2631 Intrinsic Elements of the ASPAT diode
In order to extract the intrinsic electrical characteristic of the ASPAT diode a
generic structure as shown in Figure 218 is essential Two main sources of contribution
to the electrical characteristics are the interfaces of each layer and properties of the
materials themselves
Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
64
The electrical current flowing from the top contact to the bottom contact will go
through each epitaxial layer producing a close loop Each junction interface limits the
current flow and sum up the total resistance resulting in what is known as the diode
series resistance (Rs) In the ASPAT main structure there is a junction capacitance (Cj)
due to the undoped regions surrounded by heavily doped contacts thus acting as a
parallel plate capacitor The fully depleted capacitance (Cj) of the diode can be
expressed as in Eq (230)
2632 Series resistance of the ASPAT diode
The total series resistance (Rs) of an ASPAT diode can be calculated based on the
finished fabricated diode structure In general Rs depends on three contributors namely
the non-uniformities in the contact metallization the un-depleted epitaxial layer (total
thickness) on both side of the heterostructures and the resistance caused by the
spreading current from the Mesa into the much wider second contact layer ie doped
substrate or 2nd
ohmic layer[76] In fact the contribution toward building up the total Rs
solely depends on how the structure is designed In this work two types of structures
were deployed namely lateral structures and vertical structures These will be described
in the next subsection
For both types of structures the series resistance (Rs) of the ASPAT diode consists
of aspecific Ohmic contact resistance (ρcA) contact epitaxial layer resistance (Repi-
Layers) and spreading resistance (Rspr)[33 77] where Rspr is influenced by the type of
structure The specific contact resistance is obtained from Transmission Line
Measurements (TLM) of the sample The theory of the TLM will be discussed in detail
in the next section The expression for the specific contact resistance is
120588119888 = 119877119888119871119879119908sinh119889
119871119879frasl
cosh 119889119871119879
frasl
(239)
Here Rc is the contact resistance LT is the transfer length (effective length) w is the
contact pad width and d is the length of the contact pad
65
Repi-Layer is the sum of all doped layers that sandwich the main ASPAT device For
each doped layer the resistance is given by
119877119890119901119894minus119897119886119910119890119903 = 120588
119871
119860
(240)
Where ρ is the resistivity which is given by 120588 = 1
120583119899119902119873119863 L is the epitaxial layer thickness
in cm A is the device area (emitter size) micron denotes the mobility of the electron q is the
electron charge and ND is the donor concentration The spreading resistance depends on
the structure design of the device This will be elaborated in detail in the following
section
26321 Vertical structure (doped Substrate)
The XMBE307 structures were grown on n+ GaAs substrate to provide the
simplest fabrication process The cross section of the finished single diode can be seen in
Figure 219 below
Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b and h are not
drawn to scale
66
At low frequency and in a mesa that is etched into a doped substrate material the
spreading resistance can be approximated by[76]
119877119904119901119903 =120588119904
2119889
(241)
Where ρs is the substrate resistivity and d is the ASPAT diode mesa length
However the spreading resistance is increased at high enough frequencies as the skin
depth (δ) in the substrate is much lower than the effective mesa length (d) of the diode
A new spreading resistance is then calculated also based on the assumption that the skin
depth is much lower than the chip thickness (h) but much larger than the mesa length
Thus the spreading resistance at high frequency is given by
119877119904119901119903(119891) =
120588119904
120587120575[05 ln (
119887
119889) +
ℎ
119887]
(242)
Where the skin depth (δ) is taken from standard planar formula and can be expressed as
120575 = [
2120588
(120583120596)]
12frasl
(243)
Where micro is the permeability and ω is the angular frequency During DC measurement
this type of structure requires having good suction on the stage for a good contact
However for small die (15mm times15mm) the suction sometimes is not strong enough to
provide a very good adhesion to the sample Therefore another type of ASPAT diode is
deployed which is based on the lateral structure by utilising semi-insulating substrate
and both contacts are connected to probes
67
26322 Lateral structure (Semi-insulating Substrate)
Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304) The dimensions
are not drawn to scale
In order to obtain accurate measurement results so as to avoid contact errors to the
substrate between stage and Device Under Test (DUT) a lateral structure as shown in
Figure 220 above is deployed This type of design offers many advantages ie it
provides a path for on-wafer RF measurement However the proper design has to take
into account the increase in RS due to improper attention to the spreading resistance
This spreading resistance is different from the vertical structure that was discussed
above In this case it is mainly caused by a gap at the bottom contact The gap in the
horizontal direction between epitaxial layer and metal at bottom contact is denoted as D
gap in in Figure 220 Therefore Rspr for the lateral design can be expressed as [77]
119877119904119901119903 =
1
120587120590119889119866119886119860119904ln (
119886
119886119898119890119904119886)
(244)
Where σ is the conductivity between two coaxial half-cylindrical electrodes with inner
(amesa) and outer (a) rectangular length or bottom ohmic layer which is given by (σ =1
ρ) a d and amesa are the length and thickness indicated in Figure 220 above Noticeably
68
the D gap will have direct effect on the outer length (a) of the device which is also
proportional to Rspr For high-frequency operation where the skin depth is less than
d(GaAs) σ becomes
120590(120596) =
120590(0)
[1 + (120596120591119903119890119897)2]
(245)
Where τrel =microme and micro m as well as e are the mobility effective mass and electron
charge respectively It is recommended that for high-frequency applications the device
series resistance must be as low as possible
Hence for both type of structure the ASPAT series resistance is calculated based on
all the above-stated resistances and these are set by
119877119904 =120588119862
119860+ 119877119890119901119894minus119897119886119910119890119903119904 + 119877119904119901119903
(246)
The total RS can be decreased by increasing the emitter area of the diode However a
large device will not able to reach millimetre and submillimeter wave region (THz) as
the capacitance will also increase (Eq 230) Therefore both parameters will have a
trade-off between them to be able to work at ultra-high frequencies
27 Characterization of Ohmic Contacts
The semiconductor Ohmic contact can be characterised using techniques that will
be described in the following section First is the Cox-Strack technique which is
specially designed to characterise bulk type semiconductor (thick) contact resistance on
two opposite sides The detailed description of this technique can be found in [78]
Second is a technique called Four Point Probe This technique was developed in 1954 by
Valdes etel [79] to characterise semiconductor resistivity It can also be used to
characterise the contact resistance for planar type devices As this research does not
cover this method the details of the measurement can be referred to [80] Finally the
most common method which is also extensively used in this research is the standard
Transmission Line Measurement (TLM) The details of this method will be explained in
the next section There are simplified versions of the TLM method which require just
one lithography step but are nevertheless very powerful in characterising and optimising
the contact resistance known as Circular Transmission Line Measurement (CTLM)[81
69
82] However in this research this is not to be covered as the standard TLM is already
adequate for planar type devices
271 Transmission Line Measurement (TLM)
The formation of metal and semiconductor interfaces will create a contact that
becomes very important for the characterisations of any fabricated device Additionally
it enables the quality of certain process flow to be determined This interface must be
evaluated by a technique known as the Transmission Line Measurement (TLM) TLM
which was first introduced by Murrmann and Widmand [83] in 1969 underwent some
refinements by Berger [84] in 1971 The theory of the TLM can be described by
constructing a TLM structure which comprises a set of metals contact pads placed in
series on a highly doped semiconductor layer as depicted in Figure 221 The structure is
designed like a series of the islands to permit current flow in parallel to the contact pads
[80] which is a direction defined by etched patterns Each contact metal pad behaves
like a MESA which has a thickness (t) and width (W) The distance between each metal
contact pads is defined by d1 the gap between two neighbouring contact pads which are
beneath each contact pad is defined as effective length LT This will allow current flow
in and out of the subsequent neighbouring metal pad The resistance elements that will
be extracted are RA and RB which sit under the contact and in between two metal pads
These two elements represent the sheet resistance under the metal contact pad area and a
sheet resistance of the material between two metal pads
Figure 221 A simple TLM structure with effective length and sheet resistance underneath
t L
T
LT
RA R
A R
B
dn
Probe Probe
Metal Pad
GaAs
MESA
70
The basic relationship of resistance R with respect to the size of the metal contact
or in the standard transmission line can be expressed as [44]
119877 = 120588
119871
119860= 120588
119871
119905 times 119882=
120588
119905times
119871
119882= 119877119904ℎ
119871
119882
(247)
Where ρ is the materialrsquos resistivity L is the length t is the thickness W is the width
Rsh is the sheet resistance and A is the cross-sectional area of the transmission line The
unit for ρ and Rsh are Ωm and Ωm2 respectively
The total resistance RT of this structure can be taken from the sum of the two
neighbouring padrsquos resistance RA and RB In order to relate with Eq (247) above this
RT will be substituted into Eq(247) to become
119877119879 = 2119877119860 + 119877119861 = 2119877119904ℎ119860
119871119879
119882+ 119877119904ℎ119861
119889119899
119882
(248)
As suggested in [85] RshA and RshB are assumed to be identical Therefore Eq(248)
can be reorganised into specific contact resistance RC and semiconductor sheet
resistance Rsh above as 119877119862 = 119877119904ℎ119860119871119879
119882 the new equation is then
119877119879 = 2119877119862 + 119877119904ℎ119861
119889119899
119882
(249)
The common practice throughout this research is to design a TLM structure that
has a ladder structure consisting of 10 metal pads with each one measuring to a size of
100microm width and 50microm length and the space between the first and second metal pad
5microm The gap is increased after the second metal pad by a further 5microm until ten metal
pads are completed produce a separation between the ninth and tenth pad of 45microm The
TLM ladder structure as depicted in Figure 222 is supplied by a constant current of
1mA at the very left and right metal contacts by two probes This allows the extraction
of RC (Ωmm) and Rsh (Ω) instantly from such structure The potential difference
between the two adjacent metal pads is measured by another two probes and the reading
of a voltmeter is recorded The total resistance is obtained by using Ohm law where
voltage is divided by current (VI) Another voltage reading is taken for the next two
neighbouring metal pads until the largest gap is reached The readings of (conversion
71
VI) which result in the corresponding resistance RT are then plotted against spacing and
the result can be seen in the graph in Figure 223
Figure 222 Top view of TLM ladder structure use in this work
Additionally in the measurement the voltmeter used in work has a very high resistance
Otherwise there will be leakage of current occurring through the probes and cables
Therefore the parasitic resistance of the cable or connector and the probe contact can be
ignored The key parameters that can be extracted from the graph will be discussed in
the next paragraph
Figure 223 Typical plot of resistance versus TLM spacing
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50Res
ista
nce
Rn (
Oh
ms)
TLM Spacing dn (um)
LT
d1 d
2 d
3 d
n
I (1mA)
V
V
LT
ME
SA
Su
bst
rate
72
The straight-line graph plotted in Figure 223 can be referred to Eq (249) and
this must be done by assuming the sheet resistance Rsh of the material is constant If the
straight line of the graph is extended up to initial gap (d=0) the intercept on the y-axis
provides the 2RC value To extract the 2LT further extrapolation is made until the
interception at RT = 0 is reached Therefore an important parameter which is the specific
contact resistance ρC can be found from this expression[85 86]
120588119888 = 119877119862119871119879119882sinh
119897119871119879
cosh119897
119871119879
(250)
Where l represents the total conductive semiconductor thickness The final part that can
be extracted from the graph is the slope of the line This is obtained by dividing the sheet
resistance with the width of the metal pad ie represented by expression (119877119904ℎ
119882frasl )
28 Basic Characterization Techniques and procedures
281 Measuring tools and apparatuses
The success of every experiment is determined by the backend results that are
obtained from the measurements It is important to choose an appropriate instrument
which will provide the required data for a valid and detail analysis Thus this section
will give a brief explanation of the measuring instruments and methods that were
exploited in this research The measurement apparatus systems that are available and
have been utilised in completing this thesis are ldquoset of DCrdquo and ldquoSet of RFrdquo
measurements The DC set measurement consists of room temperature and variable
temperature system This system is built to perform process monitoring during device
fabrication and it comprises of five main components
The fundamental component in the ldquoDCrsquos set toolrdquo is the Agilent B1500A
Parameter Analyser [87] used to provide fixed currentbias during testing The other
component is a Karl Suss PM5 Cascade Prober [88] which is used to receive fixed
currentvoltage and to supply its to the semiconductor contact via probe tip The PM5
Prober has at least four probe arms and each of them is fitted with ldquoneedlerdquo called probe
73
tip The size of the tip that is normally used here is 2microm and in some cases the tip size
of 1microm is also utilised The currentbias supplied to the sample must go through the two
of Source Measurement Units (SMU) namely SMU1 and SMU2 to ensure no mismatch
occurs between parameter analyser and diode All the testing are controlled using a
software called Integrated Circuit Characterization and Analysis Program (IC-CAP
2009) brought from Keysight Technologies[89] The software is installed on a standard
Personal Computer (PC) and the PC is connected to a General Purpose Bus Interface
(GPIB) to link with the B1500A Parameter Analyser This system can be organised
based on the purpose of measurements ie IV characteristics TLM Schottky Diode
and transistor as it is very flexible to change the configuration For examples
Transmission Line Measurement (TLM) configuration requires the addition of a digital
multi-meter and four-point probe tip while diode measurement just needs two point
probe tip without a digital multi-meter Figure 224 illustrates the measurement system
for a set of DC to test the TLM structure
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM
On the other hand the set of RF measurement consists of five block elements
configuration in the system namely the Vector Network Analyser (VNA) DC
sourcemonitor Cascade Microtech Prober SMU and Control PC via GPIB The RF set
Agilent B1500A
Parameter analyser
DUT
(TLM Diode
Capacitance)
Karl Suss
PM5 Cascade
Prober
PC
(MS windows 2000)
Digital Multi-meter
ICCAP 2014 Provide current
source
Measure and read the
voltage Stage and Probe
Signal
Current Source
SMU1 SMU2
General purpose bus interface
74
performs RF characterisation after the device fabrication is completed This system can
also perform DC characterisation as its basic instrument has this function too The VNA
machine used in this research is the Anritsu 37369A [90] which can perform the
Scattering Parameter (S-Parameter) measurement with a frequency range of 40MHz to
40GHz The DC sourceMonitor utilised in this experiment is the HP 4142B Modular
DC SourceMonitor [91] Both of these sub-systems are controlled by a standard PC
which exploits GPIB port to link them During operation the HP 4142B is connected to
the VNA by an internal bridge network and two SMUs to the Cascade Microtech Prober
which is then connected to the bond pads of the device It is identical to the set of DC
measurement where the SMU setting and data assembly are accomplished by IC-CAP
software package therefore the data that was obtained before and after completing the
fabrication can be compared This will enhance the validation of the data
However the stage and probes in both sets of measurement are different The
Cascade Microtech Prober has only two probe arms with each arm fitted with a 3-
fingers probe tip in the arrangement of Ground-Signal-Ground (GSG) as shown in
Figure 225 Each finger (pitch) is separated by 100microm thus to fit in with the pitch and
to reduce the mismatch in resistance the bond pad design must follow this separation
between each contact The GSG is configured by connecting the outer pads (Collector)
to the Ground probe tip while the inner pads (Emitter) are attached to the Signal probe
tip where the RF signal is sent and received through it Figure 226 shows the actual set-
up for RF measurement used in this research
75
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
Figure 226 Actual VNA system that was used for RF characterization
282 Measurement steps using a VNA
The RF measurement steps can be summarised in the following
- Step 1 Select or find the suitable VNA depending on applications
PC
(MS windows 2000)
ICCAP 2014
VNA
Anristru 32379A
40MHz to
40GHz
HP4142B
Modular DC
source
DC Bias Source
Cascade
Microtech
Probe Station
One 50microm pitch G-
S-G probe tips
Ground
SMU1
Cathode
Gen
eral
purp
ose
bus
inte
rfac
e
Lo
w P
ow
er H
igh P
ow
er
Cathode
Anode
SMU2
Ground
Ground
Signal
76
There are few factors that need to be well-thought-out before starting to use a VNA
especially for S-parameter measurements The factors are the availability of the VNA in
term of operational frequency and measurement port types air-filled metallic waveguide
or on-wafer Not all VNA can have an operational frequency for banded measurement
ie W-band Ku-band etc All these may require external signal sources to extend the
operational frequency
- Step 2 Properly setting up the VNA
The VNA can be set up depending on its application and the goal of measurement for an
instant number of point requires a desired frequency span IF bandwidth and the supplied
power level This very important to ensure the desired measurements are correct and
appropriate
- Step 3 Appropriate calibration system
In order to have a valid calibration appropriate calibration method has to be chosen
depending on the applications This will determine the accuracy and standards of
calibration As for on-wafer calibrations the de-embedding is normally used while for
the off-wafer the SOLR technique is more suitable to employ
- Step 4 Validation or verification of the calibration results
It is vital to validate the calibration results to ensure that the system has been properly
calibrated
- Step 5 Proper measurement
Proper alignment positioning and touching from probes tip to DUT is necessary to
guarantee a good repeatability and reproducibility of measurement results Normally
when positioning the probe an alignment marker is used as an aid By doing this similar
travel distance for the probes can be achieved The measuring plane will also be equally
well-defined
283 Measurement Practice and Flowchart
Essentially the device characterisation is performed in two stages ie during
fabrication as a process monitoring and after completion for data collection and
analysis Figure 227 shows the block diagram of a flow chart for testing a 15mm times
15mm wafer processing performance In the wafer processing after reaching the top and
77
bottom contactrsquos step the sample can be examined by measuring the TLM structure
according to the TLM procedure The measurement is conducted by exploiting a set of
DC measurement apparatus as mentioned above analogous to the TLM ladder structure
on the wafer surface Based on the TLM results the presence of any process issue during
the fabrication can be identified by examining the parameter such as contact resistance
and sheet resistance Thus a decision can be made either to proceed or to terminate the
fabrication should any issue is found early on As a result no materials will be wasted
further When a dielectric layer is involved Capacitance Dielectric measurement can be
tested This practise can be used to obtain the quality of the dielectric layer To connect
between a diode effective area and probe a bridge is requires It can be attached to the
diode emitter (to determine the diode size) to a bond pad for probe tip to touch This
bridge can either be left hanging in air or sticking to the isolated dielectric layer For the
GaAsAlAs material system the latter technique is preferable since it avoids issues with
the air-bridge which will be discussed in detail in Chapter 3 The opening area (via) for
metal connection can be checked by measuring the resistance on a special design pad
after a plasma dry etching step
Figure 227 Block diagram of the ASPAT measurement step
The next stage of characterising the device is the on-wafer diode measurement
which takes place after completion of all processing (including bond padsco-planar
pads) The work is carried out using the above set for RF measurement and employed
Ohmic Contact
Opening Via
TLM
Qualified
Device
Bad device
Dielectric
capacitance
Bonding pad DC and RF
Good
Good Good
Fail
Fail
Fail
78
purposely to access the DC and RF performance of each diode where the current-voltage
(I-V) characteristic and S-Parameter results are obtained In fact DC measurements are
first performed using a set of DC measurement and a rough IV characteristic can be
obtained to ensure the diode is working properly Usually the yield of any fabricated
device on 15mm times 15mm wafer in this research is between 70 to 90 In this research
the outcomes that will be discussed in the subsequent chapters are in term of the average
of measured values Thus it is very important to have a meaningful data to compare with
physical modelling and simulation in the future The diode IV characteristics are studied
by applying different DC bias at the emitter to collector terminals to extract its keys
parameters ie turn on voltage (supposedly zero bias) non-linear characteristic Rj RS
Cj etc
The device that has been measured by DC and having produced a valid result
will be marked for the next investigation ie the S-Parameter measurement This
measurement is executed using a similar system but with different probe types The
three fingers probe type is used and the device frequency response is measured via the
one-port network from the VNA The important parameters extracted from this
measurement are usually S11 (depending on how many ports are measured) Although
working devices are selected to measure accordingly there is a need to ensure the VNA
RF cable and probe tips are calibrated so that only valid data without errors will be
obtained A calibration technique called SHORT-OPEN-LOAD (SOL) is performed
prior to each daily measurement by exploiting a calibration sample with WinCal
software (Cascade Microtech)[92]
To avoid confusion it is worth mentioning that this technique used to calibrate
the device structure is different from what is used in SOL calibration to the equipment
Furthermore the de-embedding calibration is made on-wafer with the same substrate of
the actual device whereas the SOL is performed on a special calibration substrate
Normally the de-embedding results are not constantly automated with the VNA
equipment However the measurement is done separately starting with the special DUT
substrate then followed by the OPEN and SHORT de-embedding structures
79
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES
31 Introduction
This chapter presents in detail the general fabrication techniques for a generic and
development work of micron scale ASPAT diodes The discussions will focus on the
semiconductor growth technique used in this work ie MBE and the fabrication process
steps which include sample cleaning photolithography etching and contact
metallization These techniques are ample to build and deliver commercially marketable
fabricated structure Hence all photolithography techniques used to complete this
project are based on conventional i-line optical lithography which is adaptable to
industry and commercial purposes
The fabrication process in this work can be fragmented into two major works
firstly the fabrication towards reproducibility repeatability and manufacturability in
term of device structure process flow and DC amp RF characteristics This work will
involve relatively larger emitter area which varies from 15times15microm2 to 100times100microm
2 The
larger area provides for ease and fast fabrication as well as DCamp RF measurements
Once repeatability and reproducibility of the process flow and performance is confirmed
the second part of this work which is concerned with applications in millimetre and sub-
millimetre-wave then took place In this work small emitter designs varying from
2times2microm2 up to 10times10microm
2 were considered with appropriate measurement pads The
successful fabrication of smaller diode geometries in the second part of the programme
naturally leads to a further investigations to understand its epitaxial layer structure and
extracting intrinsic components ie junction resistance junction capacitance and series
resistance which will determine the device performance in high-frequency applications
The I-V characteristic is obtained from DC measurement which is usually performed at
room temperature Its results are then compiled and compared with advanced simulation
It is worth mentioning that all samples that are investigated in this project are grown by
means of MBE and the activities related to the epitaxial layer growth using MBE in the
University of Manchester were done by the Materials Growth Team (Prof Missous) and
the authors has no responsibility for this particular task
80
32 Epitaxial Layer Growth Techniques
Before discussing the principle of the common lithography technique it is
important to discuss the wafer growth technique as it comes first before the fabrication
The growth technique that is extensively used in this study as well contributing a lot in
the electronic semiconductor industry is Molecular Beam Epitaxy (MBE) The following
section will discuss the basic operating principle of solid source MBE
321 Molecular Beam Epitaxy (MBE)
The MBE technique was developed in the early 1970s [27] and is purposely used for
growing high purity epitaxial layers of compound semiconductors Such sophisticated
growth technique provides significant functionality ie precise control of the thickness
(to one atomic layer) and contributes to the growth of various types of complex
semiconductor multilayers high quality and advanced materials This level of control is
vital for an assortment of heterostructures devices that are being utilized as part of the
development of the advanced electronics devices especially for the ASPAT diode which
require 01ML control over the AlAs barrier to attain acceptable variability in device
characteristics Additionally the accurate doping profile and excellent junction
abruptness also can be achieved by using this technique
Practically the MBE system used in this work is a solid source MBE which
utilises beams produced by heating up various sources The sources can be Si Al Ga
As and other group III-V compound semiconductors When the crucibles which contain
the sources are heated atoms or molecules of the various elements are evaporated and
travel in straight lines paths like beams directed toward a target (heated and rotating
substrate surface) The condition of the vacuum during evaporation is ultra-high vacuum
(UHV) ~10-11
torr in order to have high quality crystals The substrate is heated and
rotated to provide good growth uniformity over large areas ( up to 4times4rdquo wafers) [93]
The growth rate in typical MBE growth is ~1ML second and can be controlled
by the source temperature in the crucible The abruptness at the heterojunctions interface
and switching of the growth compositions can be obtained by precise control of shutters
that are placed in front of the crucibles Therefore an abrupt junction at GaAs and AlAs
81
interface can be formed to realize the barrier in the ASPAT diode In order to monitor
the quality of the growing crystal and measure the layer by layer growth mode
Reflection High Energy Electron diffraction (RHEED) technique is utilised This
technique works based on the diffraction of electrons from the crystal surface [93]
Additionally given that the ASPAT current density is very sensitive to the barrier
thickness a study has been made using different growth techniques namely MBE and
Metal-Organic Chemical Vapour Deposition (MOCVD)[59] From this investigation it
was concluded that the percentage local variability of current density produced by MBE
grown diodes is better than those grown by MOCVD Thus in this study to get benefit
from its performance all wafers are MBE grown
33 Basic Principles of Common Fabrication techniques
This section covers the generic fabrication process which underpins
reproducibility repeatability and process optimisations for high-frequency applications
331 Sample cleaning
Essentially semiconductor processing requires a ldquoclean environmentrdquo to produce
devices The clean environment is classified according to how many ldquounwantedrdquo
particles are present in a cubic meter There are four categories of clean room available
in the industry Class 10 Class 100 Class 1000 and Class 10000 [94]
The fabrication of all ASPAT diodes in this project was performed in a clean
room environment of Class 1000 equipped with laminar air flow and filter system to
give Class 100 or better during processing Although the sample was processed in a
highly controlled particle environment there is still a high chance for a sample to get
contaminated when handled by a human Besides this the source of particle which
contributes to the contamination can be from the apparatuses and processing equipment
used in the laboratory themselves Thus the process of cleaning the sample wafer
surface before the start of each step is vital
Generally in a clean room the standard solutions that are used to clean a sample are
N-Methyl Pyrrolidone (NMP) Acetone Propan-3-ol (Iso-Propane-ol) (IPA) and
82
deionized (DI) water The sample which is cut up into 15times15mm2 size tiles is cleaned
based on the following procedures
1 Hot NMP- The sample is dipped into the solution at 80˚C for 10 minutes This
solution acts as an organic type of nature pollutants removal
2 DI water- acts as NMP remover The sample is then washed by flowing DI water
throughout the samplersquos surface
3 Acetone- to ensure any remaining NMP is completely removed from the sample
The sample is dipped into Acetone for 5 minutes in a low power ultrasonic bath
at ambient temperature
4 IPA- is used to remove the Acetone from the samplersquos surface The sample is
then dipped into the IPA for 5 minutes in a low power ultrasonic bath at room
temperature The use of low power for the ultrasonic bath is to avoid the sample
cracking or breaking
5 Once done the sample is then blow-dried using nitrogen (N2) gun to remove any
moisture coming from the IPA Fortunately it is easy to remove the IPA
completely from the sample surface given its higher rate of evaporation
Once all these steps are accomplished a visual inspection using a high magnification
optical microscope is conducted to ensure the sample surface is clean The cleanliness of
the sample is determined by the (lack) of particles or other spots (liquid mark) that can
sometime be observed during the inspection Obviously the lower the number is the
better the sample is as it is impossible to totally remove dirt especially marks
Sometimes it is hard to remove the particles in one go There is always a need to repeat
each cleaning step for a few times However this will not affect the sample in term of
electrical performance as the cleaning solutions used are non-destructive
332 Photolithography
Lithography or sometimes called pattern transfer is the most important step in
realizing microelectronic devices The designed geometry and dimensions on a quartz
glass plate called a ldquophoto-maskrdquo must be done prior to the fabrication process While
the photo mask can be designed by using various software tools in this work the design
83
is done via the Advance Design System (ADS) by Keysight The details of the design
which includes three different mask designs will be covered in Section 34 The mask
consists of the desired patterns (master) that can be printed onto solid materialrsquos surface
by means of an electrochemically sensitive polymer (photoresist) using
photolithography In fact this type of optical lithography technique can be performed
with and without a mask due to its simplicity It is also easy and cheaper compared to
other techniques such as x-ray lithography or Electron-beam lithography (EBL)
Although the latter is expensive it is still worth to have since it provides a higher
resolution which is preferable when developing sub-micrometre technology
processing[95] The special feature about EBL is that it does not need a mask to pattern
samples but can be produced by the movement of an electron beam point source and
hence writing the patterns directly on the surface
The ultra-violet (UV) based light sources are more popular among researchers
and development workers because they are cheaper and have modest resolution Usually
photolithography operates at wavelengths (λ) from 193 nm to 436nm The source that
provides the UV light is a Mercury (Hg) arc lamp which uses narrowband filters to select
single emission lines First is the i-line at λ= 365nm then the h-line which is of lower
resolution and has λ of 405nm and thirdly the g-line with a λ= 436nm[96] The
conventional optical lithography used in this research uses the ldquoi-linerdquo at a wavelength of
365nm For shorter wavelengths than these excimer laser or krypton fluoride laser with
a λ= 248nm and argon-Fluoride with a λ = 193nm are also used in the industry The
higher power levels enable higher productivity (throughput) while narrower spectral
widths reduce chromatic aberration provide better resolution and larger depth-of-focus
In this research all the fabrication process are done by utilizing a conventional optical
lithography (i-line) using a Karl Suss MA4 mask aligner Before starting any UV
exposure it is important to check the UV light intensity as it will affect the resolution
and thus desired device dimensions Therefore every corner that is exposed to the UV
light is calibrated to be at 09mWatt power exposure
The complete set of photolithography components consists of photoresist
(photosensitive polymer) photo-mask (chromium) which is used to block the UV to
form a pattern mask-aligner and developer (chemical solutions) Standard fabrication
84
process usually practiced at the University of Manchester starts with sample cleaning as
mentioned earlier Then the sample needs to go through heat treatment to remove all the
moisture with a temperature set to be 150˚C and bake for 5-10 minutes After having
cooled down the samplersquos surface is coated with a thin layer of photoresist via a
technique called spin-coating using a Laurell CZ-650 series spinner The spinning speed
is set depending on the type of resist ie 3000rpm for negative photoresist and 5000rpm
for positive photoresist The rotating speed of the spinner does not have much effect on
the coated photoresist thickness but will have consequence on the uniformity distribution
over the sample surface The coated thickness photoresist however depends on the
concentration of the specific photoresist Once spin-coated is done another short heat
treatment (1 minute) is required to ensure the resist is hard enough to contact a
photomask and to remove any excess solvent The temperature is set on the hot plate to
about 115˚C and 110˚C for positive and negative photoresists respectively
The important segments contained in the photoresist are a polymer (base resin)
a sensitizer and a casting solvent [97] The polymer will react by changing its structure
when exposed to the radiation While sensitizers will govern the reaction of the
photochemical in the polymeric phase the casting solvent will permit the spin-coated
application on the wafer surface The photoresist consists of positive and negative
photoresist both of which were used in this research Their basic difference is with
respect to the area that is exposed by UV light ie whether it will remain on the
semiconductor surface or will be removed In the case of a positive resist the exposed
area will be removed by the developer and the covered area will remain In other words
whatever is displayed on the photomask goes onto the sample surface On the other
hand for the negative photoresist the area that is covered from UV exposure will be
dissolved by the developer Figure 31 shows a 3D picture of both processes used in this
research
85
Figure 31 3D illustration of Optical lithography process used in this research
To obtain the desired pattern on the surface after UV exposure for a certain
duration the sample is required to go through a development procedure by using a
developer The developer is used to expel the dissolvable part of the photoresist after
being exposed to UV The usefulness of the developer depends on the photoresist ie
MF319 developer is specifically for positive photoresist while MIF326 is suitable for
negative photoresist Both types of developers will not harm the devices as they are a
kind of metal free ion solution Thus no free ion will change the characteristic of the
device The common practice in the clean room at the University of Manchester is to use
positive photoresist namely Shipley Microposit S1800 supplied by The Dow Chemical
and negative resist AZnLOF2020 (AZ2microm) which is supplied by MicroChem For the
S1800 series the thickness of the photoresist is determined by the last two digits ie
13microm thick for S1813 and 05microm thick for S1805 Both positive photoresists are used
Resist
GaAs
Dielectric
Photo Mask
Negative Resist Positive Resist
After Etching
86
mostly as protective area during wet chemical etching and as sacrificial dielectric layer if
higher temperature is applied ie 190˚C On the contrary AZ2microm which normally has a
thickness of 2microm is useful for patterning small dimension which leaves small gaparea
for the metallization process to fill It has good aspect ratio and useful in single layer lift-
off (post metallization process) In fact this type of resist can be thinned by diluting into
an Edge Bead Removal (EBR) solution and smaller device feature size can be obtained
The final dimension of certain devices (mesa size) is governed by the exposure
time the distance between photomask and samplersquos surface and the development time
The appropriate UV exposure time is required to avoid over-exposure which will cause
the spreading of light into the purportedly dark-field area[98] However the effect of the
exposure time differs between the photoresist types smaller opening area than the mask
pattern for negative resist and larger opening area for positive resist[45] The gap
between the photomask and wafer surface must be reduced as much as possible to avoid
the UV light going through the unwanted area To obtain a good gap value an applied
pressure from stage to the mask is required The normal pressure used in this research is
between 04 to 1 Pascal depending on the type of photoresist (negative and positive) as
well as its thickness Lastly the development time also influences the dimension of the
device Appropriate development time is required because ie over-development will
cause the polymerized photoresist to etch laterally resulting in bad patterned geometries
On the other hand under-development will cause non-uniformity in the surface after wet
chemical etching (positive resist) as well as causing lift-off problem (negative resist)
333 Etching Process
The etching process is a process of removing unwanted semiconductor layers to
define device geometry and isolate each individual device in one sample There are two
types of etching technique used in this research ie wet chemical etching and plasma
dry etching The wet chemical etching is based on Orthophosphoric(H3PO4) solution
which is a selective etchant to materials like GaAs InGaAs and AlAs The selective
etchant is referred to a solution that can etch away a specific semiconductor with a
specific etch rate The etch rate depends on the mixture ratio and concentration of the
solutions ie the higher the concentration the higher the etching rate In practice the
87
temperature humidity and epitaxial layer doping level also have an impact on the etch
rate Hence to minimize variation in the etch rate both temperature and humidity in the
clean room are constantly monitored and regulated Ambient temperature between 18degC
to 19degC is usually suitable while humidity is kept within 30 to 40 The advantage of
the wet chemical etching is that it is inexpensive controllable and with high throughput
highly selective and simple The mixture solution that is used in this work is
Orthophosphoric (H3PO4) Hydrogen Peroxide (H2O2) and Di-ionised water (H2O) with
ratios of 3150 3110 and 212 The ratio of 3150 provides an etch rate of about
600Aminute and is good to define the area and opening the under-cut in air bridges for
InGaAs samples[99] The 3110 ratio results with highly anisotropic shape but is easy to
control as the etch rate is about 1500Aminute for GaAs material system However the
212 etchant solution will provide extremely anisotropic etch rate of about
1000Asecond and is quite difficult to control For GaAsAlAs ASPAT diode it can still
be controlled since the thickness that needs to be removed is about 7000A (refer to
section 342 for details on the fabrication of ASPAT) Table 31 summarizes the etch
rate with different ratios and different selective materials Common to all the ratios
mentioned above are the isotropic side walls with lateral and vertical etch rate of 11
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and Ammonia on GaAs
and InGaAs materials
Material Etchant Ratio Etch Rate (Aringminute)
GaAs H3PO4H2O2H2O 3150 600
GaAs H3PO4H2O2H2O 3110 1500
GaAs H3PO4H2O2H2O 212 60000
GaAs NH4OHH2O2H2O 118 2000~3500
InGaAs H3PO4H2O2H2O 3150 850
The plasma dry etch is purposely run to obtain extremely high anisotropic etch
profile vertically and horizontally It can be done via mask with positive photoresist and
self-align mask which is metal contact as a mesa protector The precursors that are used
to etch away GaAs InGaAs and AlAs layer in this technique are Methane and
Hydrogen (CH4+H2) On the other hand Carbon Tetrafluoromethane (CF4) and H2 is
88
used in removing Si3N4 The etch rate is determined by how much power is applied to
the plasma to hit the sample surface the pressure inside the chamber and amount of the
precursor In this research plasma Technology is used for dry etching This machine
which is a conventional OXFORD INSTRUMENTS 1990 machine can produce an etch
rate on average of 100Aminute for an RF power of 100mWatt
334 Sputtering (dielectric deposition)
In this work a Kurt JLesker PVD 75 is used to deposit Si3N4 layer on the sample
surface The deposition rate depends on the RF power that is applied To avoid surface
damage on the sample surface a sacrificial layer formed by SiO is deposited using the
Bio-Rad Thermal evaporator before transferring to the PVD 75 to start deposition with a
low (75Watt) RF power Once the deposition time reaches 30 minutes the power is
increased up to 200Watt As a result good uniformity of the dielectric layer is obtained
335 Metallization Process Lift-off and Annealing
The metallization process is a process in which metal contacts on semiconductor
devices are created The purpose of this process is to make a proper interconnection
between the semiconductor devices to other parts of the circuit elements In other words
it is to connect the semiconductor device to the outside world This process will allow
the device to be examined electrically so that all electrical characteristics can be obtained
ie resistance I-V curve capacitance conductance etc The metal scheme used in this
process depends on the semiconductor material In the case of GaAsAlAs ASPAT
diode Gold-Germanium (AuGe) Nickel (Ni) and Gold (Au) are used However in the
case of InGaAsAlAs ASPAT diode the metal scheme used is Titanium (Ti) and Au
The technique used in this process is resistive thermal evaporation
The metallization process starts by cleaning all the metallic sources and boats
ie tungsten boat Au Ni and Ti metals by using Trichloroethylene Acetone and IPA
consecutively for 5 minutes each in a high power ultrasonic bath This step is very
important to reduce the risk of contamination during thermal evaporation Once done all
the metallic materials are dried using a high-pressure nitrogen gun and then dipped in
89
Hydrochloric acid (HCL) solution for 2 minutes to de-oxidize the metals so that it has
minimal effect on the series resistance of the ASPAT diode
Two types of thermal evaporators were used extensively in this study both
Edwards Auto 306 (one denoted as Junior Auto 306) The latter is used to deposit alloy
type of metals while the former is used for the non-alloyed type of metals In the case of
GaAsAlAs ASPAT alloy type metals are used while for InGaAsAlAs non-alloyed
metals are used The cleaned metals are then loaded in the thermal evaporators and
placed on a resistive tungsten boat Each metal is placed on its specific tungsten boat to
avoid unnecessary mixture during the evaporation
Figure 32 Actual picture of thermal evaporator used in this study
Prior to loading the sample into the evaporator a standard fabrication process for
ASPAT diodes takes place by patterning the samples with AZ2microm negative photoresist
At the end of this step an opening area is created for the metal contact to be filled and
connected to the ohmic contact of the semiconductor The sample is also deoxidised
using a mixture of HCL and water in the ratio of 11 prior to evaporation This has to be
done in a very short time in order to avoid re-development of the native oxide layer
Inside the chamber the sample is securely placed on a chuck upside down facing the
filled tungsten boat The distance between the sample and metallic source boat is about
90
40 cm Figure 32 illustrates the actual thermal evaporation system used in this study
The thermal evaporator chamber is pumped down to reach a minimum pressure below
1times10-5
mbar before vaporizing the metal It is important that the mean free path between
metal amp sample is created and each vaporized metal stick firmly on the samplersquos surface
The normal practice in this study is to keep the vacuum pressure under 1 times10-6
bar so
that better device performance can be obtained The amount of current required to melt
down the metal is between 4 Amps to 6 Amp This amount of current is forced through
the tungsten boat and generates very high heat melting down the metallic source and
vaporizing it towards the sample surface The deposition rate for each metal can be
monitored by using a built-in film thickness monitoring (FTM) on the thermal
evaporator which proportionally depends on the amount of materials deposited The
GaAsAlAs sample is started with deposit of 55nm AuGe 13nm Ni and 500nm of Au
The reason of depositing AuGe first is due to the fact that the ohmic layer of the
ASPAT only can only be doped with a maximum doping of 4 times1018
cm-3
which is not
high enough for good conductivity Thus here Ge atoms will diffuse into the GaAs and
replaces Ga atoms during annealing process leading to higher doping levels (gt1 times1019
cm-3
) and hence improved conductivity
3351 Lift-off
The use of AZ2microm allows for the exact patterning of metals without the need for etching
using a single layer lift-off technique The negative photoresist also provides an undercut
profile which will create disjointedness between the desired metal pattern (on the
semiconductor) and undesired metal (on photoresist) The process of getting rid of the
unwanted metal from a sample surface is called lift-off The process starts once the
evaporation process is accomplished The sample is soaked into 80˚C N-Methyl-2-
Pyrrolidone (NMP) solution for usually 20 minutes (fast lift-off process) In most
instances the sample is in NMP for more than 12 hours in ambient temperature (slow
lift-off process) as the NMP solution is not destructive to the sample In this solution
the negative resist will be softened and the metal part which sticks on it will also be
eliminated from the sample As depicted in Figure 33 the lift-off process for a single
device shows the usual photoresist undercut profile observed To ensure that NMP
91
residues on the sample surface are completely removed DI water is used to rinse the
sample which is then blown dry with a nitrogen gun
Figure 33 Single layer lift-off process using negative photoresist
3352 Annealing
The alloyed (AuGeNiAu) metal stack requires a thermal treatment called annealing to
improve the ohmic contact between metal and semiconductor The sample which has
deposited top and bottom contacts is loaded into an annealing furnace at a temperature of
420˚C for 2 minutes In the case of GaAs during thermal annealing Ge atoms penetrates
into the GaAs crystal for approximately 70nm-250nm depending on evaporated
thickness of the metal layers annealing temperature as well as time [100] In this work
the total metal thickness evaporated for each contact layer is around 500nm This
thermal annealing treatment will also melt down the Au if it is too thick and is subjected
to too long a heat treatment Therefore it is not advisable to do annealing after the
sample is coated with bond pad metals as it can result in short circuited devices
sometimes
Az2micro Negative
photoresist profile
after UV exposure
and development
Evaporation to
form metal layer
(AuGe Ni Au)
Desired metal
contact
Metallisation
process
Lift-off undesired metal
92
34 GaAsAlAs ASPAT Process Optimization
As mentioned earlier this section present details two major process flows of the
fabrication process for the ASPAT diodes which utilised three stages of development of
photomasks design namely a ldquoFirst generation mask designrdquo (1st Gen) a ldquoSecond
Generation mask (2nd
Gen)rdquo and a ldquoThird Generation mask (3rd
Gen)rdquo design The 1st
and 2nd
generations mask designs are the designs that were produced in the first stage of
this work to develop the fabrication process know-how and to get familiarized with the
actual fabrication techniques in the cleanroom The difference between the 1st Gen and
2nd
Gen masks is in term of the development towards realizing Air Bridges and
Dielectric Bridges which were mostly covered by the 2nd
Gen mask design The
analyses in term of reproducibility repeatability and manufacturability for process
control and current-voltage characteristic as well as ultimately RF measurement are
obtained on relatively large size devices via these two mask designs The large area
emitter dimensions range in size from 15times15 microm2 to 100times100microm
2
The 3rd
Gen mask design was designed based on the optimization of the 2nd
Gen
mask which was to realize ASPAT diodes that are able to work at very high operating
frequencies Therefore in such design the ASPAT devices have to have a minimal
amount of capacitance and low series resistance this is can be achieved by shrinking the
emitter size of the diode to the smallest area possible as well as optimising the
fabrication process ton reduce parasitics The smallest fabricated devices designed on the
new mask has an 2times2 microm2 MESA area which also includes Ground Signal Ground bond
pads for both device and de-embedding structures (open and Short) for RF
measurements
Before the commencement of any fabrications and designing any layouts on eg
Si GaAs InP etc the epitaxial layer must be grown first to a desired design In the
University of Manchester the epitaxial layer structures are grown using one of the two
Molecular Beam Epitaxy (MBE) machines which are either the RIBER V90H or the
V100HU system Both systems are managed by Professor Missous Epitaxial wafers or
sample grown by each system are identified by a prefix and numbers that are prefix
VMBE for the V90H system and XMBE for the V100 system The epitaxial layers are
93
grown on four-inch wafer diameter The maximum diameter that can be grown on using
the V100H is 8 inches but generally single 4rdquo or 4x4rdquo wafers are used The wafers are
then diced and cut using a diamond scriber into 15mm times 15mm tiles for easy handling
and fabrication in the D12 cleanroom lab in the University of Manchester
In this section the structures fabrication and performance of the various ASPAT
diodes for both repeatability and high frequency applications will be discussed further
The ASPAT is manufactured on wafer sample XMBE304 which is a GaAsAlAsGaAs
lattice matched to a GaAs semi insulating substrate is the main focus The ground works
on this ASPAT such as the initial design and fabrication process flow optimization had
been conducted by fellow PhD colleagues in the group led by Professor Missous at the
University of Manchester
341 ASPAT Devices used in Fabrication
3411 XMBE368 and XMBE307
Table 32 Epitaxial layer of Doped substrate samples
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~50
Spacer1 GaAs NID 50 50
Barrier AlAs NID 28 28
Spacer 2 GaAs NID 1000 1000
Buffer GaAs(Si) 4times1017
50 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~3500
Substrate GaAs (Si) Doped 50000 50000
These two samples were the first batch of diode structures used in this work and
were grown using the RIBER V100 MBE machine A great deal of work was expanded
to ensure that it is able to produce appropriate non-linear I-V characteristics The work
carried out including finding suitable fabrication process steps mask designs process
control limitations ie etching rates etc The results obtained from processing these
94
samples mostly on large area anode and cathode sizes and their analysis included both
growth profiles and fabrication process flows These samples were grown on doped
GaAs substrates As such the finished diodes were vertical structures and the fabrication
process has marked differences compared to undoped substrate samples While
XMBE368 had similar epitaxial layer profile to XMBE307 during growth the AlAs
layer was set to be stagnant (ie no-rotation of the substrate during growth) to
investigate the effects of slight variations in barrier thickness
3412 XMBE304
The next sets of samples were all grown on semi-insulating GaAs substrates
Table 33 details the epitaxial layer profile of sample XMBE304 the main work horse
of this research work The growth of this structure was performed on a multi-wafer
platen and consisted of 9 x 2rdquo wafers (from XMBE304A to XMBE304I)
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm
Epitaxial layer Material Doping(cm-3
) Thickness(Aring)
Emitter GaAs(Si) 4e+18
3000
Emitter 2 GaAs(Si) 1e+17
400
Spacer GaAs NID 50
Barrier AlAs NID 28
Spacer 2 GaAs NID 2000
Collector GaAs(Si) 1e+17
400
Collector 2 GaAs(Si) 4e+18
4500
Substrate GaAs(SI) Semi-Insulating
For a typical ASPAT structure the emitter is essentially highly doped to
4times10+18
cm-3
to provide accumulation of electron in the emitter contact region It was
purposely highly doped to also achieve low ohmic contact with the metal The spacers
are used to avoid diffusion of dopants to the subsequent layers The ASPAT structure as
mentioned earlier has a single AlAs barrier with a very small thickness sandwiched
between two different length GaAs spacer layers
Batch XMBE304 is the main focus in these studies All activities required for
repeatability reproducibility process flow and devices as well as qualifying new or
95
optimization fabrication technique for small devices and RF performance which were
then used for high frequency were based on the set of wafers grow in this batch
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability
As the new wafer structures have to be tested and evaluated to gauge the
performance of the ASPAT diodes their uniformity also needs to be tested so as to
ensure it exhibited fully functional diode with zero bias detection in minimal variation in
IV characteristics between diodes As described previously 4rdquo wafers are always diced
up into 15mm times15 mm size for ease of handling in the cleanroom and for masks cost
purposes
3421 Doped n+ Substrate Wafers
For wafers grown on n+ substrates (XMBE368 and XMBE307) a two-level mask
set is sufficient to complete the fabrication process In this case the devices are designed
with mesa structures and top metal contact on the upper surface of the wafer and a
bottom contact on the backside of the wafer One mask plate is used for defining the
mesa structure (wet etch) and the other mask plate is used for defining the metal pad
Since the mesa is relatively large (30times30microm2
to 100times100microm2) there is no requirement to
define bond pads for measurement purposes A prior RTD mask designed by fellow
colleague Dr Md Adzhar for his PhD work was used for processing the ASPAT diodes
as well in the first instance The detail fabrication process is summarized in appendix I
for the doped substrate wafers Figure 34 shows typical IV characteristics for 30x30microm2
emitter size diodes obtained from sample XMBE368
96
The I-V measurement was taken from two different tiles (15mm times15 mm) located
on top and bottom of a 4rdquo XMBE368 wafer The location 1 marked as a blue line in
figure 34 refers to a device on a tile taken from the top of the 4rdquo wafer while location
2 (red) refers to a device on a tile taken from the bottom of 4rdquo wafer At 07V the
separation difference in current is ~228 for both tiles This shows that the device in
tile 1 is less resistive than the sample in tile 2 implying that the AlAs layer for tile
located on the top corner of the wafer is thinner and thus allows more electrons to tunnel
through it at a given bias
3422 First Generation Mask Design (1st Gen)
-0015
0005
0025
0045
0065
0085
-15 -1 -05 0 05 1 15
I C
urr
en
t (A
mp
)
V Voltage (Volt)
Current vs Voltage (XMBE368_1) for 30x30microm2
MidLeft2
MidRight3
Figure 34 Current-Voltage characteristic of sample XMBE368 used
in this study at two different locations on the wafer tile
(a) (b) (c)
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2 diode dimensions
designed in the 1st Gen Mask
Location 2
Location 1
97
The fabrication of the GaAsAlAs ASPAT conducted in this 1st Gen mask is
followed the established generic process flow for InGaAs material which was done by
former co-worker Dr Md Adzhar Md Zawawi[101] The generic process flow is fairly
simple consisting of four mask steps as shown in Table 34 below The fabrication
process starts with the sample being cleaned in a NMP solution at a temperature of 80˚C
with Acetone and Propan-2-ol (IPA) The purpose of cleaning using NMP and Acetone
is to remove any organic material The IPA is used to remove Acetone residues
Table 34 Generic fabrication steps established by Dr Md Adzhar [101]
Step number Process
1 Top Contact
2 Mesa Etch
3 Isolation
4 Bottom Contact
In the 1st Gen mask the first step in fabricating the GaAsAlAs ASPAT diodes is
to use the first mask to define the emitter contact area The emitter has three different
sizes 100times100microm2 30times30microm
2 and 15times15microm
2 The lithography technique uses the
negative photo-resists AZ2micron with 55 second UV-photolithography to pattern the
top contact Then it is developed using MC319 developer to clear and define the
exposed area for the metals to stick to The sample is then subjected to plasma etching to
remove all organic residues and contaminants Then it is dipped into a mixture of
diluted Hydrochloric acid and water HCL H2O with a concentration of 11 for de-
oxidation This must be done in a short time right before the evaporation in order to
ensure good contact between metal and semiconductor surface with very low oxide
formation in between The ASPAT device performance depends on this step as contact
to the channel is by means of current flowing through the anode to the cathode terminals
In our lab the approach taken to achieve the Ohmic contact is by evaporation of Gold
Germanium (AuGe) Nickel (Ni) and Gold (Au) metals layers on top of the cap layer
Subsequently the metal is defined via a lift-off process using NMP
98
The next critical step is to define the MESA or island The mesa etch mask is
designed with two options with 05 microm or 10 microm tolerance The different mesa
tolerances are introduced to act as a safeguard for the emitter from producing excessive
undercut caused by lateral etching This step is to isolate and eliminate the unwanted
GaAs which will electrically link the active layers as many devices will be fabricated at
the same time on the same wafer tile (15mm times 15mm size) The lithography process in
this step uses positive resist and is developed using MC326 developer This step is
achieved using a wet etch process where a non-selective etchants mixture of
H3PO4H2O2H2O etches down the epitaxial layers until it slightly exceeds the AlAs
barrier with an etch rate of about 600Aring to 900Aring per minute The outcome of the MESA
or island step is the formation MESA active layers which are surrounded by inactive
layers of semi-insulating substrate (when using semi-insulating substrates)
The isolation mask is a step that is basically the same as the MESA etch step
eg using similar etchants mixture same lithography process but a different mask This
step is used to etch down until the GaAs substrate is reached which means that the
etching time is longer than that in the MESA etching step The purpose of this step is to
fully isolate the device from other neighboring devices hence ensuring no electrical
connection exists between each device within one sample Since these ASPAT diodes
employ an air bridge structure of size 1times5 microm the two minutes mesa etches will
simultaneously provide an initial undercut through lateral etching for the air bridge
formation
Based on the results so far obtained using the first-generation mask which
provided large mesa areas the current voltage characteristics of the ASPAT as far as the
non-linear zero bias is concerned did work very well However there was a need to
reduce the ASPAT mesa area down to very small dimensions to achieve mm-wave or
THz detection frequencies It is certainly a general rule for semiconductor device which
operate at very high frequency to have extremely small lateral dimension which
minimises the capacitance within the ASPAT device Furthermore for wider adoption of
the technology it is also important to develop a simple reproducible and low-cost
fabrication method for ASPAT diodes Details of this fabrication process are attached in
appendix II
99
3423 Second Generation (2nd
Gen) mask (ASPAT-GSG)
This work intended to enhance the 1st Gen-Large Area ASPAT photomask by
adding many features including 2 times 2microm2 mesa areas ground-signal-ground (GSG) bond
pads to enable RF measurement and three options device processing eg Air Bridge
Dielectric Bridge for semi-insulating doped substrate and dry etch-mesa Other reasons
for designing this mask was also to qualify process steps when deploying thin (1microm
width) bridge to connect small mesa area ASPAT diodes to the co-planar GSG bond pad
for DC and ultimately RF measurements
The mask was designed to fulfil the basic rules of fabricating various types of
tunnelling diode for instance RTD and ASPAT The diodes layouts were designed using
the commercial software Advanced Design Software (ADS) from Keysight
Technologies Ltd Once the design was completed it was ready to be sent to Compu-
Graphics Company for printing and patterned on a special chrome coated glass plate
The new 2nd
Gen mask design was termed ASPAT with Ground-Signal-Ground
(ASPAT-GSG) and consisted of two main designs ldquoAir Bridge and Dielectric Bridgerdquo
where each contained eight diodes with different emitter sizes (100times100μm2 50times50μm
2
30times30μm2 20times20μm
2 15times15μm
2 10times10μm
2 6times6μm
2 and 2times2μm
2) The Air Bridge
design is comprised of Design 1 (doped substrate) and Design 2 (undoped substrate)
This can be selected by changing the order of each individual layer of the mask steps
The same options are applied for Dielectric Bridge design which included processing for
doped and undoped substrates The details of the masks will be explained in the
following paragraph
(1) Air Bridge
Design 1 Contains five steps or layers mask of size 15mm times 15mm
suitable for air-bridge for undoped semi-insulating substrate
Design 2 Consist of seven layers steps mask of 15mm times 15mm size
There are 413 die chips in about 6mm times 6mm sizes in this design Figure 36 shows both
type of design for Air Bridge mask processing
(i) Mask 1- Top Contact
(ii) Mask 2- MESA
100
(iii) Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5- Collector Bond pad with GSG
(vi) Mask 2A-Dielectric
(vii) Mask 6A-Collector Bond Pad with GSG
(2) Dielectric Bridge
Design 1 Consists of seven identical steplayers masks with lateral
lengths of 15mm times 15mm each suitable for fabrication on semi-insulating
substrate
Design 2 Also has seven steps layers masked with dimension of 15mm
times15mm each suitable for doped substrate processing
There are 357 die chips in this type of mask design with an estimated size of 6mm times
6mm separately The smallest emitter size that is connected with a dielectric as the
bridge is 6times6microm2 The smallest 2times2microm
2 diodes was designed with the air-bridge
connected to the emitter bond pad due to the difficulties of opening viascavity for less
than 2 microm2 devices Figure 37 show both options for Dielectric Bridge mask processing
(i) Mask 1- Top Contact
(ii)Mask 2- MESA
(iii)Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5-GSG bond pad
(vi) Mask 6- Via Dielectric
(vii) Mask 7- Dielectric Bridge
(vii)Mask 5A- Via Dielectric
(ix) Mask 6A-GSG bond Pad
(x) Dielectric Bridge
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates
Figure 37 The layout of 1st design of Dielectric Bridge (green circle) mask design for 100 times
100microm2 emitter size with option for doped substrate processing
101
34231 Fabrication Process of the Air-Bridge Design
The fabrication using 1st Gen mask as mentioned in Section 3422 is less
complex however the fabrication process for Air-Bridge mask design contains a few
additional steps which are to add bond pads for the Ground-Signal-Ground radio
frequency (RF) layouts If the sample is on a doped substrate another layer needs to be
added leading to a total of six steps all together
Table 35 Standard process flow for Air-Bridge design fabrication
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa EtchDielectric
3 3 Isolation
4
5
4
5
Bottom Contact
Bond Pad
In this work the samples that have been processed so far are XMBE304
XMBE314 (GaAsAlAs base material system) and XMBE326 (InGaAsAlAs base
material system) All of them are built up on semi-insulating substrate thus the normal
process flow was followed Step 1 to step 4 follow exactly the same route as the 1st Gen-
ASPAT Large Area mask formerly discussed in Section 3422 This process is then
continued by spin coating AZ2microm on the surface Mask 5 is used to pattern the bond
pads The metallisation scheme used for bond pads is TiAu and the thickness must be at
least 1 micrometre thick This is to minimise series resistance at the pads and ensure a
robust surface is created when used for DC and RF measurements
342311 Air-Bridge Process Optimization
Since the Air Bridge design approach is focused more on developing air-bridges
which have a width of 1 microm and as the smallest device is 2 times2 microm2 the negative resist
(Az2microm) which was used in the 1st Gen design type was changed to Az1microm After spin
coating an Edge Bead Remover (EBR) is required to remove the beads at the edge of the
sample this is to ensure no gap is created between samples and mask when ldquohard-
102
contactrdquo is applied during the photolithography step The use of Az1microm and EBR are
critical to enable the fabrication of small air-bridges and emitter sizes
The exposure time during the photolithography technique also needs to be
increased to achieve a 1microm size air bridge A longer time than normal is required thus
95 seconds is used for exposure under UV light Once finished appropriate
development time must be applied to ensure the line for the air bridge is perfectly
opened for the metal to fill up To get impeccable result in this step both combination of
exposure and development have to be tuned naturally leading to trade off in both Too
long exposure and developing time will break the bridge whereas for too short exposure
time and developing the air bridge will not open
There are two types of etching method used in this fabrication wet
(H3PO4H2O2H2O) and dry (NH4H2) etching Both have their own advantages and
disadvantages Wet etching is faster than dry etching However the etching profile is
highly isotropic and causes serious undercut The smaller devices which have
dimensional sizes of 6times6microm2 and below will ldquoshrinkrdquo the effective area under the top
contact metal Even though dry etching can have highly anisotropic etching profile
which can prevent excessive undercuts it requires a lot of time for etching the
semiconductor layers The NH4 and H2 plasma that are used in this technique do not only
etch the GaAs and AlAs layers but also etch the metal contact at the same rate as the
semiconductors Thus the metal area must be covered with a photoresist or thicker metal
(~1microm) must be used to counter this issue Figure 38 shows that the emitter bond pad
which is not covered by the resist will eventually be etched away by the dry etching
Figure 38 Dry Etching for the first run in this study
As mentioned in section 333 the advantage of H3PO4H2O2H2O wet etching is
that it can be made using two solutions fast and slow The fast solution is based on a
concentration ratio of 212 while the slow solution is based on a 3150 mixture The
103
212 fast solution will produce good anisotropic etch profile but is tricky to control due
to the rather high etch rate of 1000Aring per second Both fast and slow wet etching
solutions being carried out in this experiment are replicated from successful recipes that
were developed by other co-worker from Prof Missousrsquos group
342312 Issue of Over Etch under Top Metal (Wet Etching for Air-Bridge
Design)
The first run using the solutions mentioned above started with the deposited
metal as a top contact (Top contact must be defined first to make a bridge) then Mesa
etching to remove ~7000Aring GaAs using the fast etch solution The next process to be
followed was to employ the slow etch solution to etch down the epitaxial layer to the
substrate Doing this ensured that air-bridge was open and the devices isolated
individually Unfortunately unexpected results were observed where large undercuts
still appeared for both 2times2 microm2 and 6times6microm
2 devices Figure 39 shows severe undercut
under the big device that can clearly be seen in the digital scope Most probably this
problem occurs due to excessive time used for the wet etching (10 seconds for fast
solution and 10 minutes for the slow etch solution)
Figure 39 Severe undercut of 2times2 microm2 and 6times6 microm
2 devices
The second run was employed to reduce the wet etching time in total thus dry
etching was needed As discussed above CH4 and H2 are used to etch away the GaAs
and AlAs semiconductor material while O2 is used to remove polymer residues To
reduce redundant generated polymer during dry etching the process must be separated
into several goes (runs) In this run at the mesa etch step the metal area is covered by
S1805 resist and then the plasma etches down until the heavily doped Ohmic layer is
reached For the isolation step the slow wet etching solution is used to ensure the
semiconductor under the bridge is removed The etching time is still long ie over 5
Zoomed Zoomed
104
minutes Hence this will still generate appreciable undercuts Although this run
managed to reduce the wet etching time it still did not solve the undercut Figure 310
shows undercuts under the effective mesa area still occurring in this run
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet etched
Further investigation has been made to find the root cause of this issue Scanning
Electron Microscopy (SEM) picture were taken to see deep into the completed devices to
investigate what is actually happening Figure 311 shows clearly that the semiconductor
under the bridge and effective area under the 2times2 microm2 device went missing The same
goes to for the large device where about half the size of the designed effective area under
to metal was also unintentionally removed by the solution
Figure 311 SEM Images of the GaAs sample
Since this work was also run together with an InGaAs based sample
(XMBE326) new knowledge regarding etching profile was acquired The lesson learnt
from this run is that the wet etch profile of the Gallium Arsenic (GaAs) material is
totally different from that of InGaAs Figure 312 shows the cross section of GaAs and
InGaAs materials after wet etching The evidences of these issues are also indicated by
the SEM images in Figure 313 and Figure 314 This more or less explained the reason
why the semiconductor under the top metal contact is always missing when wet
chemical etching is applied
Zoomed Zoomed
105
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in this study
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
Figure 314 SEM images for InP and InGaAs taken from [56]
Furthermore previous work done by co-worker Dr Md Adzhar Md Zawawi has
optimised the process for RTD samples based on InGaAs and InAlAs heterojuction
semiconductor materials In this work Dr Zawawi found out that achieving submicron
dimensions is possible when using the soft reflow technique on InGaAs[102] However
it does not apply to GaAs when using the same technique There are few reasons to
106
believe that the work that was carried out by the previous student is not repeatable to the
XMBE304 GaAsAlAs material The main reason is due to the much thicker Ohmic
layers used in the GaAs of ASPAT structures which requires longer etch time The
sample that was used in the previous submicron work namely XMBE277 (RTD) [101]
and corresponding epitaxial layer structure is attached in appendix III The thickness
needed to be removed for the MESA step is 1421Aring compared to XMBE304 (ASPAT)
which is ~6900Aring
The fabrication results shown from the Air-Bridge design does not seem
favourable to the GaAsAlAs heterojunction sample These include unreproducible IV
characteristics and excessive undercut under the metal Therefore the GaAsAlAs
ASPAT sample cannot be processed using this type of mask (Air-Bridge approach) The
fabrication efforts were then moved to the Dielectric Bridge design described below
342313 DC measurement
Fully functional ASPAT I-V characteristics were not obtainable in this run due to
severe damages caused by the undercuts that happened underneath the top metal contact
As can be seen from Figure 315 the behaviour of the current response suggests a very
leaky diode This confirms that the air bridge approach does not work with the
GaAsAlAs ASPAT diode
Figure 315 Short circuit behaviour on one of the fabricated device in this run
-0015
-001
-0005
0
0005
001
0015
002
0025
003
0035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
mp
)
Voltage (Volt)
30x30BP
107
34232 Fabrication Process of the Dielectric-Bridge Design
Since the Air-Bridge design was not successful an alternative Dielectric-bridge
process flow was then designed to solve this issue The first run in this Dielectric-bridge
process was performed to ensure that when the fabrication was completed it was able to
produce the correct and reproducible ASPAT current-voltage characteristics The
process flow in this run is to follow the initial design which identifies the steps according
to the mask number Step 1 to step 4 in the process are exactly the same as in the 1st Gen
mask design Step 5 which is the bond pad process is then continued with spin coating
the AZ2microm After exposure and development a TiAu metal scheme with a minimum
thickness of approximately 1 microm is deposited
Table 36 Standard fabrication process flow for Dielectric-Bridge design
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa Etch
3 3 Isolation
4
5
6
7
4
5
6
7
Bottom Contact
Bond Pad
Via Etch
Bridge
Step 6 is quite complicated compared to the other steps where the introduction of
S1805 resist is used as a dielectric layer to prevent short circuit between top and bottom
contacts This includes opening the smallest via (holes within the dielectric layer) of 2times2
microm2 and 6times6 microm
2 emitter sizes This step started by spin-coating the S1805 resist and
was then followed by baking it at 150˚C for 30 minutes The longer baking time is to
ensure it is hard enough to be deployed as a dielectric layer Once the S1805 had
hardened as dielectric layer the sample was then spin-coated again with S1813 (thicker
resist) on the dielectric layer to act as a mask for vias opening (to cover the dielectric
layer from via etching damages) After the S813 was developed O2 plasma etches was
108
applied to remove the S1805 that covered the top metal and bond pads The hole on the
metal was then exposed This required only two minutersquos plasma etches time
As soon as the holes were created within the dielectric layer a quick clean to
remove S1813 was performed using Acetone and IPA This has to be fast enough to
remove the S1813 without removing the S1805 dielectric layer Mask 7 then defined the
area for the metal that will fill up into the open vias This metal connected the top
contact metal of the device to the bond pad (GSG pad) The same metal scheme as
mentioned in Section 3422 was used as the bond pad
The fabrication using the dielectric bridge approach in the 2nd
Gen mask design
appeared to work successfully when initial I-V characteristics were taken and it also
showed that the ASPAT diode was fully functional However using hardened S1805 as
a dielectric layer is not a good practise for manufacturing device since there were left
over residue on the sample surface as depicted in Figure 316 This residue comes from
the non-uniformity of S1805 resit that was formed during heat treatment Therefore the
next run was to avoid using S1805 but replacing it with a standard dielectric layer based
on Silicon nitrite (Si3N4)
Figure 316 The surface of the sample after final processing
342321 DC measurements
Given that the process of qualifying mask steps for GaAsAlAs ASPAT diodes
looked promising using the dielectric bridge approaches initial I-V characteristics
measurements were carried out for XMBE304A Figure 317 shows that the I-V
characteristics are comparable to those of the other runs ie in the 1st Gen mask
Noticeably the IV characteristic (Figure 317) between each device size does not scale
109
on a single line This is attributed to the unintentional variation in the size of the emitter
during wet etching within each sample
Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2 2500 microm2 900
microm2 400 microm2 225 microm2 100 microm2 and 36 microm2
The current densities shown in Figure 317 are calculated based on a reduced
effective area of the devices by a factor of 08 This assumption is made as actual area
(without metal) is un-measurable Theoretically devices with small areas will have
higher resistances compared to larger devices However the opposite occurred in these
devices This problem is still under investigation It could be due to the spreading
resistance producing different values according to device sizes (smaller devices have
longer D while bigger devices have shorter D)
34233 Dielectric-Bridge Process Optimization (Si3N4)
Due to poor surface roughness of the sample when using S1805 as dielectric
layer this run was employed to improve the surface quality by using Si3N4 In order to
get the actual size of the emitter the processing needed to start by defining the
semiconductor area using either top contact mask or mesa etch mask and not to deposit
the metal first Smaller effective area will be obtained if the top contact mask is used to
define the area compared to the MESA mask since there are 05 microm and 1 microm tolerances
designed in the MESA mask
-000001
0
000001
000002
000003
000004
000005
-2 -1 0 1 2
Cu
rren
t D
en
sity
(A
mp
microm
2 )
Voltage (Volt)
Current Density vs Voltage
density36
density100
density225
density400
density900
density2500
density10000
110
Table 37 New arrangement of the mask number and step in Second Run
Mask Number Step number Process
3 1 Isolation
22A 2 Mesa Etch
4 3 Bottom Contact
6
1
7
5
4
5
6
7
Via Etch
Top Contact
Bridge
Bond Pad
The fabrication was initiated by isolating each device using Mask 3 to define
them individually Then MESA mask (Mask 2) was used to cover the area from wet
etching optical measurement were used to obtain the actual size of the emitter without
metal Figure 318 shows the process results after H3P04H2O2H2O etching for a ratio of
3150
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm Tolerance
Although the mask was designed with smaller size of 6times6microm2 using the slow etchant
solution the effective emitter size can still shrink to ~3times3 microm2 and ~2times2 microm
2 as can be
seen in Figure 318 The next step was to define the bottom contact using a metal scheme
that is suitable for GaAs ohmic layer ie AuGeNiAu After lift-off the samples were
then cleaned and spin-coated with AZ2microm Then the area was defined by using Mask 6
allowing the exposed area to be filled by Si3N4 which is the dielectric layer used in the
second run However a tricky issue happened here as the Si3N4 was difficult to lift-off
especially on the smallest emitter area in this mask In this run the lift-off process was
successfully done after three days Step five which uses Mask 1 was to define the top
111
contact The same metal scheme will fill up the tiny holes within the dielectric layer to
attach on the emitter semiconductor Figure 319 below shows an optical image of a
6times6microm2
device after the top contact lift-off process Once lifted-off annealing took place
to ensure Ge diffuse into the GaAs contact layer to lower the resistance
Figure 319 After lift-off processing
Step six uses Mask 7 to define the area of metal connection between active areas
to the bond pad In this step and step seven a different metal scheme from the top and
bottom contact was used to connect metal to metal Here a TiAu scheme was used The
final step (step 7) was to define the bond pad area In this context mask 5 is used The
bond pad requires thicker metal thickness to reduce the series resistance and to increase
the robustness of the metal surface when probed with needles during measurements
This second run of 2nd
Gen mask dielectric approach went well with better samplersquos
surface when using Si3N4 as the dielectric layer compared to the previous run using
S1805 Once the bond pad were defined for each device as done in previous run the
preliminary current-voltage characteristics of the Si3N4 run were obtained This is
described in the next section
342331 DC measurements
As mentioned in the previous section the Si3N4 run started with a defined emitter
area This allows actual ASPAT dimension to be measured thus the current density
versus voltage that are plotted in the following figures are based on actual measured
sizes
112
Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
Although the actual area of each device is obtainable from measurement the current
density of this sample does not scale well either Figure 320 show the current density is
not scalable from 03V to 1V This probably happened due to the same issue related to
the spreading resistance for each diode varying To investigate this issue new runs were
required with intention of reducing Rsprd and were expected to lead to more scalable
devices Therefore a study of reducing the spreading resistance (Rsprd ) due to
contribution of the large D-gap was carried out using the 2nd
Gen mask with the Si3N4
dielectric bridge approach The following section discusses in detail the steps used in
reducing the gap between the top and bottom contact for the GaAsAlAs ASPAT diode
34234 Dielectric-Bridge (Si3N4) Process Optimization by varying the D-Gap
The series resistance as discussed in detail in Section 26322 is generally due to
the total contribution of specific contact resistance in particular the diode size the sum
of all doped layer resistances that sandwich the main ASPAT layer and the spreading
resistance which comes from the lateral structure diode design[33] Thus in order to
acquire better performance at high frequency these contributors must be controlled One
parameter that can be controlled through this fabrication process is to reduce the
spreading resistance by controlling the separation between top and bottom contact ie
the D-gap as indicated in Figure 321
-000001
0
000001
000002
000003
000004
000005
-1 -05 0 05 1
Cu
rren
t D
ensi
ty
(Am
pm
2)
Voltage (Volt)
Current Density vs Voltage
D36
D100
D225
D400
D900
D2500
D10000
113
Figure 321 side view of lateral ASPAT structure
Without designing a new mask at this stage the same 2nd
Gen Dielectric-Bridge
mask was used but the process flows did not follow the sequence order of mask
numbers The reason for deciding not to design a new mask to reduce the D-Gap was
because the fabrication process flow had not yet confirmed it repeatability and
reproducibility Thus the available photo mask at that moment was fully utilised
Furthermore the feature of the 2nd
Gen mask that included the mesa tolerance can be
exploited in this study Hence the initial idea was to reduce the length of D by using the
tolerance that was designed in with Mask 2 (MESA etch mask)
Table 38 New arrangement for the Third run using Dielectric-Bridge mask
Mask Number Step number Process
1 1 Mesa Etch
3 2 Isolation
3
2
3
4
Bottom Contact
Mesa Cover
6
1
7
5
5
6
7
8
Via Etch
Top Contact
Bridge
Bond Pad
The process therefore was initiated by cleaning the sample and was then
followed by spin-coating it with S1805 to cover the emitter contact and define the actual
D-gap
114
size of the diode This first step used Mask 1 with wet chemical etching using the slow
solution (H3P04H2O2H2O etch with a ratio of 3150) Once the resist was striped
optical measurements were performed to obtain the effective area of the emitter Figure
322 below shows the smallest emitter area obtained after etching
Figure 322 The measured size of the emitter area and the length D (blue color marked)
Step two was to isolate the devices individually by using Mask 3 This was
performed using the fast etch solution (H3P04H2O2H2O etch with ratio of 212) This
took about 10 seconds to remove about 10000Aring of material
Step three which involved two masks was the most complicated in this process
Firstly Mask 3 was used to define the bottom contact by covering the sample with
AZ2microm and then the sample was hard- baked at 190 ˚C for 4- 5 minutes to ensure it had
totally dried before applying Polydimethylglutarimide (PMGI) The PMGI type used in
this process is Lift-off Resist (LOR) SF11 After spin-coating the SF11 at 7000RPM for
45 seconds it was post-baked at 190 ˚C for 4 minutes This was done to ensure that the
LOR SF11 was hard enough for the S1805 to stick on it This was followed by spin-
coating S1805 at 4000RPM for 30 seconds and exposing it under i-line UV for 20
seconds and developed using Micro Dev mix with DI water (11 ratio) for one minute
When the correct shape of S1805 was formed the sample was exposed under flood UV
for 15 minutes The SF11 was developed with 101A developer for 1 minute Figure 323
below summarizes the whole process in step three The step three processes concluded
by depositing the bottom contact with alloyed metal scheme and once lift-off had taken
place the next step continues as usual
115
Figure 323 Summary of LOR technique steps
Step four as well as the subsequent steps were completed in this run by copying
from the previous run (ie second run) which was to deposit the Si3N4 as the dielectric
layer and so on All the devices that underwent fabrication using this technique were
measured under optical microscope MC60 assisted by the Walsall software tool in the
lab From the measured value obtained it was expected that reducing the length of D in
this technique would improve the spreading resistance by up to 70 from the original
2nd
Gen mask design Table 39 summarizes the calculation of original spreading
resistance and improvement using this technique The calculation method and equation
are taken from Section 26322
Table 39 The outcome of the spreading resistance before and after using LOR technique
Device Size(microm2) D-original(microm) RSprd(Ω) D-new(microm) RSprd(Ω)
100x100 4 056 163 023
50x50 14 327 194 054
30x30 19 602 163 097
20x20 21 832 212 135
15x15 22 1007 202 18
10x10 24 1293 205 252
6x6 25 1643 230 418
116
Technically from the experiment in this run it was observed that the development time
also controlled the final length of D longer development time produced shorter D
lengths while shorter time yielded larger D gap lengths Therefore in this run the
development time was kept constant because of the desired D length from the mesa
tolerance in general is only ~2microm
342341 DC measurement
As usual when wafer processing was completed early DC measurement took
place to check the diodes performance Each diode size was measured and compiled
into one graph as shown in Figure 324 It is clear that the performance was better than
that in the previous run in term of scalability and current conductivity
Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
To compare the current conductivity from this run and the previous run current
density at 05V was measured for both 2nd
and 3rd
runs Assuming the contact resistances
(TLM) for both runs were constant for 50times50microm2 device size the improvement of
current in the 3rd
run is about 92 This showed that such approach to reduce the D-gap
-500E-06
000E+00
500E-06
100E-05
150E-05
200E-05
-2 -15 -1 -05 0 05 1 15 2Cu
rre
nt
De
nsi
ty (
Amicro
m2)
Voltage (Volt)
Den_100microm2
Den_225microm2
Den_400microm2
Den_900microm2
Den_2500microm2
Den_10000microm2
Den2_36microm2
117
was successful in this run A new mask design was ready to take the challenge for
processing toward millimetre and sub-millimetre wave application
343 Fabrication process of GaAsAlAs ASPAT diode toward High frequency
Applications
So far the information that can be gathered from previous processing is that the
optimum process flow is achieved through dielectric approach design The effort in
reducing the series resistance by lowering its biggest contribution was attained through
lowering the D-Gap in the structure Once everything had been optimized ie the
process flow series resistance junction capacitance etc it was time to develop a new
mask design which only focused on the development of small ASPAT devices for use in
the millimetre and sub-millimetre wave regions
3431 Third Generation (3rd
Gen) mask design
The 3rd
Gen mask design was developed by taking into the account every aspect
of parameters that can contribute to the device by means of robust devices that are able
to function properly at ultra-high frequency The device cut-off frequency is given by
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(31)
Here RS is the series resistance and Cj is the junction capacitance To obtain high cut-off
frequencies Rs and Cj must be kept as low as possible From the fabrication point of
view two parameters that can be directly and easily controlled are the device area (A)
and the D-gap (which contributes to Rs)
Therefore calculations were made to find the best option Table 310 shows the
calculated value of capacitance (eq230 in page 44) and cut-off frequencies (eq31
above) for the ASPAT diodes studied These two equations extract the cut-off frequency
of the ASPAT assuming no external effects and for fully depleted devices The
XMBE304 ASPAT sample is expected to be suitable for millimetre wave applications
if small devices are successfully made In real devices sub-millimetrewave operation
can be hard to achieve due to increased series resistance and other process related
parasitics
118
Table 310 DC and RF characteristics for XMBE304
Device Size (microm2) Fully depleted
Capacitance(fF)
Calculated Series
Resistance (Ω)
Fully depleted Cut-Off
Frequency(GHz)
10000 5490 04 72
900 490 15 216
36 198 7 1148
16 879 11 1646
4 22 29 2500
Therefore in the 3rd
Gen mask design the smallest device that can possibly be obtained
in the GaAs based material fabricated using i-line lithography which is available at the
University of Manchester is 2times2microm2 and the gap between top and bottom is 15microm at
least The connecting bridge technique applied only utilised dielectric bridge method for
GSG features Figure 325 shows the layout of actual 3rd
Gen mask used in this study
There are 344 die chips on this type of mask design It also includes the Ground-signal
ground pad with 50um pitch for each chip and six de-embedding test structures as well
as eight TLM structures
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and alignment mark
structures used in this study
119
This mask is designed generally from optimizations from 2nd
Gen Mask which
deploys a dielectric bridge for connection between the devices to the bond pads
Consequently the processing steps are not being much different but mostly follow what
is shown in Table 311 below The difference only applies to the much smaller mesa
size Other features included in this mask are de-embedding structures for RF
measurements via-hole test structure TLM structures and parallel plate capacitance test
structures
Table 311 3rd
Gen Mask process step
Mask Number Step number Process
1 1 Mesa Etch
2 2 Isolation
3
4
3
4
Bottom Contact
Mesa Cover
5
6
7
5
6
7
Via Etch
Top Contact
Bond Pad
The high frequency fabrication process flow is summarized in the following section
which shows illustrations in three dimensional and cross sectional (Figure 326) views
for easy understanding
34311 Step by Step Processing
0 Wafer preparation
Cleaning using NMP and DI
water or
Acetone and IPA
120
1 Mesa Etch
2 Isolation
3 Bottom Contact
4 Mesa Cover (Dielectric Deposition)
5 Via Etch
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 3110
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 212
Metal deposition with metal
scheme AuGeNiAu for
~500nm thick
Dielectric deposition 500nm
thick Si3N4
Via etch to open holes for metal
contact using reactive ion
etching using CF4
121
6 Top Contact
7 Bridge and Bond Pad
Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-insulating
substrate device type used in this study
Figure 327 Example finished process device with bond pad using 3rd
Gen mask
3432 TLM measurements
Transmission Line model (TLM) measurements for this run were carried out
after annealing (ie at 420˚C for 2 minutes) for process control monitoring by extracting
contact resistance (Rc) values These values are a measure of the quality of ohmic metal
contacts for a given process As discussed in Chapter 2 the TLM technique used four-
Metal deposition with metal
scheme AuGeNiAu for ~500nm
thickness and thermal annealing
420˚C for 2 minutes
Metal deposition with metal
scheme TiAu (1microm thick)
122
point measurement on TLM test structures located around the 15times15mm2 tiles as shown
in Figure 222 (in page 55) Normally five TLM structures are measured across the tile
for both top and bottom contacts Figures 328 and 329 display graphical TLM results
for top and bottom contact respectively As can be seen both graphs exhibit excellent
uniformity
Figure 328 XMBE304 TLM measurement for the top contact after annealing
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing
Based on the graphs above for the top metal contact the average contact
resistance (RC) value using the metal scheme of AuGeNiAu is found to be ~005Ωmicrom
and the sheet resistance (RSH) is 22Ω However for the bottom contact the average
value for contact resistance is 012Ωmicrom and sheet resistance obtained is 26Ω Both
values are in a very good agreement with the known doping of both ohmic contact
0
2
4
6
8
10
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins top contact
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins bottom contact
y = 02157x + 01053
123
layers Therefore the specific contact resistance (Eq 250) that contributes to the total
series resistance can be calculated and the value obtained is 15Ωmicrom2 and 54Ωmicrom
2 for
top and bottom TLM structures respectively
3433 DC characteristic measurements
Again once the wafer processing is completed room temperature DC
characteristics are taken using an HP 414B or HP500B parameter analyser and its actual
setup is as described in Chapter 2 This initial measurement was to ensure the
functionality of the diodes For this run using the 3rd
Gen mask the I-V measurements
for mesa active area of 4times4microm2 6times6 microm
2 and 10times10 microm
2 were taken and are depicted in
Figure 330 Figure 331 and Figure 332 respectively Nine diodes were measured for
each three device sizes to check their uniformity Thus the average current and standard
deviation are taken at two voltage steps of 1V and 15V Table 312 summarizes the
standard deviation for each measured data obtained from this final run
Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
4times4microm2 mesa size
-00005
0
00005
0001
00015
0002
00025
0003
00035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C01_4um_1P_SI
C22_4um_1P_SI
C40_4um_1P_SI
W01_4um_1P_SI
W22_4um_1P_SI
W40_4um_1P_SI
AI01_4um_1P_SI
AI22_4um_1P_SI
AI40_4um_1P_SI
124
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
6times6microm2 mesa size
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature
for 10times10microm2 mesa size
Table 312 Standard deviation at two different voltages
Device size (um2) Standard Deviation 1V () Standard Deviation 15V ()
4times4 14 14
6times6 65 72
10times10 44 39
Noticeably the standard deviation of the device increases for the smaller size
devices This trend happened probably because the active mesa area is not uniform
causing different series resistances Since the smallest mesa active area which achieved
-0001
0
0001
0002
0003
0004
0005
0006
0007
0008
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C02_6um_1P_SI
C23_6um_1P_SI
C41_6um_1P_SI
W02_6um_1P_SI
W23_6um_1P_SI
W41_6um_1P_SI
AI02_6um_1P_SI
AI23_6um_1P_SI
AI41_6um_1P_SI
-0005
0
0005
001
0015
002
0025
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C03_10um_1P_SI
C24_10um_1P_SI
C42_10um_1P_SI
W03_10um_1P_SI
W24_10um_1P_SI
W42_10um_1P_SI
AI03_10um_1P_SI
AI24_10um_1P_SI
AI42_10um_1P_SI
125
a good I-V characteristic is 4times4microm2
in this run these devices were used for the next step
of characterisation which is the S-parameter measurement to extract their behaviour at
different frequencies
35 Conclusions
In this chapter basic fabrication techniques of GaAsAlAs ASPAT on both doped
and semi insulating substrates using standard I-line lithography as well as step by step
descriptions to achieve reproducibility in the process fabrication flow has been
demonstrated with relevant initial measured results Two major outcomes have been
demonstrated firstly related to repeatability reproducibility and manufacturability
mostly done on large device areas (15times15microm2 to 100times100 microm
2) Secondly a successful
process flow for small emitter size devices (2times2 microm2 to 10times10 microm
2) has been
developed
Subsequently two types of designs during process optimization were developed
namely Air-Bridge and Dielectric-Bridge approaches The latter approach seems
favourable for GaAsAlAs materials but was only successful when reducing the series
resistance of the device This problem was addressed by optimising the D-gap between
top and bottom contact which resulted in good scalability of each ASPAT dimensions
improving current conductivity by 92 and achieving a reproducible process On the
other hand in the former approach issues were encountered with over etching underneath
the diode effective area and thus it was hard to achieve reproducible devices
Repeatability reproducibility and manufacturability fabrication processes based on
dielectric bridge method were successfully developed This new process provides a
highly efficient and economical solution for the fabrication of GaAsAlAs ASPAT
diode Emitter sizes down to 4times4 microm2 dimensions are routinely and reproducibly
achieved in this process Series resistance which is an important parameter in
determining high frequency application are greatly reduced by changing the gap between
top and bottom contact
With all the new improvements implemented the possibility of the proposed Dielectric
Bridge method fabrication process was successfully applied for the fabrication of
ASPAT diodes
126
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT
DIODE USING SILVACO
41 Introduction
Fabricating any device or circuit requires a lot of time resources cost etc
especially elements related to the production of semiconductor devices Furthermore in
realising such a device a clean room is required Hence fabrication and processing in
wafer fab need full attention to get it done with a higher rate of success reproducibility
and manufacturability One solution that can be highlighted which will be able to reduce
all the resources that are mentioned above is by using computer simulation approaches
or to be precise physical modelling For epitaxial layer based devices physical
modelling is a good choice as it would give a better understanding and insight into each
layer and how electrical characteristics are derived A software that is most suitable for
epitaxial layer physically modelled is SILVACO This software is a very comprehensive
tool to simulate epitaxial based devices and to predict their behaviour Such software
covers many aspects starting from the first principles of physic epitaxial layer
definition as well as device layout thus making it the most powerful virtual wafer fab
tool in the market
In this chapter the SILVACO packages are discussed The discussions include the
method of defining a new material defining models and constructing the AC or DC
supply to obtain the output characteristics of the virtual device Apart from these the
focus will also be on the ASPAT diode modelling simulation and analyses of the results
which will include the ASPAT structure suitable models and DC current-voltage
characteristics The dependencies of individual structure on the I-V curves will also be
highlighted Finally the discussion of results and analyses involving a range of
operational temperatures dependency as well as from comparison made to conventional
SBD used in this study will be examined
127
42 SILVACO modelling Tools
SILVACO is a modelling software introduced in 1984 by Dr Ivan Pesic It is
purposely created for electronicsrsquo devices physical modelling and characterization This
software company has become the major supplier for most of the Electronic Design
Automation (EDA) for circuit simulation amp design of analogue Mixed-Signal and RF
circuit market This Technology Computer Aided Design (TCAD) software can predict
the simulated device performances starting from first principles It has a package which
can provide Virtual Wafer Fabrication (VWF) simulation to the device designer and
which has the capability to perform two or three dimensional physical device modelling
by using the ATLAS simulator [103] SILVACO allows all parameters such as
electrical thermal and optical characteristics of a device to be simulated under desired
bias conditions It offers cost effectiveness as well as quick prediction of results for
many semiconductor devices compared to real experiments Some hands-on experiment
may not always perform hence SILVACO can be used as an alternative
The core of SILVACO is Atlas itself which provides a platform to perform DC AC
and transient analysis for such dimensional device structure regardless of the
heterojunction material type ie binary ternary quaternary etc As the brain of
SILVACO Atlas which receives input command files containing instruction text for
execution from a runtime environment known as Decbuild will process the instruction
text and display progression error and warning via Runtime Output All the calculations
of the resultsoutcomes of the simulation are plotted via a tool called TonyPlot which is a
tool to visualise the output Figure 41 below shows how precisely the physical
modelling takes place the process of building the structure how its parameters and
variables are defined how an appropriate model statement is selected how performance
is analysed and lastly how the outcomes are displayed
128
Figure 41 SILVACO Atlas simulation process flow
As can be seen in Figure 41 the structure specification statement is used to define
any desired structure by setting the command in Deckbuid of the following parameters
a) Mesh where the structure can be defined either in 2D or 3D Cartesian grids The
unit of the coordinates used is in microns and the spacing parameters which
define the netting size can be used to improve the accuracy of the analysis at any
given position The density of netting size in this statement determines the
processing time
b) Region where the multi-layers in a structure are defined and this statement has
to outline each layer that represents a separated region independently The mesh
must be assigned to a region and the sequence of the region is arranged from low
to high
-Mesh -Region -Electrode
-Contact -Material
Structure Specification
-Model -Interface
Model Specification
Method
Numerical Method
-Log -Solve -Load -Save
Solution Specification
-Tony Plot
Display Results
129
c) Electrode are used to define the location of bias point for a designed structure
when performing the electrical analysis In this work or for the case of a diode
two electrodes are allocated as an anode and a cathode In a vertical device the
latter electrode is placed at the bottom of the device while the anode is at the top
d) Doping this statement refers to doping concentration injected into the desired
region and it normally depends on the material types
e) Materials since SILVACO was developed specifically for Silicon-based devices
default parameters are set up for Silicon properties However the use of
materials statement allows SILVACO to run for different material ie GaAs
InGaAs etc In order to make it work this parameter is defined first and then
followed by the material name and its properties such as bandgap permittivity
conductionamp valence band discontinuities mobility etc
The most crucial part is to determine whether the simulated structure of a particular
device is correct or incorrect This is done by properly choosing the specific model
statement The Specific model statement is employed to express the physic equations
that are used during the device analysis The models statement depends solely on the
structure definition Examples are device structure with double barrier use Non-
equilibrium Green function (NEGF) model and single barrier uses Semiconductor-
insulator-Semiconductor (SIS) model for effective and accurate analysis process For the
case of a single barrier in SILVACO there are many model statements that can be used
for such analysis Therefore it is recommended to check model by model in order to
ensure that all the needed parameters are defined in the material statements and results
produced are valid
SILVACO is able to calculate such models by using different numerical methods
which means semiconductor device problematic is computed to make successive
solutions by random discretisation There are three different numerical methods that are
regularly used by SILVACO to perform its calculations which are Newton Gummel and
Block Basically this is solved by using a non-linear iteration procedure which begins
from an initial guess and which then uses an iterative process to find the predicted
solution The detail of these can be found in reference [103]
130
In order to turn on the problem solution the solution specification is defined This
include log solve save and load statement All these work together to provide data for
analysis by other functions The log statement is a file type that saves in memory and can
be loaded by Atlas Any solved device will be stored in the log file Therefore it is
necessary to define the LOG before SOLVE statement and close it after the calculations
While the save statement is used to store all data point to a node in the output file the
load statement is utilised to recall all the saved data to be read by Atlas
Finally all these files can be displayed or plotted on TonyPlot it is recommended to
make SET files at plotting point for a better visualisation The plotted or displayed files
in TonyPlot can be manipulated for scaling graphs overlaying different curves and most
importantly to export the data to other files formats
43 SILVACO Implementation GaAs AlAs ASPAT Modelling
The structures play an important role in determining the terminal output
characteristics Therefore to start simulating the ASPAT device the first thing that must
be specified is its structure As mentioned earlier in Section 3412 the ASPAT diode is
a top down multilayer structure This structure which is adopted from that of Section
3412 will be used as a basis to perform the ASPAT simulation Figure 42 shows the
structure of the ASPAT in this real simulation which is exactly the same as been
discussed in Section 26322 The ASPAT diode consists of two heavily doped (up to
5x1018119888119898minus3) GaAs contact layers on top and bottom slices adjacent to lightly doped (up
to 3x1017119888119898minus3) GaAs intermediate layers In between these layers is a sandwiched
structure consisting of two different lengths of undoped GaAs spacer layers and a thin
layer of AlAs that act as a tunnel barrier In this work the simulation result will be
compared with the fabricated measurement result depending on the size of the diode
The actual device that will be used to validate the simulation is the main device used in
this study (XMBE304) which is based on a lattice matched GaAsAlAs grown on a
semi-insulating substrate Therefore the design structures that are proposed in the
fabrication are compatible with the fabricated devices and are based on lateral structures
as can be seen in Figure 42
131
Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the diode
multilayer heterostructures on the right
In the consequent simulations a key observation regarding the AlAsGaAs
heterojunction is that there are two types of tunnelling processes direct tunnelling and
indirect tunnelling Figure 43 shows the Energy-Momentum (Ek) diagram depicting the
three valleys for the AlAs conduction band namely L Γ and X points In normal
circumstances the transition of electrons happens to the X-point which is the lowest
energy in the conduction band In the case of very thin barrier the tunnelling process
occurs at the Γ point in both AlAs and GaAs materials which is the direct tunnelling
process[18] It has been reported that in the case of an ASPAT diode tunnelling which
occurs at the Γ point will be the dominant component in the tunnelling current
Therefore the actual band gap will be different from the one at the X-point which is
which 216eV[15] By contrast the energy band gap at the Γ-point is around
283eV[104] Thus this simulation uses this band gap value
Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor
216eV
Γ
X
E
K
L
AlAs
CB
VB
283e
132
The simulation code as attached in Appendix IV and the output of the simulation with all
the input mentioned above are shown in Figure 44 (a) and Figure 44 (b) Figure 44 (a)
is the band diagram at equilibrium and Figure 44 (b) is the band diagram when a bias is
applied
Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure (b) the
energy band diagram of the ASPAT diode structure when under three different biases
44 Simulation Result and Analysis
Basically the SILVACOrsquos Atlas simulation package is used to calculate the I-V
characteristics from multilayers structures In the case of GaAsAlAs heterojunctions all
details of the structure as shown in Figure 44 above are calculated based on solving the
Schrodinger time-independent equation in each layer taking into account the variation of
effective mass and conduction band offset between GaAs and AlAs
For thermionic emission and tunnelling mechanism across an abrupt heterojunction
interface the general method used in SILVACO is taken from K Y Yang work [105]
The tunnelling current of the ASPAT diode uses the equation below[74]
119869 = sum2119898lowast119864119894(1 minus 119877)119896119879
1205872ħ3
119873
119894=1ln [
1 + exp (119864119865 minus 119864119894
119896119879)
1 + exp (119864119865 minus 119881 minus 119864119894
119896119879)]
(41)
Where m is the electron effective mass E denotes the energy of the electron R is the
total resistance k represent Boltzmann constant ħ is the reduced Planck constant EF is
the fermi level V is applied voltage and Ei is the electron energy perpendicular to the
-2
-15
-1
-05
0
05
1
15
1
82
16
3
24
4
32
5
40
6
48
7
56
8
64
9
73
0
81
1
89
2
97
3
Ene
rgy(
eV
)
Thickness (microm)
VB
CB
133
barrier The important parameters that enable SILVACO Atlas to perform correct
calculations and analysis are the choice of appropriate models The suitable model that is
available for evaluating the GaAsAlAs ASPAT is based on the Semiconductor-
insulator-semiconductor (SIS) model
Thus in this run Non-local Quantum Barrier Tunnelling Model (SISEL and
SISHO) are utilized specifically semiconductor-insulator-semiconductor mode This
model enables the tunnelling current between two semiconducting regions separated by a
quantum barrier to be calculated [103] It is assumed that the charge tunnels across the
whole barrier with the source or sinks at the interface with the semiconductor regions
Under the Non-Local Quantum Barrier tunnelling model another model that can be used
is semiconductor-semiconductor-semiconductor (SS) tunnelling model if the materials
are specified By correctly inserting all parameters with the right model an excellent DC
IV characteristic match between simulation and measurement can be produced as shown
in Figure 45
441 DC Current-Voltage Characteristic
In this simulation the current at each bias step and each mesh point can be set up by the
user however the detailed calculation such as formula usage methodology and
approach that is adopted by SILVACO Atlas is unknown As mentioned above in order
to produce the energy band diagram of the ASPAT the DC characteristic of the structure
can be solved by using the Schroumldinger and Poisson equation self-consistently
To ensure that these simulations are valid one fabrication was performed on an
ASPAT diode sample XMBE304 For this sample the structure parameters are the
same as has been set in this simulation The result of the measurement and simulation
are then compared Figure 45 shows that the simulation result is in excellent agreement
with the measured data for this sample
134
Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm2) and (4times4microm
2)
using SILVACO Atlas simulator for structure device XMBE304 showing excellent agreement
between simulated and experimental data
These fitted results were performed on both a large 100times100microm2 device and the
smallest obtainable from fabrication (4times4microm2) which was to be used for the repeatability
amp reproducibility studies as well as for high-frequency applications study respectively at
room temperature In order to get a good fit a few parameters had been modified in the
SILVACO software via the Deck-built tool for example energy band effective masses
and bandgap discontinuity of GaAs spacer and AlAs barrier (The mentioned parameters
values are summarized in Table 41) The percentages of bandgap discontinuity in
SILVACO using the ALIGN parameter is given by[103]
119860119897119894119892119899 =
Δ119864119862
Δ119864119862 + Δ119864119881
(42)
Where ΔEc and ΔEv are the conduction band discontinuity and valence band
discontinuity respectively The m0 in the tables denotes the electron rest mass Once all
agreement between measurement and simulation has been met the simulation is then
carried out with structure analysis at room temperature and different temperatures
simulation
Table 41 The parameter values used in this simulation
Material Bandgap(eV) ΔEg(eV) Effective mass(kg)
GaAs 1424 03 0067m0
AlAs 2835 071 0126m0
-00002
0
00002
00004
00006
00008
0001
00012
-2 -1 0 1 2
Cu
rre
nt
I (A
mp
)
Voltage V (Volt)
Current vs Voltage
Measurment
Simulation
135
45 Structure Analysis of ASPAT Diode
Once the device structure was modelled and having successfully produced a
precise band diagram as well as validated the simulation results with experimental I-V
characteristics the next step is to further analyse the relationship between basic device
structure and its I-V characteristics This approach is used to predict what would happen
to the DC output if some of the parameters were varied especially with regards to the
AlAs barrier thickness In the subsequence simulations the thickness of each main
ASPAT (unequal spacers and barrier) layer will be studied independently as a variable in
order to determine how each parameter affects the I-V characteristic in both magnitude
and curvature The analysis will also include manufacturing tolerance where the
structure parameter which will result in a 10 difference in their I-V characteristics is
examined[59 75] This will provide an overview of how precisely to manufacture each
layer of the device The following simulation is based on the XMBE304 structure with
emitter size of 4x4microm2
451 Dependencies of current on AlAs Barrier thickness
Since the AlAs barrier is what limits the transportation of electron flow and
hence the current (which depends exponentially on the tunnelling barrier thickness)
therefore the first analysis to run on the simulation is the variation on barrier thickness
In the simulation the barrier thickness is measured in term of the monolayer Generally
one monolayer can be calculated by dividing the lattice constant of the material by two
In the case of AlAs one monolayer is calculated as follows
119900119899119890 119898119900119899119900119897119886119910119890119903(1119872119871) =
119860119897119860119904 119897119886119905119905119894119888119890 119898119886119905119888ℎ119890119889 (5666Å)
2
(43)
= 283Å
The nominal value of the AlAs barrier thickness for sample XMBE304 is 283nm
ie ten monolayers In the first simulation test the current change due to the barrier
thickness variation from 9ML to 11ML was examined first followed by the amount of
barrier thickness change that would produce a 10 change in current The simulation is
setup by fixing all other parameters and varying the AlAs barrier thickness as mentioned
136
above with a step of 02ML In order to determine what fraction of a ML would yield a
10 difference in the current the barrier thickness is slightly changed to fit the curve for
both 5 above and 5 below the original curve
Figure 46 IV characteristics of the dependencies of current on AlAs barrier
The current-voltage characteristics of the ASPAT diode do change dramatically with
barrier thickness in forward bias but not that much in reverse bias (Figure 46) The
current decreases as the barrier thickness increases For a 1ML change in layer thickness
(from 9ML to 11ML) the current changes by over ~300 at 05V
Figure 47 Example of analysis at -1 and 1V to the current
-00002
0
00002
00004
00006
00008
0001
00012
00014
-15 -1 -05 0 05 1 15
Cu
rre
nt
(A)
Voltage(V)
9ML
92ML
94ML
96ML
98ML
10ML
102ML
104ML
106ML
108ML
11ML
973E-06
0
0000005
000001
0000015
000002
0000025
000003
0000035
85 95 105 115
Cu
rren
t a
t 1V
B
ias
(Am
p)
Barrier Thickness (ML)
Current change with tunnel barrier thickness
Forward Current
5
-5
137
From the simulation result shown in Figure 46 a 9945ML barrier thickness will
give a 5 higher current and a 10056ML barrier will give a 5 lower current (Figure
47) Therefore in total 01 ML difference yields 10 current difference These indicate
that in order to control the current within 10 barrier thickness difference the growth
precision in the barrier must be precise to better than 01ML Extensive studies have
also shown that the I-V characteristic of a GaAsAlAsGaAs diode is very sensitive to
the thickness of AlAs barrier This work has been reported elsewhere[17]
452 Dependence of current on Spacer I length l1
For the longer spacer length (l1) five different values are chosen from 01microm to
03microm The lengths are changed in the order of 005microm Therefore the arrangement of
length is as follows l1=01microm l1=015microm l1=02microm l1=0 25microm and l1=03microm
respectively The results are plotted from -15V to 15V anode voltage in Figure 48 The
I-V characteristic of the ASPAT diode does not change much with the length in the
forward bias region but in the reverse bias region the current decreases as the layer
thickness increases Here the l1 layer acts as a voltage arm and a small size device
cannot sustain big changes in spacer length Changing the length at the forward region
will also change the energy states on the anode side as well changing the states
distribution on the cathode side in reverse bias
Figure 48 I-V characteristic of the dependencies current to Spacer I layer
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=01
L=015
L=02
L=025
L=03
138
By fixing the current at -1V and 1V the current and the layer thickness relationship is
illustrated in Figure 49
Figure 49 Current changes with layer thickness l1
It is noticeable that there is a dramatic change in reverse current from 01 microm to
05 microm layer thicknesses However the forward current only falls slightly from 01microm to
015microm and is stable afterwards Hence for a small size device a large change in spacer
layer at the cathode will allow more current to pass
453 Dependence of current on Spacer II length l2
Finally is the variation in the spacer II Similar to spacer I above five values are
chosen for the shorter undoped GaAs layer length l2 the thickness is varied from
00025microm to 00075 microm (steps are l2=00025microm l2=000375microm l2=0005microm
l2=000625microm and l2=00075microm respectively The results are plotted from -15V to
15V anode voltage as shown in Figure 410 In this case a slight change in I-V
characteristic in the forward bias can be seen clearly which means the I-V
characteristic depends on the length of the shorter undoped layer Therefore the l2 layer
also acts as another voltage arm due to the asymmetrical length The effect is quite
similar to the spacer l1 but this times the forward current only slight changes The reason
for the small change in current is that the length change is small and it linearly affect the
states distribution
-000002
-0000018
-0000016
-0000014
-0000012
-000001
-0000008
-0000006
-0000004
-0000002
0
0
000005
00001
000015
00002
000025
00003
000035
01 015 02 025 03
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)Reverse Current(-1V)
139
Figure 410 IV characteristic of the dependencies current to Spacer 1 layer
Fixing the current at -1V and 1V the current versus layer thickness relationship is
illustrated in Figure 411
Figure 411Current change with layer thickness l2
The I-V curve depends on the length of the shorter undoped spacer layer quite linearly
The forward current changes in increase to the layer compared to the backward current
The layer thickness l2 should be small as long as it prevents carrier diffusion Therefore
all these three layers must be kept within limit to ensure that the high performance of the
ASPAT diode can be fully utilised
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=75n
L=25n
L=625n
L=5n
L=375n
-2E-07
-18E-07
-16E-07
-14E-07
-12E-07
-1E-07
-8E-08
-6E-08
-4E-08
-2E-08
0
0
00002
00004
00006
00008
0001
00012
0002 0004 0006 0008
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)
Reverse Current(-1V)
140
46 Temperature Dependent Simulation
This section will discuss in detail how changes in operating temperatures influence
the IV characteristics of the ASPAT diode The same codes as in the previous
simulation with fitted results are used for this temperature dependence study but a few
parameters were changed for different temperatures
Theoretically the material parameters that are influenced by the change of
temperature are band gap electron effective mass the density of state (NC NV) light
hole mass heavy hole mass permittivity and electron amp hole mobilities However not
all mentioned parameters will have a large impact on the IV characteristic in the
SILVACO Atlas simulation The most significant factors that give appreciable impact on
the DC output current-voltage were the energy bandgap and the effective mass The
GaAs bandgap as a function of temperature is given by the equation below [106]
119864119892 = 1198641198920 minus
120572 1198791198712
120573 + 119879119871
(44)
Here Eg is the bandgap Eg0 denotes the bandgap at 0K TL is the Temperature α=
Constant (Varshni Parameter) AlAs6e-4 GaAs5405e-4 β= Constant (Varshni
Parameter) AlAs408 and GaAs204 The calculated parameters that are used in this
simulation are shown in Table 42
Table 42 The calculated values of bandgap at different temperatures
Temperature (K) GaAs Eg(eV) AlAs Eg(eV)
77 1506 2903
100 1500 2899
125 149 2893
150 1486 2887
175 1478 2879
200 1470 2871
225 1461 2863
250 1452 2854
275 1443 2844
300 1424 2835
325 1419 2824
350 1414 2814
375 1404 2803
398 1394 2793
141
The effective mass of the materials used in this simulation can be expressed by
119898119899 = 1198980119899 + 11989810 (
119879119871
300119870)
119898119901 = 1198980119901 + 1198981119901 (119879119871
300119870) + 1198982119901 (
119879119871
300119870)2
(45)
Where mn is the effective electron mass mp represents the effective hole mass m1n and
m1p are constant number for the basic GaAs material m0n
for 119898119883119898119871 119886119903119890 119892119894119907119890119899 119887119910 119905ℎ119890 119890119902119906119886119905119894119900119899 (1198981198991199052 lowast 119898119899119897)
13 while m0p is based on the
expression 1198980119901 = (11989811990111989732
+ 119898119901ℎ32
)23 The calculated parameters are shown in Table
43
Table 43 The calculated effective masses for each temperature used in this simulation
Temperatures (K) GaAs Effective Mass (kg) AlAs Effective Mass (kg)
77 00660m0 03790 m0
100 00658 m0 03788 m0
125 00655 m0 03785 m0
150 00652 m0 03782 m0
175 00649 m0 03779 m0
200 00646 m0 03776 m0
225 00643 m0 03773 m0
250 0064 m0 0377 m0
275 00637 m0 03767 m0
300 00634 m0 03764 m0
325 00631 m0 03761 m0
350 00628 m0 03758 m0
375 00625 m0 03755 m0
398 00622 m0 03752 m0
142
Figure 412 Measurement and simulation comparison result as a function of temperature range
from 100K to 398K
Figure 412 above shows excellent agreement between simulation and
measurement results at various temperatures The IV characteristics correspond to a
device of size 100times100microm2 as presented in Chapter 3
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes
As mentioned earlier in chapter one the tunnelling diode has many advantages
over conventional Schottky barrier diodes some of which are a large dynamic range
low power consumption and very weak temperature dependence This section will
discuss the effect of variable temperature applied to the GaAsAlAs ASPAT diode and a
similarly processed TiAu Schottky diode Two samples were fabricated together for
these studies (XMBE304 and XMBE104 representing an ASPAT and a SBD
respectively) The fabrication technique is exactly the same as has been discussed in
Chapter 3 In order to make it fair for direct comparisons as well as easy probing both
diodes were fabricated with the same emitter size (100times100microm2) The DC measurements
at different temperature were carried out using a Lakeshore Cryogenic probe station over
the range of 77K to 398K in 25K step interval
-002
-001
0
001
002
003
004
005
006
-2 -15 -1 -05 0 05 1 15 2
Cu
rren
t I
(Am
p)
Voltage V (Volt)
T=100K_Simu
T=100K_Meas
T=398K_Simu
T=398K_Meas
T=200K_Simu
T=200K_Meas
T=300K_Simu
T=300K_Meas
143
471 GaAsAlAs ASPAT diode vs TiAu SBD
Once fabrication and measurement were completed both DC outputs of the diodes
were characterised and analysed Figure 413 shows a semi-logarithmic plot for
measured current versus voltage as a function of temperature for ASPAT sample
XMBE304 In forwards bias the current changes for different temperatures from 77K
to 398K are less than 5 percent This confirms the very weak temperature dependence of
current transport as it is dominated by tunnelling through the barrier On the other hand
the backward bias shows the current changes at different temperature are slightly bigger
than in forward this due to band bending occurring faster (making the effective barrier
lower) and allowing thermionic emission to significantly contribute to transport of the
current The only other study of temperature dependence for the ASPAT was made by et
el RT Syme[15] but details were not stated in their report
Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample XMBE304
The effective barrier height for the GaAsAlAs ASPAT diode is higher than that of
the SBD (See Figure 414) therefore there is an expectation of more limited thermionic
current flow in the ASPAT than the SBD As mentioned earlier the conventional
Schottky Barrier diode that is used in this study consists of a Gold Titanium and GaAs
(AuTiGaAs) interface which is the baseline for the temperature dependence study
0000001
000001
00001
0001
001
-15 -1 -05 0 05 1 15
Log
Cu
rren
t (A
)
Voltage (V)
T=77K
T=100K
T=125K
T=150K
T=175K
T=200K
T=225K
T=250K
T=275K
T=300K
T=325K
T=350K
T=375K
T=398K
144
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT Diode [3]
The SBD epitaxial layers profile is as shown in Table 44 below Theoretically the SBD
obey thermionic emission transport[44] and its I-V characteristic is given by
119868 = 1198680[exp (
119902119881
119899119896119879) minus 1]
(46)
Where q is the electron charge V is the applied voltage across the diode n denotes the
diode ideality factor k is the Boltzmann Constant T is the absolute temperature in
Kelvin and I0 is the diode saturation current which is given by the expression
1198680 = 119860119860lowast1198792 exp (minus
119902empty1198870
119899119896119879) exp (minus120572120594119890
12120575)
(47)
here A is the area of the diode A denotes the effective Richardson constant Oslashb0 is the
barrier height at zero bias δ represents the thickness of interfacial insulator layer χ
denotes the mean tunnelling barrier and α = radic(4120587
ℎ)(2119898lowast) is a constant value The
ideality factor n is taken from the slope of the SBD current-voltage characteristic and in
this study its value varies from 1 to 2 (depending on temperature) In the case of the
ASPAT diode thermionic emission can also happen if a thicker barrier is used (~ 100Aring
or thicker) as shown by CS Kyono et el [104] who concluded that when a thicker
barrier of AlAs barrier is used the current transport is dominated by thermionic emission
145
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104)
Layer Material Doping(cm-3
) Thickness(Aring) Bandgap (eV)
Schottky GaAs(Si) 500E+15 7500 14
Semiconductor GaAs(Si) 300E+16 7500 14
Semiconductor GaAs(Si) 100E+17 7500 14
Ohmic GaAs(Si) 500E+17 7500 14
Buffer GaAs(Si) 300E+18 7500 14
Substrate GaAs(Si) N+ 3000 14
The fabricated SBD was also measured and its I-V characteristic is plotted as a
function of temperature in Figure 415 Unlike the ASPAT diode the current at forward
bias for the SBD change enormously with temperature from 77K to 398K and at all
biases For the ASPAT diode the slight change in current only started after 08V bias as
the current starts to have some component of thermionic emission over barrier
Figure 415 Log Current vs voltage as a function of temperature for SBD sample XMBE104
In order to see clearly how much the current is changing in forward bias for both
ASPAT and SBDs diode a log current at different voltages versus 1000temperature is
plotted as shown in Figure 416
1E-08
00000001
0000001
000001
00001
0001
001
01
-2 -1 0 1 2
Log
Cu
rren
t (A
)
Voltage (V)
T=398K
T=375K
T=350K
T=325K
T=300K
T=275K
T=250K
T=225K
T=200K
T=175K
T=150K
T=125K
T=100K
T=77K
146
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and SBD
Semi-logarithmic plots of current (at V= 05 06 07 08V) versus inverse
temperature for both SBD and ASPAT are shown in Figure 416 When the temperature
is increased the current also increases in the SBD as a result of thermionic emission
over the barrier for sample XMBE104 This is in contrast to the temperature-
independent tunnelling through the thin AlAs barrier of sample XMBE304 ASPAT
diode where when the temperature is increased the current is almost constant
At low and high temperatures the ASPAT shows excellent temperature
independence with a constant current flow It exhibits a tunnelling current in excess of
values expected by the elastic tunnelling current calculation equation suggested by RT
Syme [16 18] above (Eq 1) using a Oslash value of 105eV (ΓGaAs to Γ AlAs tunnelling) By
contrast for the SBD at low temperature (77K-275K) the changes of currents were very
high and for every 02V there is an exponential change of more than 40 This
temperature dependent study was also reported in[68]
147
48 Conclusions
This chapter demonstrated the establishment of an excellent physical model and
comparison of room temperature I-V characteristics of GaAsAlAs ASPAT diodes for
different emitter sizes their scalability as well as an investigation of their characteristics
at different temperatures from 77K to 398K Simulation are validated on well-
characterized experimental data and excellent fitting which had been achieved in this
work permit the designer to extract all related parameters of heterojunctionmultilayer
ASPAT structures thus creating modification for future growth specification in order to
achieved precise designs
It is clear that the work which had been carried out in this chapter is able to
achieve with adequate accuracy a claim of reverse engineering capability The ability of
the GaAsAlAs ASPAT to act as a zero-bias detector has been analysed and compared
with the SBD It is clear that the temperature stability which is shown by the
GaAsAlAs ASPAT is much better than that of the SBD thus demonstrating that the
tunnelling current is dominant over the thermionic emission in ASPAT diodes
148
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES
51 Introduction
To assist in circuit designs for any type of high-frequency circuits such as
millimetre wave detectors frequency multipliers and mixer circuits which are built
based on non-linear devices (diodes) an equivalent-circuit model for the diode is
required This is among the simplest and most effective method for analysing
semiconductor devices which work at high frequency where the electrical characteristics
measured obtained from the devices are extracted and presented in a circuit consisting of
lumped elements components (resistor inductor capacitor etc) However accurate DC
and RF measurement data is essential to extract the equivalent-circuit elements quickly
and correctly The extracted parameters values from the circuit that are taken into
account usually depends on bias and frequency associated with the device physically
which is also interrelated to the semiconductor material parameters device structure as
well as fabrication process flows
In this work the DC and RF data were derived from DC and S-parameter
measurements respectively These measurements were carried out both in-house and at
the University of Cambridge by a collaborator partner (Prof MJ Kelly) The I-V
characteristics of the diode obtained from DC measurements were measured from -2V to
2V while the S-parameters were carried out over a wide frequency range from 40MHz to
40GHz with eight different biases In this chapter the DC measurements for various
sizes of the diodes with analysis of their IV characteristics will be discussed The one-
port on-wafer ASPAT measurement setup as well as the de-embedding method will
also be explained Thereafter the equivalent circuit models with all lumped element
effect will be discussed This work is carried out with the help of the VNA which
principle has been described in Chapter 2 and Keysight ADS simulation tool All
technical details regarding the equivalent circuit models will be explained together with
the method used for the ASPAT diode evaluation The equivalent circuit model also will
cover the diode intrinsic elements such as Cj Rj and Rs and extrinsic elements ie CP
149
and RP Finally an equivalent circuit model with the small signal characterization of the
fabricated ASPAT diodes will be presented
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes
The recent development of state-of-art for DC measurement apparatus has led to
capabilities for high-level accuracy of measuring voltages to a few nano Volts and
current signals in the femto Amp range[107] This can easily be obtained by exploitation
of proper connections and high-quality cables connecting the equipment to the Device
under Test (DUT) In this work the DC measurements were carried out using an Agilent
B1500A Parameter analyser whose description was covered in Chapter 2
As was discussed in Chapter 3 the GaAsAlAs ASPAT diodes have been
fabricated with different mesa areas between 2times2microm2 to 100times100microm
2 but the smallest
size obtained with good I-Vs was 4times4microm2 In this section the focus will be on how the
extracted data can be expanded further for empirical modelling Figure 51 shows typical
results for measured ASPAT diodes with various dimensions to check for their
uniformity According to our standard procedure the DC measurement has to be
conducted prior to the RF to ensure the diode is in fully working order as this will later
save a lot of time during RF characterization
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2 6x6um
2 and
10x10um2 Note the good scalability
1E-10
1E-09
1E-08
00000001
0000001
000001
00001
0001-2 -1 0 1 2
Cu
rre
nt
De
nsi
ti (
Amicro
m2)
Voltage (V)
4x4microm^2
6x6microm^2
10x10microm^2
150
Figure 51 above demonstrates the IV Characteristics of measured GaAsAlAs
ASPAT diodes (XMBE304) for emitter sizes of 4times4um2 6times6um
2 and 10times10um
2 This
sample was processed using the dielectric bridge technique developed in this work It
can be observed that current per unit area for each dimension fits and scales to each
other The scalability of each diodes measurement is very important to ensure no process
related issues are hampering the devicersquos proper operations This also confirms that the
diodes are completely functional and can be used for the next stage of measurements
The advantage of having an excellent scalability of those diode sizes is that a prediction
of smaller emitter size can be made
This type of IV characteristic shows asymmetric behaviour which results from
the unequal spacer lengths of the device This behaviour is very useful for detection
application as it obeys a square law model The square law predicts that the current is
proportional to the square of the applied bias
119868 = 1198861198812 119908ℎ119890119899 119881 gt 0
119868 = 0 119908ℎ119890119899 119881 lt 0
(51)
To extract the first order effects of ASPAT diodes DC measurements which
result in asymmetric I-V characteristics are analysed The slope of the non-linear region
is used to determine the junction resistance (Rj) which is obtained from the first
derivative of voltage versus current (dVdI) The expression of Rj is given by
119877119895 =
120597119881
120597119868
(52)
In order to understand the relationship between Rj and diode sizes of the ASPAT the IV
characteristic for each diode displayed in Figure 51 is used to extract the Rj This has
been done by using the expression in equation (52) above and their response is plotted
against bias as displayed in Figure 52
151
Figure 52 Junction resistance versus voltage
As can be seen in the Figure 52 above the Rj for each device decreases strongly
when the voltage increases At zero bias the 4times4um2 devices show the highest Rj value
followed by 6times6um2 and 10times10um
2 devices The junction resistance at zero bias obtained
from the 4times4um2 diode is around 86KΩ while reducing by a third for the 6times6um
2 and
10times10um2 diodes with Rj of 27KΩ and 10KΩ respectively A diode with a smaller
forward current under the same applied voltage will exhibit a larger Rj For a good
millimetre wave detector a device with a large value of Rj is desirable since it will
provide high detection sensitivity
The slope at the IV characteristic contributes to an important parameter that is
commonly used by electronic manufacturers to describe diode specification namely the
video impedance (RV) which is also known as the non-linear resistance The RV which is
extracted from the real part of the diode small signal impedance is highly dependent on
the DC bias current and only weakly depends on the series resistance of the diode (RS)
Therefore the video impedance is given by
119877119881 = 119877119895 + 119877119878 (53)
Where RS is the series resistance of the diode whose value is normally very small and
does not contribute much to the whole slope and hence RV is dominated by Rj The RV
changes in behaviour if any DC current is flowing through the diode Practically small
DC current in the range of 1 to 10 microAmp or total zero bias is used to maintain the
appropriate RV value (1-2KΩ to several MΩ) RV will also determine the voltage
-10
10
30
50
70
90
110
130
150
-01 0 01 02 03
Rj(
KΩ
)
Voltage (V)
6x6um^2
10x10um^2
4x4um^2
152
sensitivity of the whole detector circuit This will be explained further in the next
chapter In the case of a detector with an amplifier RV of the diode acts as the RF
impedance which needs to be matched with the video amplifier ( impedance looking into
the diode from the amplifier)[108 109]
The quotient of the second order derivative to the first derivative
((d2IdV
2)dIdV)) when calculated from the whole I-V characteristic translates directly
into a curvature coefficient (k) This is the most commonly used figure-of-merit to
quantify diode nonlinearity at zero bias Figure 53 below shows the variation of k with
bias and more importantly the zero bias rectifying action for device sizes of 4times4 um2
6times6 um2 10times10 um
2 This parameter which represents the small-signal rectifying
action of the diode will affect the performance of the detector (voltage sensitivity)
Detailed discussions on how this parameter effect the detector performance will also be
discussed in the next chapter
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT high sensitivity
near zero bias detection
Figure 53 above shows calculated curvature coefficient of the measured I-V
characteristics from the same diodes shown in Figure 51 The highest k value is
obtained from the diodes with size of 4times4um2 followed by 6times6um
2 then 10times10um
2
The curvature coefficient decreases sharply as the bias increases for each diode This can
be attributed to a significantly increasing number of electrons that tunnel through the
thin barrier which were accumulated in the 2DEG formed in the intrinsic spacer region
-5
0
5
10
15
20
25
30
-001 004 009
Cu
rvat
ure
Co
effi
cien
t(V
-1)
Voltage (V)
k(10x10 um^2)
k(6x6 um^2)
k(4x4 um^2)
153
An ASPAT diode with a smaller size will have a larger Rj with a corresponding smaller
current under the same bias condition and hence will demonstrate a larger k value In
this calculation the curvature coefficient at zero bias obtained from 4times4um2 6times6um
2
and 10times10um2 diode is 23V
-1 17V
-1 and 16V
-1 respectively
A summary of the ASPAT diodes parameters obtained from measured I-V
characteristics that have been translated into first and second order differentials are
gathered in Table 51 below and compared to other diodes in the literature
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics in this work
Sample Rj(Ω) k(1volt)
ASPAT 10times10 microm2 10K 16
ASPAT 6times6 microm2 27K 17
ASPAT 4times4 microm2 86K 23
Ge Backward diode 182K[110] 159[110]
InGaAs Backward diode 154[110] 23[110]
Sb Backward diode 5K[111] 47[111]
Si-Backward diode 135K[112] 31[112]
PDB 15K[8] -
AlGaAs SBD 20-100K[113] 34-38[113]
GaN HBD - 16[114]
From Table 51 above it is clearly that the ASPAT diode has a comparable value of Rj
and k to existing detector diode in the research community and in the commercial
market Based on literature of each diodes stated in the table the key to obtaining a high
value of k at zero bias is to minimize any forward tunnelling current Furthermore the
largest ASPAT diode used here (10times10microm2) has very close performances to that of a
commercial diode ie discrete Ge backward diode (ref[110]) where both Rj and k value
are close to each other
53 RF Test Fixture Theory and Experiment
RF measurements differ from DC measurement as they are more complicated
and it is necessary to comprehend the basic measurement principles to achieve
meaningful data This is obligatory especially for on-wafer RF characterization and
154
analysis to attain precise results Most of the electronics component measurements
which have input and output for instance antenna amplifier cables etc are based on a
two-port network configuration The characteristics which can be extracted from these
components are usually used to define their impact on a more complicated system
The performance of the two-port network can be described by a few parameters
ie scattering (S-Parameter) admittance (Y-Parameter) Impedance (Z-parameter) and
Hybrid (H-Parameter) However the S-parameter approach is favoured for high-
frequency measurements as it is relatively easier to characterize the microwave
performance and is able to convert to other parameters when necessary The advantage
of S-parameters is that they can straightforwardlydirectly convert into other two-port
parameters as mentioned above in term of currents and voltages[115] In fact to obtain
the device capacitance the appropriate S-parameters needs to be transformed into Y-
parameters using specific equations Furthermore the devicersquos cut-off frequency can
also be obtained when S-parameter measurements are performed over a wide frequency
range
531 On-Wafer Measurement and Small Signal One-Port Characterizations
In this work the arrangement of the RF measurement setup is assumed to be a
linear system as small voltage amplitude signals are used this means that the signals
have only a linear effect on the network without any gain compression or attenuation
The assumption is still acceptable even though the typical ASPAT is characterised as
non-linear in nature because it is a passive device which will act linearly at any input
power level
Generally the S-Parameter measurements on a diode can be adequately and
suitably performed using a one port measurement The technique used to characterise the
output is similar to the two ports technique but only incident and reflected waves are
used to characterise the input and output ports of the device Essentially this is because
the ASPAT has only two terminals and it is a passive device like other diodes
Therefore the analysis will revolve around the S11 parameter Figure 54 below show the
S11 is a ratio of reflected wave to the incident wave
155
11987811 =
119877119890119891119897119890119888119905119890119889
119868119899119888119894119889119890119899119905=
1198871
1198861 119908ℎ119890119899 1198862 = 0
(54)
A VNA as described in Chapter 2 is used to measure the ASPAT diodes This
powerful equipment is able to measure S-parameters up to 40 GHz To conduct accurate
S-parameter measurement at the diode the measurement setup must be calibrated prior
to the actual measurements taking place
54 Device Calibration
541 Open and Short De-Embedding Technique
Further calibration to be made involves anything related or attached to the
device The co-planar waveguide (CPW) bond pad and interconnect line that are
attached to the intrinsic diode are the main contributors of the errors also are required to
be calibrated In general the bonds pad could generate a capacitance (parasitic) in
parallel with the intrinsic diode and its contribution depends on the size of the bonds pad
as well as the operating frequency Meanwhile the CPW and interconnect line may
cause a parasitic inductance in series with the diode
The method that is used to get rid of this parasitic is called de-embedding and the
most common technique to realise it is by introducing OPEN-SHORT structure[116]
This method is based on a lumped-elements model Parasitic elements of the diode
De-Embedding Structure
Incident wave
Reflected wave
One-port device
a1
b1
Figure 54 One port S-parameter measurements
156
equivalent circuit correlate directly to the access section of the CPW hence can be
derived from de-embedding structures The aim of the de-embedding technique is to
represent these parasitic elements so that the one-port characteristic of the actual diode
can be determined
The two types of de-embedding structure OPEN and SHORT are conventional
techniques that are widely used in this study The design of all structure must be
identical (in size) to the device to avoid any discrepancy It is very simple to design all
these three structures for example open structures are obtained by eliminating the diode
layout and keeping the bond pad layer only The short structure just adds a bridge and
ensures ground and signal pad are connected to each other Through structures are
realised by disconnecting both ground pad and leaving the signal pad to connect to each
other
To gain more accuracy this external effect must be removed by the implementation of
de-embedding structures on the same tile as the actual device Figure 55 shows the
fabricated de-embedding structures used in this study
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use for RF
calibration and measurements (Note Images are not to scale)
In summary the de-embedding which is used to extract out the parasitic elements
from entire single diode measurement is a very important step as normally on-wafer
measurement requires coplanar waveguide (CPW) to access the diode structure (active
region) The CPW will have some effects which will disturb the accuracy of the device
characteristics
157
55 S-Parameter Measurement Result and Analysis
This section will only present RF measurement results after all VNA setup and
calibration were performed The S-Parameter measurements were carried out on ASPAT
diodes at five different DC biases from -2 to 05 volt with a sweep frequency from
40MHz to 40GHz using a calibrated VNA and the input power was fixed at -30dBm
The measurement procedure as described in Chapter 2 was performed on the device
(on-wafer) equipped with the appropriate bond pads This is important to ensure the
results obtained are valid The reason for using different biases is to find at what voltage
the device capacitance is fully depleted This is also very important in determining the
cut- off frequency of the devices
In this research two phases of the experiment on the S-parameter measurements
were carried out The first phase is to qualify the process flow ie for manufacturability
and repeatability which can be obtained from the consistency of the result The S-
parameter measurements taken on the same wafer dies are repeated several times on
different GaAsAlAs ASPAT diodes There are three different tiles taken from 3
different wafers namely XMBE304A XMBE304B and XMBE304C carried out in
this experiment The repeatability tests are done mostly on the large devices (15times15microm2
up to 100times100 microm2) and the results are analysed based on the reflection coefficient (S11)
on Real and Imaginary measurements
In the second phase the measurement is toward producing devices that can
perform at high-frequencies This can be realised by utilising small emitter size devices
(4times4microm2 6times6 microm
2 and 10times10 microm
2) The measurement results of these devices will be
used to build the equivalent circuit models while both the intrinsic as well as the
parasitics of the device will be evaluated Hence all the values obtained from these S-
parameter measurements will be used to design the device that can be used in
millimetres-wave applications As can be seen in Figure 56 below the extracted S-
parameter measurement results comprise of a reflection coefficient (S11) for real
imaginary and Smith chart for XMBE304A While these measurement results are
extracted at zero bias voltage the other bias voltages will be used to extract the
capacitance This will be described in the final section of this chapter
158
551 Diode to diode uniformity
In order to study within tile uniformity and reproducibility statistics of the RF
performance five devices of different mesa sizes in the same tile (XMBE304A) were
measured at zero bias and represented in term of Real and Imaginary reflection
coefficient (S11) the uniformity check is carried out at three different frequencies step
under 15GHz since the cut-off frequency for these big devices is relatively low at about
~20GHz on average The variation of the reflection coefficient is taken from the
percentage of the (standard deviationmean values) for all five diodes from this run The
following figures show Real and Imaginary S11 of large mesa area ASPAT diode from
15times15microm2 up to 100times100microm
2 which are represented by lines graph in a few different
colours
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices from
15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero bias
159
The variance data extracted from the graph (Real S11) above for each device within-
wafer (device to device) uniformity study is summarize in Table 52 below
Table 52 Device to device uniformity check for large ASPAT diode
Device Size 100times100 microm2 50times50 microm
2 30times30 microm
2 20times20 microm
2 15times15 microm
2
Variation 5GHz 181 115 405 151 145
Variation 10GHz 106 133 522 424 293
Variation 15GHz 119 198 281 76 509
The majority of diodes show that the variations of S11 measurements are below
3 and only a few are below 8 These finding still can be considered as good for
manufacturing control since absolute I-V characteristics reported in [63] is set by
designerrsquos specification to be not more than plusmn10 variation Further extensive RF
measurements were carried out by the research collaboration with the University of
Cambridge on the same GaAsAlAs ASPAT diodes wafer [117] In their study they
focused on 50times50 microm2
mesa size 17 of diodes were chosen to be measured The study of
uniformity of RF characteristic only focused on frequencies below 20GHz The same
approach was used to get the variation of the reflection coefficient for all 17 diodes but
this work was carried at four different frequencies Table 53 shows the zero bias S11
result for four different frequencies and standard deviation of the devices
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at four different
frequencies[117]
Frequency (GHz) 5 10 15 20
Variation () 197 243 26 276
From the results the variations of 50times50 microm2 mesa sizes measured in-house and
at the University of Cambridge are comparable with all variations showing good
uniformity ie recording variations below 3 This indicates that the RF performance
of the GaAs AlAs diode is valid and reproducible and is thus considered as a good
achievement for manufacturing Once the reproducibility and repeatability of the large
devices showed stable results the fabrication process then continued to obtain smaller
emitter size for work at high-frequencies
160
552 Wafer to wafer uniformity
Other RF measurements were conducted on sample XMBE304B which was
fabricated in-house using the same process steps but the only difference from
XMBE304A was the use of SiN3 as dielectric In this run three different mesa sizes
were measured (15times15mmicro2 20times20microm
2 and 30times30 microm
2) and Real and Imaginary S11
plotted against frequency The RF performances of both samples are gathered in one
graph as shown in Figure 58 below
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B) to qualify
the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2 device sizes (Real and
Imaginary) Note blue colour is XMBE304A and red colour is XMBE304B
For this wafer to wafer uniformity study four diodes with three different sizes as
specified previously were measured from sample XMBE304B and four diodes from
previous measurements of XMBE304A The blue line in Figure 58 represent
measurement result of real and imaginary for sample XMBE304A while the red line
161
represents XMBE304B The uniformity data is compared at three different frequencies
and gathered in the table below
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B
Device Size 30times30 microm2 20times20 microm
2 15times15 microm
2
Wafer A vs wafer B variation 5GHz 305 31 1 314
Wafer A vs wafer B Variation 10GHz 352 344 329
Wafer A vs wafer B Variation 15GHz 321 376 359
As can be seen in the Table 54 above the wafer to wafer uniformity is rather
large (30) on average The main reasons being that sample XMBE304A was
processed by utilizing S1805 as a dielectric layer while sample XMBE304B used
Si4N3 Although the process steps are similar for both wafer processing the use of
different dielectric layer will influence the diode parameters especially resistance and
capacitance as the dielectric constant for each materials is different Secondly the wafer
processing is not run concurrently at the same time thus the moisture and temperature in
the clean room might differ for both processing Although the wafer to wafer uniformity
test for this run might not be favourable for manufacturing tolerance at least the use of
different dielectric layer shows some significant result in term of capacitance resistance
effect to the GaAsAlAs ASPAT diode
553 Small devices RF measurements
The first objective of this study was to make smaller size mesa devices ie
1times2microm2 1times3 microm
2 2times2 microm
2 and 3times3 microm
2 However for GaAsAlAs ASPAT type this is
difficult to achieve in practise These issues were discussed in detail in Chapter 3
Hence the smallest emitter size that yields repeatable and reproducible results was
4times4um2 The final measurement which was done on sample XMBE304C focused on
small devices The measurements were done on four devices two with the diode bond
pads sitting on substrate (GaAs SI) and the other two sitting on dielectric layer (Si4N3)
Figure 59 below shows three measured results obtained from sample XMBE304C
using the 3rd
Gen Mask
162
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and 4times4microm
2 (Real and
Imaginary) Note that green red and blue colour represents 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and 4times4 microm2
(Smith Chart) Note that green red and blue colour represents 4times4microm2 6times6mmicro2 and 10times10microm2
diodes respectively
30MHz
40GHz
163
As can be seen in Figure 59 (Real Imaginary) and Figure 510 (Smith Chart) are
obtained from measurement of four diodes in the same tile The diode to diode
uniformity that is sitting on the same platform obtained at 35GHz frequency in this run
on average is ~15 25 and 1 for 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively On the other hand the uniformity between diode to diode sitting on
dielectric and substrate is quite high due to different capacitance value of devices on
average ~7 are attained from three different sizes of diode
From the measurement results above the Real S11 measurement of four different
sizes show the same trend for each frequency At low frequency resistances for each
diode is high as the S11 value is large At intermediate frequency the values drop
tremendously for big devices (30times30 mmicro2 and 20times20 mmicro
2) ie in Figure 57 At high
frequency all diode reach saturation limit as the value are constant Small devices
(4times4mmicro2 6times6mmicro
2 and 10times10microm
2) ie Figure 59 show S11 values that are higher than
those of large devices as smaller emitter diode have larger resistance value
The imaginary S11 value also shows the same trend as for big devices However
for small devices in this run (4times4mmicro2 6times6mmicro
2 and 10times10microm
2) the S11 value keep
dropping toward negative values at increasing frequencies This indicates that bigger
devices with positive value at high frequency are more capacitive than the smaller
devices It is worth mentioned that the capacitance and inductance values for device
sizes of 4times4microm2and 6times6microm
2 come from the CPW layouts and these are dominant while
for device sizes of 15times15 mmicro2 and above the device capacitance itself is dominant
The Smith Chart shows the reflection coefficient (S11) as a function of the
applied frequency (30MHz to 40GHz) All measurements from each mesa size follow
unique impedance circle which is that most of the lines are at the lower right outer ring
This means that the diode capacitance value is frequency dependent For the case of
10times10microm2
devices these impedance circles are mostly toward the outer ring meaning a
higher capacitance than the other two mesa dimensions All the device constantly follow
the outer ring without crossing any real axis at any frequency point meaning that the Cj
is not shorted at the maximum 40GHz measurement frequency (not reached cut-off
frequency) Therefore the entire small GaAsAlAs diodes in this run have capability to
work in the millimetre wave frequencies range
164
56 Extracting RF models of ASPAT at Zero Bias Voltage
The methodology used in the S-Parameters measurement for high-frequency
analysis must ensure that the derivation of the equivalent circuit corresponds to their port
characteristics In other words the component representing the ASPAT in the equivalent
circuit model must have physical significance otherwise the circuit will be meaningless
The fabricated ASPAT diodes as discussed in Chapter 3 have the cross section shown in
Figure 511
There are two main components that can be extracted from the fabricated
ASPAT depicted above ie intrinsic and parasitic The intrinsic refers to the main
structure of the diode itself and are represented by three bias dependent elements
namely Junction Resistance (Rj) Junction Capacitance (Cj) and diode Series Resistance
(Rs) The parasitic is the elements related to the bond pad of the anode and cathode as
well as interconnects They are represented by parasitic inductance (LP) resistance (RP)
and capacitance (CP)
The diode parameter extraction is different from the three terminal devices
(FETs) in the sense that FETs are a kind of direct extraction in which all the elements in
the transistor have linear functions to the port characteristics ie S-parameter Y-
Parameter Z-Parameter and can easily be solved by the matrix calculation method for
those particular parameters[118] The same extraction method cannot be applied to the
diodes because its elements will embroil with each other Therefore only one method is
used to extract the diode element which is optimisation by tuning the initial value toward
the measured S-Parameter values
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding equivalent circuit
model
165
The strategy used to model the ASPAT is based on an initial fitting value of the
lumped elements to the extracted value from measurement on three S-parameter graphs
(real imaginary and Smith chart) for the reflection coefficient (S11) The refinement is
accomplished by optimisation and fine tuning of the values which result in minimum
error between extracted and modelled values Figure 517 (on page 153) shows fitted S-
parameter result for extracted and model numbers with each one fitted in a single line as
an example However to achieve this excellent fitting key prior steps have to be used
de-embedding fitting the intrinsic value and optimisation
561 Extraction of ASPAT parasitic element
Once the S-parameter measurements achieve stability repeatability and
reproducibility for each measurement in term of S11 results as mentioned above the
results of the de-embedding structure which had been measured prior to the device
structure are then extracted to form a well-defined equivalent circuit In order to build
and analyse the equivalent circuit firstly the measured data is imported into the ADS
software prior to any fitting This can be realised via the ldquoStart The Data File Toolrdquo
features provided by this particular software When successfully imported the data is
read by the function S2PMDIF (These files are a natural extension of two-port S-
parameter Touchstone files) as depicted in Figure 512 below
Figure 512 The S-parameter Touchstone file is used to read the measured files
166
For the open and short techniques after de-embedding the equivalent circuit
model which is represented by mainly a capacitor and an inductor is built The open
structure requires resistance and the capacitance values of 20KΩ and 26fF respectively
connected in parallel to be well fitted to the real imaginary and Smith chart (S11) output
On the other hand for the short structure the Real imaginary and Smith chart (S11) have
to satisfy the values of resistance and inductance elements of 1Ω and ~47pH respectively
connected in series These values strongly rely on the bond pad or CPW dimension and
length The Equivalent circuit models and fitted data as well as measurement can be
seen in Figure 513 and Figure 514 below
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure
Figure 514 Equivalent circuit model for short de-embedded structure
To satisfy the equivalent circuit a self-consistence method introduced by
Ren[119] is utilised This approach accurately extracts the CPW capacitance (Cpad) and
inductance (Lpad) as well as intrinsic Junction capacitor (Cj) which is attained from the
one-port S-parameter measurements Therefore the pad capacitance introduced by the
self-consistence method for the open structure can be expressed by
167
119862119875 =
119868119898(11988411119874119901119890119899)
120596
(55)
Lpad which represents the short structure is given by
119871119875 =
1
120596(119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
))
(56)
Here Y is the admittance parameter (Y-parameter) converted from the S-parameter
measurement data and ω is the angular frequency The extracted measurement data
represented in the equivalent circuit fits with the simulated data in three S11 graphs as
can be seen in Figure 515 below From the Smith Chart it can be clearly seen that both
open and short S11 results are on the circumference which means the resistance of the
short structure is very small while in the open it is very large Additionally the
calculated Cpad and Lpad using Equations 55 and 56 above produce results similar to
those obtained in the equivalent circuit model for the open and short structure The
values are ~25fF and ~45pH respectively These data completely verify and validate
both results
Figure 515 Smith chart representative S-parameter measurement for short (left) and open (right)
CPW The blue lines represent simulated data and the red is measured data
Short
Open
168
562 Extraction of ASPAT intrinsic elements
Once the parasitic elements are determined it is easy to build a complete ASPAT
equivalent circuit The ASPAT is not like other tunnelling diode which their equivalent
circuit models widely studied ie RTD [120] IMPATT and PDB The only literature
which reports ASPAT equivalent circuits can be found in [15] and other RT Symersquos
journal paper[16] Fortunately its equivalent circuit model is not much different
compared to other diode video detectors Thus other literature which is based on
Schottky diode equivalent circuit model used for detector application can be referred to
The simplest form of ASPAT equivalent circuit and other video detectors intrinsically
consist of junction capacitance (Cj) series resistance (RS) and junction resistance (Rj)
First and foremost to extract the equivalent circuit one must know the theory behind
each parameter that is developedbuilt as a spine to become a complete element This is
vital to ensure the equivalent circuit is correct In the case of the ASPAT Cj is predicted
from a simple fully depleted parallel plate capacitor approximation which was discussed
previously in Eq (230)[15] Additionally for the S-parameter measurements the Cj can
also be validated by the self-consistence method mentioned earlier and thus can be
expressed by
119862119895 =
[
(1
120596)
1
1
119868119898 (11988411119905119900119905119886119897minus 11988411119874119901119890119899
)+
1
119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
)]
(57)
This approach helps to verify both the fully depleted parallel plate capacitor in S-
parameter measurements The basic component which is responsible for the ASPAT
series resistance RS was discussed in detail in Chapter 2 RS and Cj are key contributors
to the high-frequency operation as expressed by the device cut-off frequency Equation
(58) below
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(58)
The R and C parameters must be kept as low as possible in order to obtain high cut-off
frequencies for millimetre wave applications From the fabrication point of view Cj can
169
be reduced by making as small a diode emitter size as possible while for RS reducing
the D gap is of paramount importance as it dominates the series resistance The ASPAT
contact resistance in the electrodes (contacts between metal and semiconductor) can be
reduced by using high doping in the ohmic layers
The junction resistance (Rj) of the ASPAT is taken from the 1st derivative or
slope of the current-voltage characteristics Normally the value of Rj is very large
(several kilo Ω) compared to Rs The small signals ASPAT equivalent circuit built with
intrinsic and extrinsic components is shown in Figure 516 below while the fitting
results is shown in Figure 517 and Figure 518
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
(Real and Imaginary) results for various small device designs
Rj
Cj
Cpad Rpad
Rs Lpad
Figure 516 Equivalent circuit of the ASPAT diode
170
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
results (Smith Chart) for various small device designs
The equivalent circuit that was built for the ASPAT is taken from sample
XMBE304C with emitter dimensions of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 These
devices are expected to work in the millimetre-wave region and have cut-off frequencies
(intrinsic) of ~650GHz ~200GHz and ~100GHz respectively
Table 55 Comparison between calculated (fully Depleted) and extracted (different biases) values
from equivalent circuit parameters for different ASPAT mesa sizes at zero bias voltage
Parameters 4times4microm2 6times6 microm
2 10times10 microm
2
Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted
0V -05V -1V 0V -05V -1V 0V -05V -1V
Cj(fF) 879 23 7 6 198 55 148 139 549 171 486 46
Cpad(fF) - 15 15 15 - 15 152 152 - 15 15 15
Lpad(pH) - 45 43 42 - 50 473 473 - 51 51 46
Rj(KΩ) - 90 833 522 - 35 392 392 - 12 125 13
Rs(Ω) 99 11 11 11 67 95 8 7 41 95 45 37
fcut-off
Cj(GHz)
1828 629 2066 241
1
1208 192 1344 163
5
710 107 728 935
fcut-off
Cj+Cp(GHz)
- 380 658 688 - 151 663 781 - 98 556 705
171
The focus in this study is purposely to build ASPATs as zero bias detectors that are able
to work in the millimetre and sub-millimetre frequency range therefore all the
parameters which are obtained from equivalent circuit were extracted at zero bias
voltage Theoretically the calculations which are derived from both self-consistence amp
theory can only be solved for fully depleted device capacitance (using a parallel plate
configuration) Hence both extracted and calculated results are compiled in Table 55
Noticeably the calculation can only produce the intrinsic parameters of the
ASPAT for fully depleted capacitance On the other hand both intrinsic and extrinsic
parameters of GaAsAlAs ASPAT are obtainable from extraction and thus help to
determine at what bias the diode is start to deplete The junction and series resistance (Rj
and RS) of each dimensions shown in Table 55 above were achieved by fitting the
elements of the equivalent circuit with the three measured S11 graphs whereas the Cpad
and Lpad were extracted by utilising the self-consistent method from the S-parameter
measurements which is fitting the de-embedding structure Additionally the Cj values
are obtained via fitting the measured S11 data and employing the self-consistence
approach Results obtained from both techniques are identical
At zero bias all extracted junction capacitance from each device sizes are very
different from the calculated one while the extracted series resistance are closer to the
calculation This means that Cj is a highly voltage dependent parameter and Rs is
voltage independent but solely dependent on device structure and material used to
fabricate it The extraction at -05V and -1V shows that the values of junction resistance
is changing for most of the devices which means this parameter also rely on bias voltage
as discussed earlier in Section 52
The cut-off frequency for each calculated devices are near the THz range even
for the 100microm2 emitter area However with the introduction of parasitics elements ie
pad capacitances fcut-off is degraded tremendously Therefore it is important to make sure
all the intrinsic elements have optimum values so that the target operating frequency of
the ASPAT diode can be met Due to this it is advisable to operate the devices at no
more than 13 of fcut-off when designing detector systems
The parameters extraction at -05 and -1V also show that Cj values are closer the
calculated ones which means the ASPAT diode is reaching full depletion
172
563 Capacitances -Voltage (C-V) Extraction
Theoretically the junction capacitance of the ASPAT is calculated from the fully
depleted formula 119862119895 = 휀119900휀119903119860119889 which was also discussed in Equation (230) in Chapter
2 in page 43 Its value depends on the change of voltages to depletion at the emitter
contact[15] and make it one of the voltage dependent parameter for the diode[121]
Therefore the C-V characteristic of the GaAsAlAs must be precisely extracted
In practice the capacitance is difficult to measure due to the very low resistance at zero-
bias However alternatively it can be measured and extracted by applying different
voltage and identifying the point at which there is change which essentially represents
full-depletion Apart from these it can also be extracted from S-parameters measurement
which is then converted to Y-parameters A C-V characteristic of the GaAsAlAs
ASPAT from XMBE304C is extracted and plotted as depicted in Figure 518 below
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled capacitance vs
Voltage)
From the graph shown in Figure 518 the capacitance is extracted at eight
different biases for 4times4 microm2 6times6 microm
2 and 10times10 microm
2 The devicersquos junction
capacitance for each dimension increases and reaches a maximum value at 025V There
are additional quantum capacitance effect which comes from an increase in the negative
charges in the 2DEG region (when band bending happens creating an accumulation
0
50
100
150
200
250
-2 -15 -1 -05 0 05
Cap
acit
ance
(fF
)
Voltage (V)
Cj(4x4microm^2)
Cj(6x6microm^2)
Cj(10x10microm^2)
173
region at the barrier) This charge is imaged by the positive charge in the whole
depletion region Increasing the voltage toward positive values leads to a lowering of
the AlAs barrier and thus allowing thermionic emission to take place after certain bias
values leaving only the depletion capacitance and making the quantum capacitance
negligibly small
In the reverse bias case the device junction capacitance reaches a saturation
(fully depleted capacitance) at a voltage of -025V and remain constant up to -2V If the
reverse bias voltage is increased further the ASPAT may reach breakdown Therefore it
is important to know how far the diode can withstand applied reverse bias to ensure it
can still give full performance
57 Conclusions
In this chapter scalable DC characteristics of GaAsAlAs ASPAT diode derived
from three different emitter sizes of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 was
demonstrated The current density obtained at zero bias is several microAmicrom2 These allow
1st order differential effect to exhibit high value of Junction resistance (Rj) at zero bias
However Rj is highly bias dependent The 2nd
order differential effect on IV
characteristics display a high value of curvature coefficient leading to high voltage
sensitivity when applied in millimeter wave detector applications These two parameters
are vital in the design of millimeter wave detectors and especially those operating at zero
bias
Subsequently RF measurement up to 40GHz of uniformity study for both within
wafer and wafer to wafer variance were undertaken An average uniformity below 7
was obtained for within wafer study on large device area ( 15times15 microm2 to 100times100 microm
2)
while for small device area ( 4times4 microm2 to 10times10 microm
2) a smaller 3 uniformity variance
was achieved in average However for wafer to wafer study the variant uniformity was
quite high at around 30 on average for relatively large device (15x15 microm2 to 30x30
microm2) This was mainly attributed to different dielectric layers used in the process flows
of the sample rather than fundamental MBE control of the AlAs barrier thickness
174
It was demonstrated in this chapter that careful on-wafer RF measurements of small
size GaAsAlAs ASPAT diodes allow accurate device parameter extraction of both
extrinsic and intrinsic parameters The extrinsic parameters are namely pad capacitance
and inductance with obtained values of 26fF and 47pH respectively These values were
obtained from de-embedding structure fabricated on the same tile as the real devices
The intrinsic parameters such as junction capacitor junction resistor and series
resistance had different values according to device dimensions The smallest zero bias
value of Cj obtained from 4times4 microm2 diodes was 23fF ensuring a high cut-off frequency of
380GHz and hence in the next chapter a 100GHz detector will be presented working at
slightly less than 13 of this cut off frequency
The C-V data extraction confirmed that the fully depleted capacitance started to
happen at around -025V The maximum junction resistance occurs at +025V largely
caused by the depletion region and an additional quantum capacitance effect CQ This
effect is strongly related to the size of a 2DEG which occurs under forward bias (01V to
025V) and can be reduced by having a smaller thickness AlAs barrier
175
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR
DESIGN USING ADS
61 Introduction
The ASPAT diode having features of non-linear IV characteristics at zero voltage
make it useful for signals rectification ie detector and mixer for millimetre-wave
applications Additionally ASPAT diodes have a range of advantages such as large
dynamic range strong temperature insensitivity etc[15]over other rectifier diode This
makes ASPAT an appropriate candidate in RF detection applications Since 1940 the
only two terminals device that has been the workhorse for RF applications is the
Schottky Barrier Diode (SBD)[9] In its earliest form the SBD was built based on a
point-contact device which could not perform at high frequencies It was then developed
to work at higher frequencies by exploitation of epitaxial structures [10] and to date the
SBD remains the mainstay of two terminal devices that are able to work in the
millimetre and submillimetre-wave regions However as discussed in Chapter 4 the
performance of SBD is degraded at extremes of temperatures and these circuits
employing SBDs require temperature compensating circuitry Thus there is additional
complexity associated with technologies and applications related to SBDs
Before this work was carried out no model for the ASPAT diode as detector had
been available or developed especially using the empirical modelling ADS software
When the ASPAT diode was first introduced its function was conceptually explained it
was then built and tested to compare with other microwave detectors at X-band
frequency (95GHz) The comparisons were made in terms of detector parameters ie
sensitivity dynamic range temperature dependence etc[15] These early works lead by
RT Syme et al supplied the basic knowledge to model the ASPAT diode as a zero-bias
detector for mm-wave frequency gt100GHz For the SBD many models and equivalent
circuit approaches have been reported [122 123] The modelling of conventional SBD is
mostly implemented through fitting the S-parameter curves of the model to the
experimental one This approach is also carried out in this research since it is accurate to
predict the performance of the device under test [124]
176
This Chapter aims to introduce low cost reliable and sophisticated detector design
based on ASPAT diodes which is believed to be able to improvereplace SBD in
millimetre-wave applications especially in imaging The focus was on developing and
establishing an appropriate circuit design that suit the new ASPAT diode for such
applications The detector sensitivity as its key parameter ultimately limits the quality
and acquisition time of the detector In the subsequence section the theory of detection
including both direct and heterodyne will be discussed This is followed by definition of
detector characteristics of interest as well as noise consideration Section 65 present the
main focus of this chapter which is the development of 100GHz ASPAT detectors and
their result will be explained in term of all detector characteristic of interest
62 Detection Theory
Any incoming signal such as RF microwave or mm-wave in the form of envelope
function or single wave can be detected by rectification of the signal using a nonlinear
device ie transistor or diode The input and output signal (RF) signals are normally in
the form of amplitude as a function of time Typically the detector output is a low-
frequency signal known as the video signal which has amplitudes that are proportional to
the square of the input RF signalrsquos voltage amplitude
A complete receiver system as shown in Figure 61 below consists of receiver
antenna and a circuit designed to extract the signal and then amplify it The function of
the receiver system is the converse of the function of the transmitter side At the receiver
side the antenna is used to receive the signal it then conveys the signal to the extraction
circuit for detection as the information-bearing part of the signal (using the nonlinear
device as its heart) The signal is finally amplified to avoid any information strength
decay Additionally in a digital system the output signal which had been processed by
the detector circuit has to maintain an optimum input signal conveyed to in-phase and
quadrature (IQ) demodulators The output signal will go through a low pass filter then
to an analogue-to-digital converter (ADC) and thus a digital baseband output signals
will be produced
177
Figure 61 Block diagram represent a complete direct receiver system
There are two types of millimetre wave integrated circuit (MMIC) used for
detection purposes namely direct detectors and heterodyne detectors The direct detector
MMIC is the simplest circuit used for detector applications and has the simplest way of
extracting the RF information Due to its simplicity the direct detection method is
inexpensive and most attractive method used for measuring power in RF Laboratories
and Industries This detection scheme is also sometimes known as video detection[125]
The simplest way of explaining the detection process is that the incoming RF or
microwave signals depicted in Figure 62 below with an appropriate input power (Pin) is
rectified by using a diode and results in a corresponding output voltage (Vout) A detector
IC designed based on diodes is normally able to rectify very low levels of RF power (lt-
40dBm) then produces an output DC voltage that is proportional to the RF power A
rectifier diode can function at zero bias (which is very good for reducing noise) at very
small DC bias (003mA) and relatively high RF impedance which will produce around
600Ω This will affect the capacitance value and a low capacitance is needed to realise a
high detection sensitivity
Figure 62 The detection process of a single wave through a non-linear IV characteristic of a diode
Detector
Speakerdisplay unit Amplifier
Antenna
Vout
Pin
Tuner Amplifier
178
However this type of detector has a drawback which is itrsquos relatively low signal to
noise ratio Thus it will also rectify any incoming electrical noise at all frequencies and
up to the cut-off frequency (fC) The basics lumped components circuit as shown in
Figure 63 is used to build such detector which consists of Source impedance (Zo)
Rectifier diode (ASPAT or Schottky) wire or pad inductance and capacitance and Load
impedance (RL)
Figure 63 Lumped element illustration of microwave detector circuit
Another type of detector is the heterodyne method which mixes incoming RF or
microwave signal (fRF) with another constant signal produced by a secondary circuit
called the Local Oscillator (LO) The LO frequency (fLO) must be slightly higher than fRF
to enhance the RF signal This mixing between fRF and fLO happens in the nonlinear
device as depicted in the Figure 64 This will produce a signal at a different frequency
called the intermediate frequency (fIF) which can then be amplified and detected as
explained in the previous paragraph Theoretically a basic requirement of the mixer is to
have fIF as efficient as possible while practically the minimum conversion efficiency
obtained is around 20 The main reason for using a mixer is due to the fact that
selective amplifiers at RF frequencies are costly and hard to achieve Hence a mixer is a
good technique as it only convert the signal to a lower frequency in which good
selectivity and high gain can be more effortlessly realised[14] A good mixer diode is the
one that can produce a high cut-off frequency and reduce conversion losses (Lc) A
mixer and detector diode with a low driven input power result in reducing overall noise
figure and thus in the ideal case the fIF amplifier also should have a low noise figure for
better performance The advantage of the heterodyne method is that it has a higher
179
sensitivity compared to the direct detection method this is achieved by producing an fIF
which has a lower frequency than the incoming RF signal[14] Obviously a zero-bias
voltage diode is more favourable to be used in mixer and detector applications
Figure 64 The mixing process where the signals are processed by the non-linear I-V characteristic
to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and fRF are applied to the
diode
To have good detection efficiency for both types of detectors the operating
frequency (fO) must be several times smaller than fC In the case of an incoming
maximum modulated signal fM the frequency that can be acquired is in the range of fO
plusmnfM and will normally come with noise The standard method that is used to reduce the
noise is using a filter of bandwidth about 2fM at the centre of fO with the condition that fO
must be smaller than fM (f0lefM) Otherwise it would be difficult to attain However in
most cases fM is smaller than fO and fO is smaller than fC thus this will make the video
impedance (RV) (or nonlinear impedance) very close to the differential resistance of the
diode (at fO) in the equivalent circuit[74]
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis
Theoretically a transfer function measurement is preferable prior to any empirical
modelling since no assumption can be made due to the detector non-linearity
Furthermore measuring voltage output at high frequency can be very low while
measuring the power incident on the detector is hard to achieve where the linearity of
180
the typical power meter is normally less than 3 over its operating range[126]
Therefore the modelling of detector output voltage vs input power (ie transfer
function) can help to determine both nonlinearity correction and appropriate operating
range for the detector itself
The performance of the diode that is often taken into account is the transfer function
(output voltage Vout versus incident power Pin) and the main parameters that is used to
characterise and determine the quality of any detector diode are the voltage sensitivity
(βV) tangential sensitivity (TSS) dynamic range (P1dB) ie under 1 dB roll off power and
variation of output voltage when examined in extreme temperature situation (ΔV(T))
The voltage sensitivity in small signal analysis can use the approach introduced by
Torrey and Whitmer [9] then βV can be expressed as
120573119881(119894119889119890119886119897) =
119877119895119877119871120581
2(119877119881 + 119877119871) (1 +119877119904
119877119895)
2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(61)
Where ω is the angular frequency (2πf) Cj is the junction capacitance of the diode
active region RL is the load resistance RV is the video impedance taken from the
expression of Rj + Rs and κ is the curvature efficiency that give small signal rectifying
action of the ASPAT diode which is given by the second order term and itrsquos expression
is
κ =
11988921198681198891198812frasl
119889119868119889119881frasl
(62)
The curvature coefficient or responsivity (κ) is translated directly from the non-linearity
of the IV characteristics of the ASPAT diode for detector application Both RV and κ are
the parameters that can be extracted directly from diode DC measurement as discussed
in Chapter 5
The voltage sensitivity is actually a quantitative relationship between input
power and detector response Meaning that it is a change in signal output over change in
input power Normally output power is measured in Volts and input signal is measured
in Watts Therefore the unit of responsivity is VW[127 128]
181
TSS is referred to the lowest or minimum signal that the detector could detect it is
determined by the diodersquos βV and total noise available in the system (from the diode and
any amplifiers in the detector circuit) For any diode with fO=10 GHz and low noise of
1MHz bandwidth amplifier the TSS is typically less than -55 dBm[74] The TSS equation
is given by
119879119878119878 =
radic[4119884119870119861119879119861(119865119886 + 119905 minus 1)]
119872
(63)
Where M is a figure of merits and is derived based on the expression M= 120573119881 radic119877119881frasl t
denotes the diode noise temperature Fa is the noise figure B T and Y are the amplifierrsquos
bandwidth temperature and power for signal-to-noise ratio respectively For a low-level
video detector ie lt10GHz the sensitivity mainly depends upon three factors firstly on
RF matching structure secondly on the rectification efficiency output impedance and
noise properties of the diode and finally the input impedance bandwidth and noise
properties of the video amplifier at the detector output The RF matching structure
controls the quantity of overall energy at the active junction for rectification The second
factor controls the reaction of the diode to incident microwave radiation and the last
factor will influence the detector sensitivity in general[109]
In practical the Tss is a direct measure of the signal-to-noise ratio of a detector and
is achieved by varying the amplitude of the input pulse (RF signal) until a point in which
the top of the noise level with no signal applied is at the same level of noise at the
bottom level of RF signal It is commonly measured on an oscilloscope as depicted in
Figure 65 below It is defined as the input power at which a signal to noise ratio of 251
is produced[109]
Figure 65 Measurement of Tangential Sensitivity[108 129]
182
The transfer function in many detector diodes is often divided into three sections
Firstly at low incident power secondly at higher input power and finally at very high
power static (continuous) In the first region the detector diode performs as a square-law
detector in which Vout is proportional to Pin This region normally is used to extract the
dynamic range of the diode detector In the second region Vout is approximately
proportional to Vin and this region is known as the linear regime Finally at higher Pin
still the transfer function or response rolls off and thus Vout ultimately become saturated
This roll-off point where Vout has dropped by 1dB below an extrapolation of the
dependence at low Pin is termed the ldquo1dB roll-off pointrdquo and this value is usually in the
range of -11 to 12 dBm[15] Therefore a dynamic range of the detector diode can be
obtained by taking the interval between TSS and 1dB roll-off point (in dBm)
Finally the temperature dependence of Vout for a detector is normally taken from
two extreme points of the temperature (-40C˚ to +80C˚) and thus can be determined
from
Δ119881(119879) = 10 11989711990011989210 |
119881(1198791)
119881(1198792)|
(64)
This Vout variation between -40C˚ and +80C˚ normally expressed in dB
64 Noise Consideration in a Detector diode
The existence of noise in a system limits the accuracy of device performance and
the precision of measurements In a detector system specifically using a diode the noise
which can reduce the sensitivity of signal encryption is called the Noise Equivalent
Power (NEP) By definition the NEP is a noise power density over the detection
sensitivity and it can be exploited to determine the overall noise performance of a
detector[130 131] In other words NEP is defined as the power from the input source
(Pin) that is required to supply a voltage output (Vout) equal to the root means square
noise at Vout [132] For an ideal lossless match and assuming only Johnson-Nyquist is
present the NEP of a zero-bias detector can be expressed as
119873119864119875119900119901119905 = radic4119896119879119861119877119881120573119900119901119905 (65)
183
Where βopt is responsivity with an optimum match which is given by1 2frasl 119877119895120581 This type
of noise appears when changing voltages across a diode and a noise voltage (Vn)
normally will arise Theoretically the NEP has units of Watts (as it is actually a power)
but it often normalized to 1Hz as it is independent of bandwidth and thus the unit
becomes WHz12
Additionally there are also several noise sources that contribute to Vn in a
semiconductor diode which are Johnson-Nyquist noise Flicker Noise and shot noise
Johnson-Nyquist noise [133 134] appears across any conductor or semiconductor at
thermal equilibrium this is due to the thermal agitation of the carriers or charges It can
be expressed in root mean square voltage as below
119881119869minus119873 = radic4119896119879119861119877119895
(66)
Where Rj is the differential intrinsic resistance B denotes the post-detection bandwidth
T is the device temperature and k is the Boltzmann constant[134]
The second noise that is taken into consideration when dealing with semiconductor
devices is Flicker noise more commonly known as 1f noise It is a group of known and
unknown noise sources that can be observed in the frequency spectrum and normally
display an opposite to the frequency power density curve[135] It comes from a variety
of different causes ie recombination effects at a defect in semiconductor mobility
fluctuation and flow of direct current as well as interface phenomena [136-138] In term
of voltage source Flicker noise can be expressed as[139]
1198811119891 = 119870119891119881119909119891119910 (67)
Where Kf denotes a device-specific constant V is the voltage and f is the frequency The
value of x and y typically used are 2 and -1 respectively This type of noise (1f noise)
will be neglected at frequencies high enough due to the fact that the NEP of the diode is
proportional to the thermal noise and resistance of the diode
Finally the noise that causes time-dependent fluctuation in a flow of electrical
current because of the carrier or electron charge crossing a potential barrier is called shot
noise Shot noise is due to the randomness in the diffusion and recombination of both
majority and minority carriers[140] The equation of shot noise term at random time is
given by[141]
184
119881119878ℎ119900119905 = 2119902119868119861 (68)
Where q is the electron charge I is the current and B is the bandwidth This type of noise
is not affected by changes in temperature or device parameters Therefore the total noise
voltage appearing in the semiconductor is found to be [141]
1198811198992 = 119881119869minus119873
2 + 11988111198912 + 119881119904ℎ119900119905
2 (69)
However a zero-bias device will greatly eliminate both shot and flicker noise
compared to a biased device This has been explained by Equation (66) and Equation
(67) above where both noises are significantly related to the current and voltage Thus
if V and I =0 in the nonappearance of incident power then Vn will also become zero For
a detection process with bias the diode will be self-biased by ΔV which causes both
flicker and shot noise to appear But the shot noise in practical situation is much smaller
and thus normally ignored [142-144] Usually the noise in a zero-bias detector is
estimated by considering the low power limit as good first order estimation in which the
presence of only Johnson-Nyquist noise and ΔV is arbitrarily low [11 145 146]
Additionally it has been reported that the noise in tunnelling type diodes displays very
low or no excess noise in the bias region of the current-voltage characteristic[147 148]
Therefore in general most of the noise specifically in tunnelling type of diode will be
neglected this is a great advantage compared to SBD or transistors
65 Modelling of a 100GHz Zero-biased ASPAT Detector
Once the DC and RF characteristics of the ASPAT diode had been accurately
obtained the next step is to model and design a detector circuit based on S-parameter
measurement results as was explained in the previous chapter The aim is to realise a
detector circuit design which can be operated at millimetre and sub-millimetre wave
regions from an accurate diode model prior to the circuit design A diode detector model
puts experimental observations into context and offers insight into future experiment
results Consequently an electrical model based on lumped element component is vital
for a deeper understanding of how and to what extent a new device like the ASPAT
diode can affect all the key detector parameters that were previously discussed The
prediction of the detector parameters mostly depends upon the ASPAT diode
185
geometrical emitter size and material parameters However for millimetre wave
operating frequency the accuracy of the model is more sensitive not only to diode size
but also to the diode periphery ie substrate as well as coplanar amp transmission line
adopted in the circuit Therefore both extracted intrinsic and parasitic element of such a
device must be taken into account
In this work an ASPAT diode with an emitter size of 4times4microm2 which is the
smallest size that could be fabricated so far was chosen to be exploited for detector
designs The important parameters related to the 4times4microm2 GaAsAlAs ASPAT which
works at 0V is summarize in table 61 below
Table 61 A summary of all the important parameters of the 4x4 microm2 diode
Device Rj(Ω) Rs(Ω) Cj(fF) Cp(fF) κ(V-1) Intrinsic_fcut-off(GHz)
4times4microm2 90K 11 21 15 23 629
The actual measured I-V characteristic is used to model the diode since the library
in the ADS simulation tool does not have an ASPAT diode model or any tunnelling
diode for that matter The procedure of realizing the diode model is by taking the I-V
characteristic obtained from the 4times4microm2 emitter size measurement results and
converting it into a10th
orders polynomial equation via MATLAB software to create a
virtual I-V characteristic Thereafter this equation is then defined as a two terminals
device namely Symbolically-defined Device (SDD1P) ie a component of the non-
linear equation provided by ADS (Figure 66) to represent the ASPAT Figure 67
shows the measured data and 10th
orders polynomial equation fit very well to each other
Hence this new component used to represent the whole ASPAT diode will be used in
this research for MMIC detector and Frequency Multiplier designs The device chosen to
be modelled (4times4microm2) has measured junction capacitance of 21fF (at 0V at 40GHz) The
detector circuit is designed to operate at 100GHz for a safe side due to the extrinsic
calculated fcut-off is around 380GHz Since there are a lot of advantages in using unbiased
detectors compared to biased one this work will discuss the performance of millimetre-
wave detector at zero-bias and their result will be compared to the current performance
of other diodes reported in the literature
186
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted from
MATLAB to realize a virtual GaAsAlAs ASPAT diode
Figure 67 Verification of actual (blue measured) and virtual (red_10th order polynomial) I-V
characteristic of the 4times4 microm2 diode used in this study
To realize the ASPAT detector circuit a simple detector circuit topology as
depicted in Figure 68 was constructed Initial simulation was run to perform a
functionality check of the detector circuit utilizing the Harmonic Balance (HB)
simulation tool embedded in that particular software Such simulation tools will analyse
the detector performances in the frequency-domain as it is mostly beneficial and fully
compatible with microwave and millimetre wave problems The frequency domain is
also suitable for single and multi-tone power excitation The importance of harmonic
balance are described in [149]
-00005
0
00005
0001
00015
0002
00025
0003
-3 -2 -1 0 1 2 3
Cu
rre
nt
(A)
Voltage (V)
ADS
4x4
187
Figure 68 Direct detector circuit topology using an ASPAT diode
Initially the circuit topology that consists of P1_Tone power supply ASPAT
bypass capacitor and load resistance is simulated by setting up a fixed input frequency at
100GHz The ASPAT diode provides a DC output voltage proportional to the input
power strength depending on the absolute values of the DC terms associated with the
nonlinearity of the I-V characteristics The capacitance in the output part is a bypass
capacitor used to prevent millimetre-waves from leaking to the output The load
resistance is large enough to ensure the voltage divider between load impedance and
device impedance gives maximum voltage sensitivity This large load resistance is
achieved by creating an open circuit at the end of detector circuit terminals
Noted that this simulation was run using diode parameters that were extracted from on-
wafer one port S-Parameter measurements as described in chapter 5 To apply them in a
two port application ie detector circuit may or may not provide a very accurate
outcome it however worked adequately in the particular circuit described in this chapter
but may not work in other circuits in general Thus the one port extractions in this work
still provide adequate parameters to build and design specific MMIC detector circuits
but not in general applications
The main reason for these simulations and their results to be used in high frequency
applications is due to the fact that actual RF measurement were done up to 40GHz
Additionally the 100GHz operating frequency was obtained from extrapolation of each
ASPATrsquos component Since the on-wafer measurement that were carried out were
limited to one port characterization applying them to two port network applications may
188
have extra consequences which are unknown Therefore actual MMIC detectors are
needed to be built and test to validate this work
To find out what power the 4times4microm2 ASPAT diode can withstand the input power
is varied from -40dBm to 10dBm via control by the P1_tone As can be seen in Figure
69 the diode starts to saturate when the received input power is about -8 dBm Above
this power limit both output voltage and sensitivity drop dramatically
Figure 69 Output voltage and detector sensitivity over wide range of input power
This diode detector circuit can thus operate adequately at given input powers from -30
dBm to -8 dBm with a sensitivity of 950VW However for the best possible sensitivity
over a range of input frequencies only one optimized input power needs to be chosen
The parameters that directly influence the voltage sensitivity are the curvature
coefficients load resistance and video resistance as can be seen from Equation (61)
Therefore in the following simulation the values RL will be optimized according to the
diodes optimum input power with regards to the highest possible voltage sensitivity
Consequently five values of load resistance were chosen from few ohms to infinity
and with the same applied input power as depicted in Figure 610 For most load
resistors the sensitivity is constant at low input power and drop at the diode saturation
region (-8dBm and greater) However for an RL value of 100KΩ and below the loaded
voltage sensitivity shows a peak near 0dBm input power which corresponds to the
maximum slope of the ASPAT detector transfer function The highest voltage sensitivity
is obtained by using an Open circuit load impedance as shown in the graph The Open
circuit load impedance gives the highest voltage sensitivity due to the voltage divider
189
between source and load impedance therefore RL must be at least 5-10 times larger than
Rj to give a better sensitivity
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load resistance of
the ASPAT detector
Furthermore the value of voltage sensitivity (βV) depends on the junction
resistance of the diode and thus the large value of Rj of the ASPAT diode yields the high
βV observed Rj which was taken from the non-linear measured IV characteristic is a
voltage dependent parameter [142]and is inversely proportional to the forward bias
voltage as depicted in Figure 611 below
Figure 611 Junction resistance as a function of forward voltage
1
10
100
1000
-40 -30 -20 -10 0 10
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Incident Power Pin (dBm)
Infinity
1KΩ
10KΩ
1MΩ
100Ω
100KΩ
0
20
40
60
80
100
0 001 002 003 004 005 006 007 008 009 01
Ju
nct
ion
Res
ista
nce
(k
Ω)
Bias Voltage (V)
190
In fact the expression of (120597119881120597119868frasl ) contribute to the video impedance expression via the
expression RV=Rj+RS (nonlinear resistance) As RS is very small compared to Rj thus it
was ignored when calculating RV Although the large value of Rj will increase the
voltage sensitivity it will also make matching difficult to achieve Therefore there will
be a compromise between the size of the matching circuit and voltage sensitivity to
attain the correct value of Rj Additionally a very high Rj (around ~1MΩ) will also
increase the detectorrsquos noise equivalent power (NEP in Eq(65)) Thus an average value
of RJ typically around 100kΩ is satisfactory[150] By having a large value of RJ one can
benefit from a low input power to drive the diode into the non-linear region and thus the
detector can work at very low RF input power The NEP for GaAsAlAs ASPAT diode
is then calculated based on parameters obtained from this simulation at room
temperature The values are compared to other diode detector available in the literature
as shown in Table 62 below
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode
Device NEP (pWHz12) RJ(KΩ) Frequency(GHz)
ASPAT (4times4 microm2) 188 92 100
Tunnel Diode (08times08 microm2)[150] 370 26 220-330
Zero bias SBD[11] 15 3 150
Sb-Heterojunction Backward Diode[145] 024 32 94
VDI Zero bias SBD[151] 2 18 110
From the Table 62 above the NEP of the ASPAT is calculated based on RF input power
which is required to obtain an output signal-to-noise ratio of unity in a 1Hz at detector
output[142] and also the assumption of only Johnson-Nyquist (thermal noise) is
dominant for small incident power (-25dBm)[152 153] The prediction of NEP for the
ASPAT is comparable to the VDI Zero bias detector since the value of their junction
resistance is much lower than that of the ASPAT Therefore it is very important to
obtain a reasonable value of junction resistance From this it is clear that a trade-off of
high voltage sensitivity and low junction resistance is best to obtain low noise
191
Finally the curvature coefficient at specific operating voltages also influences
the voltage sensitivity of the detector Figure 612 shows the calculated curvature
coefficient of the 4times4microm2 ASPAT diode used in this work
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size of 4times4μm2
The high zero-bias curvature (23V) is reached from the mutual effect of the intra-band
tunnelling in the GaAs-AlAs-GaAs and the highly doped GaAs at the anode and cathode
(Rs amp Rj) This was shown in the numerical simulation in[154] where the combined
effects of the optimum anode AlAs composition increases the curvature coefficients by
thinning the energy tunnelling window (intraband tunnelling process)
Other approaches that can lead to a large curvature is using smaller device area
with minimum series resistance [155] as was also discussed in Section 52 Having a
better curvature coefficient leads to increased voltage sensitivity as seen from Equation
(61) above and βV is also proportional to κ [111] The curvature coefficient calculated
using the above formula is nearly 23V at 1mV peak and high voltage sensitivity can be
achieved by having large value of curvature coefficient But one needs to remember that
this will also decrease with increasing input power because RJ which will also decrease
Therefore for a safe operating region the incident power that can be applied through the
diode is in between -30dBm to -8dBm for a 100GHz operating frequency
In this simulation -25dBm is chosen to simulate the GaAsAlAs ASPTAT diode
detector working at 100GHz input frequency By fixing the P1_Tone to this input power
-5
0
5
10
15
20
25
30
-001 001 003 005 007 009
Cu
rva
ture
Co
effi
cien
t(V
-1)
Voltage (V)
k(4x4 um^2)
192
the frequency is varied from 90GHz to 110GHz and the results are depicted in Figure
613 below
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power
Noticeably the voltage sensitivity of the diode detector decreases linearly with
increasing input frequency At 100GHz a sensitivity of around 540VW is obtained
However the sensitivity in this case is roughly estimated from the Equation (61) above
and will not be sufficiently accurate because of the effect of other key factors such as
reflective power which was not included This parameter must be taken into the account
due the P_1Tone power source which provides a 50 Ω impedance source (Zin) which
does not match the load impedance (ZL) which consists of JωL 1JωC and Z and which
mainly comes from the ASPAT diode itself In order to determine the load impedance at
the diode a typical ohmrsquos law (Z=VI) equation must be used at the input side of the
diode with regards to the applied frequency (100GHz)
As a result the total load impedance obtained from the simulation is 11055-
j69057Ω which is clearly not matched to the 50Ω impedance source The mismatch
between source and load leads the available power from the source to be not fully
delivered to the load and hence there is loss of power leading to a lower detector
sensitivity Therefore actual calculation must take into the account the reflection impact
as expressed in the equation below
193
120573119881(119886119888119905119906119886119897) =
119877119869119877119871120581(1 minus |Γ|2)
2(119877119881 + 119877119871) (1 +119877119904
119877119895)2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(610)
Where the term (1-|Г|2) refers to the normalized power absorption by the ASPAT diode
and Г is the reflection coefficient due to discrepancy between 50Ω input impedance (Zin)
of the input port and the diode Consequently the calculation of reflection coefficient
(eq611) is carried out by using this expression and the result is shown in Figure 614
Γ =
119885119871 minus 119885119894119899
119885119871 + 119885119894119899
(611)
Figure 614 Reflection Coefficient versus operating frequency without matching circuitry
As can be seen in Figure 614 without the matching circuit the S11 is decrease
linearly with frequency but only very slowly This means that most of the RF power
transmitted from the source is reflected back (by that ratio) when it went through the
diode Therefore in order to resolve the mismatch a matching circuit is introduced in
between the source and load of the detector circuit as shown in Figure 615 (red
rectangular) This matching circuit works by transforming the load impedance into an
impedance that is identical to the source or input impedance Note that for any
impedance matching circuit the main purpose is usually to obtain maximum power
transfer to the load however in some cases (ie oscillators) the matching circuit is to
achieve a lower noise figure Hence in a broad sense the introduction of the matching
194
circuit in a detector circuit can be defined as a circuit that convert available impedance
into wanted impedance by obeying the maximum power transfer theorem [156]
Figure 615 Detector circuit with impedance matching circuit placed in between diode and source
There are many type of matching circuit that can be used to achieve both
objectives above such as circuits using lumped element transmission-line-impedance
matching circuit single and double-stub tuners as well as a quarter-wavelength In this
design the technique used to match source and load impedance is the single open and
short stub (in red rectangular) as it is simple convenient and very efficient in ADS
simulation The important parameter that needs to be tuned in both stubs is the electrical
length (E) at any designed frequency ie 100GHz in this case The E tuning is realized
by using the Smith Chart features available in the ADS simulation tools Figure 616
shows the reflection coefficient with matching circuit modelled over a broad frequency
band and it is clearly shown that at the desired operating frequency the reflection is very
low Note that it is difficult to obtain wide frequency band matching
Matching circuit
195
Figure 616 Reflection Coefficient over wide frequency band with matching
The simulation is continued to find the effect of the matching circuit placed in
the detector circuit on the voltage sensitivity The same input power (-25dBm) is applied
to the diode and the voltage sensitivity is plotted against frequency as depicted in Figure
617 Obviously at the desired operating frequency (100GHz) the sensitivity rises up to
a maximum value of 2100VW with this value obtained without any reflection and the
input port being completely matched with the ASPAT diode model used in this work
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band frequency
Once the matching circuit to be used for 100GHz operating frequency was confirmed
further simulations were made by applying a series of low input power to find the
tangential sensitivity (Tss) of the detector diode When determining the Tss it is very
important to include the matching circuit as it will minimize any power losses through
the diode thus a very small input power can be detected
196
Figure 618 Lowest detectable signal at 100GHz operating frequency
The transfer function depicted in Figure 618 shows incident power of -80 dBm
to -50 dBm applied and the lowest detectable signal that can be obtained with 4times4microm2
mesa size ASPAT diode is around 138microV at -68dBm Although a typical value of Tss is
normally not more than ~-55dBm as in ref [74] the lower value obtained in the
simulation is because the device is operated at zero bias operation and does not use any
amplifier therefore the noise and values related to amplifier as in Equation 63 have been
neglected Even though the TSS appeared very low it is most likely very dependant to
the 10th
order polynomial equation embedded into SDD in ADS software Therefore in
near future the TSS value has to be determined in real fabricated MMIC ASPAT detector
As discusses in Section 63 other important parameter that can be extracted from
the diode transfer function is the Dynamic Range of the diode It can be obtained in a
region called square law region which is a region where the Vout of the ASPAT diode is
proportional to the square law of the input power signal From Figure 619 the square
law region is in between -68dBm and -12dBm and the linear region or in this case
saturated region is above -12dBm Taking to the account the roll-off point where Vout
has dropped 1dB below the extrapolation of the dependence at low input power and
therefore the dynamic range of the detector diode can be obtained by taking the interval
between TSS and the 1dB roll-off point (in dBm) which is ~55dBm
197
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of diode operation
The figure of Merit (M) of the detector (ie equation 63) is 2100 (90K) 12
where 2100 is the sensitivity and 90K is the value of RJ at zero bias which is equivalent
to 652 W The M value should be large however in this case due to RJ being very
large it has dropped tremendously when compared to the voltage sensitivity obtained in
this simulation The results obtained indicate a reasonably successful design of the
MMIC detector using the 4times4microm2
emitter size GaAsAlAs ASPAT diode The results
obtained lead to the design of other MMIC detector using the other fabricated diode
sizes (6times6microm2 and 10times10microm
2) A Similar procedure to the one used for the 4times4microm
2
diode was followed The only difference was the use a slight higher input power (-
20dBm) than in the 4times4microm2 design Hence the simulation results obtained are then
compiled and compared as depicted in Figure 620
Saturated
Region
198
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained from the
fabricated ASPAT in this work
The graph plotted for each dimension was taken after matching circuits were included
As can be seen in Figure 620 the highest sensitivity is achieved using the smallest
device size as this has the highest cut off frequency Table 63 below summarises the
performances of the 100GHz ASPAT detectors obtained from the simulation in this
work
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector
Device Tss(dBm) fcut-
off(GHz)
Bv
(VW)
Dynamic range dB(dBm) M(W-12
)
4times4microm2 -68 380 2100 55 65
6times6microm2 -50 151 1445 48 45
10times10microm2 -40 98 247 40 21
From table 63 above it is clear that a lower cut-off frequency will affect the
voltage sensitivity The dynamic range between each ASPAT is different because larger
size area will allow more power to go through the diode as a result of high current that
such a device can handle before reaching the saturation their lowest detectable is higher
Small diode size will detect lowest voltage but cannot handle high power On the other
hand a large diode size is able to receive high power however can only offer lower
voltage output Therefore there is a trade-off between small diode size and receiving
input power which will directly affect Tss and 1dB roll off Once again all the
100
1000
10000
90 95 100 105 110
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Frequency (GHz)
10times10microm^2
6times6microm^2
4times4microm^2
199
parameters obtained in this simulation are just estimation from the 10th
order polynomial
equation thus real ASPAT detector has to be fabricated for verification
The best device performance among all GaAsAlAs ASPAT diodes was obtained
with the 4times4microm2 mesa area size diode which was compared to other exiting millimetre
wave detector diode available in the literature Since the 100GHz is located in the W-
band spectrum frequency therefore the comparison will be performed in this frequency
band but with low input power The parameters for the-state-of-the-art zero bias
detectors are gathered in Table 64 below
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero bias detector
at W-band (75GHz-110GHz)
Device Size(microm2) Tss(dBm) βv (VW) Pin (dBm) f (GHz)
GaAsAlAs ASPAT 4times4 -68 2100 -25 100
GaAs SBD HSCH-
9161[157]
- -49 2200 94
HBD[158] 15x15 2540 -20 95
Planar SBD[159] - -68 2100 -25 100
Note that the ASPAT diode retains its favourable temperature stable characteristics
which are not the case for all the diodes used for comparison in Table 64
66 Conclusions
In this chapter all theory regarding RF detection using diodes ie parameters of
interest noise consideration etc have been discussed The aim to design and develop a
low cost reliable and sophisticated zero bias 100GHz detector circuit was achieved
through exploitation of a 4times4microm2 GaAsAlAs ASPAT diode The design was performed
with the aid of Keysight ADS modelling software utilizing harmonic balance simulation
The effect of load resistance junction resistor to the detector voltage sensitivity was also
discussed in details The 90KΩ Rj value and open circuit load resistance was chosen for
high sensitivity
200
A step by step design of a W-band ASPAT detector was presented The effect of
matching circuit was discussed in detail and where an unmatched sensitivity of 843VW
is obtained which then increases to 2100VW after matching Through RF
characterization simulation a detection at 100GHz (W-band) was successfully achieved
with a relatively large device mesa area (4times4microm2) at an input power of -25dBm
(8microWatt) leading to a 2100VW voltage sensitivity a -68dBm TSS and 55dBm dynamic
range All these values are comparable to others fabricated diodes in the literature
The zero bias ASPAT detectors based on the GaAsAlAs material system in this
work are still at an early stage of development a lot of work is still required to realize
high yielding integrated millimeter and sub-millimeter wave (MMIC) detector circuits
However as this work is on-going at Manchester it is expected that fabricated ASPAT
MMICs with even higher voltage sensitivity will be fabricated in the near future through
collaborating bodies involved in this research especially the University of Cambridge
and ICS Limited
201
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING
GAASALAS ASPAT DIODES
71 Introduction
Originally the key application for the ASPAT diode was for use as microwave and
millimetre wave detectors[18] This is due to the fact that such diode demonstrates
strong non-linearity low noise and high cut-off frequency features as described in the
previous chapters However these features are not only beneficial for detection purposes
but also allow them to be used and designed as microwave and millimetre wave sources
The only way to generateenhance continuous wave (CW) power using a non-linear
device is through frequency multiplication techniques It is known that the frequency
multiplier is the alternative approach (to 3 terminal transistors) using non-linear devices
that are used to generate high frequency low phase noise signals Any high quality low
frequency signal that goes through a frequency multiplier circuit can be generated to any
desired high output frequency[160] Therefore the main objective of this chapter is to
demonstrate the feasibility of the ASPAT diode as a compact source of microwave and
millimeter-wave receiver for imaging applications[161]
The study of the ASPAT diode as a power source begins with a brief explanation
of the importance of a frequency source and the lack of compact device and technologies
at high-frequency signals The state-of-the-art for frequency multiplier will also be
discussed In the next section (Section 74) the fundamentals of the frequency multiplier
architecture ie the principle of operation and appropriate devices will be presented
Since this is the first attempt at using GaAsAlAs ASPAT diodes a simple multiplier
circuit design and topology was built This will be discussed in detail in the subsequent
sections where simulation results are discussed The focus of the discussion will be to
demonstrate the possibility of a GaAsAlAs ASPAT diode functioning as a frequency
multiplier and comparison with other state-of-the-art varistor mode frequency
multipliers
202
72 Motivation and Background
Typically continuous wave (CW) sources generating below 100 GHz can be
obtained through oscillators amplifiers and pin diode comb generator Below 10THz
the sources can be made from RTD IMPATT diodes and Gunn oscillators and above 10
THz it is commonly done by photonic mixing quantum cascade laser (QCL) and gas
lasers [162] Both types of sources and their performance are plotted in Figure 71
However these conventional ways of generating millimetre and sub-millimetre waves
have their own limitations ie high cost complexity and sometimes requirement for
cryonic cooling The most effective way to tackle the limitations of conventional mm-
wave and THz sources is by implementing frequency multiplication technique using
solid state nonlinear diodes [163-165] such as SBD and ASPAT diodes
Figure 71 performance of state-of the-art millimetre wave source [166]
Twenty years ago there were only two types of diodes (SBD and P-N junction
diodes) often used for frequency multiplication To date besides the SBD there are
many types of diode that have been used as frequency multipliers These include the
high electron mobility varactor (HEMV) single barrier varactor (SBV) [167] and hetero-
structure barrier varactor (HBV) (270GHz with 90mW input power and Conversion
Efficiency of 72)[168 169] Other variants that have developed to enhance the
frequency multiplier performance of the classic SBD [170] include the Barrier-intrinsic-
203
n+ (BIN)diode and Barrier N-layer N+ (BNN) diode [171] Other diodes for use in such
applications are the planar doped barrier diode (PDB) Resonant tunnelling diode (RTD)
amp it families ie Quantum well diode (QWD) and step recovery diode which is a
modification of the P-N junction diode
Although three terminal devices ie FET GaAs MESFET and HEMT had
shown better performance and are capable of achieving greater efficiency and
bandwidth as well as having additional conversion gain features [160] two terminal
devices (ie varactor diodes) which are passive multiplier are still preferred This is due
to their simplicity and most importantly their ability to generate very little noise Among
these types of device technologies the SBD is preferable as it is mature and has been
shown to be very suitable for high-frequency applications [172 173]
The ASPAT diode is exploited to investigate the possibility and the feasibility of
generating microwave and millimetre-wave power through well-known frequency
multiplication methods The utilisation of the ASPAT in frequency multiplication will
also aid in generating local oscillator sources which are critical components in
heterodyne receivers The ASPAT diode will work in resistive I-V mode (varistor mode)
and has features to work also at zero bias condition thus offering low power handling
than traditional high-efficiency varactor diode since the varactor diode requires a large
reverse bias supply of several tens of volts
73 Frequency Multiplier Architecture the Basics
In principle a frequency multiplier is an electronic circuit that gives an output
frequency that is a multiple integer of its input frequency signal pumped from a local
oscillator as depicted in Figure 72 The ability to generate any desired multiple output
signals is realised by a nonlinear device ie diode or transistor Such devices though
also can give distortion or cause sudden change to the input frequency Additionally
these devices generate multiples of the input frequency (fout) The distortion of the
sinusoidal signal refers to an abruptsudden change versus amplitude or time which thus
generates higher frequency with lower amplitudes of the input signal Usually a
frequency multiplier circuit will include a bandpass filter to select the desired harmonic
204
frequencies and deselect undesired harmonic frequencies especially fundamental
harmonic at the output for further processing
Any non-linear device either in symmetricalantisymmetric current-voltage or
capacitance-voltage can be utilised to realise a frequency multiplier source [168 174]
Figure 73 describes the method where a nonlinear resistance is utilised to convert a
harmonic input signal into periodic output signal containing components at multiples of
the input frequency Both non-linear resistance and reactance characteristics can be
extended into power series methods
Figure 73 Principle of operation for frequency multiplier utilising a non-linear resistance [10]
The operating principle of the frequency multiplier is shown in Figure 73 where
the I-V curve converts a harmonic frequency input into a periodic frequency output
including components at multiples of the input frequency The non-linear I-V
characteristic can be explained in term of a power series at the operating fixed point of
bias voltage (VB) [174]
Frequency
Multiplier Circuit
finput
foutput
= nfinput
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
205
119868(119881119861 + ∆119881) = 1198860 + 1198861∆119881 + 1198862∆1198812 + 1198863∆1198813 helliphellip (71)
For a given input voltage as below
∆119881 = 119881119904 cos120596119878119905 (72)
The input signal harmonics will become
119868(119905) = 1198680 + 1198681 cos120596119904119905 + 1198682 cos 2120596119904119905 + 1198683 cos 3120596119904119905 (73)
Where t and ω are the time and angular frequency respectively based on equation (73)
the output contains both signal source and harmonics Therefore a complete frequency
multiplier circuit has to have non-linear device and filter to allow the selection of any
frequency components needed
731 Types of frequency multipliers
Frequency multipliers can be classified into passive and active multipliers This
classification is based on the ability of the frequency multiplier to yield any conversion
gainlosses The passive multiplier is the one that only produces conversion losses In
other words it can be described as a multiplier that generates an output power level
lower than the excitation input power and it is mostly dominated by passive nonlinear
devices ie Diodes On the other hand the active multipliers refer to a device that would
produce an output signal with a power level that is greater than the input signal power
This conversion of power is termed as conversion gain These types of multipliers attract
much attention as they do not only increase the frequency at the output but also the
signal power
Passive frequency multiplier can be formed by using diodes that are classified as
being of the varistor (non-linear I-V) or varactor (non-linear C-V) type [160 174] The
varistor type will influence the frequency multiplication with a non-linear resistance or
conductance (resistive diodes) and this results in a very large potential bandwidth at the
output but poor conversion efficiency The varactor diode type where the frequency
multiplications are affected by the non-linear capacitance (reactive diode) as their
reactive element typical result is high conversion efficiency A diode that is used in this
206
application must have strong nonlinearity stable electrical characteristic repeatable and
has fast enough response to an applied frequency Therefore multipliers are classified
into Doubler Tripler quintuple and so forth depending on the highest power of output
harmonic signal
In general all varactor type diodes with such characteristics will produce high
power at odd-order harmonic oscillation if any microwave signal is pumped into them
The benefit of having odd-order in multiplier design is that it reduces the complexity of
the overall circuit ie it eliminates even-order idler frequencies [175] The varactor type
diode had been shown by Manley-Rowe to a get maximum 100 conversion efficiency
for generating an ideal harmonic [176] compared to the varistor type where the
maximum efficiency achievable ideally is 1 1198992frasl where n is the multiplication factor
(output harmonics number) [174] In the case of power handling (input excitation power)
for multipliers varactor mode diode required greater power (several milli Watt) than the
varistor mode due to the fact that reverse applied voltages are very large (many tens of
volts) Therefore these types of frequency multipliers may not be suitable for the case of
high input power excitation There no report in the literature of varistor based
multipliers working with high power excitations
74 Parameters of interest for Frequency Multipliers
The simplest way to describe an equivalent circuit for a complete frequency
multiplier is by setting a Source impedance (ZS) at the input side and load impedance
(ZL) at the output side as depicted in Figure 74 below This circuit usually has the same
properties as described in the previous chapter and most of the others two ports
networks However in this case the purpose is different and is the conversion of a sine
wave signal source (Vs) with angular frequency ωs to an output signal with frequency
nωs where n is the multiplication integer or the order of multiplication
207
Figure 74 A standard system for two port frequency multiplier circuit
Referring to Figure 74 above there are few sets of parameters for the frequency
multiplier to be taken out and compared Examples are the conversion loss maximum
input signal power Impedance at source and load Bandwidth multiplication factor or
harmonic amp subharmonic content and noise conversion properties The conversion loss
(CL) is described by the ratio of available power at source (Ps) to the output harmonic
power delivered to load resistance (PL) and is normally expressed in dB It occurs due to
the nature of passive semiconductor diodes and the electronic circuit itself that are lossy
and dissipate energy On the other hand the conversion efficiency (ηn) is a ratio of the
output power at load (PL) to the available power at the input (Ps) This is often expressed
in percentage () The conversion efficiency can be determined as
120578 =
119875119878
119875119871
(74)
while the conversion loss is expressed as[174]
119871119899[119889119861] = 10 log
119875119904
119875119871= 10 log (
|1198811199042|
4 119877119890 |119885119904||1198681198712|119877119890|119885119871|
) (75)
Where Vs is the input voltage and IL is the output current amplitude Besides this the
conversion efficiency is often referred to as the inverted value of the Ln In designing a
frequency multiplier it is crucial to minimise the conversion loss and maximise the
conversion efficiency value
To achieve a perfect multiplier with minimum conversion loss the impedance of
source and load must be at an optimum level This implies that the source impedance
Frequency
Multiplier Z
L
Zout
Z
in
V
Z
SWR Г
208
(Zs) must be very close to the complex conjugate of the multiplier input impedance
(Zin) hence minimum reflection loss will occur at the input side This can be realised by
introducing an impedance matching circuit between the diode and source The power
transfer between the source and the multiplier is quantitatively described by the value of
the multiplier input reflection coefficient (Ѓ) with source Zs assumed to represent a
reference impedance This specification also can be explained in the standing wave ratio
(SWR) Both relationships are described below respectively [174]
Γ =
119885119894119899 minus 119885119904lowast
119885119894119899 + 119885119904
(76)
119878119882119877 =
1 + |Γ|
1 minus |Γ|
(77)
Where the asterisk () represents the complex conjugate of the Zs impedance
On the other hand the situation of the load impedance is different when a standard
or an optimum value is provided by the designer This will either increase the conversion
loss or decrease the output power Thus one has to keep in mind that frequency
multipliers are non-linear devices and power transfer condition both at the input and the
output depend on each other and the input signal level[174]
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler
In this work a similar ASPAT diode (4times4microm2) to that in designing millimetre
wave detector in the previous chapter is used The main objective of designing the
frequency multiplier circuit was first to investigate the performance of the ASPAT
diode as a microwave or millimetre wave signal source A design is deemed successful
when the diode physical parameters are optimised and the suitable impedance matching
network is produced for each desired harmonic as well as maximising the output power
These goals however are hard to achieve when a higher frequency operation is targeted
for use
There are many types of multiplier circuit topologies that can be implemented
using GaAsAlAs ASPAT diode in varistor mode to achieve high order of multiplication
209
Examples are single diode multiplier series or parallel connected diode multiplier anti-
parallel amp anti-series connection diode pair multiplier anti-parallel-series connected
diode multiplier and bridge frequency multiplier as well as nonlinear transmission line
frequency multiplier [174] Before designing a circuit there is one most important
consideration to make Prior to choosing any mentioned circuits to be used for frequency
doubler the design considerations are made based on the capability of ASPAT diode to
receive an optimum amount of input excitation RF power From the discussions in
Chapter 6 the ASPAT diode will reach saturation level (linear regime) at power ~
-10dBm for a device size of 4x4microm2 Once the optimum input power was confirmed the
circuit topology was carefully chosen to balance between the requirements of the
ASPAT to work at high frequencies ie low Rs and Cj amp high diode cut-off frequency
as well as the desired output signal frequency that needs to be produced
To realise the first attempt of an ASPAT diode as a signal source a simple circuit
topology of a frequency doubler was deployed as depicted in Figure 75 below The
frequency doubler circuit consists of a voltage source (can be power source) input
filtering with matching network ASPAT diode output filtering with matching network
and load impedance (ZL)
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode
In order to investigate the doubler performance the Keysight ADS simulation
tool and similar procedure to obtain accurate ASPAT model using a 10th
order
polynomial equation as in Section 65 was used The circuit in Figure 75 is translated
into ADS format as illustrated in Figure 76 Once the circuit was constructed the
analysis was performed using the Harmonics Balance (HB) simulator The circuit
requirements are matched terminations at the input and output frequencies open
Input Filtering
and matching network
Output Filtering
and matching network
Zs
Vs
ZL
Pin
fin
Pout
nfout
210
circuited terminations at the higher harmonics and optimum reactive terminations (an
inductance which resonates with the junction capacitance) at the output frequencies
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool
The circuit in Figure 76 is the simplest way of constructing a frequency doubler
circuit which consists of the signal source (P_1Tone) input matching circuit (Stubs)
filter (Short stub) ASPAT diode low pass filter output matching circuit(Stubs) and ZL
(load resistance) The utilisation of the stubs is an ideal case of simulation since in the
real fabrication stubs are normally formed in large sizes Therefore a proper design such
as using CPW instead of stubs is essential in real fabrication
Again this simulation works for this particular circuit in this chapter as all the diode
parameters were extracted from on-wafer one port S-Parameter measurement described
in chapter 5 To apply them in such two ports applications may not very accurate
however it still provides adequate parameters to build and design particular frequency
multipliers but not in general applications These simulations and results are adequate for
high frequency applications due to the fact that the actual RF measurements on the
diodes were carried out up to 40GHz and the target operating frequency in this multiplier
design does not exceed 40GHz
Since the on-wafer measurement that were carried out were limited to one port
characterization applying them to two port network applications may have extra
consequences which are unknown Therefore actual MMIC frequency multiplier is
needed to be built and test to validate this work
Input Matching
Output Matching
211
To find the optimum output power initial simulation without matching circuit
was performed This simulation was run by varying the input power from -35dBm to
20dBm but fixing the input frequency at 20GHz As can be seen in Figure 77 the lowest
point in the conversion loss (CL) and the highest point of the conversion efficiency (CE)
are obtained from an input power of -1dBm However this amount of input power is too
high for the ASPAT diode The lowest CL at -1dBm may not be accurate since it was
applied without matching Note that it is difficult to achieve a matching between source
impedance and load impedance when varying the input power Therefore a lower input
power of -10dBm is chosen for this frequency doubler operation Figure 77 shows the
Conversion Loss and Conversion Efficiency as a function of the available power of the
given input source
Figure 77 Conversion loss and conversion efficiency as a function of input power
The circuit in Figure 76 works with a -10dBm input power and 20GHz centre
frequency input signal is pumped from the power source (P1_tone) to the ASPAT diode
and distortionabrupt change of input waveform occurs at the fundamental frequency (f0
in this case 20GHz) Such abrupt change produces harmonics and these harmonics can
be classified into desired frequency component by placing two-quarter wavelength (λ4)
stubs (90˚) at both sides of the ASPAT diode At the input side of the diode short circuit
stubs are utilised to permit the f0 tone to reach the ASPAT diode and block the second
harmonics (2f0 in this case 40GHz) back to the input side and pushes it towards the
load resistance On the contrary at the output side of the diode the open circuit stubs are
used to ldquoopen circuitrdquo the 2f0 signals while ldquoshort circuitrdquo the f0 component Thus 2f0
212
signal will not be affected due to the open circuit stubs being half wave (λ2) long The
function of both stubs is basically to isolate the input and output signal from mixing each
other Therefore the design of input and output matching circuit can be achieved easily
The input matching circuit was designed based on the mentioned input frequency
(f0=20GHz) for an available input power (Ps=-10dBm) which is set up at the power
source by using two stubs with the same configuration as used in Chapter 6 Such
configuration is purposely deployed to increase the 50Ω coming from the P1_tone
source impedance to the conjugate thus reducing the reflection coefficient to the
ASPAT diode From the simulation without matching the input impedance to the diode
is 551Ω in magnitude for an available input power of -10dBm
On the output side of the diode output matching circuit is available to transform the 50Ω
port impedance in the optimum load impedance which provides minimum conversion
loss for the ASPAT diode The output matching circuit is designed based on expected
output frequency which is in this case 2f0 =40GHz Other than this optimum
impedance between load impedance and ASPAT will not be achieved thus resulting in
higher conversion loss
To ensure the proposed circuit is valid and suitable for the specific ASPAT diode
mesa size the response of conversion loss and efficiency are plotted as a function of
output frequency from 20GHz to 100GHz The results of both conversions are illustrated
in Figure 78
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
213
As can be seen in Figure 78 the conversion loss is obtained at the lowest point where
the output frequency is needed Meanwhile the conversion efficiency is maximum at the
same output frequency Therefore this indicates that the first attempt of an ASPAT
Doubler frequency source works well However the values obtained for Ln from this
simulation is 28dB which is rather high On the contrary the η achieved in this study is
very low with a value less than 1
Since the ASPAT is in varistor mode with no bias applied the conversion
efficiency is expected to be low due to resistive losses Another factor that may
contribute to lower η is the diode model itself as it is taken from a 10th
order polynomial
equation not from a diode model provided in the ADS software tools Thus some
properties of such tunnelling diode may not be included Hence it is necessary in due
course to fabricate and build such a compact frequency doubler in the future to verify
the simulation results
From the simulation point of view the less than 1 Conversion Efficiency
obtained is still good enough for a first attempt at a frequency doubler which utilises the
new ASPAT tunnelling diode The frequency doubler obtained from this work is suitable
for use in zero bias varistor modes for low power application The varistor mode doubler
performances from this simulation work are gathered and compared to other in the
literature as summarized in Table 71 below where fout is 40GHz η is 015 Ln is 28dB
and Pi is -10dBm
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art multiplier
diode
Device fout (GHz) η() Ln(dB) Pi (dBm)
ASPAT 40 015 28 -10
SBD (Si)[177] 104 2 134 -10
SBD (GaAs)[178] 13 2 137 -16
214
The performance of the 2040GHz is compared to the literature based on their input
power below -8dBm since the ASPAT is only capable of working at low power To the
best of the author knowledge very few diodes operating in varistor mode at low power
excitation can be found in the field of research and industry Therefore this 2040GHz
ASPAT Doubler might a first for tunnel diodes if it can be fabricated and test at Ka band
and above
76 Conclusions
In this chapter another alternative application based on non-linear features of
GaAsAlAs ASPAT has been presented The simulation of a frequency multiplier
(doubler) was carried out utilizing the 4times4microm2 size ASPAT diode The theory and the
ability of the ASPAT diode to operate as a frequency source were explained in detail
A unique varistor mode frequency multiplier circuit topology for the 2040GHz
ASPAT doubler has been demonstrated and briefly discussed The details and step by
step simulation technique utilizing harmonic balance from Keysight ADS has been
presented Even though the conversion efficiency is very small at 015 and large
conversion loss of 28dB there is still space for improvement in term of design ie
different circuit topology optimized input and output matching circuit etc This design
can be a good reference for a doubler operating at very low power but produce high
frequencies in Ka band
215
8 CONCLUSION AND FUTURE WORK
81 Conclusion
The main focus of this research was the development of a new tunneling diode
namely the asymmetrical spacer layer tunnel (ASPAT) diode for process repeatability
manufacturability and reproducibility The broad study undertaken was to improve the
microwave performance technology by introducing a new type of tunneling diode
For years the asymmetrical spacer layer tunnel diode was unable to be manufactured
due to the high sensitivity of the tunneling current to the barrier thickness This changed
dramatically when the MBE method was carefully optimized to precisely control the
growth to sub-monolayer precisions When stability repeatability and reproducibility in
the epitaxial growth was achieved the next step was to qualify the fabrication process of
the diodes themselves thus ensuring high performance device can be delivered to the
market
For this purpose GaAsAlAs ASPAT diodes made of two different types of
substrates were grown The first batch was grown in the Riber V100HU SSMBE and
used doped substrates Samples XMBE307 and XMBE368 were successfully grown
and fabricated from that batch The DC characterization obtained from measurement
proved that this first batch had fully functional reproducible and manufacturable
devices Later a second batch using semi insulating substrates improvement in spacer
layer and doping concentration were grown This set of samples (9 x 2rdquo wafers grown
simultaneously) and denoted as XMBE304 also showed fully functional DC
characteristic and was used for RF characterization and detector integrated circuits
The conventional GaAsAlAs ASPAT diode structures grown on doped
substrates and developed previously in our lab were not suitable for high frequency RF
characterizations Therefore a major contribution of this work was to develop a new
fabrication technique for a new GaAsAlAs ASPAT structure using semi insulating
substrates to achieve repeatability manufacturability and reproducibility in term of
process flow DC characteristics and ultimately RF characteristics Apart from the
enhancement of the epitaxial layer the other important contribution of this research was
216
the optimization of the small 4times4microm2 emitter size by incorporating both vertical and
lateral structure based purely on low cost I-line optical lithography
To obtain a repeatable and manufacturable fabrication process of lateral
GaAsAlAs ASPAT structures the key issue was to solve the over etching of the
effective mesa area when qualifying the Air Bridge technique This issue caused all
semiconductors under the metal contact to be completely lost thus leaving the metal
contact hanging without connection to any bond pad area However the developments of
the Dielectric Bridge technique realized the true performance of the GaAsAlAs ASPAT
diode structures The samplersquos surface cleanliness as well as DC and RF performance
showed significant improvement when using Si3N4 as a dielectric layer Due to the
highly isotropic etching profile and thicker GaAs layer in XMBE304 samples and
although the smallest emitter size designed on the mask was 2times2microm2 only 4times4microm
2 were
reproducible and showed good uniformity in I-V characteristics
Upon successful optimization in the fabrication process flow of the small emitter
size diodes (4times4microm2 6times6microm
2 and 10times10microm
2) a good uniformity of better than 91
was obtained for DC measurement results within a tile containing over 1000 devices
This confirmed that the lateral GaAsAlAs ASPAT diode structure can only be realized
through the Dielectric Bridge technique These devices were further characterized with
S-parameter measurements and their intrinsic and extrinsic parameter values and
junction capacitances series resistances and junction resistances were extracted leading
to intrinsic cut-off frequencies of 600GHz 429GHz and 100GHz for the three device
sizes respectively
Temperature dependence measurements and simulations were also carried out in
order to confirm that the ASPAT diodersquos characteristics were temperature insensitive
showing less than 5 change in current at both extremes of temperatures 77K to 400K
By comparison the SBD I-V characteristics variations with temperature span orders of
magnitude Physical modelling agreed very well with measured data confirming good
and validated models that can also describe temperature effects
For the realization of the integrated ASPAT millimeter wave detector empirical
modelling using ADS simulation tools was carried out This was performed to predict
the detector performance at 100GHz to comply with the initial objective to develop a
217
millimeter wave detector circuit The simulations using the 4times4microm2 diode models led to
a successful 100GHz circuit design able to detect 100GHz incoming frequency with
2100VW voltage sensitivity
The first ever GaAsAlAs ASPAT diode frequency multiplier design was also
attempted A reasonably good result was obtained for a 20 to 40GHz frequency doubler
operating in varistor mode However the conversion efficiency obtained was less than
1 Further research on this is required to improve the efficiency by using other circuit
topology ie using a balun or other Co-planar waveguides Ultimately fabricating and
testing the actual multiplier circuits are essential to validate the simulation data
82 Future Work
This work has provided a foundation for a reproducible and repeatable GaAsAlAs
ASPAT (SI substrate) wafer fabrication process and recommendations for design and
simulation of ASPAT diode MMIC detectors and frequency source has also been
provided However the GaAsAlAs ASPAT diodes still remain immature and there are
many ways to improve its DC and RF performances both experimentally and in
simulations which will directly affect the detection performances
In term of fabrication process smaller size diodes ie submicron level can be
achieved using dry etching technique with proper calibration For wet etch technique the
etched profile still can be improved by thinning the doped layers so that etching time
will be reduced and hence dimensions down to 2times2microm2 or even 15times15microm
2 can be
reproducibly made
For simulations advanced AC and RF modelling utilizing physical device
simulation available software (SILVACO) must be include in future research hence
holistic study can be conducted to improve the understanding of the ASPAT
For MMIC detector and multiplier design it is vital to produce actual MMIC
devices so that the simulation results can be validated Ultimately tested devices with
good performances can be realized and manufactured
218
REFERENCES
1 Laeri F U Simon and M Wark Host-Guest-Systems Based on Nanoporous
Crystals 2006 John Wiley amp Sons
2 Łukasiak L and A Jakubowski History of semiconductors Journal of
Telecommunications and information technology 2010 p 3-9
3 Song H-J and T Nagatsuma Present and future of terahertz communications
IEEE Transactions on Terahertz Science and Technology 2011 1(1) p 256-
263
4 Hu B and M Nuss Imaging with terahertz waves Optics letters 1995 20(16)
p 1716-1718
5 Smith PR DH Auston and MC Nuss Subpicosecond photoconducting
dipole antennas IEEE Journal of Quantum Electronics 1988 24(2) p 255-260
6 Nagatsuma T Terahertz technologies present and future IEICE Electronics
Express 2011 8(14) p 1127-1142
7 Kumar S et al A 18-THz quantum cascade laser operating significantly above
the temperature of [planck][omega]kB Nature Physics 2011 7(2) p 166-171
8 Phillips T and D Woody Millimeter-and submillimeter-wave receivers Annual
Review of Astronomy and Astrophysics 1982 20(1) p 285-321
9 Whitmer HCTaCA Crystal Rectifiers McGraw-Hill book Company
London 1948
10 Young D and J Irvin Millimeter frequency conversion using Au-n-type GaAs
Schottky barrier epitaxial diodes with a novel contacting technique Proceedings
of the Ieee 1965 53(12) p 2130-2131
11 Liu L et al A broadband quasi-optical terahertz detector utilizing a zero bias
Schottky diode IEEE microwave and wireless components letters 2010 20(9) p
504-506
12 Sankaran S Schottky barrier diodes for millimeter wave detection in a foundry
CMOS process IEEE Electron Device Letters 2005 26(7) p 492-494
13 Chattopadhyay G Submillimeter-wave coherent and incoherent sensors for
space applications in Sensors 2008 Springer p 387-414
14 Anand Y and WJ Moroney Microwave mixer and detector diodes
Proceedings of the Ieee 1971 59(8) p 1182-1190
15 Syme RT Microwave Detection Using GaasAlas Tunnel Structures Gec
Journal of Research 1993 11(1) p 12-23
16 Syme RT et al Asymmetric superlattices for microwave detection in Physical
Concepts of Materials for Novel Optoelectronic Device Applications 1991
International Society for Optics and Photonics
17 Missous M MJ Kelly and J Sexton Extremely uniform tunnel barriers for
low-cost device manufacture IEEE Electron Device Letters 2015 36(6) p 543-
545
18 Syme RT et al Novel GaAsAlAs tunnel structures as microwave detectors in
Semiconductors 92 1992 International Society for Optics and Photonics
19 Schwierz F and JJ Liou Semiconductor devices for RF applications evolution
and current status Microelectronics Reliability 2001 41(2) p 145-168
219
20 HayasHi H Development of Compound Semiconductor DevicesmdashIn Search of
Immense Possibilitiesmdash SEI TECHNICAL REVIEW 2011(72) p 5
21 Mead C Schottky barrier gate field effect transistor Proceedings of the Ieee
1966 54(2) p 307-308
22 Hooper W and W Lehrer An epitaxial GaAs field-effect transistor Proceedings
of the Ieee 1967 55(7) p 1237-1238
23 Drangeid K R Sommerhalder and W Walter High-speed gallium-arsenide
Schottky-barrier field-effect transistors Electronics Letters 1970 6(8) p 228-
229
24 Pillarisetty R Academic and industry research progress in germanium
nanodevices Nature 2011 479(7373) p 324-328
25 Oxley TH 50 years development of the microwave mixer for heterodyne
reception IEEE transactions on microwave theory and techniques 2002 50(3)
p 867-876
26 Baca AG and CI Ashby Fabrication of GaAs devices 2005 IET
27 Cho AY and J Arthur Molecular beam epitaxy Progress in solid state
chemistry 1975 10 p 157-191
28 Cho A Growth of IIIndashV semiconductors by molecular beam epitaxy and their
properties Thin Solid Films 1983 100(4) p 291-317
29 Kiehl RA and TG Sollner High speed heterostructure devices 1994
Academic Press
30 Feiginov M et al Resonant-tunnelling-diode oscillators operating at
frequencies above 11 THz Applied Physics Letters 2011 99(23) p 233506
31 Chang LL L Esaki and R Tsu Resonant tunneling in semiconductor double
barriers Applied Physics Letters 1974 24(12) p 593-595
32 Kasjoo SR Novel Electronic Nanodevices Operating in the Terahertz Region
2012
33 Kanaya H et al Structure dependence of oscillation characteristics of
resonant-tunneling-diode terahertz oscillators associated with intrinsic and
extrinsic delay times Japanese Journal of Applied Physics 2015 54(9) p
094103
34 Chattopadhyay G Technology capabilities and performance of low power
terahertz sources IEEE Transactions on Terahertz Science and Technology
2011 1(1) p 33-53
35 Betz A and R Boreiko A practical Schottky mixer for 5 THz in Proceedings of
the 7th International Symposium on Space Terahertz Technology 1996
36 Yu D et al Ultra high-speed 025-spl mum emitter InP-InGaAs SHBTs with
fsub maxof 687 GHz in Electron Devices Meeting 2004 IEDM Technical
Digest IEEE International 2004 IEEE
37 Das MB Optoelectronic detectors and receivers speed and sensitivity limits in
Optoelectronic and Microelectronic Materials Devices 1998 Proceedings 1998
Conference on 1999 IEEE
38 Rodwell MJ et al Submicron scaling of HBTs IEEE Transactions on Electron
Devices 2001 48(11) p 2606-2624
220
39 Bouloukou A and S Missous Novel High-breakdown Low-noise InGaAs-
InA1As Transistors for Radio Astronomy Applications 2006 University of
Manchester
40 Bean J Materials and technologies 1990 John Wiley amp Sons New York p
13
41 Swaminathan V and A Macrander Materials aspects of GaAs and InP based
structures 1991 Prentice-Hall Inc
42 Vurgaftman I J Meyer and L Ram-Mohan Band parameters for IIIndashV
compound semiconductors and their alloys Journal of applied physics 2001
89(11) p 5815-5875
43 Dingle R W Wiegmann and CH Henry Quantum states of confined carriers
in very thin Al x Ga 1minus x As-GaAs-Al x Ga 1minus x As heterostructures Physical
Review Letters 1974 33(14) p 827
44 Sze SM and KK Ng Physics of semiconductor devices 2006 John wiley amp
sons
45 Tyagi MS Introduction to semiconductor materials and devices 2008 John
Wiley amp Sons
46 Schubert E Delta doping of IIIndashV compound semiconductors Fundamentals
and device applications Journal of Vacuum Science amp Technology A Vacuum
Surfaces and Films 1990 8(3) p 2980-2996
47 Rhoderick EH Metal-semiconductor contacts IEE Proceedings I-Solid-State
and Electron Devices 1982 129(1) p 1
48 Piotrowska A A Guivarch and G Pelous Ohmic contacts to IIIndashV compound
semiconductors A review of fabrication techniques Solid-State Electronics
1983 26(3) p 179-197
49 Rideout V A review of the theory and technology for ohmic contacts to group
IIIndashV compound semiconductors Solid-State Electronics 1975 18(6) p 541-
550
50 Baca A et al A survey of ohmic contacts to III-V compound semiconductors
Thin Solid Films 1997 308 p 599-606
51 Higman T et al Structural analysis of AundashNindashGe and AundashAgndashGe alloyed
ohmic contacts on modulation‐doped AlGaAsndashGaAs heterostructures Journal of
applied physics 1986 60(2) p 677-680
52 Chen KJ et al High-performance enhancement-mode InAlAsInGaAs HEMTs
using non-alloyed ohmic contact and Pt-based buried-gate in Indium Phosphide
and Related Materials 1995 Conference Proceedings Seventh International
Conference on 1995 IEEE
53 Berlin L The man behind the microchip Robert Noyce and the invention of
Silicon Valley 2005 Oxford University Press
54 Goodhue W et al Large room‐temperature effects from resonant tunneling
through AlAs barriers Applied Physics Letters 1986 49(17) p 1086-1088
55 Kerr A and Y Anand Schottky diode MM detectors with improved sensitivity
and dynamic range Microwave Journal 1981 24 p 67-71
56 Davies R Simulations of the current-voltage characteristics of semiconductor
tunnel structures Gec Journal of Research 1987 5(2) p 65-75
221
57 Kelly M Tunnel structures and devices over the coming decade Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2291-2293
58 Wilkinson V and M Kelly Manufacturability of quantum semiconductor
devices in High Performance Electron Devices for Microwave and
Optoelectronic Applications 1995 EDMO IEEE 1995 Workshop on 1995
IEEE
59 Wilkinson V M Kelly and M Carr Tunnel devices are not yet
manufacturable Semiconductor Science and Technology 1997 12(1) p 91
60 Eaves L and MJ Kelly The current status of semiconductor tunnelling devices
Philos trans of the Roy soc of London Ser A Math phys and eng sciences
1996 354(1717)
61 Billen K V Wilkinson and M Kelly Manufacturability of heterojunction
tunnel devices further progress Semiconductor Science and Technology 1997
12(7) p 894
62 Kelly M The engineering of quantumndashdot devices Philosophical Transactions
of the Royal Society of London A Mathematical Physical and Engineering
Sciences 2003 361(1803) p 393-401
63 Kelly M New statistical analysis of tunnel diode barriers Semiconductor
Science and Technology 2000 15(1) p 79
64 Hayden R et al Ex situ re-calibration method for low-cost precision epitaxial
growth of heterostructure devices Semiconductor Science and Technology
2002 17(2) p 135
65 Dasmahapatra P et al Thickness control of molecular beam epitaxy grown
layers at the 001ndash01 monolayer level Semiconductor Science and Technology
2012 27(8) p 085007
66 Hayden R M Missous and M Kelly Precision growth for the manufacture of
semiconductor heterostructure devices Semiconductor Science and Technology
2001 16(8) p 676
67 Shao C et al Highly reproducible tunnel currents in MBE-grown
semiconductor multilayers Electronics Letters 2012 48(13) p 792-794
68 Abdullah MR et al GaAsAlAs tunnelling structure Temperature dependence
of ASPAT detectors in Millimeter Waves and THz Technology Workshop
(UCMMT) 2015 8th UK Europe China 2015 IEEE
69 Ariffin KZ et al Asymmetric Spacer Layer Tunnel In0 18Ga0 82AsAlAs
(ASPAT) Diode using double quantum wells for dual functions Detection and
oscillation in Millimeter Waves and THz Technology Workshop (UCMMT)
2015 8th UK Europe China 2015 IEEE
70 Liboff RL Introductory quantum mechanics 2003 Addison-Wesley
71 Esaki L Discovery of the tunnel diode IEEE Transactions on Electron Devices
1976 23(7) p 644-647
72 Landau LD LEM Quantum Mechanics Non-relativistic Theory Pergamon 3
73 Landau LD et al Quantum Mechanics Non‐Relativistic Theory Vol 3 of
Course of Theoretical Physics 1958 AIP
222
74 Syme R Tunnelling devices as microwave mixers and detectors Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2351-2364
75 Syme R et al Tunnel diode with asymmetric spacer layers for use as
microwave detector Electronics Letters 1991 27(23) p 2192-2194
76 Brown E W Goodhue and T Sollner Fundamental oscillations up to 200 GHz
in resonant tunneling diodes and new estimates of their maximum oscillation
frequency from stationary‐state tunneling theory Journal of applied physics
1988 64(3) p 1519-1529
77 Reddy M Schottky-collector resonant tunnel diodes for sub-millimeter-wave
applications 1997 University of California Santa Barbara
78 Cox R and H Strack Ohmic contacts for GaAs devices Solid-State Electronics
1967 10(12) p 1213IN71215-1214IN81218
79 Valdes LB Resistivity measurements on germanium for transistors
Proceedings of the IRE 1954 42(2) p 420-427
80 Schroder DK Semiconductor material and device characterization 2006 John
Wiley amp Sons
81 Klootwijk J and C Timmering Merits and Limitations of Circular TLM
structures for contact resistance determination for novel 111-V HBTs Proc
fEEE 2004
82 Marlow GS and MB Das The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance Solid-State
Electronics 1982 25(2) p 91-94
83 Murrmann H and D Widmann Current crowding on metal contacts to planar
devices IEEE Transactions on Electron Devices 1969 16(12) p 1022-1024
84 Berger H Models for contacts to planar devices Solid-State Electronics 1972
15(2) p 145-158
85 Reeves G and H Harrison Obtaining the specific contact resistance from
transmission line model measurements IEEE Electron Device Letters 1982
3(5) p 111-113
86 Shur MS GaAs devices and circuits 2013 Springer Science amp Business
Media
87 Popescu D and B Odbert The Advantages Of Remote Labs In Engineering
Education Educatorrsquos Corner-Agilent Technologies-application note 2011 p
11
88 DataSheet Karl Suss- PM5 Probe System Datasheet 2013
89 Keysight IC-CAP Device Modeling Software 2016 Available from
httpwwwkeysightcomenpc-1297149ic-cap-device-modeling-software-
measurement-control-and-parameter-extractioncc=USamplc=eng
90 DataSheet Anritsu 37369A Vector Network Analyzer Datasheet 2016 Available
from httpwwwtestequipmenthqcomdatasheetsANRITSU-37397D-
Datasheetpdf
91 Packard H HP 4142B Modular DC SourceManual Operation Manual 1992
Available from httpcpliteratureagilentcomlitwebpdf04142-90010pdf
223
92 Microtech C Cascade Microtech- Wincal High Performence RF calaibration
Software (Official Website) 2016 Available from
httpswwwcascademicrotechcom
93 Singh J Electronic and optoelectronic properties of semiconductor structures
2007 Cambridge University Press
94 Whyte W Cleanroom design 1999 Wiley Online Library
95 Vieu C et al Electron beam lithography resolution limits and applications
Applied Surface Science 2000 164(1) p 111-117
96 La Fontaine B Lasers and Moorersquos law SPIE Professional October 2010 p
20
97 Madou MJ Fundamentals of microfabrication the science of miniaturization
2002 CRC press
98 Serway R Physics for Scientists and Engineers 1996 Saunders Publ
Philadelphia
99 Jalali B and S Pearton InP HBTs growth processing and applications 1995
Artech House Publishers
100 Shih YC et al Effects of interfacial microstructure on uniformity and thermal
stability of AuNiGe ohmic contact to n‐type GaAs Journal of applied physics
1987 62(2) p 582-590
101 Zawawi M Advanced In0 8Ga0 2AsAlAs Resonant Tunneling Diodes
forApplications in Integrated mm-waves MMIC Oscillators 2015
102 Zawawi MAM et al Fabrication of Submicrometer InGaAsAlAs Resonant
Tunneling Diode Using a Trilayer Soft Reflow Technique With Excellent
Scalability IEEE Transactions on Electron Devices 2014 61(7) p 2338-2342
103 Silvaco I ATLAS Users Manual Device Simulation Software 2010 Santa
Clara CA
104 Kyono C et al Dependence of apparent barrier height on barrier thickness for
perpendicular transport in AlAsGaAs single‐barrier structures grown by
molecular beam epitaxy Applied Physics Letters 1989 54(6) p 549-551
105 Yang K JR East and GI Haddad Numerical modeling of abrupt
heterojunctions using a thermionic-field emission boundary condition Solid-
State Electronics 1993 36(3) p 321-330
106 Varshni YP Temperature dependence of the energy gap in semiconductors
Physica 1967 34(1) p 149-154
107 Handbook LLM Precision DC Current Voltage and Resistance
Measurements Keithley Instruments Inc[online] 6th revision Ohio 2004
108 Lipsky SE Microwave passive direction finding 2004 SciTech Publishing
109 Howell CM and SJ Parisi Principles Applications and Selection of Receiving
Diodes MACOM Semiconductor Products Division Application note AG314
110 Schulman J D Chow and D Jang InGaAs zero bias backward diodes for
millimeter wave direct detection IEEE Electron Device Letters 2001 22(5) p
200-202
111 Zhang Z et al Sub-Micron Area Heterojunction Backward Diode Millimeter-
Wave Detectors With 018$ rm pWHz^12 $ Noise Equivalent Power IEEE
microwave and wireless components letters 2011 21(5) p 267-269
224
112 Jin N et al High sensitivity Si-based backward diodes for zero-biased square-
law detection and the effect of post-growth annealing on performance IEEE
Electron Device Letters 2005 26(8) p 575-578
113 Shashkin VI et al Millimeter-wave detectors based on antenna-coupled low-
barrier Schottky diodes International journal of infrared and millimeter waves
2007 28(11) p 945-952
114 Zhao P et al GaN Heterostructure Barrier Diodes Exploiting Polarization-
Induced $delta $-Doping IEEE Electron Device Letters 2014 35(6) p 615-
617
115 Pozar DM Microwave engineering 2009 John Wiley amp Sons
116 Koolen M J Geelen and M Versleijen An improved de-embedding technique
for on-wafer high-frequency characterization in Bipolar Circuits and
Technology Meeting 1991 Proceedings of the 1991 1991 IEEE
117 Cao M et al RF characteristics uniformity of GaAsAlAs tunnel diodes in
Infrared Millimeter and Terahertz waves (IRMMW-THz) 2016 41st
International Conference on 2016 IEEE
118 Gao J RF and microwave modeling and measurement techniques for field effect
transistors 2010 SciTec
119 Ren T et al A 340-400 GHz Zero-Biased Waveguide Detector Using an Self-
Consistent Method to Extract the Parameters of Schottky Barrier Diode Applied
Computational Electromagnetics Society Journal 2015 30(12)
120 Fobelets K et al High‐frequency capacitances in resonant interband tunneling
diodes Applied Physics Letters 1994 64(19) p 2523-2525
121 Diebold S et al Modeling and Simulation of Terahertz Resonant Tunneling
Diode-Based Circuits IEEE Transactions on Terahertz Science and Technology
2016 6(5) p 716-723
122 Yong Z et al Design of a 220 GHz frequency tripler based on EM model of
Schottky diodes JOURNAL OF INFRARED AND MILLIMETER WAVES
2014 33(4) p 405-411
123 Louhi JT and AV Raisanen On the modeling and optimization of Schottky
varactor frequency multipliers at submillimeter wavelengths IEEE transactions
on microwave theory and techniques 1995 43(4) p 922-926
124 Guo J Z Zhang and C Qian Modeling of commercial millimeter wave
Schottky diodes in Microwave and Millimeter Wave Technology (ICMMT) 2016
IEEE International Conference on 2016 IEEE
125 Schneider M Metal-semiconductor junctions as frequency converters Infrared
and Millimeter Waves 1982 6 p 209
126 Muth C et al Advanced technology microwave sounder on NPOESS and NPP
in Geoscience and Remote Sensing Symposium 2004 IGARSS04 Proceedings
2004 IEEE International 2004 IEEE
127 Putley E Thermal detectors in Optical and Infrared Detectors 1977 Springer
p 71-100
128 Martin DH Spectroscopic techniques for far infra-red submillimetre and
millimetre waves in Spectroscopic Techniques for Far Infra-red Submillimetre
and Millimetre Waves 1967
225
129 Lucas W Tangential sensitivity of a detector video system with RF
preamplification in Proceedings of the Institution of Electrical Engineers 1966
IET
130 Balocco C et al Low-frequency noise of unipolar nanorectifiers Applied
Physics Letters 2011 99(11) p 113511
131 Benford D T Hunter and TG Phillips Noise equivalent power of background
limited thermal detectors at submillimeter wavelengths International journal of
infrared and millimeter waves 1998 19(7) p 931-938
132 Papoušek D Vibration-rotational Spectroscopy and Molecular Dynamics
Advances in Quantum Chemical and Spectroscopical Studies of Molecular
Structures and Dynamics Vol 9 1997 World Scientific
133 Nyquist H Thermal agitation of electric charge in conductors Physical review
1928 32(1) p 110
134 Turner CS Johnson-Nyquist Noise url httpwww claysturner
comdspJohnson-NyquistNoise pdf(Letzter Abruf Juli 2012)
135 Voss RF 1f (flicker) noise A brief review in 33rd Annual Symposium on
Frequency Control 1979 1979 IEEE
136 McWhorter AL 1f noise and related surface effects in germanium 1955
137 Hooge FN 1ƒ noise is no surface effect Physics letters A 1969 29(3) p 139-
140
138 Van der Ziel A Noise Sources characterization measurement Prentice-Hall
Information and System Sciences Series Englewood Cliffs Prentice-Hall 1970
1970
139 Hooge F 1f noise sources IEEE Transactions on Electron Devices 1994
41(11) p 1926-1935
140 Der Ziel A Theory of shot noise in junction diodes and junction transistors
Proceedings of the IRE 1955 43(11) p 1639-1646
141 Schottky W Small-shot effect and flicker effect Physical review 1926 28(1)
p 74
142 Cowley A and H Sorensen Quantitative comparison of solid-state microwave
detectors IEEE transactions on microwave theory and techniques 1966 14(12)
p 588-602
143 Schulman J et al 1$f $ Noise of Sb-Heterostructure Diodes for Pre-Amplified
Detection IEEE microwave and wireless components letters 2007 17(5) p
355-357
144 Lynch JJ et al Passive millimeter-wave imaging module with preamplified
zero-bias detection IEEE transactions on microwave theory and techniques
2008 56(7) p 1592-1600
145 Su N et al Sb-heterostructure millimeter-wave detectors with reduced
capacitance and noise equivalent power IEEE Electron Device Letters 2008
29(6) p 536-539
146 Westlund A Self-Switching Diodes for Zero-Bias Terahertz Detection 2015
Chalmers University of Technology
147 Yajima T and L Esaki Excess noise in narrow germanium pn junctions
Journal of the physical society of Japan 1958 13(11) p 1281-1287
226
148 Sommers H Tunnel diodes as high-frequency devices Proceedings of the IRE
1959 47(7) p 1201-1206
149 Miraftab V and A Abdipour Harmonic balance analysis of a microwave
balanced power amplifier in Electrical and Computer Engineering 2001
Canadian Conference on 2001 IEEE
150 Patrashin M et al GaAsSbInAlAsInGaAs Tunnel Diodes for Millimeter Wave
Detection in 220ndash330-GHz Band IEEE Transactions on Electron Devices 2015
62(3) p 1068-1071
151 Hesler JL and TW Crowe Responsivity and noise measurements of zero-bias
Schottky diode detectors Proc ISSTT 2007 p 89-92
152 Su N et al Temperature dependence of high frequency and noise performance
of Sb-heterostructure millimeter-wave detectors IEEE Electron Device Letters
2007 28(5) p 336-339
153 Lynch J et al Unamplified direct detection sensor for passive millimeter wave
imaging in Proc of SPIE Vol 2006
154 ZHANG Z et al A physics-based tunneling model for Sb-heterostructure
backward tunnel diode millimeter-wave detectors International Journal of High
Speed Electronics and Systems 2011 20(03) p 589-596
155 Bahl IJ and P Bhartia Microwave solid state circuit design 2003 John Wiley
amp Sons
156 Yeom K-W Microwave Circuit Design A Practical Approach Using ADS
2015 Prentice Hall Press
157 Xie L et al A W-band detector with high tangential signal sensitivity and
voltage sensitivity in Microwave and Millimeter Wave Technology (ICMMT)
2010 International Conference on 2010 IEEE
158 Fay P et al High-performance antimonide-based heterostructure backward
diodes for millimeter-wave detection IEEE Electron Device Letters 2002
23(10) p 585-587
159 Hrobak M et al Planar zero bias Schottky diode detector operating in the E-
and W-band in Microwave Conference (EuMC) 2013 European 2013 IEEE
160 Maas SA Nonlinear microwave and RF circuits 2003 Artech House
161 Appleby R and RN Anderton Millimeter-wave and submillimeter-wave
imaging for security and surveillance Proceedings of the Ieee 2007 95(8) p
1683-1690
162 Crowe TW et al Opening the terahertz window with integrated diode circuits
IEEE Journal of Solid-State Circuits 2005 40(10) p 2104-2110
163 Raisanen AV Frequency multipliers for millimeter and submillimeter
wavelengths Proceedings of the Ieee 1992 80(11) p 1842-1852
164 Erickson NR Diode frequency multipliers for terahertz local-oscillator
applications in Astronomical Telescopes amp Instrumentation 1998 International
Society for Optics and Photonics
165 Mehdi I et al Terahertz local oscillator sources performance and capabilities
in Astronomical Telescopes and Instrumentation 2003 International Society for
Optics and Photonics
166 Tonouchi M Cutting-edge terahertz technology Nature photonics 2007 1(2)
p 97-105
227
167 Nilsen SM et al Single barrier varactors for submillimeter wave power
generation IEEE transactions on microwave theory and techniques 1993 41(4)
p 572-580
168 Xiao Q et al A 270-GHz tuner-less heterostructure barrier varactor frequency
tripler IEEE microwave and wireless components letters 2007 17(4) p 241-
243
169 David T et al Monolithic integrated circuits incorporating InP-based
heterostructure barrier varactors IEEE microwave and wireless components
letters 2002 12(8) p 281-283
170 Lieneweg U B Hancock and J Maserjian Barrier-intrinsic-N+(BIN) diodes
for near-millimeter wave generation in Conference Digest for the Twelft
International Conference on Infrared and Millimeter Waves 1987
171 Lieneweg U et al Modeling of planar varactor frequency multiplier devices
with blocking barriers IEEE transactions on microwave theory and techniques
1992 40(5) p 839-845
172 Chattopadhyay G et al An all-solid-state broad-band frequency multiplier
chain at 1500 GHz IEEE transactions on microwave theory and techniques
2004 52(5) p 1538-1547
173 Maestrini A et al A 17-19 THz local oscillator source IEEE microwave and
wireless components letters 2004 14(6) p 253-255
174 Faber MT J Chramiec and ME Adamski Microwave and millimeter-wave
diode frequency multipliers 1995 Artech House Publishers
175 Frerking MA and JR East Novel heterojunction varactors Proceedings of the
Ieee 1992 80(11) p 1853-1860
176 Penfield P and RP Rafuse Varactor applications 1962
177 Palazzi V et al Low-power frequency doubler in cellulose-based materials for
harmonic RFID applications IEEE microwave and wireless components letters
2014 24(12) p 896-898
178 Presas SM Microwave frequency doubler integrated with miniaturized planar
antennas 2008
228
APPENDICES
Appendix I Doped substrate process details
Mask Stage Process Stage Process step Process detail Equipment
Mask 1 (Mesa
Etch)
Sample clean NMP 10 min 80˚C Beaker
Acetone 5 min Beaker
Isopropanol (IPA) 5 min Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist S1805 - Program 4 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
1 min 09mW iline
(Compensation error set to 1)
MA4 Mask
aligner
Develop MIF 319 for 1 min Beaker
Post Exposure
Bake Oven or Bake 120C for 15
minutes Hotplate
Etch Etch Cal Cal Sample - etch for 2 minutes Beaker
Etch
H3PO4H2O2H2O 3150
time is determined by the etch cal Beaker
Resist Strip Acetone - 5 min and IPA - 5 min Beaker
Mask2 (Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3 Beaker
Acetone ultrasonic for 5 Min Power 3 Beaker
Isopropanol (IPA) ultrasonic for 5 Min Power 3 Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist AznLoF - 2um grade - Program 6 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
55 seconds 09mW i-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 326 for 1 mins Beaker
Clean O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
Surface De-oxide HCLH2O 11 40 sec Beaker
Metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Anneal 420˚C 2min Furnace
229
TLM
Measurement ICCAP
Measurement
Bench
Mask 3
(BottomBacks
ide Contact)
Sample clean Acetone Optional Beaker
Isopropanol (IPA) Optional Beaker
Apply Resist Prebake
Bake for 5mins 150C to dry
the sample Hotplate
Resist (top side) S1813 - Program 6 Laurell Spinner
Soft bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Exposure
10 seconds 09mW I-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 319 for 2 mins Beaker
De-scum O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
De-oxidise
Surface De-oxide
HCLH2O 11 40
sec Beaker
metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Clean Water 3min Beaker
TLM
Measurement ICCAP
230
Appendix II Four Mask step Process Flow
Mask Stage Process Stage Process step Process detail
Mask1 Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3
Acetone ultrasonic for 5 Min Power 3
Isopropanol (IPA) ultrasonic for 5 Min Power 3
Apply Resist Prebake Bake for 5mins 150C
1st Resist AznLoF - 2um grade - Program 6
Hot Plate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 55 seconds 09mW iline (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 1 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
Mask 2 (Mesa
Etch)
Sample clean NMP Optional
Acetone Optional
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C
1st Resist S1805 - Program 4
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 1 min 09mW i-line (Compensation error set
to 1)
Develop MIF 319 for 1 min
Post Exposure Bake Oven or Bake 120C for 15 minutes
Etch Etch Cal Cal Sample - etch for 2 minutes
Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Measure TLM
Resist Strip Acetone - 5 min and IPA - 5 min
Mask 3(Isolation) Sample clean Acetone Optional
Isopropanol (IPA) Optional
231
Apply Resist Prebake Bake for 5mins 150C
Resist S1828 - Program 4
Hot Plate 115C for 1 mins
Photolithography Mask Align mask to wafer
Expose 9 mins 09mW iline (Compensation error set
to 1)
Develop MF 319 3 mins
Post Bake Oven Bake 120C for 15mins
Etch Etch Cal Refer to Etch Cal instr tab
Sub-collector Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Resist Strip Acetone 5mins + IPA 5 mins in ultrasonic bath
power 1
inspection Microscope
Sample clean Acetone Optional
Mask 4 (Bottom
Contact)
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C 1st
Resist AznLoF - 2um grade - Program 6
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 10 seconds 09mW i-line (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 2 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide
HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
232
Appendix III Epitaxial Layer XMBE277
TABLE I The epitaxial structure for sample XMBE277
Layer Thickness (nm) Doping Concentration (cm-3)
n+- In053Ga047As 45 200 x 1019
n- In053Ga047As 25 300 x 1018
In053Ga047As 20 undoped
AlAs 13 undoped
In08Ga02As 45 undoped
AlAs 13 undoped
In053Ga047As 20 undoped
n- In053Ga047As 25 300 x 1018
n+- In053Ga047As 400 100 x 1019
Semi-insulating InP
233
Appendix IV SilVaco (Atlas) Simulation Code
go atlas
---------------------------------------------------------
Structure parameter definition (Constants) values in um
---------------------------------------------------------
Thicknesses
set t_contact1=0
set t_ohmic1=03
set t_emitter=004
set t_spacer1=0005
set t_barrier=000283
set t_spacer2=02
set t_collector=004
set t_ohmic2=045
Doping concentrations
set d_ohmic1=4e18
set d_emitter=2e17
set d_collector=2e17
set d_ohmic2=4e18
set d_gap=2
set d_mesa=4
set d_device=10
set d_etch=008
Layers
set I=$t_contact1
set A=$I+$t_ohmic1
set B=$A+$t_emitter
set C=$B+$t_spacer1
set D=$C+$t_barrier
set E=$D+$t_spacer2
set F=$E+$t_collector
set G=$F+$t_ohmic2
-------------------------------------
Mesh generator
-------------------------------------
mesh diagflip width=45
xmesh location=0 s=1
xmesh location=1 s=1
xmesh location=2 s=1
xmesh location=4 s=1
xmesh location=5 s=1
xmesh location=6 s=1
xmesh location=7 s=1
xmesh location=8 s=1
xmesh location=$d_mesa s=1
xmesh location=$d_mesa+$d_gap s=1
xmesh location=$d_device s=1
Ohmic1
ymesh l=0000 s=005
ymesh l=$I s=005
234
ymesh l=$A s=0005
ymesh l=$B s=0005
ymesh l=$C s=00005
ymesh l=$D s=00005
ymesh l=$E s=0009
ymesh l=$F s=0005
ymesh l=$G s=0005
-----------------------------------
SECTION 2 Regions Structure definition
-----------------------------------
region num=1 name=contact1 material=Gold ymin=0 ymax=$I
region num=2 name=ohmic1 material=GaAs ymin=$I ymax=$A
region num=3 name=emitter material=GaAs ymin=$A ymax=$B
region num=4 name=spacer1 material=GaAs ymin=$B ymax=$C
region num=5 name=barrier material=AlAs ymin=$C ymax=$D xmin=0 xmax=$d_mesa
calcstrain qtregion=1
region num=6 name=spacer2 material=GaAs ymin=$D ymax=$E
region num=7 name=collector material=GaAs ymin=$E ymax=$F
region num=8 name=ohmic2 material=GaAs ymin=$F ymax=$G
region num=9
name=etch material=Air ymin=0 ymax=$F+$d_etch xmin=$d_mesa xmax=$d
_device
---------------------------------
Electrodes
---------------------------------
electrode num=1 name=anode xmin=0 xmax=$d_mesa ymin=0 ymax
=$I material=Gold
electrode num=2 name=cathode xmin=$d_mesa+$d_gap xmax=$d_device ymin=$F+
$d_etch ymax=$F+$d_etch material=Gold
--------------------------------
Doping
--------------------------------
doping uniform ntype conc=$d_ohmic1 Region=2 ymin=$I ymax=$A
doping uniform ntype conc=$d_emitter Region=3 ymin=$A ymax=$B
doping uniform ntype conc=$d_collector Region=7 ymin=$E ymax=$F
doping uniform ntype conc=$d_ohmic2 Region=8 ymin=$F ymax=$G
--------------------------
Contacts
--------------------------
interface sc region=1
interface ss region=2
interface ss region=3
interface si region=4
interface si region=5
interface ss region=6
interface ss region=7
interface sc ymin=$F ymax=$F xmin=$d_mesa+$d_gap xmax=$d_device
interface tunnel region=5 dytunnel=0001
contact name=cathode
contact name=anode
235
------------------------------------------
SECTION 3 Material amp Models Definitions
------------------------------------------
material material=AlAs
permittivity=10 eg300=28 mc=004 affinity=305 nc300=4e19 nimin=1e1
material material=GaAs permittivity=139 eg300=14 mc=0067
affinity=407 nc300=09e17 nimin=1e6
BAND DIAGRAM
output tquantum bandparam qfn qfp valband conband charge polarcharge flowlines
STRUCTURE GRAPHIC
solve init
save outf=XMBE304+real2str
tonyplot XMBE304+real2str
------------------------------------------
SECTION 4 ANALYSIS
------------------------------------------
trap acceptor structure=top elevel=03 density=48e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$A ymax=$C xmin=0 xmax=$d_mesa
trap acceptor structure=BOTTOM elevel=035 density=47e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$E ymax=$F xmin=0 xmax=$d_mesa
models sisel sisnlderivs qtregion=1 print
method climit=1e-4 itlimit=50 maxtraps=20
DC ANALYSIS
log outf=XMBE304log
solve init
solve vanode=0 name=anode vstep=001 vfinal=15
save outf=XMBE304str
log off
tonyplot XMBE304str
tonyplot XMBE304log
5
72 Motivation and Background 202
73 Frequency Multiplier Architecture the Basics 203
731 Types of frequency multipliers 205
74 Parameters of interest for Frequency Multipliers 206
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler 208
76 Conclusions 214
8 CONCLUSION AND FUTURE WORK 215
81 Conclusion 215
82 Future Work 217
REFERENCES 218
APPENDICES 228
Word count including footnotes and endnotes 61500(approximately)
6
LIST OF TABLES
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials
structure grown on GaAs Substrates by MBE 23
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314
grown on a GaAs substrate by MBE 24
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP
substrate 24
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary
compound semiconductors a room temperature [41 42] 38
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work 56
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and
Ammonia on GaAs and InGaAs materials 87
Table 32 Epitaxial layer of Doped substrate samples 93
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm 94
Table 34 Generic fabrication steps established by Dr Md Adzhar [101] 97
Table 35 Standard process flow for Air-Bridge design fabrication 101
Table 36 Standard fabrication process flow for Dielectric-Bridge design 107
Table 37 New arrangement of the mask number and step in Second Run 110
Table 38 New arrangement for the Third run using Dielectric-Bridge mask 113
Table 39 The outcome of the spreading resistance before and after using LOR
technique 115
Table 310 DC and RF characteristics for XMBE304 118
Table 311 3rd
Gen Mask process step 119
Table 312 Standard deviation at two different voltages 124
Table 41 The parameter values used in this simulation 134
Table 42 The calculated values of bandgap at different temperatures 140
Table 43 The calculated effective masses for each temperature used in this simulation
141
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104) 145
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics
in this work 153
Table 52 Device to device uniformity check for large ASPAT diode 159
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at
four different frequencies[117] 159
7
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B 161
Table 55 Comparison between calculated (fully Depleted) and extracted (different
biases) values from equivalent circuit parameters for different ASPAT mesa sizes at zero
bias voltage 170
Table 61 A summary of all the important parameters of the 4x4 microm2 diode 185
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode 190
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector 198
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero
bias detector at W-band (75GHz-110GHz) 199
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art
multiplier diode 213
8
LIST OF FIGURES
Figure 21 III-V compound semiconductors mobility and band gap[24] 31 Figure 22 illustration of Homojunctions band structure material before (left) and after
(right) equilibrium 34 Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium 35
Figure 24 Lattice Matching for both materials when aL=aS 37 Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40] 37 Figure 26 Lattice mismatched material 39
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and
(b) tensile strain [1] 40 Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg
GaAs (a) Structure (b) energy band diagram and (c) Conduction band diagram when
AlGaAs is n-doped[43] 41 Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact 43
Figure 210 Energy band diagram of Schottky contact on n-type material under (a)
reverse and (b) forward bias 45 Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping
concentration ND (a) Low (b) Intermediate and (c) high 47 Figure 212 Classical view of whether an electron is can surmount a barrier or not
Quantum mechanical view allows an electron to tunnel through a barrier The probability
(blue) is related to the barrier thickness 51
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave
function[70] 52
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in
this study 55 Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27] 57
Figure 216 Conduction band diagram showing band bending and 2DEG formation at
the L1 spacer 60 Figure 217 I-V characteristics of a fabricated ASPAT diode 63 Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
63 Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b
and h are not drawn to scale 65 Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304)
The dimensions are not drawn to scale 67 Figure 221 A simple TLM structure with effective length and sheet resistance
underneath 69 Figure 222 Top view of TLM ladder structure use in this work 71 Figure 223 Typical plot of resistance versus TLM spacing 71
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM 73
9
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
75 Figure 226 Actual VNA system that was used for RF characterization 75 Figure 227 Block diagram of the ASPAT measurement step 77
Figure 31 3D illustration of Optical lithography process used in this research 85 Figure 32 Actual picture of thermal evaporator used in this study 89 Figure 33 Single layer lift-off process using negative photoresist 91 Figure 34 Current-Voltage characteristic of sample XMBE368 used in this study at
two different locations on the wafer tile 96
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2
diode dimensions designed in the 1st Gen Mask 96
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates 100 Figure 37 The layout of 1
st design of Dielectric Bridge (green circle) mask design for
100 times 100microm2 emitter size with option for doped substrate processing 100
Figure 38 Dry Etching for the first run in this study 102 Figure 39 Severe undercut of 2times2 microm
2 and 6times6 microm
2 devices 103
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet
etched 104 Figure 311 SEM Images of the GaAs sample 104
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in
this study 105
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
105
Figure 314 SEM images for InP and InGaAs taken from [56] 105 Figure 315 Short circuit behaviour on one of the fabricated device in this run 106
Figure 316 The surface of the sample after final processing 108 Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2
2500 microm2 900 microm2 400 microm2 225 microm2 100 microm2 and 36 microm2 109
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm
Tolerance 110
Figure 319 After lift-off processing 111 Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
112
Figure 321 side view of lateral ASPAT structure 113
Figure 322 The measured size of the emitter area and the length D (blue color marked)
114 Figure 323 Summary of LOR technique steps 115 Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
116
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and
alignment mark structures used in this study 118 Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-
insulating substrate device type used in this study 121 Figure 327 Example finished process device with bond pad using 3
rd Gen mask 121
Figure 328 XMBE304 TLM measurement for the top contact after annealing 122
10
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing 122 Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 4times4microm2 mesa size 123
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 6times6microm2 mesa size 124
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room
temperature for 10times10microm2 mesa size 124
Figure 41 SILVACO Atlas simulation process flow 128 Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the
diode multilayer heterostructures on the right 131 Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor 131 Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure
(b) the energy band diagram of the ASPAT diode structure when under three different
biases 132 Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm
2) and
(4times4microm2) using SILVACO Atlas simulator for structure device XMBE304 showing
excellent agreement between simulated and experimental data 134
Figure 46 IV characteristics of the dependencies of current on AlAs barrier 136 Figure 47 Example of analysis at -1 and 1V to the current 136 Figure 48 I-V characteristic of the dependencies current to Spacer I layer 137
Figure 49 Current changes with layer thickness l1 138 Figure 410 IV characteristic of the dependencies current to Spacer 1 layer 139
Figure 411Current change with layer thickness l2 139
Figure 412 Measurement and simulation comparison result as a function of temperature
range from 100K to 398K 142 Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample
XMBE304 143
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT
Diode [3] 144
Figure 415 Log Current vs voltage as a function of temperature for SBD sample
XMBE104 145
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and
SBD 146
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2
6x6um2 and 10x10um
2 Note the good scalability 149
Figure 52 Junction resistance versus voltage 151
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT
high sensitivity near zero bias detection 152
Figure 54 One port S-parameter measurements 155
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use
for RF calibration and measurements (Note Images are not to scale) 156
11
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices
from 15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check 158
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero
bias 158
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B)
to qualify the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2
device sizes (Real and Imaginary) Note blue colour is XMBE304A and red colour is
XMBE304B 160
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and
4times4microm2
(Real and Imaginary) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm
2 diodes respectively 162
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and
4times4 microm2 (Smith Chart) Note that green red and blue colour represents 4times4microm2
6times6mmicro2 and 10times10microm2 diodes respectively 162
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding
equivalent circuit model 164
Figure 512 The S-parameter Touchstone file is used to read the measured files 165
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure 166
Figure 514 Equivalent circuit model for short de-embedded structure 166
Figure 515 Smith chart representative S-parameter measurement for short (left) and
open (right) CPW The blue lines represent simulated data and the red is measured data
167
Figure 516 Equivalent circuit of the ASPAT diode 169
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 (Real and Imaginary) results for various small device designs 169
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour)
for S11 results (Smith Chart) for various small device designs 170
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled
capacitance vs Voltage) 172
Figure 61 Block diagram represent a complete direct receiver system 177
Figure 62 The detection process of a single wave through a non-linear IV characteristic
of a diode 177
Figure 63 Lumped element illustration of microwave detector circuit 178
Figure 64 The mixing process where the signals are processed by the non-linear I-V
characteristic to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and
fRF are applied to the diode 179
Figure 65 Measurement of Tangential Sensitivity[108 129] 181
12
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted
from MATLAB to realize a virtual GaAsAlAs ASPAT diode 186
Figure 67 Verification of actual (blue measured) and virtual (red_10th order
polynomial) I-V characteristic of the 4times4 microm2 diode used in this study 186
Figure 68 Direct detector circuit topology using an ASPAT diode 187
Figure 69 Output voltage and detector sensitivity over wide range of input power 188
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load
resistance of the ASPAT detector 189
Figure 611 Junction resistance as a function of forward voltage 189
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size
of 4times4μm2 191
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power 192
Figure 614 Reflection Coefficient versus operating frequency without matching
circuitry 193
Figure 615 Detector circuit with impedance matching circuit placed in between diode
and source 194
Figure 616 Reflection Coefficient over wide frequency band with matching 195
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band
frequency 195
Figure 618 Lowest detectable signal at 100GHz operating frequency 196
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of
diode operation 197
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained
from the fabricated ASPAT in this work 198
Figure 71 performance of state-of the-art millimetre wave source [166] 202
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
204
Figure 73 Principle of operation for frequency multiplier utilising a non-linear
resistance [10] 204
Figure 74 A standard system for two port frequency multiplier circuit 207
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode 209
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool 210
Figure 77 Conversion loss and conversion efficiency as a function of input power 211
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
212
13
LIST OF PUBLICATIONS CONFERENCE PRESENTATIONS
PUBLICATIONS
1 MRR Abdullah Y K Wang J Sexton M Missous and M J Kelly ldquoGaAsAlAs
Tunnelling Structure Temperature Dependence of ASPAT Detectorsrdquo 8th UK-Europe-
China Workshop on mm-waves and THz Technologies 2015 Cardiff University IEEE
proceedings DOI 101109UCMMT20157460591
2 Yuekun Wang Mohd Rashid Redza Abdullah James Sexton and M Missous
ldquoInGaAs-AlAs asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo 8th
UK-Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings DOI 101109UCMMT20157460589
3 K N Zainul Ariffin S G Muttlak M Abdullah M R R Abdullah Y Wang and M
Missous ldquoAsymmetric Spacer Layer Tunnel In018Ga082AsAlAs (ASPAT) Diode using
Double Quantum Wells for Dual Functions Detection and Oscillationrdquo 8th UK-
Europe-China Workshop on mm-waves and THz Technologies 2015 Cardiff
University IEEE proceedings Doi 101109UCMMT20157460599
4 K N Zainul Ariffin M R R Abdullah Y K Wang S G Muttlak O S
Abdulwahid J Sexton MJ Kelly and M Missous ldquoAsymmetric Spacer Layer Tunnel
Diode (ASPAT) Quantum Structure Design Linked to Current-Voltage Characteristics
A Physical Simulation Studyrdquo UK-China Millimetre Waves and Terahertz Technology
Workshop September 2017 Submitted 14 July 2017 Conference held on 11th -13th
September 2017 DOI 101109UCMMT20178068358
5 K N Zainul Ariffin Y Wang M R R Abdullah S G Muttlak Omar S
Abdulwahid J Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoInvestigations of
Asymmetric Spacer Tunnel Layer (ASPAT) Diode for High-Frequency Applicationsrdquo
DOI 101109TED20172777803
6 Omar S Abdulwahid S G Muttlak M R R Abdullah K N Zainul Ariffin J
Sexton Ka Wa Ian Michael J Kelly and M Missous ldquoA 100GHz Zero-Biased
Quantum Tunnelling ASPAT Detectorrdquo Submitted to IEEE TED on DEC 2016 under
correctionamendment Pending fabrication data
14
CONFERENCE PRESENTATIONS
1 Mohd Rashid Redza Abdullah J Sexton Kawa Ian MJKelly and M Missousldquo
G2040GHz Frequency Doubler Varistor Mode using ASPAT diodesrdquo UK
Semiconductors 2017 2017 University of Sheffield Oral presentation
2 M R R Abdullah YueKun Wang J Sexton Kawa Ian and M Missousldquo
Microwave Performance of GaAsAlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diodesrdquo UK Semiconductors 2016 2016 University of Sheffield Oral presentation
3 M R R Abdullah J Sexton and M Missousldquo GaAsAlAs Tunnelling Structures
THz RTD oscillators and ASPAT detectorsrdquo UK Semiconductors 2015 2015
University of Sheffield Oral presentation
4 Yuekun Wang Mohd Rashid Redza Abdullah and M MissousldquoInGaAs-AlAs
asymmetric space layer tunnel (ASPAT) diodes for THz electronicsrdquo UK
Semiconductors 2015 2015 University of Sheffield Oral presentation
5 Mohd Rashid Redza Abdullah and M Missousldquo GaAsAlAs Tunnelling
Structure Temperature Dependence of ASPAT Detectorsrdquo PGR Conference2016
2016 University of Manchester Poster presentation
6 YueKun Wang KNZainul Ariffin Mohd Rashid Redza Abdullah J Sexton
Kawa Ian and M Missous ldquoPhysical Modelling and Experimental Studies of
InGaAsAlAs Asymmetric spacer Layer Tunnel Diodesrdquo UK Semiconductors 2016
2016 University of Sheffield Oral presentation
7 K N Zainul Ariffin S G Muttlak M R R Abdullah Y Wang Omar S
Abdulwahid M Missous ldquoExperimental and Physical Modelling of Temperature
Dependence of a Double Quantum Well In018Ga082AsAlAs ASPAT Dioderdquo UK
Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral Presentation
8 Omar S Abdulwahid Mohd Rashid Redza Abdullah S G Muttlak K N Zainul
Ariffin Mohamed Missous ldquoTunnelling Barrier Diode for Millimetre Wave
Mixingrdquo UK Semiconductor Conference 2016 Sheffield 6 ndash 7 July 2016 Oral
Presentation
9 M Abdullah K N Zainul Ariffin MRR Abdullah J Sexton M Missous and
MJ Kelly ldquoA Novel In18Ga82As-AlAs Asymmetric Spacer Layer Tunnel (ASPAT)
Diode with Double Quantum Wells for Microwave Detectionrdquo UK Semiconductor
Conference 2015 Sheffield 1 ndash 2 July 2015 Oral Presentation
15
ABSTRACT
Thesis Title GaAsAlAs ASPAT Diodes for Millimetre and Sub-Millimetre Wave
Applications
Institute School of Electrical and Electronic Engineering the University of Manchester
Candidate Mohd Rashid Redza bin Abdullah
Degree Doctor of Philosophy (PhD)
Date 3 October 2017
The Asymmetric Spacer layer Tunnel (ASPAT) diode is a new diode invented in
the early 90s as an alternative to the Schottky barrier diode (SBD) technology for
microwave detector applications due to its highly stable temperature characteristics The
ASPAT features a strong non-linear I-V characteristic as a result of tunnelling through a
thin barrier which enables RF detection at zero bias from microwaves up to
submillimetre wave frequencies In this work two heavily doped GaAs contact layer on
top and bottom layers adjacent to lightly doped GaAs intermediate layers enclose
undoped GaAs spacers with different lengths sandwiching an undoped AlAs layer that
acts as a tunnel barrier The ultimate ambition of this work was to develop a MMIC
detector as well as a frequency source based on optimized ASPAT diodes for millimetre
wave (100GHz) applications The effect of material parameter and dimensions on the
ASPAT source performances was described using an empirical model for the first time
Since this is a new device keys challenges in this work were to improve DC and
RF characteristic as well as to develop a repeatable reproducible and ultimately
manufacturable fabrication process flow This was investigated using two approaches
namely air-bridge and dielectric-bridge fabrication process flows Through this work it
was found that the GaAsAlAs heterostructures ASPAT diode are more amenable to the
dielectric-bridge technique as large-scale fabrication of mesa area up to 4times4microm2 with
device yields exceeding 80 routinely produced The fabrication of the ASPAT using i-
line optical lithography which has the capability to reduce emitter area to 4times4microm2 to
lower down the device capacitance for millimetre wave application has been made
feasible in this work The former challenge was extensively studied through materials
and structural characterisations by a SILVACO physical modelling and confirmed by
comparison with experimental data The I-V characteristic of the fabricated ASPAT
demonstrated outstanding scalability demonstrating robust processing A fair
comparison has been made between ASPAT and SBD fabricated in-house indicating
ASPAT is extremely stable to the temperature The RF characterisations were carried out
with the aid of Keysight ADS software
The DC characteristic from fabricated GaAsAlAs ASPAT diodes were absorbed
into an ADS simulation tool and utilized to demonstrate the performance of MMIC
100GHz detector as well as 20GHz40GHz signal generators Zero bias ASPAT with
mesa area of 4times4microm2 with video resistance of 90KΩ junction capacitance of 23fF and
curvature coefficient of 23V-1
has demonstrated detector voltage sensitivity above
2000VW while the signal source conversion loss and conversion efficiency are 28dB
and 03 respectively An estimate noise equivalent power (NEP) for this particular
device is 188pWHz12
16
DECLARATION AND COPYRIGHT STATEMENT
No portion of the work referred to in the dissertation has been submitted in support of an
application for another degree or qualification of this or any other university or other
institute of learning
COPYRIGHT STATEMENT
i The author of this thesis (including any appendices andor schedules to this thesis) owns
certain copyright or related rights in it (the ldquoCopyrightrdquo) and he has given The University of
Manchester certain rights to use such Copyright including for administrative purposes
ii Copies of this thesis either in full or in extracts and whether in hard or electronic copy
may be made only in accordance with the Copyright Designs and Patents Act 1988 (as
amended) and regulations issued under it or where appropriate in accordance with licensing
agreements which the University has from time to time This page must form part of any
such copies made
iii The ownership of certain Copyright patents designs trademarks and other intellectual
property (the ldquoIntellectual Propertyrdquo) and any reproductions of copyright works in the thesis
for example graphs and tables (ldquoReproductionsrdquo) which may be described in this thesis
may not be owned by the author and may be owned by third parties Such Intellectual
Property and Reproductions cannot and must not be made available for use without the prior
written permission of the owner(s) of the relevant Intellectual Property andor
Reproductions
iv Further information on the conditions under which disclosure publication and
commercialisation of this thesis the Copyright and any Intellectual Property andor
Reproductions described in it may take place is available in the University IP Policy
(httpdocumentsmanchesteracukDocuInfoaspxDocID=487) in any relevant Thesis
restriction declarations deposited in the University Library The University Libraryrsquos
regulations (httpwwwmanchesteracuklibraryaboutusregulations) and in The
Universityrsquos policy on Presentation of Theses
17
ACKNOWLEDGEMENTS
First and foremost all gratefulness and praise is to Allah swt for everything in my
life He is the one and the only one who granted me knowledge health patience and
ability to complete this thesis as well as colouring the whole journey of my PhD
I give my deepest and sincere gratitude to my PhD supervisor Professor Mohamed
Missous for his time support patience and guidance throughout the journey of this PhD
studies His encouragements valuable advice precious ideas and a wealth of knowledge
amp experiences have had a direct inspiration on this research Special thanks also to our
experimental officer Dr James Sexton for not only sharing his knowledge advice and
semiconductor fabrication skills but also his effort in maintaining our clean room
facilities to a great level My gratitude also extends to Mr Mallachi McGowan for his
help and assist in the lab-related issue
I am also obligated to Prof MJ Kelly from University of Cambridge and Dr Kawa
Ian from ICS limited for their measurement of the ASPAT samples on realizing the RF
characteristics This collaboration effort can hopefully last longer in designing and
implementing the ASPAT MMIC detectors
My deepest appreciation also goes to my PhD colleagues Khairul Nabilah Saad
GMuttlak Omar AbdulWahid and Yuekun Wang for their support as well as working
together with me to realize this exciting project directly and indirectly A sincere
thankfulness similarly to my seniors Dr Md Adzhar Zawawi and Dr Fauzi Packeer for
their support during the first and second year of my research For other friends and staff
members under Prof Missous and Dr M Migliorato I will always remember the strong
bond and friendship we made
I am really fortunate that I been blessed with my motherrsquos care who always make doarsquo
for my success every day during my studies As for my beloved wife Dr Nik Maryam
Anisah Nik Mursquotasim who had always encouraged me supported me and gave me
patience through all the hardship in this journey thank you very much
Finally I also would like to thank and acknowledge my sponsor Majlis Amanah
Rakyat (MARA) for financially supporting me during this studies I am greatly indebted
with your kind support which was vital to my study
18
DEDICATION
This thesis dedicated to
My respected and beloved parentshellip
My loving wife dearest siblings and in-lawshellip
19
1 INTRODUCTION
11 Background
It is an undeniable fact that semiconductors have changed the world much further
than anything people could have predicted in the last 60 or 70 years ie after the lsquocats
whisker and vacuum tube eras This field of research has been expanding from year to
year starting from the discovery of the first semiconductor (silver sulfide) in 1833 by
Michael Faraday [1 2] and it still remains very active to the present Semiconductors
have a large range of applications and are not just limited to use in communications they
can be found everywhere in other applications from Earth to space The widespread
usage and sheer number of applications have led to it growing very quickly and
contributing greatly to the growth of World Economics Over time the successful
development of semiconductor growth techniques such as Molecular Beam Epitaxy
(MBE) has enabled researchers to tailor and precisely control the semiconductor
material for new electronic devices with extra functionalities This has led to the
development of advanced devices such as high electron mobility transistors (HEMTs)
and Heterojunction bipolar transistors (HBTs) for use in wireless communication
technology Given this development today electronic devices such as computers
handheld smartphone tablets etc are no longer perceived as luxury and attractive items
but rather have become crucial in everyday life Such devices provide the means to allow
for people to remain connected to each other via the sending and receiving of
information electronically The huge demand for such types of devices has resulted in
competition in both the electronic market and technologies which only goes on to
advance the semiconductor industry
Nowadays the demand for electronic devices characterised by high speed high
efficiency ultra-low power and low manufacturing cost has increased exponentially To
fulfil this growth in demand high data rate systems are required in other words the
system must work at a higher frequency for both the transmitter and receiver The
frequency of interest for advanced wireless communication is in the Millimetre and sub-
20
millimetre wave region which is around 30-300GHz and 300 - 3000GHz respectively
The second frequency region is also sometime known as the terahertz (THz)
electromagnetic region This band lies between the microwave and infrared frequency
bands From the first time it was revealed in the late 80s[3-5] the THz region has gained
a lot of international attention due to its unique properties and since then the motivation
to develop these devices has increased significantly To date the THz frequencies region
has shown its ability to fulfil various applications such as high-resolution imaging in
medical security and surveillance field atmospheric monitoring and environment radio
astronomy as well as compact range radars[3] to name a few
However despite these developments not much effort has been made in exploring
alternative compact THz devices As a result electronic THz devices are still in the state
of immaturity as compared to microwave and photonics devices This is due to their high
cost and absence of compact amp solid-state THz sources (oscillators) and receivers
(detectors) that are capable of operating at both room and extreme temperatures[6 7] A
great deal of work still continues to fill up the lsquoTHz gaprsquo (between 300GHz and 3THz)
used for the most important part of a communication system namely the front-end
receiver or first stage Such a system is responsible for receiving detecting and
processing the received signal to be translated into useful information Furthermore THz
receivers systems still require the best-integrated components such as source mixer and
detector to reach their complete competencies[8] The detector which remains the
critical part of the receiver system requires devices or components that are able to fulfil
the THz gap requirement Studies conducted over a number of years have found out that
the key element in improving THz detection relies upon the use of passive devices ie
diodes Based on these findings many types of diode ie tunnelling diode point-contact
diode and Schottky barrier diode (SBD) have been proposed for detection applications
Amongst microwave and millimetre wave detector diode devices the Schottky
Barrier Diode (SBD) is the dominant detector that has been used since the 1940s[9] The
reason for this dominance is the ease of fabrication of a SBD (by either a point-contact
or evaporated semiconductor-metal structure) and its ability to produce a non-linear
current-voltage (I-V) characteristic which is necessary for rectifyingdetecting diodes [9
10] SBDs also have high cut-off frequency good dynamic range and are low cost To
21
date the SBD has been able to detect signals up to 100GHz [11] 1THz[12] and as high
as 10 THz[13] However the current transport mechanism in a SBD relies on thermionic
emission and therefore is strongly dependent on temperature and means that using them
in extreme conditions ie military and automotive applications is complex The SBD
also suffers from high noise figure[14] and is susceptible to burnout at a modest pulse
power level this will limit the use of ultra-high frequencies and low power signal
applications Other diodes that share the same characteristics are Planar Doped Barrier
(PDB) Germanium Backward Diode (GBD) ie a type of Esaki tunnel diode These
diodes are well known and are reliably used as millimetre wave detectors However it
still proves inefficient to substitute the SDB with any of the previously mentioned
diodes This is due to some drawbacks such as strong temperature dependence limited
dynamic range fabrication complications and hence poor reproducibility (ie GBD) and
other circuit complexities
Hence there is strong compulsion to study examine and produce new detector
diode structures that are able to solve the mentioned diodes limitations and which have
high sensitivity larger dynamic range low noise strong independence to temperature as
well as being able to work efficiently in the high-frequency band and at zero bias The
advantages of working at zero-bias relates very much to the need for a system with less
power consumption so that the device (ie mobile communication) is able to run off
small batteries for a reasonable length of time eliminating extra biasing circuit as well as
noise Therefore a new tunnelling device namely the Asymmetrical Spacer Layer
Tunnel diode (ASPAT) developed by RT Syme [15 16] and refined by Missous et
al[17] has been examined in this work The ASPAT which is in essence a
Semiconductor-insulator-semiconductor structure relies on tunnelling through a barrier
to provide current compared to conventional thermionic emission in SBDs The ASPAT
diode has many advantages a zero bias turn-on voltage very weak sensitivity to changes
in temperature (due to tunnelling) very low noise large dynamic range high resistance
to pulse burn-out [18] and as demonstrated recently can be reproducibly
manufactured[17] The growing interest in THz frequencies nowadays makes the
ASPAT an excellent choice to fulfil all requirements for ultra-high speed applications
22
ie communication (mobile computer networking) radar (military equipment) scalar
analyser and built-in test equipment
In this work an ASPAT diode based on group III-V elements of the periodic table
comprising compound semiconductors of large band gap material Aluminium Arsenide
(AlAs) sandwiched between two lower bandgap Gallium Arsenide (GaAs) are used and
intensively examined The AlAs semiconductor which is ten-monolayer thick has
almost the same lattice constant as GaAs but has a larger bandgap Consequently in the
conduction band a thin barrier of the AlAs is formed from the arrangement of such
structure The structure is made up of GaAs and AlAs both materials are grown on
GaAs substrate using Solid Source Molecular Beam Epitaxy (SSMBE) Therefore in
this study the ASPAT diode will be referred to as ldquoGaAsAlAs ASPATrdquo diode The
conventional GaAsAlAs ASPAT diode has been developed and successfully fabricated
in two different stages This work was the first carried out using facilities provided by
the University of Manchester The first stage of the work was to qualify the
reproducibility and repeatability of growth and fabrication technique which is mostly
performed on larger emitteranode size The second was to develop conventional
ASPAT diodes that can perform at Millimetre and sub-millimetre wave frequencies and
which are comprised of small emitter area
Prior to this work full physical modelling using SILVACO design software was
undertaken to generate models and to fully characterise and identify the fundamental
physical phenomenon of multi-junction ASPAT diode Therefore insight into and
performance based on diode structure and electron movement can be understood and
predicted which lead to the crucial idea in helping and advising iterations to epitaxial
growth as well as diode fabrication The verification of the physical models must be set
as a priority goal by comparing the results of statistically fabricated measured data The
advantage of physical modelling is that it can help reduce materials resources cost and
fabrication time
Further research into the field has led to the development of two other types of
ASPAT diodes that are used to compare with the conventional GaAsAlAs ASPAT
diode Their configuration involved the use of a more advanced semiconductor
technology which comprises InGaAsAlAs materials and GaAsAlAs with InGaAs
23
quantum wells The latter was a novel ASPAT diode and the former is identified as
advanced ASPAT diode However these two advanced ASPAT diodes have not been
extensively studied in this thesis as they will be covered by other co-workers at
Manchester Hence due to these some important parameters are compared to the
conventional one as it is the main focus of this work In the case of temperature
dependent studies the DC characteristic of conventional ASPAT is compared to in-
house fabrication AuGaAs SBD All the ASPATs epitaxial layer materials structures are
shown in the following tables
Table 11 Sample XMBE304 XMBE307 and XMBE368 GaAsAlAs materials structure grown
on GaAs Substrates by MBE
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE304 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~400 ~50
Spacer1 GaAs NID 50 50 50
Barrier AlAs NID 28 28 28
Spacer 2 GaAs NID 1000 2000 1000
Buffer GaAs(Si) 4times1017
50 400 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~4500 ~3500
Substrate GaAs (Si) 50000 50000 50000
Note that sample XMBE368 and XMBE304 are grown on doped GaAs
substrates Sample XMBE368 was grown un-rotated to study the effect of barrier
thickness variation
24
Table 12 Quantum wells sandwiching the quantum barrier for sample XMBE314 grown on a
GaAs substrate by MBE
XMBE314
Layer Material Doping (119836119846minus120785) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018
3000 142
Emitter GaAs (Si) 1times1017
400 142
Spacer GaAs Undoped 50 142
Quantum Well In18Ga82As Undoped 60 116
Barrier AlAs Undoped 28 283
Quantum Well In18Ga82As Undoped 60 116
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017
400 142
Ohmic Layer GaAs (Si) 4times1018
4500 142
Substrate GaAs
Table 13 Novel InGaAsAlAs ASPAT diode grown on InP substrate by MBE on InP substrate
XMBE326
Layer Material Doping (cm-3
) Thickness (Aring) Bandgap (eV)
Top Ohmic1 In053Ga047As(Si) 5times1019
3000 075
Buffer 1 In053Ga047As(Si) 1times1017
350 075
Spacer1 In053Ga047As NID 50 073
Barrier AlAs NID 283 283
Spacer 2 In053Ga047As NID 2000 075
Buffer In053Ga047As(Si) 1times1017
350 075
Bottom Ohmic In053Ga047As(Si) 15times1019
4200 075
Substrate InP (Si) NID 620000
From the above tables it can be noted that XMBE307 is the first batch that was grown
in-house using a Riber V100HU MBE machine followed by XMBE368 XMBE 304
XMBE314 and finally XMBE326 The two earlier batches were grown on n+
substrate hence their fabrication process flow is simpler On the other hand the three
other batches were grown on semi insulating substrate thus requiring the development
of new repeatable reproducible and robust process flow which will be covered in this
thesis
25
In general the fabrication of the ASPAT diode is based on top-down processes this
is because the ASPAT is a vertical structure device and the junction capacitance of the
ASPAT is directly associated with the size of the anodeemitter area Further to these
the capacitance directly influences the diode cut-off frequency Therefore the simplest
way to reduce the capacitance is by reducing the lateral area of the device of the ASPAT
structure since it can be represented by a parallel plate capacitor where the capacitance
is inversely proportional to the area of the device In order to achieve high cut-off
frequencies minimising capacitance via small dimensions ie sub-micrometre level is
essential However this will also increase the series resistance of the diode As a result
the cut-off frequency will be degraded Thus there is a trade-off between small
dimension of device and high cut-off frequency to be achieved
Finally successful growth and fabrication for small area GaAsAlAs ASPAT diode
in this work has led to carefully extracted RF characteristics This becomes a stepping
stone to designing a millimetre wave integrated circuit (MMIC) detector using empirical
modelling in Keysight ADS tools Therefore a predicted performance for a 4times4 um2
fabricated ASPAT is that can operate at 100GHz ASPAT as a zero-bias detector with a
voltage sensitivity of over 2000VW Additionally the design of a millimetre wave
source using similar ASPAT diodes was also carried out The performance of a 2040
GHz doubler using GaAsAlAs ASPAT in varistor mode is demonstrated for the first
time with a conversion loss of 33dB and conversion efficiency of ~ 02
26
12 Aims and objectives
The aim of this study is to further improve the performance of microwave and
millimetre wave technology by incorporating the Asymmetrical Spacer Layer Tunnel
Diode (ASPAT) for ultimate operation near THz frequencies by designing a range of
low power high-speed devices enhancing the methods of Simulation layout and
materials amp structural characterisations with fabrication process optimization using the
facilities available at the University of Manchester
There are three main objectives in this research firstly to streamline the physical
device design and modelling using the GaAsAlAsGaAs materials systems in order to
produce a zero bias detector which is basically a rectifier of a microwave signal by
using the SILVACO Atlas simulation tools
Secondly to achieve reproducibility and manufacturability of the fabrication
process for new type of GaAsAlAs ASPAT structure (lateral structure) hence small size
ASPAT emitter by improving the device processing technique and maximising the
capability limit of the conventional i-line optical lithography that is available in Prof
Missousrsquos group laboratory
Thirdly to optimise DC parameters through electrical properties investigation as a
stepping stone to the next objective that is to characterise the RF performance of the
GaAsAlAs ASPAT detector circuit The detection properties of microwave and
millimetre wave diode will also be investigated with different ASPAT diode size at
100GHz Further to these the properties of microwave signal source will also be
developed by way of utilizing the non-linearity feature of the diode Therefore this new
type of tunnelling diode can be applied to both applications of signal detection and
signal source in the microwave and millimetre wave ranges
27
13 Outline of this Thesis
This thesis is organized into eight chapters The first chapter discusses the
contextual information that motivates the undertaking of the study An overview of the
work which includes the details of the studied samples the aim and objectives of the
whole research project are also outlined in this chapter
Chapter 2 deals with the literature review of the basic principles and concepts of
the group III-V compound semiconductors The historical background of such
semiconductors which is essential to the development of ternary structures etc and the
advancement of semiconductor materials engineering is presented The types of existing
tunneling diode as well as conventional microwave diodes are also discussed and
compared The fundamentals of ASPAT diode which includes structural parameters and
its operation are then explained in detail Finally discussions of the ASPAT key DC
characteristics which are important for detection purposes are presented
Chapter 3 focusses on the development of the experimental techniques which can
be divided into two stages In the first stage the development is towards repeatability
reproducibility and manufacturability of the ASPAT grown in-house by MBE and
fabricated by conventional i-line optical lithography The second stage involves
optimisation and fine tuning such fabrication method for GaAsAlAs ASPAT samples
that can operate at high frequency ie 100GHz detector For both stages of the
fabrication process all techniques including mask design generic and special process
flow are presented The chapter ends with discussions on issues related to sample
processing and improvements that are proposed to solve these issues
Chapter 4 dwells on the modelling of the GaAsAlAs ASPAT using the SILVACO
simulation package The discussions are expected to offer a better understanding or
insight into each layer that forms the ASPAT diode structure The chapter begins with
discussions of the operation of the SILVACO Atlas tool A validation of physical
modelling is essential and presented according to the fabricated mesa sizes of the diode
28
Thereafter towards the end of the chapter the analyses of the relationship between
device current-voltage (I-V) characteristics the structural parameter including various
temperatures dependent simulations with a comparison to an in-house fabricated SBD
are offered
Chapter 5 presents relevant DC results based on optimized fabrication process and
RF characterization which enable obtaining an intrinsic and extrinsic element of the
GaAsAlAs ASPAT diode The discussions also highlight the analysis of DC zero bias
equivalent circuit and de-embedding extraction using ADS The chapter ends with
discussions on the RF reproducibility performance which includes the performance as
well for millimeter-wave and sub-millimeter wave applications
Chapter 6 discusses the main applications of ASPAT diodes The chapter begins
with discussions on detection theory followed by the parameters of interest and ends
with circuit design as well as the performance of a 100GHz detector The circuit design
was conducted using Keysight ADS software via harmonics balance simulation tool The
performance in term of sensitivity depending on measured ASPAT emitter size is
demonstrated Finally a comparison with conventional Schottky diode is presented
towards the end of the chapter
Chapter 7 discusses a secondary application that can be applied to the ASPAT by
utilizing the nonlinearity feature of the diode to create a signal source namely a 20 to
40GHz frequency doubler in varistor mode The doubler performance of ASPAT will be
explored through circuit design constructed via Keysight ADS simulation software Each
key parameter is highlighted and discussed in detail
The final chapter of this thesis that is Chapter 8 discusses the conclusions of the
study with emphasis on the overall key research findings The chapter also highlights
suggestions for further research in this particular field of study
29
2 LITERATURE REVIEW
21 Introduction
Since 1940s the development in the technology of semiconductor electronics has
been expanding and now has led to the establishment one of the most astonishing
industries of the 3rd
-millennium era Leading this advancement is the integrated circuit
(IC) or chip which was driven mostly by silicon (Si) Overtime the IC has undergone
substantial revolution in term of power economics size and efficient energy
consumption Currently it covers every aspect of human life ie from desktop personal
computers in the office and house to the compact smartphone in the pocket and from a
gigantic satellite in space to small satellite navigation in cars In other words
semiconductor technology is crucial to human life Without developments in
semiconductor materials engineering and shrinking of device size such accomplishment
may not have been realised today Therefore this chapter presents a macro view of the
development in compound semiconductor technology especially in radio frequency (RF)
towards Millimetre and submillimetre wave applications with regard to the improvement
of material and device structures
The essentials of group III-V compound semiconductor will be emphasised for its
points of interest and application in this field (RF technology) This chapter comprises
five main sections The first section is an overview of the semiconductor history with
concentration on its advantages and applications in the RF field while the second and
third discuss the effects of III-V compounds when the interface occurs between
semiconductor-semiconductor and semiconductor-metal respectively which leads to a
basic understanding of hetero-structures device as well as contacts namely Schottky and
Ohmic The fourth section is predominantly concerned with high-speed devices ie
diodes and materials in this field which leads to the exploitation of the main researchrsquos
device Then the following section describes in detail the background works basic
principle and intrinsic amp extrinsic parameters of the Asymmetric spacer Tunnel Diode
(ASPAT) Finally the basic way of characterising the device will also include giving an
overview of how the device is measured and what parameters are needed
30
22 Historical review of III-V Compound Semiconductor for RF applications
The beginning of commercial electronic devices was marked with the first point-
contact semiconductor transistor developed in 1947 by William Shockley at Bell
Laboratories in New Jersey Shockley developed a device based on a Germanium
Bipolar Junction Transistor (Ge BJT) structure [19] with operating frequency above 1
GHz Since then and until early 1950s the development of Ge BJT was fast and it
became foremost in the market of semiconductor technology However the emergence
of Silicon (Si) challenged Ge in the market in the 1960s Si has the upper hand primarily
because it has better electron transport and low manufacturing costs compared to Ge
[19] By the 1970s almost all RF transistors were based on Si BJT Additionally the
development of Si which forms a new material from the formation of native oxide
namely Silicon Dioxide (SiO2) led to the invention of the Metal Oxide Semiconductor
Field Effect Transistor (MOSFET) [19] The future of digital electronic industries has
been ldquobrightrdquo ever since the MOSFET was ldquobornrdquo as it has become a fundamental
building block component in complex microprocessors and flash memories Despite this
development the exploitation of Si at RF frequencies did not last long since Si is not an
optimum semiconductor for RF electronic devices The emergence of GaAs has
improved RF applications for high-speed transistors
Ge and Si which are categorised as single element semiconductor are the earliest
materials used to build the first transistor devices These devices played a crucial role
towards the development of more advanced material such as GaAs of the compound
semiconductor type[20] A compound semiconductor is a semiconductor formed by the
ionic bond of different types of semiconductor material most widely known as the group
III-V compound semiconductors The main reason for the progression of the III-V
compound semiconductors is due to their better electron mobility compared to the single
element semiconductors The term ldquomobilityrdquo in the semiconductor industry refers to the
easiness of movement of charges in many directions inside a crystal In fact it is
determined by the access resistances values with saturated velocity under certain values
of electric fields (bias) the higher the electric field the faster is the carrier movement in
the crystal Figure 21 shows the electron mobility and band gap for the most common
31
group III-V compound semiconductors Besides higher mobility III-V compound
semiconductors also have light-emission capability and are suitable for bandgap-
engineering techniques
The work on III-V compound semiconductors mainly on GaAs FETs led to a new
change for the whole RF electronics industry For example in 1966 the first GaAs
MESFET was invented[21] and achieved a maximum operating frequency of operation
of 3GHz [22] Three years later the frequency increased to 30GHz [23]
Figure 21 III-V compound semiconductors mobility and band gap[24]
With better features in terms of having a higher electron mobility compared to Si
electronic devices based on III-V materials developed rapidly This attracted attention in
many aspects especially in military radar application electronic warfare system missile
guidance control electronic for smart warfare system and secure communication To be
specific those demands were fulfilled through the application of microwave mixer and
detectors [25] which were achieved based on Schottky barrier diodes and FETs
However these applications remained largely as niche markets for use only in military
and exotic scientific projects until 1980 In addition to the microwave industry two
important diodes that played a large role in very high-frequency power source namely
the Gunn diode and the Impact Avalanche and Transit Time (IMPATT) diode which
were discovered in the 1960s[26]
100
1000
10000
100000
0 05 1 15
Bu
lk M
ob
ility
(cm
2 V
-1 s
-1
BandGap (eV)
InS
b
InA
s
Ge
Ga
Sb
In
GaA
s
Si
GaA
s
InP
32
Furthermore the invention of Molecular Beam Epitaxy (MBE) growth technique at
the beginning of 1970s has enhanced the full potential of the III-V compound
semiconductors[27] This technique has led to the formation of a new class of materials
and heterojunction device with high-quality interfaces and accurate control of the
thickness during growth[28] The advancement of material engineering that tailored the
III-V compound semiconductor with MBE effect has been beneficial for both three-
terminal and two-terminal devices As a result of this more advanced devices in both
electronics and optics were developed such as quantum well (QW) laser Resonant
tunnelling diode (RTD) high electron mobility transistor (HEMT) and many more[29]
The aim was to achieve high-speed devices transporting data at high data rates and
robust devices These devices promised an excellent option to conventional transistor
(three terminal devices) in high-frequency systems especially in the terahertz (THz) or
Millimetre and sub-millimetre wave regions [30]
One of the promising diodes that received a lot of attention is the resonant
tunnelling diode (RTD) which was first described in 1974 by Chang [31] This device
which consists of a double barrier and one quantum well is the classical tunnelling diode
Due to its good symmetrical non-linearity in its current- voltage characteristic it can be
exploited for signal generation and detection However the main focus of RTD to date
has been in the generation of continuous wave (CW) ultra-high frequency and to a lesser
extent in detection Therefore other tunnelling based diodes were developed specifically
for detection purposes which are the main foci of this work The PDB and ASPAT
diodes are the workhorse candidates for detection purposes Most of these are built based
on group III-V compound semiconductors [32]
Unlike the Very Large Scale Integration (VLSI) market ie CMOS for personal
computer (PCs) the RF electronic device for civilian application reached the consumer
market only in the late 1980s through satellite television with operating frequencies
around 12GHz [19] Since then many RF application have been deployed on the mass
market depending on their operating frequency such as 09GHz ndash 25GHz for wireless
communication 20GHz to 30GHz for satellite communication 77GHz for car radar
systems and above 90GHz for different sensor applications Utilising GaAs as the main
material RF devices have become the key underpinning components for modern
33
communication systems As a result in 1998 the volume production of mobile phones
was greater than that of PCs for the first time in history Presently production is being
made for devices like smartphones cellular phones mobile internet access and new
communication services and tablets
The development of the RF field is never ending More and more improvements are
being made especially through the design and fabrication of oscillators and detectors
which are mainly built based on group III-V compound semiconductors When RF
devices were used by the military (in the 1970s to 1980s) cost was not a concern
However after getting into civil application market (ie in the 1990s) the most frequent
issues highlighted were performance and cost[19]
The ability to generate or receive high operating frequencies with high power large
bandwidth and high sensitivity is an indicator for a good performance of RF devices
(depending on specific applications) For example the highest room temperature based
oscillator of up to 186 THz was achieved in thin well AlAs-InGaAs RTD by Professor
Masahiro Asada from Tokyo Institute of Technology [33] An excellent review on THz
sources can be found in [34] For ultra-high frequency detector and mixer applications
the two terminals RF device that is mostly used is the SBD In 1996 the highest cut off
frequency achieved by a mixer utilizing the SBD was about 5THz[35] and this has kept
increasing ever since The factor that motivates the development of THz devices is the
requirement to have a compact coherent source in the THz range Undoubtedly in the
future there will be very exciting times for enthusiasts of terahertz sources and receiver
as new generations of compact broadband and tuneable solid source device based on
advanced compound semiconductor are developed
23 The Concept of Heterostructures
A III-V compound semiconductor is mostly grown on a single semiconductor
substrate forming a layer called epitaxial heterojunction layer It is a starting point and
the key feature that brings the idea of realising the most advanced semiconductor
devices currently being developed and manufactured by combining several epitaxial
semiconductors [36-38] Heterojunctions have the capability of manipulating carrier
transport ie electron and holes transport in crystal separately unlike homojunctions
34
This has resulted in the successful development of new devices for high-speed and high-
frequency applications as well as optical sources and detectors [37] This section will
discuss lattice matched material pseudomorphic material hetero-junction band
discontinuities and quantum wells
231 Homojunctions Heterojunctions and Band Discontinuities
The term homo-junction refers to the interface between identical semiconductor
materials that have different polarity ie p-type or n-type but similar in energy gap This
phenomenon is usually applied in forming p-n junction diodes and can be understood by
referring to Figure 22 below
Figure 22 illustration of Homojunctions band structure material before (left) and after (right)
equilibrium
The materials A and B which have similar bandgap (Eg) and different dopant
types ie p-type and n-type will have their Fermi levels (Ef) closer to the valence band
(EV) and conduction band (EC) respectively before ldquothermal equilibriumrdquo Once
equilibrium is achieved Ef of both p-type and n-type will be aligned causing band
bending of EC and EV As a result a built-in electric field is introduced (via diffusion of
carriers) for both holes and electrons and forcing them to move in one direction
On the contrary a heterojunction occurs when the interface between two
semiconductor materials with different bandgap energy are brought together (ie large
energy band gap material combined with a low band gap one eg wide band gap AlAs
and narrow bandgap GaAs) This results in a steep band bending which leads to the
formation of energy band discontinuities at the junction as shown in Figure 23 In a
semiconductor heterojunction the most important parameter is the band gap energy
EC
EV
Ef
Eg
p-type E
g
n-type
EC
EV
Ef
Material A
p-type
n-type
Material B Material A Material B
35
associated with each material in the structure where the degree of discontinuity can be
utilised in varying the carriers transport properties as well as the quality of the junction
depending on the interest of the designer This leads to flexibility in tailoring device
characteristics leading to vastly improved performance of the device
Figure 23 Energy band diagrams before (left) and after (after) interface combination at
equilibrium
Based on Figure 23 above Material A indicated with blue line is a large band
gap energy material and Material B highlighted with the red line is a low band gap
material EV represents the valence band EC the conduction band and Ef is the Fermi
level of the materials Alternatively the two materials band discontinuities are denoted
by ΔEC for the conduction band and ΔEV for the valence band χ and Eg represent the
electron affinity and band gap energy respectively
At some point where by the Fermi energy of both semiconductor materials are levelled
the structure would have reached its thermal equilibrium The band gap of materials A
and B have a discontinuity at the interface (ΔEg) of these two materials In general this
is given by
120549119864119892 = 119864119892119860 minus 119864119892
119861 (21)
Furthermore when thermal equilibrium is achieved ΔEg is then divided between
conduction band and valence band discontinuities (ΔEC and ΔEV respectively) at the
material A and B junction interfaces Their relationships can be expressed as
EC
A
EV
A
Ef
A
Eg
A
Material A Material B
χA
χ
B
ΔEC
ΔEV
Ef
B
E
g
B
EC
B
EV
B
EV
A
χA
ΔE
C
ΔEV
EC
A
Ef
EC
B
EV
B
χB
Material A Material B
Vacuum
Level Vacuum
Level
36
∆119864119862 = 120594119860 minus 120594119861 (22)
∆119864119881 = (119864119892119861 minus 119864119892
119860) minus (120594119860 minus 120594119861) (23)
∆119864119892 = 119864119892119860 minus 119864119892
119861 = ∆119864119862 + ∆119864119881 (24)
However these relationships which were introduced by Anderson can only offer an
approximation In practice the results are always different since dislocation and
interface strain occur at the junction Therefore precise control during epitaxial growth is
always required and growth technologies such as MBE are employed In due course the
band gap discontinuity can be further exploited by using different types of material
combination Examples are GaAsAl052Ga048As and In053Ga047As In052Al048As [39]
232 Lattice-Matched and Pseudomorphic Materials
As discussed earlier a heterojunction happens when any two different
semiconductor materials that have different bandgap are joined together At the atomic
level both materials often differ in lattice constant The easiest way to explain this is by
setting the formation of heterojunction which can be separated into two types lattice
matched and lattice mismatched (pseudomorphic)
2321 Lattice Matched Systems
To create discontinuities for use as a high-performance device the combination of
semiconductor materials is essential Selecting the appropriate materials that have
similar or very close lattice constants to combine is crucial to avoid disruption at the
atomic level heterojunction interface Figure 24 shows that the lattice constant of a
material A ie substrate (aS) and material B ie deposited over layer (aL) are identical
or very close and their surface atoms are perfectly matched This scenario is known as
lattice matching
37
Figure 24 Lattice Matching for both materials when aL=aS
As can be seen in Figure 25 while there are restricted binary materials available to
form good heterojunction interfaces it is possible to combine semiconductor materials in
binary ternary and quaternary forms to allow the formation of a variety of lattice-
matched heterojunction interfaces The examples of materials that have successfully
been alloyed are In053Ga047As In052Al048AsInP and GaAsAlxGa(1-x)As (x=0 to 1)
Even though the materials system hetero-junction of these materials has close lattice
constant value their band-gap will experience an abrupt variation
Figure 25 Energy gap and lattice constant for direct and indirect band gap of compound
semiconductor at ambient temperature[40]
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
38
The existence of binary ternary and quaternary semiconductors formed by alloying
semiconductors has expanded the opportunity for heterojunction formation in devices
The alloy semiconductor which is produced by the combinations of two semiconductors
A and B has a lattice constant that obeys Vegardrsquos Law as follows
119886(119886119897119897119900119910) = 119909119886119860 + (1 minus 119909)119886(119861) (25)
For the alloy the band gap normally follows the virtual crystal approximation
119864119892(119886119897119897119900119910) = 119909119864119892(119860) + (1 minus 119909)119864119892(119861) (26)
Table 21 shows the list of the semiconductor alloy band gap and lattice constant for
common binary and ternary for group III-V compound semiconductors[41]
Table 21 Lattice constant (a) and band gap for group III-V binary and ternary compound
semiconductors a room temperature [41 42]
Alloy Lattice constant a(Aring) Band gap EgeV)
AlAs 5661 2239
AlSb 6136 1581
GaAs 5653 1424
GaN 3189 34
InAs 6058 0417
InP 5869 1344
Al052Ga048As 5657 2072
In053Ga047As 5868 0773
In052Al048As 5852 1543
39
2322 Pseudo-morphic Materials
The other scenario is when two different materials with different lattice constants
are brought into contact The observation can be made at the atomic level where the
atom will try to match each other as shown in Figure 26 below
Figure 26 Lattice mismatched material
In fact for both situations (ie lattice matched and lattice mismatched) the atom of
the material at the hetero-interface will change their position to maintain the geometry of
the lattice Due to distortion at this atomic level a strain is then induced at the hetero-
interface In order to form a good hetero-junction interface the strain must not exceed a
certain specific critical value which will cause crystal dislocations to occur The result of
crystal dislocation is generally bad as it will affect the carriers which will be
concentrated in the defect area thus degrading the carriersrsquo mobility This then makes
the overall function or performance of the device to become poor
Nowadays the Molecular Beam Epitaxial (MBE) technique is able to grow epitaxial
layers of mismatched semiconductor layers profile ie mismatched in their lattice
constant (aLneaS) The growth method works when the grown epitaxial layer assumes the
lattice parameters of the layer it is deposited on Nonetheless the layers must be kept
within a certain limit and the deposited layer must be thin enough to avoid defect or
dislocation formations This new layer known as a ldquopseudomorphicrdquo material will alter
its original crystal structure and physical properties
Material A(layer)
Material B(substrate)
aL
aL
aS
aS
40
Figure 27 The formation of Pseudomorphic-layer in two situations (a) compressive and (b) tensile
strain [1]
Figure 27 shows material A in which the pseudomorphic materials can be related to
two situations compressive and tensile strain The compressive strain occurs when the
deposited layer has a larger lattice constant than the substrate (aL gtaS) while tensile strain
happens when the deposited layer has a smaller lattice constant than the substrate
(aLltaS) These leads to aL either to compress or stretch to fit aS respectively Note that
the pseudomorphic layers can only be grown to a certain critical thickness hc From
Figure 27 the strain between the substrate and the deposited epitaxial layer is given by
휀 =119886119871 minus 119886119878
119886119878 (27)
Where Ɛ is strain between two layers aL is lattice constant of the deposited layer and
aS is lattice constant of the substrate layer The concern in deposition of the over layer is
to avoid dislocation occurring at the interface if there is too much strain at the junction
The strain is naturally influenced by the thickness of the deposited layer and thus the
thickness of growth must be controlled below the critical thickness hc which is
expresses as
(b)
41
ℎ119888 =119886119904
2Ɛ
(28)
Moreover one needs to appreciate that even though the crystal structure and their
physical properties change the total energy within the unit cell is maintained This is
possible by distortion of the deposited layer in the direction perpendicular to the growth
direction while leading to lattice matching in the lateral plane Example of lattice
matched materials is GaAsAlAs and pseudomorphic material is In08Ga02AsInP
233 Quantum well and 2DEG
A typical application of heterojunction interface is one in which utilises ΔEC and ΔEV to
form barriers for electrons and holes One example of barriers that confines these
carriers is known as a Quantum Well (QW) A QW is a layered semiconductor usually
very thin ie about ~ 100 Aring thicknesses in which many quantum mechanical effects can
occur It is formed by a thin layer of a low bandgap energy semiconductor material eg
GaAs sandwiched between two similar large bandgap energy semiconductors eg AlAs
or AlGaAs The growth technique to achieve thin layers of QW is usually MBE The
benefit of this method is that it allows the formation of heterojunction with very thin
epitaxial layer
Figure 28 The band diagram of an ideal quantum well formed by a narrow band gap
semiconductor eg InGaAs sandwiched between two large band gap semiconductors eg GaAs (a)
Structure (b) energy band diagram and (c) Conduction band diagram when AlGaAs is n-doped[43]
42
The thickness of the layer that can be achieved can be as thin as the electron mean free
path (De Broglie wavelength) which is around 100 Aring to 300 Aring [44] The expression for
the De Broglie wavelength is given by
120582 = ℎ120588frasl (29)
Here h and ρ are Planckrsquos constant and momentum of the electron respectively Figure
28(b) illustrates a quantum well formation in abrupt semiconductor interfaces It can be
observed that the heterojunction boundary will experience discontinuities at the edges of
the conduction band and valence band with a quantum well generated for the carriers
(both electron and holes) The quantised energy sub-bands in the quantum well structure
in Figure 28(b) can be determined from [43]
119864 = 119864119899 + (
ℏ2
2119898lowast) (119896119909
2 + 1198961199102)
(210)
Where 119864119899 = (ℏ21205872
2119898lowast ) (119899
119871)2
and n is the energy level index that can be n=1 2 3hellip
The dopants in a semiconductor with large band gap layers may supply the
carrier to the quantum well and this occurs when the base or bottom of the quantum well
is lower than the Fermi Level and hence the high energy donors will go down to the
well therefore creating a Two-Dimensional Electron Gas (2DEG) In the 2DEG the
electrons and holes move freely in the quantum well in the plane perpendicular to the
growth direction however they are not capable of moving in the crystal growth
direction (confinement direction)[45 46] The 2DEG phenomena can be seen in Figure
28(c)
24 Metal-Semiconductor Contact
A semiconductor device is incomplete if there is no connection between the
semiconductors and the outside world A metal which is usually gold (Au) or gold
germanium (AuGe) is diffused into the semiconductor to allow for electrical connection
from the outside world to the semiconductor and vice versa The metal-semiconductor
contact can be either a Schottky contact or an Ohmic contact The Schottky contact is a
43
rectifying contact while the Ohmic contact is a contact that provides a low resistance
path between semiconductor and metal
241 Schottky Contact
The Schottky contact is basically a metal contact to the gate to enter a region or
channel in a transistor Figure 29 shows a schematic band diagram of a metal-
semiconductor contact before and after contact (Schottky-Mott concept)[47]
Figure 29 Metal and semiconductor in two conditions (a) separation (b) in contact
In Figure 29 the work function of the metal is represented by qm while the
semiconductor work function is qS The qχ is the energy difference of an electron
between the vacuum level and conduction band edge ie known as the electron affinity
and qVn is the difference between the conduction band and Fermi level in the
semiconductor EV EC Ef is the valence band energy conduction band energy and the
Fermi level respectively
The metal and semiconductor are brought together as showed in Figure 29(a)
both materials are at steady state However when the metal and semiconductors are in
contact as illustrated in Figure 29(b) the electrons that flow from the conduction band
in the semiconductor into the lower energy state of the metal will cause the Fermi level
to be aligned in thermal equilibrium Due to this process the positive charge donor is
trapped in the semiconductor interface hence forming a depletion region Xdep
Thereafter the upward bending of the energy in the semiconductor takes place On the
qχ(s)
Eg(s)
Vacuum Level
EV
EF(m)
E
F
EC
qϕ(m)
qϕ(s)
Metal Semiconductor
qVn
qϕB
qϕ(s)
qVbi
X
qχ(s)
Eg(s)
Vacuum Level
EV
EF
EC
qϕ(m)
Metal Semiconductor
Xdep
(a) (b)
44
other hand the negative charge (electron) will be accumulated within a narrow region in
the metal interface The existence of two different charges at the metal-semiconductor
boundary generates an electric field This leads to a potential barrier qB as seen by
electrons in the metal moving into the semiconductor and a built-in potential qVbi as
seen by electrons in the semiconductor trying to move into the metal
The built-in potential qVbi is defined as follows
119902119881119887119894 = 119902empty119861 minus 119902119881119899 (211)
The barrier height empty119861 in the ideal case is specified by the dissimilarity between a metal
work function empty119898 and electron affinity of the semiconductor
119902empty119861 = 119902empty119898 minus 119902120594 (212)
Referring to Eq (212) above the barrier height empty119861 rises linearly with the metalrsquos work
function empty119898 Nevertheless this is only in theory as the presence of localised surface
stated at the edges causes empty119861 to become unresponsive to the metal work function
Consequently Eq(211) is then reordered to match the difference in metal and
semiconductor work function Thus the new equation becomes
119902119881119887119894
= 119902(120601119898 minus 120601119904) (213)
A Schottky contact appears when a metal-semiconductor contact has a large
barrier height (B ge kT) and low doping concentration in the semiconductor (ND le NC) In
the case when the metal-semiconductor contact is under some bias eg reverse bias the
semiconductor will react to a positive bias according to the metal by a voltage V=-VR
This condition will affect the built-in potential and leads to increase from Vbi to
(Vbi+VR) thus increasing the barrier height empty119861 in the semiconductor as well
Consequently electrons are less able to flow from the semiconductor and cross into the
metal Therefore the current flow will be very small This phenomena is shown in
Figure 210(a)
45
Figure 210 Energy band diagram of Schottky contact on n-type material under (a) reverse and (b)
forward bias
As can be seen from Figure 210(b) when a forward bias is applied the semiconductor
is biased negatively with respect to the metal by a voltage V=Vf This will result in a
reduction in built-in potential from Vbi to Vbi-Vf The electrons in the semiconductor will
lower the barrier height and a lot of electrons will escape into the metal causing a large
current to flow Thus a large current flow in the forward direction compared to the
reverse direction Essentially this is the origin why the Schottky contact is named a
rectifying contact [48 49] For the metal side both forward and reverse biases applied
do not affect the barrier high empty119861 because there is no voltage drop there
In this system the electron and holes are transported by a phenomenon called
Thermionic Emission (TE) which happens when the semiconductor layer is lightly
doped Nd lt 1x1017119888119898minus3 The electron will only be thermionically emitted into the metal
when the energy is higher than the potential barrier[50] There is another phenomenon
called Thermionic Field Emission (TFE) which happens when the potential barrier
thickness is very thin (thin enough) to allow the electron to tunnel through the barrier
This will be discussed in the next section as this phenomenon leads to the formation of
an ohmic contact
(a) (b)
46
242 Ohmic Contact
Basically an ohmic contactrsquos purpose is to provide a low resistance path from
the semiconductor to the outside world It is different to a Schottky contact as it is a non-
rectifying contact and does not control the current flow the I-V characteristic of an
ohmic contact is linear in both forward and reverse directions (equality in current flow)
The ohmic contact also has a small voltage drop across it compared to the voltage drop
across the device
If a metal and semiconductor are bought together unavoidably a Schottky
contact will be formed Therefore to create an ohmic contact some techniques to reduce
barrier height and width of the depletion region must be used ie increase Nd In carrier
transport theory there are three mechanisms of carrier transport across the barrier
Firstly the Thermionic Emission (TE) which happens when the carries are excited to
overcome the barrier when the thermal energy is present Secondly the Thermionic
Field Emission (TFE) occurs when the electronholes have enough energy to tunnel
through an adequately thin barrier and some has overcome the low barrier at the top
Finally the Field Emission (FE) which results when carriers can tunnel through the
entire barrier The FE is the most favoured mechanism in the ohmic contact approach
[51]
From the three mechanisms above the current can be determined by the following
equations
1) Current in Thermionic emission (Figure 211(a))
exp (empty119861)
119896119879
(214)
2) Current in Thermionic field emission (Figure 211(b))
exp [
(empty119861)
11986400119888119900119905ℎ11986400
119896119879
] (215)
3) Current in Field Emission (Figure 211(c))
exp (empty119861)
11986400
(216)
47
Where k is the Boltzmann constant T is the temperature 11986400 is the tunnelling parameter
and is related to the doping concentration radic119873119863 The barrier height is denoted by empty119861
Figure 211 Figure 10 N-type semiconductor Ohmic contact with different doping concentration
ND (a) Low (b) Intermediate and (c) high
Figure 211 shows that the carrier transport mechanism is varied by the doping
concentration (ND) As can be seen from Figure 211(c) the doping concentration here is
the highest and influences the depletion region width Xdep to become smaller Therefore
Field Emission (FE) becomes dominant This FE method is the favourite method for
ohmic contact formation [51] and will be utilised in the fabrication carried out in this
work
In fabricating practical devices the ohmic contact is often split into two types
alloyed and Non-Alloyed The difference between the two is that the alloyed type is used
when the semiconductor is doped with a low doping concentration ie less than
1x1018119888119898minus3 while the Non-Alloyed is designed for heavily doped semiconductors with
more than1 times 1019119888119898minus3 doping
The alloyed ohmic contact requires thermal annealing to have a good performance
for electron transport In multi-layer metals one of the metals has the role of donor or
acceptor which is used to increase the doping concentration of the semiconductor If a
temperature anneals eg 420˚ Celsius is applied the metal will diffuse into the
semiconductor and carry the dopant into the semiconductor Therefore a heavily doped
region will be formed and the depletion width becomes narrow establishing the ohmic
contact The key example of this is the usage of the Gold-Germanium-Nickel (Au-Ge-
Ni) alloy where the Ge is the n-type dopant [52] which diffuses into the semiconductor
(a) (b) (c)
48
and perform atom replacement in the semiconductor ie in GaAs it replaces Ga On the
other hand the Non-Alloyed does not require any thermal annealing as it already has a
very high doping concentration and will automatically reduce the depletion region width
The Non-Alloyed ohmic contact has some advantages such as reproducible contact
reduced processing time and good uniformity [53]
25 Asymmetrical Spacer-layer Tunnel (ASPAT) diode Background work
In this section some historical background of the Asymmetrical Spacer-layer
Tunnel (ASPAT) diode is given Since this is the first thesis reporting about this new
device it is worth to mention some historical background about this tunnelling diode
The ASPAT was first proposed by a group of scientists from General Electrical
Company (GEC) in 1990[16] The works led by Richard T Syme and assisted by
Michael JKelly Angus Condie and Ian Dale initiated the idea of launching a new type
of tunnel diode The idea managed to attract the interest of many parties following the
development of resonant tunnelling diode (RTD) which earlier had shown a promising
weak temperature dependence [54] However the interest in RTD is mainly limited to
microwavesub-millimetre wave generation For THz detection the requirement is to
have a significantly asymmetric IV characteristic Given this the ASPAT which has
only a single energy barrier and most importantly weak temperature dependence and
large dynamic range would be a promising candidate for this application
The development of ASPAT is a kind of reverse engineering since it was built
purposely to replace the earliest receiver diode especially the Schottky Barrier Diode
(SBD) which has strong dependence on operating temperature [55] From the time when
it was first revealed a lot of works have been done to realise this most sophisticated
tunnel diode The first attempt which was reported in [56] was meant to gather some
insights into the device by using the well-known Schrodinger and Poissonrsquos equations
for simulation The second attempt on the other hand was directed to physically grow
and fabricate the device Here the real problem occurs At the first stage of qualifying
this device it was found not to be manufacturable Since then a new tunnel diode
structure based on GaAsAlAs materials system was built by both MBE and MOCVD
Its microwave performance was then tested at 94GHz [18] The same paper also
49
reported performance comparisons between ASPAT and another microwave diode ie
Germanium Backward Diode (GBD) PDB and SBD
Work on these devices stopped due to the inability to commercialise the ASPAT
and other tunnel based devices [57-60] The problems associated with low-cost
manufacture of tunnel diodes are due to firstly the thickness of the AlAs barrier layer
the dependence of tunnelling probability (electron) through a single barrier is
exponential and varies by a factor of more than 350 for one monolayer change in the
AlAs barrier thickness[61] The tunnelling of the electron through a barrier is
proportional to the current through a barrier as a function of a bias across the AlAs
barrier[62] Secondly the bandgap which is predominantly happens to be a ternary alloy
with relative composition ie AlxGa1-xAs Here the x can vary the bandgap in the
semiconductor layer For the ASPAT a 1 change in x results in a 30 change in the
current[62] To design an ASPAT for microwave and THz applications the designer
often allows at most plusmn10 variation of the absolute current through a specific diode at a
pre-identified bias This implies that within a wafer the uniformity that the ASPAT must
achieve is less than plusmn01 monolayers while between wafer to wafer the reproducibility
in barrier thickness in average must be identically controlled[63] This explains why at
the qualification stage of investigating ASPAT there was a need to focus on
GaAsAlAs-based material to diminish further errors because of the change in x This
type of work on ASPATs has been carried out by other co-workers at Manchester and
Cambridge
Thereafter the work then focused on repeatability and manufacturability tests
These result in many attempts being carried but failed with unacceptable between wafer
to wafer reproducibility [61 64] The development of reproducibility and repeatability of
the ASPAT was pursued for over 10 years until precise control of the growth of the
thickness AlAs layer was finally achieved using MBE[65] [66 67] This achievement is
confirmed by a current density produced which varied by less than plusmn30 indicating that
the reproducibility of AlAs barrier of the order of plusmn 02 monolayers A final step to
achieve the level control for the ASPATrsquos AlAs barrier thickness was carried out and
resulted in a 1 standard deviation of the IV characteristics for both within a wafer and
different wafer (2 inches wafer size)[17] In the early stage of this work some
50
repeatability and manufacturability test was also carried out Once this vital step is
accomplished further investigation on the ASPAT was made most recently and which
will be covered in this thesis ie temperature independence[68] and new ASPAT
types[69] characterisation to achieve smaller device RF measurement and development
of THz detectors The material systems that have been investigated so far are
GaAsAlAs and InGaAsAlAs both in the ManchesterCambridge group
Recently the ASPAT was commercialised by Linwave Technology as a wideband
zero-bias detector diode This was done in April 2016 Although it is now on the market
the ASPAT remains immature in term of research and development A lot of work is still
required to enhance the device ie working at the sub-millimetre wave using ternary
material etc
26 Asymmetrical Spacer-layer Tunnel (ASPAT) diode The Basics
The basic building block of the ASPAT diode is based on heterojunction of three
multilayer semiconductor structures which have two different band gaps The structure
comprises a thin layer of wider-gap semiconductor sandwiched between two
semiconductors with narrower-gap forming a tunnel barrier The basic principle of the
ASPAT device is based on the exploitation of quantum mechanics theory using
heterojunctions interface According to quantum mechanics theory moving particles
(electrons) with less energy than the barrier height have a probability of appearing on the
other side of the barrier by a tunneling through it This can be achieved in conditions
where the barrier must be very thin (~ 10 monolayer ) This is in contrast to classical
physics where a particle must have kinetic energy at least slightly greater than the
potential barrier height in order to overcome the barrier otherwise the probability of the
particle to appear on the side of the barrier is zero
Since the ASPAT diode operation is based on tunnelling through a barrier one
needs to know that the tunnelling mechanisms can be classified into two types[44]
intraband and interband The latter is described as tunnelling that occurs from
conduction band to valence band (electron) and valence band to conduction band (holes)
This normally happens in bipolar device ie p-n junction diode which has n-type and p-
type doped regions On the other hand intraband refers to tunnelling which occurs when
51
electron tunnel from the conduction band of a semiconductor to the conduction band of
its neighbouring semiconductor The same thing happens to the holes in the valence
band The device with this type of tunnelling is normally a unipolar device which is
either p-type or n-type doped The ASPAT diode can be considered as a device that is
based on intraband tunnelling mechanism Therefore the focus will be entirely based on
its principles
261 Principle of Quantum Tunneling
Generally all tunneling diodes obey the concept of quantum mechanical
tunneling Quantum mechanical tunneling is a phenomenon where a particle is able to go
through an energy barrier higher than the kinetic energy of the particle and if it is thin
enough compared to the de Broglie electron wavelength (λ) If the electron wave is
greater than the barrier the probability of the wave to occur at both side of the barrier is
higher
Figure 212 Classical view of whether an electron is can surmount a barrier or not Quantum
mechanical view allows an electron to tunnel through a barrier The probability (blue) is related to
the barrier thickness
For the case of classical physics (Figure 212(a)) the particles can be confined by
energy barriers of a semiconductor if their kinetic energy is less than the barrier energy
The particles thus require higher kinetic to escape to other states this phenomenon is
called thermal emission In quantum mechanics (Figure 212(b)) the particle is
described in two ways as a wave and as a particle If the particle moves like a wave it
will carry all the waversquos properties Therefore it will not brusquely end up at the
En
erg
y
(a) Classical view (b) Quantum mechanical view
En
erg
y
En
erg
y
52
boundary of the energy barrier Hence when the particles collide with the barrier
(incidence) there will be a probability of penetrating the barrier if the barrier is thin
enough and has a finite height For thicker barrier the probability of a wave that can be
found on the other side of the barrier is very small However the possibility of the
electron wave to appear on the other side of the barrier is increased by thinning the
barrier The potential barrier of semiconductor material technology can be determined by
using Homojunctions structures with different doping profile This will result in a
difference in band alignment and multilayer heterojunction structure (different
semiconductors have different band gap) which includes semiconductors insulators and
conductors (metals)
The easiest way to explain the phenomenon is by considering a potential barrier
Epot(x) with barrier height E0 energy bigger than the total energy E as shown in Figure
213 the potential energy occurs in a finite space between 0ltxlta and is 0 outside
Figure 213 Rectangular tunnelling with incident reflected and transmitted wave function[70]
The electron outside the region of the potential barrier (xlt0 and xgta) is free to
move The effective mass of the electron is different inside and outside of the barrier in
real tunneling devices when implemented using semiconductor heterostructures The
quantum mechanical equations predict the wave nature of matter which states that matter
unveils wavelike properties under some conditions and particle-like properties under
other conditions The wavelike properties as described by the Schrodinger Formula of
E0 Transmitted Ψ = 119862119890minus119894119896119909
Incident Ψ = 119860119890119894119896119909
Reflected Ψ = 119861119890minus119894119896119909 Ψ = 119863119890minus119894119896119909
0 a
E
x
V(x
)
53
quantum mechanics represent a particle penetrating through a potential barrier most
likely as an evanescent wave coupling of electromagnetic waves[44]
To start the calculation of the tunnelling probability the Schrodinger equation is given
by
119894ℏ
120597
120597119905Ψ(119903 119905) = ΨΗ(r t)
(217)
Where ℏ is Planckrsquos constant (662606957 times 10119890minus341198982119896119892119904
2120587frasl ) Ψ(119903 119905)is the wave
function at position r and time t Η is the Hamiltonian operator given by
Η = minus
ℏ2
2119898nabla2 + 119881(119903 119905)
(218)
Where 119881(119903 119905)is the potential energy which is dependent on space and time 119881(119903 119905) is
considered zero for a particle traveling in free space without any potentials The plane
wave with vector r and t is given by
Ψ(119903 119905) = 119890119894(119896119903minus120596119905) (219)
This equation satisfies Eq (217) above under the condition where the particle is
travelling in free space without potential k is the wave vector which is equivalent
to2120587120582frasl and the angular frequency 120596 is 2120587 multiplied by the frequency
In the case of tunneling through a potential barrier the method of separation of
variables is used to simplify the problem as in the equation below
Ψ(119903 119905) = 119877(119903)119879(119905) (220)
It is assumed that the problem above is divided into time-dependent and time-
independent parts 119877(119903) is the spatial component and 119879(119905) is the time-based component
of the wave function The time dependent problem as shown above in the Schroumldinger
Equation (1) can easily be solved by filling up all the finite parameters The solution of
54
the time-independent part gives the tunneling probability For the one-dimensional (1D)
time-independent Schroumldinger equation[44]
119864120595(119909) = minus
ℏ2
2119898
1198892
1198891199092120595(119909) + 119881(119909)120595(119909)
(221)
E is the total energy and 120595(119909)is the spatial component of the wave function along the x
axis The combination to the wave function is given by
120595(119903 119905) = 120595(119903)119890minus(
119894119864119905ℏ
)
(222)
The time-independent plane wave solution of 120595 = 119890119894119896119909 satisfies the equation (221) for
any constant potential V0 in space Plugging in the wave solution yields the condition
that
119896 = radic2119898lowast(119864 minus 1198810)
ℏ2
(223)
Referring to Figure 213 also the barrier with exact rectangular shape with height E0 and
width W the solution of the wave functions and tunneling probability can be extracted
by using the below equation [44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2= [1 +
11986402 sin ℎ2 (119896119882)
4119864(1198640 minus 119864)]minus1 asymp
16119864(1198640 minus 119864)
11986402 exp(minus2radic
2119898lowast(1198640 minus 119864)
ℎ2119882)
(224)
For more complex barrier shape Wentzel-Kramers-Brillouin has simplified the
Schrodinger equation for tunneling probability of carrier which becomes[44]
119879119905 =
[119862119890minus119894119896119909]2
[119860119890119894119896119909]2asymp 119890minus2int |119896(119886)|119889119886
1198860 asymp 119890
minus2int radic2119898lowast
ℎ2 [119880(119886)minus119864]1198891198861198860
(225)
55
This means that the incident electron has a finite probability T of tunneling
through the potential barrier and this leads to the concept of tunneling probability as well
as a tunnelling current Therefore this becomes the basis of tunneling phenomena and
thus all devices which are related to tunneling can be modelled and analysed based on
this basic example The tunneling phenomenon is a majority-carrier effect and the
tunneling time is set by the quantum transition probability per unit time (which is on the
order of picoseconds) rather than the transit time concept [44 71] This enables the
tunneling devices to work at a much higher switching speed They can also be used in
high-frequency applications such as microwave circuit and high-speed oscillators
262 ASPAT Structural Parameters of GaAsAlAs materials System
Figure 214 Epitaxial layer structure of device XMBE 304 (lateral structure) used in this study
Conduction band profile
56
The core materials that make up the ASPAT diode in this work is based on
heterostructure of group III-V compound semiconductors Such materials are chosen due
their mature excellent properties and their band gap which can be tailored to fit the
desired design as well as to improve the carrier mobility In this work the primary layers
that form an ASPAT diode are very thin pure Aluminium Arsenic (AlAs) of thickness
ten monolayers buried in between dissimilar thickness of pure Gallium Arsenic (GaAs)
layers as can be seen in the red circle in Figure 214 above These two GaAs layers are
known as spacer layer which normally have a ratio of 401 or 201 in thickness The
asymmetrical spacers layer and the thin barrier in such arrangement lead to an
asymmetric current-voltage characteristics as proposed firstly by Syme and Kelly[15]
To examine and investigate this GaAsAlAs ASPAT structure in term of electrical and
RF characteristics the device have been grown according to Table 22 below
Table 22 epitaxial layer of sample XMBE304 which is the main focus of this work
Material Doping (cmminus3) Thickness (Aring) Bandgap (eV)
Ohmic Layer GaAs (Si) 4times1018 3000 142
Emitter GaAs (Si) 1times1017 400 142
Spacer GaAs Undoped 50 142
Barrier AlAs Undoped 28 283
Spacer GaAs Undoped 2000 142
Collector GaAs (Si) 1times1017 400 142
Ohmic Layer GaAs (Si) 4times1018 4500 142
Substrate GaAs - 650 microm 142
The arrangement of the multi-layers that form a lattice matched GaAsAlAs ASPAT
diode can be transformed into band structure profile view for easy understanding The
conduction band profile at equilibrium is as sketched in Figure 214 As can be seen in
the Figure 214 the ASPAT diode is generally a heterojunction multilayer structure
tunnelling diode
57
Figure 215 The layer profile of ASPAT with 28nm barrier thickness [27]
The generic structure of ASPAT diode which is shown in Figure 215 above with a
schematic band structure comprises the following (starting from the top)
(1) A thick layer of heavily doped n++
about 4e+18cm-3
of GaAs with a thickness of
approximately 300nm
(2) An intermediate layer of lightly doped n-type about 1e+17cm-3
of GaAs with
thickness of approximately 40nm
(3) A spacer layer not intentionally doped (NID) GaAs with thickness of approximately
5nm
(4) An ultra-thin layer of NID AlAs with thickness of approximately 28nm
(5) A spacer layer of NID GaAs with thickness of approximately 200nm
(6) An intermediate layer of lightly doped n+ ~1e+17
GaAs with thickness of
approximately 40nm
(7) A thick layer of heavily doped n+ about 4e+18 of GaAs with a thickness of
approximately 750nm
Each layer has its own role For instance layer (1) and (7) are used as ohmic
contacts via connection to a AuGeNiAu metal stack This explains why they are
purposely heavily doped (gt 1018
cm-3
) for better low resistance ohmic contacts Two
intermediate layers (layers 2 and 6) are used to prevent the carrier in the contact layers
from diffusing into the undoped layers The two unequal length spacer layers with ratio
58
1198971 1198972 of about 401 are used as voltage arms to yield an asymmetric current-voltage
characteristic The asymmetry means that after a positive bias is applied from the long
spacer region an accumulation layer is formed and it is deeper than that formed by the
negative bias The thin layer positioned in the middle (Layer 4) is the tunneling barrier
The performance of a single barrier ASPAT diode can be optimised depending on
the applications by appropriate selection of the material system so that the band gap and
barrier height of such material can be modified Furthermore the mobility of electron
and doping concentration of the contacts region can be tuned The parameters to tune
during the growth for instant growth interrupt time and growth temperature will also
affect the performance of this diode The key layers that will affect the performance are
the barrier thickness and the two spacer layers enclosing it The study has shown that a
one monolayer change in thickness results in 300 change in in tunneling current for a
fixed voltage point[65]
The following discussions account for the effect of the main structure of the ASPAT
which is related to their performance
2621 Barrier Thickness and height
The probability of an electron tunnelling through a barrier depends exponentially on
the width and height of the barrier as well as the energy that is incident on the barrier[72
73] All these will affect the I-V characteristic of the ASPAT diode The tunnel current is
obtained by summing over all incidents electrons energies with tunnelling probabilities
through the barrier The tunnelling varies approximately as[74]
119879 prop 119890minus120581119889 (226)
Where d is the barrier thickness and κ is defined by the expression below
120581 =
radic2119898lowast(1198810 minus 119864)2
ℏfrasl
(227)
From textbook the tunnelling probability is given by
119879(119864) = 412058121198702
[(1205812 + 1198702)2119904119894119899ℎ2119870119897 + 412058121198702]frasl (228)
Where K is expressed as
59
119870 = radic2119898lowast119864
ℏfrasl (229)
Where ℏ represents the reduced Planckrsquos constant (h2π) E and m are the electron
energy and effective mass respectively Thus by inputting appropriate value into these
equations one finds that reducing the barrier thickness by one monolayer increases the
tunnelling probability by a factor of nearly three for every electron that tunnels through
the barrier As a result the current will also increase Further it indicates that the
tunnelling strongly depends upon barrier thickness and height By contrast the current
does not strongly depend on temperature
2622 Spacer Thickness
The reason for having two dissimilar undoped spacer lengths is mainly to avoid
diffusion of dopant to the barrier and subsequent layers during growth but in the case of
the ASPAT diode the spacer can also act as a voltage arm Varying the thick spacer
layer (1198971) results in the reverse current decreasing as the layer thickness increases and
varying the thin spacer layer (1198972) will affect the forward current which increases as the
thickness reduces To obtain appropriate asymmetrical I-V characteristics one needs to
maintain an adequate ratio between these two spacer thicknesses While a too thin
1198971 results in high leakage current at reverse bias a too thick 1198972 results in low forward
current One also needs to keep it thick enough to prevent carrier diffusion
These two spacers must be kept undoped or very low doped to allow the electron
moving in the electron mean free path region as it is clear from ionised donors Under
large forward bias an accumulation layer is formed between the spacer and barrier
segment and it is more noticeable compared to the accumulation layer that is formed if a
negative bias is applied
60
Figure 216 Conduction band diagram showing band bending and 2DEG formation at the L1
spacer
Consequently a triangular well is formed which creates an emitter 2D electron gas
(2DEG) population The electrons in this 2DEG occupy the quasi-bound states which
mean high excitation energy thus allowing the electron to tunnel through the barrier as
depicted in Figure 216
In term of RF performance it is important to highlight that a thicker spacer layer
will affect the depletion region which gets wider and thus will reduce the junction
capacitance of the device as per the following expression
119862 = 휀0휀119903
119860
119889
(230)
Where A is the area of the device d is the thickness of the main device structure which
consists of spacers barrier and well layers 휀0 is the permittivity of free space and the
relative permittivity of the spacer material is denoted by εr However the intrinsic delay
time will also increase and hence degrade the device high frequency performance
Therefore optimisation through spacer thickness requires trade-off between reducing
leakage current at reverse bias and degrading device junction capacitance
GaAs
GaAs
AlAs
2DEG
Γ
X
61
263 ASPAT Electrical Parameters
The classical approach in determining the current flow through an ASPAT diode is
by solving the Schrodinger and Poison equations Prior work had been done by Syme et
al in 1991 Due to the fact that AlAs barrier is very thin tunnelling is assumed to occur
at the Gamma valley ie AlAs bandgap= 283eV (rather than X valley)[18 75] and only
from accumulation layer (2DEG)[59] Here the DC characteristic of the ASPAT diode
can be calculated by solving Schroumldinger equation with the position vector represented
by z (in this case) Thus the equation is expressed as
minus
ћ2
2nabla
1
119898lowast(119911)nabla120569 + |119890|120593(119911)120569 = 119864120569(119911)
(231)
Supposing the current is uniform across x and y planes then this can be simplified to one
dimension Therefore the 1 D Schroumldinger equations becomes
minusћ2
2119898lowast
1198892
1198891199112120595 + |119890|(120595 minus ∆120595) = 119864119911120595
(232)
Where
120595 =
120569
exp (119894119896119911119911)
(233)
where ∆120595 is the correction term which reduces the effective barrier height The
Schroumldinger equation is solved using different values for Ez thus the quantum
mechanical current density in the z-direction is now expressed as[15]
119895119911 =
minus|119890|ћ
2119898lowast(120595lowast
119889120595
119889119911minus 120595
119889120595lowast
119889119911 )
(234)
It is different for a heavily doped contact which can describe as below the envelope
functions in the left and right contacts respectively can be described by plane wave
120595119897 = exp(119894119896119897119911) + 119877 exp(minus119894119896119897119911) (235)
120595119903 = 119879119890119909119901[119894119896119903(119911 minus 120580119873)] (236)
62
In this case the left contact covers the region zlt0 while the right contact covers the
regions zgt 120580119873 Equations (35 and 36) are then inserted into Eq (34) to form the
following expression
119895119911 =
|119890|ћ1198961
119898lowast(1 minus |119877|2) =
|119890|ћ1198961
119898lowast|119879|2
(237)
Where R (Ez) and T (Ez) are the complex reflection and transmission coefficients
respectively and they are solved by using the transfer matrix method This method has
been described in reference [56] The next step is to integrate the current in the z-
direction 119895119911 for all possible Ez values Thus the expression for the current density
becomes
119895119911 =|119890|119898lowast119896119861119879
2120587ћ2int(1 minus |119877|2)
infin
0
119897119899 |1 + exp (
119864119891 minus 119864119911
119896119861119879)
1 + exp (119864119891 minus 119881|119890| minus 119864119911
119896119861119879
|
(238)
The equations above are used to calculate the current density approximation from
the ASPAT main structure (two spacer layers and one barrier) only and based on
intraband tunnelling from the conduction band profile For real fabricated structure the
calculation must take into account both intrinsic and extrinsic elements of the diode
While the latter is mostly related to the pad and probe that is used to extract the I-V
characteristic the first element mostly comes from the epitaxial layer of the ASPAT
diode itself The ASPAT I-V characteristic is shown in Figure 217 which clearly
indicates nonlinear characteristics and thus can be used for detection applications
63
Figure 217 I-V characteristics of a fabricated ASPAT diode
2631 Intrinsic Elements of the ASPAT diode
In order to extract the intrinsic electrical characteristic of the ASPAT diode a
generic structure as shown in Figure 218 is essential Two main sources of contribution
to the electrical characteristics are the interfaces of each layer and properties of the
materials themselves
Figure 218 Intrinsic Elements of the Asymmetric Spacer Tunnel Layer (ASPAT) Diode
64
The electrical current flowing from the top contact to the bottom contact will go
through each epitaxial layer producing a close loop Each junction interface limits the
current flow and sum up the total resistance resulting in what is known as the diode
series resistance (Rs) In the ASPAT main structure there is a junction capacitance (Cj)
due to the undoped regions surrounded by heavily doped contacts thus acting as a
parallel plate capacitor The fully depleted capacitance (Cj) of the diode can be
expressed as in Eq (230)
2632 Series resistance of the ASPAT diode
The total series resistance (Rs) of an ASPAT diode can be calculated based on the
finished fabricated diode structure In general Rs depends on three contributors namely
the non-uniformities in the contact metallization the un-depleted epitaxial layer (total
thickness) on both side of the heterostructures and the resistance caused by the
spreading current from the Mesa into the much wider second contact layer ie doped
substrate or 2nd
ohmic layer[76] In fact the contribution toward building up the total Rs
solely depends on how the structure is designed In this work two types of structures
were deployed namely lateral structures and vertical structures These will be described
in the next subsection
For both types of structures the series resistance (Rs) of the ASPAT diode consists
of aspecific Ohmic contact resistance (ρcA) contact epitaxial layer resistance (Repi-
Layers) and spreading resistance (Rspr)[33 77] where Rspr is influenced by the type of
structure The specific contact resistance is obtained from Transmission Line
Measurements (TLM) of the sample The theory of the TLM will be discussed in detail
in the next section The expression for the specific contact resistance is
120588119888 = 119877119888119871119879119908sinh119889
119871119879frasl
cosh 119889119871119879
frasl
(239)
Here Rc is the contact resistance LT is the transfer length (effective length) w is the
contact pad width and d is the length of the contact pad
65
Repi-Layer is the sum of all doped layers that sandwich the main ASPAT device For
each doped layer the resistance is given by
119877119890119901119894minus119897119886119910119890119903 = 120588
119871
119860
(240)
Where ρ is the resistivity which is given by 120588 = 1
120583119899119902119873119863 L is the epitaxial layer thickness
in cm A is the device area (emitter size) micron denotes the mobility of the electron q is the
electron charge and ND is the donor concentration The spreading resistance depends on
the structure design of the device This will be elaborated in detail in the following
section
26321 Vertical structure (doped Substrate)
The XMBE307 structures were grown on n+ GaAs substrate to provide the
simplest fabrication process The cross section of the finished single diode can be seen in
Figure 219 below
Figure 219 Cross-sectional view of ASPAT vertical structure the dimensions of d b and h are not
drawn to scale
66
At low frequency and in a mesa that is etched into a doped substrate material the
spreading resistance can be approximated by[76]
119877119904119901119903 =120588119904
2119889
(241)
Where ρs is the substrate resistivity and d is the ASPAT diode mesa length
However the spreading resistance is increased at high enough frequencies as the skin
depth (δ) in the substrate is much lower than the effective mesa length (d) of the diode
A new spreading resistance is then calculated also based on the assumption that the skin
depth is much lower than the chip thickness (h) but much larger than the mesa length
Thus the spreading resistance at high frequency is given by
119877119904119901119903(119891) =
120588119904
120587120575[05 ln (
119887
119889) +
ℎ
119887]
(242)
Where the skin depth (δ) is taken from standard planar formula and can be expressed as
120575 = [
2120588
(120583120596)]
12frasl
(243)
Where micro is the permeability and ω is the angular frequency During DC measurement
this type of structure requires having good suction on the stage for a good contact
However for small die (15mm times15mm) the suction sometimes is not strong enough to
provide a very good adhesion to the sample Therefore another type of ASPAT diode is
deployed which is based on the lateral structure by utilising semi-insulating substrate
and both contacts are connected to probes
67
26322 Lateral structure (Semi-insulating Substrate)
Figure 220 Cross-section view of the complete process ASPAT diode (XMBE304) The dimensions
are not drawn to scale
In order to obtain accurate measurement results so as to avoid contact errors to the
substrate between stage and Device Under Test (DUT) a lateral structure as shown in
Figure 220 above is deployed This type of design offers many advantages ie it
provides a path for on-wafer RF measurement However the proper design has to take
into account the increase in RS due to improper attention to the spreading resistance
This spreading resistance is different from the vertical structure that was discussed
above In this case it is mainly caused by a gap at the bottom contact The gap in the
horizontal direction between epitaxial layer and metal at bottom contact is denoted as D
gap in in Figure 220 Therefore Rspr for the lateral design can be expressed as [77]
119877119904119901119903 =
1
120587120590119889119866119886119860119904ln (
119886
119886119898119890119904119886)
(244)
Where σ is the conductivity between two coaxial half-cylindrical electrodes with inner
(amesa) and outer (a) rectangular length or bottom ohmic layer which is given by (σ =1
ρ) a d and amesa are the length and thickness indicated in Figure 220 above Noticeably
68
the D gap will have direct effect on the outer length (a) of the device which is also
proportional to Rspr For high-frequency operation where the skin depth is less than
d(GaAs) σ becomes
120590(120596) =
120590(0)
[1 + (120596120591119903119890119897)2]
(245)
Where τrel =microme and micro m as well as e are the mobility effective mass and electron
charge respectively It is recommended that for high-frequency applications the device
series resistance must be as low as possible
Hence for both type of structure the ASPAT series resistance is calculated based on
all the above-stated resistances and these are set by
119877119904 =120588119862
119860+ 119877119890119901119894minus119897119886119910119890119903119904 + 119877119904119901119903
(246)
The total RS can be decreased by increasing the emitter area of the diode However a
large device will not able to reach millimetre and submillimeter wave region (THz) as
the capacitance will also increase (Eq 230) Therefore both parameters will have a
trade-off between them to be able to work at ultra-high frequencies
27 Characterization of Ohmic Contacts
The semiconductor Ohmic contact can be characterised using techniques that will
be described in the following section First is the Cox-Strack technique which is
specially designed to characterise bulk type semiconductor (thick) contact resistance on
two opposite sides The detailed description of this technique can be found in [78]
Second is a technique called Four Point Probe This technique was developed in 1954 by
Valdes etel [79] to characterise semiconductor resistivity It can also be used to
characterise the contact resistance for planar type devices As this research does not
cover this method the details of the measurement can be referred to [80] Finally the
most common method which is also extensively used in this research is the standard
Transmission Line Measurement (TLM) The details of this method will be explained in
the next section There are simplified versions of the TLM method which require just
one lithography step but are nevertheless very powerful in characterising and optimising
the contact resistance known as Circular Transmission Line Measurement (CTLM)[81
69
82] However in this research this is not to be covered as the standard TLM is already
adequate for planar type devices
271 Transmission Line Measurement (TLM)
The formation of metal and semiconductor interfaces will create a contact that
becomes very important for the characterisations of any fabricated device Additionally
it enables the quality of certain process flow to be determined This interface must be
evaluated by a technique known as the Transmission Line Measurement (TLM) TLM
which was first introduced by Murrmann and Widmand [83] in 1969 underwent some
refinements by Berger [84] in 1971 The theory of the TLM can be described by
constructing a TLM structure which comprises a set of metals contact pads placed in
series on a highly doped semiconductor layer as depicted in Figure 221 The structure is
designed like a series of the islands to permit current flow in parallel to the contact pads
[80] which is a direction defined by etched patterns Each contact metal pad behaves
like a MESA which has a thickness (t) and width (W) The distance between each metal
contact pads is defined by d1 the gap between two neighbouring contact pads which are
beneath each contact pad is defined as effective length LT This will allow current flow
in and out of the subsequent neighbouring metal pad The resistance elements that will
be extracted are RA and RB which sit under the contact and in between two metal pads
These two elements represent the sheet resistance under the metal contact pad area and a
sheet resistance of the material between two metal pads
Figure 221 A simple TLM structure with effective length and sheet resistance underneath
t L
T
LT
RA R
A R
B
dn
Probe Probe
Metal Pad
GaAs
MESA
70
The basic relationship of resistance R with respect to the size of the metal contact
or in the standard transmission line can be expressed as [44]
119877 = 120588
119871
119860= 120588
119871
119905 times 119882=
120588
119905times
119871
119882= 119877119904ℎ
119871
119882
(247)
Where ρ is the materialrsquos resistivity L is the length t is the thickness W is the width
Rsh is the sheet resistance and A is the cross-sectional area of the transmission line The
unit for ρ and Rsh are Ωm and Ωm2 respectively
The total resistance RT of this structure can be taken from the sum of the two
neighbouring padrsquos resistance RA and RB In order to relate with Eq (247) above this
RT will be substituted into Eq(247) to become
119877119879 = 2119877119860 + 119877119861 = 2119877119904ℎ119860
119871119879
119882+ 119877119904ℎ119861
119889119899
119882
(248)
As suggested in [85] RshA and RshB are assumed to be identical Therefore Eq(248)
can be reorganised into specific contact resistance RC and semiconductor sheet
resistance Rsh above as 119877119862 = 119877119904ℎ119860119871119879
119882 the new equation is then
119877119879 = 2119877119862 + 119877119904ℎ119861
119889119899
119882
(249)
The common practice throughout this research is to design a TLM structure that
has a ladder structure consisting of 10 metal pads with each one measuring to a size of
100microm width and 50microm length and the space between the first and second metal pad
5microm The gap is increased after the second metal pad by a further 5microm until ten metal
pads are completed produce a separation between the ninth and tenth pad of 45microm The
TLM ladder structure as depicted in Figure 222 is supplied by a constant current of
1mA at the very left and right metal contacts by two probes This allows the extraction
of RC (Ωmm) and Rsh (Ω) instantly from such structure The potential difference
between the two adjacent metal pads is measured by another two probes and the reading
of a voltmeter is recorded The total resistance is obtained by using Ohm law where
voltage is divided by current (VI) Another voltage reading is taken for the next two
neighbouring metal pads until the largest gap is reached The readings of (conversion
71
VI) which result in the corresponding resistance RT are then plotted against spacing and
the result can be seen in the graph in Figure 223
Figure 222 Top view of TLM ladder structure use in this work
Additionally in the measurement the voltmeter used in work has a very high resistance
Otherwise there will be leakage of current occurring through the probes and cables
Therefore the parasitic resistance of the cable or connector and the probe contact can be
ignored The key parameters that can be extracted from the graph will be discussed in
the next paragraph
Figure 223 Typical plot of resistance versus TLM spacing
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50Res
ista
nce
Rn (
Oh
ms)
TLM Spacing dn (um)
LT
d1 d
2 d
3 d
n
I (1mA)
V
V
LT
ME
SA
Su
bst
rate
72
The straight-line graph plotted in Figure 223 can be referred to Eq (249) and
this must be done by assuming the sheet resistance Rsh of the material is constant If the
straight line of the graph is extended up to initial gap (d=0) the intercept on the y-axis
provides the 2RC value To extract the 2LT further extrapolation is made until the
interception at RT = 0 is reached Therefore an important parameter which is the specific
contact resistance ρC can be found from this expression[85 86]
120588119888 = 119877119862119871119879119882sinh
119897119871119879
cosh119897
119871119879
(250)
Where l represents the total conductive semiconductor thickness The final part that can
be extracted from the graph is the slope of the line This is obtained by dividing the sheet
resistance with the width of the metal pad ie represented by expression (119877119904ℎ
119882frasl )
28 Basic Characterization Techniques and procedures
281 Measuring tools and apparatuses
The success of every experiment is determined by the backend results that are
obtained from the measurements It is important to choose an appropriate instrument
which will provide the required data for a valid and detail analysis Thus this section
will give a brief explanation of the measuring instruments and methods that were
exploited in this research The measurement apparatus systems that are available and
have been utilised in completing this thesis are ldquoset of DCrdquo and ldquoSet of RFrdquo
measurements The DC set measurement consists of room temperature and variable
temperature system This system is built to perform process monitoring during device
fabrication and it comprises of five main components
The fundamental component in the ldquoDCrsquos set toolrdquo is the Agilent B1500A
Parameter Analyser [87] used to provide fixed currentbias during testing The other
component is a Karl Suss PM5 Cascade Prober [88] which is used to receive fixed
currentvoltage and to supply its to the semiconductor contact via probe tip The PM5
Prober has at least four probe arms and each of them is fitted with ldquoneedlerdquo called probe
73
tip The size of the tip that is normally used here is 2microm and in some cases the tip size
of 1microm is also utilised The currentbias supplied to the sample must go through the two
of Source Measurement Units (SMU) namely SMU1 and SMU2 to ensure no mismatch
occurs between parameter analyser and diode All the testing are controlled using a
software called Integrated Circuit Characterization and Analysis Program (IC-CAP
2009) brought from Keysight Technologies[89] The software is installed on a standard
Personal Computer (PC) and the PC is connected to a General Purpose Bus Interface
(GPIB) to link with the B1500A Parameter Analyser This system can be organised
based on the purpose of measurements ie IV characteristics TLM Schottky Diode
and transistor as it is very flexible to change the configuration For examples
Transmission Line Measurement (TLM) configuration requires the addition of a digital
multi-meter and four-point probe tip while diode measurement just needs two point
probe tip without a digital multi-meter Figure 224 illustrates the measurement system
for a set of DC to test the TLM structure
Figure 224 The set of DC measurement apparatus arrangement to measure the TLM
On the other hand the set of RF measurement consists of five block elements
configuration in the system namely the Vector Network Analyser (VNA) DC
sourcemonitor Cascade Microtech Prober SMU and Control PC via GPIB The RF set
Agilent B1500A
Parameter analyser
DUT
(TLM Diode
Capacitance)
Karl Suss
PM5 Cascade
Prober
PC
(MS windows 2000)
Digital Multi-meter
ICCAP 2014 Provide current
source
Measure and read the
voltage Stage and Probe
Signal
Current Source
SMU1 SMU2
General purpose bus interface
74
performs RF characterisation after the device fabrication is completed This system can
also perform DC characterisation as its basic instrument has this function too The VNA
machine used in this research is the Anritsu 37369A [90] which can perform the
Scattering Parameter (S-Parameter) measurement with a frequency range of 40MHz to
40GHz The DC sourceMonitor utilised in this experiment is the HP 4142B Modular
DC SourceMonitor [91] Both of these sub-systems are controlled by a standard PC
which exploits GPIB port to link them During operation the HP 4142B is connected to
the VNA by an internal bridge network and two SMUs to the Cascade Microtech Prober
which is then connected to the bond pads of the device It is identical to the set of DC
measurement where the SMU setting and data assembly are accomplished by IC-CAP
software package therefore the data that was obtained before and after completing the
fabrication can be compared This will enhance the validation of the data
However the stage and probes in both sets of measurement are different The
Cascade Microtech Prober has only two probe arms with each arm fitted with a 3-
fingers probe tip in the arrangement of Ground-Signal-Ground (GSG) as shown in
Figure 225 Each finger (pitch) is separated by 100microm thus to fit in with the pitch and
to reduce the mismatch in resistance the bond pad design must follow this separation
between each contact The GSG is configured by connecting the outer pads (Collector)
to the Ground probe tip while the inner pads (Emitter) are attached to the Signal probe
tip where the RF signal is sent and received through it Figure 226 shows the actual set-
up for RF measurement used in this research
75
Figure 225 The set of RF measurement for on-wafer DC and RF one-port measurement
Figure 226 Actual VNA system that was used for RF characterization
282 Measurement steps using a VNA
The RF measurement steps can be summarised in the following
- Step 1 Select or find the suitable VNA depending on applications
PC
(MS windows 2000)
ICCAP 2014
VNA
Anristru 32379A
40MHz to
40GHz
HP4142B
Modular DC
source
DC Bias Source
Cascade
Microtech
Probe Station
One 50microm pitch G-
S-G probe tips
Ground
SMU1
Cathode
Gen
eral
purp
ose
bus
inte
rfac
e
Lo
w P
ow
er H
igh P
ow
er
Cathode
Anode
SMU2
Ground
Ground
Signal
76
There are few factors that need to be well-thought-out before starting to use a VNA
especially for S-parameter measurements The factors are the availability of the VNA in
term of operational frequency and measurement port types air-filled metallic waveguide
or on-wafer Not all VNA can have an operational frequency for banded measurement
ie W-band Ku-band etc All these may require external signal sources to extend the
operational frequency
- Step 2 Properly setting up the VNA
The VNA can be set up depending on its application and the goal of measurement for an
instant number of point requires a desired frequency span IF bandwidth and the supplied
power level This very important to ensure the desired measurements are correct and
appropriate
- Step 3 Appropriate calibration system
In order to have a valid calibration appropriate calibration method has to be chosen
depending on the applications This will determine the accuracy and standards of
calibration As for on-wafer calibrations the de-embedding is normally used while for
the off-wafer the SOLR technique is more suitable to employ
- Step 4 Validation or verification of the calibration results
It is vital to validate the calibration results to ensure that the system has been properly
calibrated
- Step 5 Proper measurement
Proper alignment positioning and touching from probes tip to DUT is necessary to
guarantee a good repeatability and reproducibility of measurement results Normally
when positioning the probe an alignment marker is used as an aid By doing this similar
travel distance for the probes can be achieved The measuring plane will also be equally
well-defined
283 Measurement Practice and Flowchart
Essentially the device characterisation is performed in two stages ie during
fabrication as a process monitoring and after completion for data collection and
analysis Figure 227 shows the block diagram of a flow chart for testing a 15mm times
15mm wafer processing performance In the wafer processing after reaching the top and
77
bottom contactrsquos step the sample can be examined by measuring the TLM structure
according to the TLM procedure The measurement is conducted by exploiting a set of
DC measurement apparatus as mentioned above analogous to the TLM ladder structure
on the wafer surface Based on the TLM results the presence of any process issue during
the fabrication can be identified by examining the parameter such as contact resistance
and sheet resistance Thus a decision can be made either to proceed or to terminate the
fabrication should any issue is found early on As a result no materials will be wasted
further When a dielectric layer is involved Capacitance Dielectric measurement can be
tested This practise can be used to obtain the quality of the dielectric layer To connect
between a diode effective area and probe a bridge is requires It can be attached to the
diode emitter (to determine the diode size) to a bond pad for probe tip to touch This
bridge can either be left hanging in air or sticking to the isolated dielectric layer For the
GaAsAlAs material system the latter technique is preferable since it avoids issues with
the air-bridge which will be discussed in detail in Chapter 3 The opening area (via) for
metal connection can be checked by measuring the resistance on a special design pad
after a plasma dry etching step
Figure 227 Block diagram of the ASPAT measurement step
The next stage of characterising the device is the on-wafer diode measurement
which takes place after completion of all processing (including bond padsco-planar
pads) The work is carried out using the above set for RF measurement and employed
Ohmic Contact
Opening Via
TLM
Qualified
Device
Bad device
Dielectric
capacitance
Bonding pad DC and RF
Good
Good Good
Fail
Fail
Fail
78
purposely to access the DC and RF performance of each diode where the current-voltage
(I-V) characteristic and S-Parameter results are obtained In fact DC measurements are
first performed using a set of DC measurement and a rough IV characteristic can be
obtained to ensure the diode is working properly Usually the yield of any fabricated
device on 15mm times 15mm wafer in this research is between 70 to 90 In this research
the outcomes that will be discussed in the subsequent chapters are in term of the average
of measured values Thus it is very important to have a meaningful data to compare with
physical modelling and simulation in the future The diode IV characteristics are studied
by applying different DC bias at the emitter to collector terminals to extract its keys
parameters ie turn on voltage (supposedly zero bias) non-linear characteristic Rj RS
Cj etc
The device that has been measured by DC and having produced a valid result
will be marked for the next investigation ie the S-Parameter measurement This
measurement is executed using a similar system but with different probe types The
three fingers probe type is used and the device frequency response is measured via the
one-port network from the VNA The important parameters extracted from this
measurement are usually S11 (depending on how many ports are measured) Although
working devices are selected to measure accordingly there is a need to ensure the VNA
RF cable and probe tips are calibrated so that only valid data without errors will be
obtained A calibration technique called SHORT-OPEN-LOAD (SOL) is performed
prior to each daily measurement by exploiting a calibration sample with WinCal
software (Cascade Microtech)[92]
To avoid confusion it is worth mentioning that this technique used to calibrate
the device structure is different from what is used in SOL calibration to the equipment
Furthermore the de-embedding calibration is made on-wafer with the same substrate of
the actual device whereas the SOL is performed on a special calibration substrate
Normally the de-embedding results are not constantly automated with the VNA
equipment However the measurement is done separately starting with the special DUT
substrate then followed by the OPEN and SHORT de-embedding structures
79
3 RESULTS OF FABRICATION PROCESS OF ASPAT DIODES
31 Introduction
This chapter presents in detail the general fabrication techniques for a generic and
development work of micron scale ASPAT diodes The discussions will focus on the
semiconductor growth technique used in this work ie MBE and the fabrication process
steps which include sample cleaning photolithography etching and contact
metallization These techniques are ample to build and deliver commercially marketable
fabricated structure Hence all photolithography techniques used to complete this
project are based on conventional i-line optical lithography which is adaptable to
industry and commercial purposes
The fabrication process in this work can be fragmented into two major works
firstly the fabrication towards reproducibility repeatability and manufacturability in
term of device structure process flow and DC amp RF characteristics This work will
involve relatively larger emitter area which varies from 15times15microm2 to 100times100microm
2 The
larger area provides for ease and fast fabrication as well as DCamp RF measurements
Once repeatability and reproducibility of the process flow and performance is confirmed
the second part of this work which is concerned with applications in millimetre and sub-
millimetre-wave then took place In this work small emitter designs varying from
2times2microm2 up to 10times10microm
2 were considered with appropriate measurement pads The
successful fabrication of smaller diode geometries in the second part of the programme
naturally leads to a further investigations to understand its epitaxial layer structure and
extracting intrinsic components ie junction resistance junction capacitance and series
resistance which will determine the device performance in high-frequency applications
The I-V characteristic is obtained from DC measurement which is usually performed at
room temperature Its results are then compiled and compared with advanced simulation
It is worth mentioning that all samples that are investigated in this project are grown by
means of MBE and the activities related to the epitaxial layer growth using MBE in the
University of Manchester were done by the Materials Growth Team (Prof Missous) and
the authors has no responsibility for this particular task
80
32 Epitaxial Layer Growth Techniques
Before discussing the principle of the common lithography technique it is
important to discuss the wafer growth technique as it comes first before the fabrication
The growth technique that is extensively used in this study as well contributing a lot in
the electronic semiconductor industry is Molecular Beam Epitaxy (MBE) The following
section will discuss the basic operating principle of solid source MBE
321 Molecular Beam Epitaxy (MBE)
The MBE technique was developed in the early 1970s [27] and is purposely used for
growing high purity epitaxial layers of compound semiconductors Such sophisticated
growth technique provides significant functionality ie precise control of the thickness
(to one atomic layer) and contributes to the growth of various types of complex
semiconductor multilayers high quality and advanced materials This level of control is
vital for an assortment of heterostructures devices that are being utilized as part of the
development of the advanced electronics devices especially for the ASPAT diode which
require 01ML control over the AlAs barrier to attain acceptable variability in device
characteristics Additionally the accurate doping profile and excellent junction
abruptness also can be achieved by using this technique
Practically the MBE system used in this work is a solid source MBE which
utilises beams produced by heating up various sources The sources can be Si Al Ga
As and other group III-V compound semiconductors When the crucibles which contain
the sources are heated atoms or molecules of the various elements are evaporated and
travel in straight lines paths like beams directed toward a target (heated and rotating
substrate surface) The condition of the vacuum during evaporation is ultra-high vacuum
(UHV) ~10-11
torr in order to have high quality crystals The substrate is heated and
rotated to provide good growth uniformity over large areas ( up to 4times4rdquo wafers) [93]
The growth rate in typical MBE growth is ~1ML second and can be controlled
by the source temperature in the crucible The abruptness at the heterojunctions interface
and switching of the growth compositions can be obtained by precise control of shutters
that are placed in front of the crucibles Therefore an abrupt junction at GaAs and AlAs
81
interface can be formed to realize the barrier in the ASPAT diode In order to monitor
the quality of the growing crystal and measure the layer by layer growth mode
Reflection High Energy Electron diffraction (RHEED) technique is utilised This
technique works based on the diffraction of electrons from the crystal surface [93]
Additionally given that the ASPAT current density is very sensitive to the barrier
thickness a study has been made using different growth techniques namely MBE and
Metal-Organic Chemical Vapour Deposition (MOCVD)[59] From this investigation it
was concluded that the percentage local variability of current density produced by MBE
grown diodes is better than those grown by MOCVD Thus in this study to get benefit
from its performance all wafers are MBE grown
33 Basic Principles of Common Fabrication techniques
This section covers the generic fabrication process which underpins
reproducibility repeatability and process optimisations for high-frequency applications
331 Sample cleaning
Essentially semiconductor processing requires a ldquoclean environmentrdquo to produce
devices The clean environment is classified according to how many ldquounwantedrdquo
particles are present in a cubic meter There are four categories of clean room available
in the industry Class 10 Class 100 Class 1000 and Class 10000 [94]
The fabrication of all ASPAT diodes in this project was performed in a clean
room environment of Class 1000 equipped with laminar air flow and filter system to
give Class 100 or better during processing Although the sample was processed in a
highly controlled particle environment there is still a high chance for a sample to get
contaminated when handled by a human Besides this the source of particle which
contributes to the contamination can be from the apparatuses and processing equipment
used in the laboratory themselves Thus the process of cleaning the sample wafer
surface before the start of each step is vital
Generally in a clean room the standard solutions that are used to clean a sample are
N-Methyl Pyrrolidone (NMP) Acetone Propan-3-ol (Iso-Propane-ol) (IPA) and
82
deionized (DI) water The sample which is cut up into 15times15mm2 size tiles is cleaned
based on the following procedures
1 Hot NMP- The sample is dipped into the solution at 80˚C for 10 minutes This
solution acts as an organic type of nature pollutants removal
2 DI water- acts as NMP remover The sample is then washed by flowing DI water
throughout the samplersquos surface
3 Acetone- to ensure any remaining NMP is completely removed from the sample
The sample is dipped into Acetone for 5 minutes in a low power ultrasonic bath
at ambient temperature
4 IPA- is used to remove the Acetone from the samplersquos surface The sample is
then dipped into the IPA for 5 minutes in a low power ultrasonic bath at room
temperature The use of low power for the ultrasonic bath is to avoid the sample
cracking or breaking
5 Once done the sample is then blow-dried using nitrogen (N2) gun to remove any
moisture coming from the IPA Fortunately it is easy to remove the IPA
completely from the sample surface given its higher rate of evaporation
Once all these steps are accomplished a visual inspection using a high magnification
optical microscope is conducted to ensure the sample surface is clean The cleanliness of
the sample is determined by the (lack) of particles or other spots (liquid mark) that can
sometime be observed during the inspection Obviously the lower the number is the
better the sample is as it is impossible to totally remove dirt especially marks
Sometimes it is hard to remove the particles in one go There is always a need to repeat
each cleaning step for a few times However this will not affect the sample in term of
electrical performance as the cleaning solutions used are non-destructive
332 Photolithography
Lithography or sometimes called pattern transfer is the most important step in
realizing microelectronic devices The designed geometry and dimensions on a quartz
glass plate called a ldquophoto-maskrdquo must be done prior to the fabrication process While
the photo mask can be designed by using various software tools in this work the design
83
is done via the Advance Design System (ADS) by Keysight The details of the design
which includes three different mask designs will be covered in Section 34 The mask
consists of the desired patterns (master) that can be printed onto solid materialrsquos surface
by means of an electrochemically sensitive polymer (photoresist) using
photolithography In fact this type of optical lithography technique can be performed
with and without a mask due to its simplicity It is also easy and cheaper compared to
other techniques such as x-ray lithography or Electron-beam lithography (EBL)
Although the latter is expensive it is still worth to have since it provides a higher
resolution which is preferable when developing sub-micrometre technology
processing[95] The special feature about EBL is that it does not need a mask to pattern
samples but can be produced by the movement of an electron beam point source and
hence writing the patterns directly on the surface
The ultra-violet (UV) based light sources are more popular among researchers
and development workers because they are cheaper and have modest resolution Usually
photolithography operates at wavelengths (λ) from 193 nm to 436nm The source that
provides the UV light is a Mercury (Hg) arc lamp which uses narrowband filters to select
single emission lines First is the i-line at λ= 365nm then the h-line which is of lower
resolution and has λ of 405nm and thirdly the g-line with a λ= 436nm[96] The
conventional optical lithography used in this research uses the ldquoi-linerdquo at a wavelength of
365nm For shorter wavelengths than these excimer laser or krypton fluoride laser with
a λ= 248nm and argon-Fluoride with a λ = 193nm are also used in the industry The
higher power levels enable higher productivity (throughput) while narrower spectral
widths reduce chromatic aberration provide better resolution and larger depth-of-focus
In this research all the fabrication process are done by utilizing a conventional optical
lithography (i-line) using a Karl Suss MA4 mask aligner Before starting any UV
exposure it is important to check the UV light intensity as it will affect the resolution
and thus desired device dimensions Therefore every corner that is exposed to the UV
light is calibrated to be at 09mWatt power exposure
The complete set of photolithography components consists of photoresist
(photosensitive polymer) photo-mask (chromium) which is used to block the UV to
form a pattern mask-aligner and developer (chemical solutions) Standard fabrication
84
process usually practiced at the University of Manchester starts with sample cleaning as
mentioned earlier Then the sample needs to go through heat treatment to remove all the
moisture with a temperature set to be 150˚C and bake for 5-10 minutes After having
cooled down the samplersquos surface is coated with a thin layer of photoresist via a
technique called spin-coating using a Laurell CZ-650 series spinner The spinning speed
is set depending on the type of resist ie 3000rpm for negative photoresist and 5000rpm
for positive photoresist The rotating speed of the spinner does not have much effect on
the coated photoresist thickness but will have consequence on the uniformity distribution
over the sample surface The coated thickness photoresist however depends on the
concentration of the specific photoresist Once spin-coated is done another short heat
treatment (1 minute) is required to ensure the resist is hard enough to contact a
photomask and to remove any excess solvent The temperature is set on the hot plate to
about 115˚C and 110˚C for positive and negative photoresists respectively
The important segments contained in the photoresist are a polymer (base resin)
a sensitizer and a casting solvent [97] The polymer will react by changing its structure
when exposed to the radiation While sensitizers will govern the reaction of the
photochemical in the polymeric phase the casting solvent will permit the spin-coated
application on the wafer surface The photoresist consists of positive and negative
photoresist both of which were used in this research Their basic difference is with
respect to the area that is exposed by UV light ie whether it will remain on the
semiconductor surface or will be removed In the case of a positive resist the exposed
area will be removed by the developer and the covered area will remain In other words
whatever is displayed on the photomask goes onto the sample surface On the other
hand for the negative photoresist the area that is covered from UV exposure will be
dissolved by the developer Figure 31 shows a 3D picture of both processes used in this
research
85
Figure 31 3D illustration of Optical lithography process used in this research
To obtain the desired pattern on the surface after UV exposure for a certain
duration the sample is required to go through a development procedure by using a
developer The developer is used to expel the dissolvable part of the photoresist after
being exposed to UV The usefulness of the developer depends on the photoresist ie
MF319 developer is specifically for positive photoresist while MIF326 is suitable for
negative photoresist Both types of developers will not harm the devices as they are a
kind of metal free ion solution Thus no free ion will change the characteristic of the
device The common practice in the clean room at the University of Manchester is to use
positive photoresist namely Shipley Microposit S1800 supplied by The Dow Chemical
and negative resist AZnLOF2020 (AZ2microm) which is supplied by MicroChem For the
S1800 series the thickness of the photoresist is determined by the last two digits ie
13microm thick for S1813 and 05microm thick for S1805 Both positive photoresists are used
Resist
GaAs
Dielectric
Photo Mask
Negative Resist Positive Resist
After Etching
86
mostly as protective area during wet chemical etching and as sacrificial dielectric layer if
higher temperature is applied ie 190˚C On the contrary AZ2microm which normally has a
thickness of 2microm is useful for patterning small dimension which leaves small gaparea
for the metallization process to fill It has good aspect ratio and useful in single layer lift-
off (post metallization process) In fact this type of resist can be thinned by diluting into
an Edge Bead Removal (EBR) solution and smaller device feature size can be obtained
The final dimension of certain devices (mesa size) is governed by the exposure
time the distance between photomask and samplersquos surface and the development time
The appropriate UV exposure time is required to avoid over-exposure which will cause
the spreading of light into the purportedly dark-field area[98] However the effect of the
exposure time differs between the photoresist types smaller opening area than the mask
pattern for negative resist and larger opening area for positive resist[45] The gap
between the photomask and wafer surface must be reduced as much as possible to avoid
the UV light going through the unwanted area To obtain a good gap value an applied
pressure from stage to the mask is required The normal pressure used in this research is
between 04 to 1 Pascal depending on the type of photoresist (negative and positive) as
well as its thickness Lastly the development time also influences the dimension of the
device Appropriate development time is required because ie over-development will
cause the polymerized photoresist to etch laterally resulting in bad patterned geometries
On the other hand under-development will cause non-uniformity in the surface after wet
chemical etching (positive resist) as well as causing lift-off problem (negative resist)
333 Etching Process
The etching process is a process of removing unwanted semiconductor layers to
define device geometry and isolate each individual device in one sample There are two
types of etching technique used in this research ie wet chemical etching and plasma
dry etching The wet chemical etching is based on Orthophosphoric(H3PO4) solution
which is a selective etchant to materials like GaAs InGaAs and AlAs The selective
etchant is referred to a solution that can etch away a specific semiconductor with a
specific etch rate The etch rate depends on the mixture ratio and concentration of the
solutions ie the higher the concentration the higher the etching rate In practice the
87
temperature humidity and epitaxial layer doping level also have an impact on the etch
rate Hence to minimize variation in the etch rate both temperature and humidity in the
clean room are constantly monitored and regulated Ambient temperature between 18degC
to 19degC is usually suitable while humidity is kept within 30 to 40 The advantage of
the wet chemical etching is that it is inexpensive controllable and with high throughput
highly selective and simple The mixture solution that is used in this work is
Orthophosphoric (H3PO4) Hydrogen Peroxide (H2O2) and Di-ionised water (H2O) with
ratios of 3150 3110 and 212 The ratio of 3150 provides an etch rate of about
600Aminute and is good to define the area and opening the under-cut in air bridges for
InGaAs samples[99] The 3110 ratio results with highly anisotropic shape but is easy to
control as the etch rate is about 1500Aminute for GaAs material system However the
212 etchant solution will provide extremely anisotropic etch rate of about
1000Asecond and is quite difficult to control For GaAsAlAs ASPAT diode it can still
be controlled since the thickness that needs to be removed is about 7000A (refer to
section 342 for details on the fabrication of ASPAT) Table 31 summarizes the etch
rate with different ratios and different selective materials Common to all the ratios
mentioned above are the isotropic side walls with lateral and vertical etch rate of 11
Table 31 Chemical wet etch characteristics using Orthophosphoric-based and Ammonia on GaAs
and InGaAs materials
Material Etchant Ratio Etch Rate (Aringminute)
GaAs H3PO4H2O2H2O 3150 600
GaAs H3PO4H2O2H2O 3110 1500
GaAs H3PO4H2O2H2O 212 60000
GaAs NH4OHH2O2H2O 118 2000~3500
InGaAs H3PO4H2O2H2O 3150 850
The plasma dry etch is purposely run to obtain extremely high anisotropic etch
profile vertically and horizontally It can be done via mask with positive photoresist and
self-align mask which is metal contact as a mesa protector The precursors that are used
to etch away GaAs InGaAs and AlAs layer in this technique are Methane and
Hydrogen (CH4+H2) On the other hand Carbon Tetrafluoromethane (CF4) and H2 is
88
used in removing Si3N4 The etch rate is determined by how much power is applied to
the plasma to hit the sample surface the pressure inside the chamber and amount of the
precursor In this research plasma Technology is used for dry etching This machine
which is a conventional OXFORD INSTRUMENTS 1990 machine can produce an etch
rate on average of 100Aminute for an RF power of 100mWatt
334 Sputtering (dielectric deposition)
In this work a Kurt JLesker PVD 75 is used to deposit Si3N4 layer on the sample
surface The deposition rate depends on the RF power that is applied To avoid surface
damage on the sample surface a sacrificial layer formed by SiO is deposited using the
Bio-Rad Thermal evaporator before transferring to the PVD 75 to start deposition with a
low (75Watt) RF power Once the deposition time reaches 30 minutes the power is
increased up to 200Watt As a result good uniformity of the dielectric layer is obtained
335 Metallization Process Lift-off and Annealing
The metallization process is a process in which metal contacts on semiconductor
devices are created The purpose of this process is to make a proper interconnection
between the semiconductor devices to other parts of the circuit elements In other words
it is to connect the semiconductor device to the outside world This process will allow
the device to be examined electrically so that all electrical characteristics can be obtained
ie resistance I-V curve capacitance conductance etc The metal scheme used in this
process depends on the semiconductor material In the case of GaAsAlAs ASPAT
diode Gold-Germanium (AuGe) Nickel (Ni) and Gold (Au) are used However in the
case of InGaAsAlAs ASPAT diode the metal scheme used is Titanium (Ti) and Au
The technique used in this process is resistive thermal evaporation
The metallization process starts by cleaning all the metallic sources and boats
ie tungsten boat Au Ni and Ti metals by using Trichloroethylene Acetone and IPA
consecutively for 5 minutes each in a high power ultrasonic bath This step is very
important to reduce the risk of contamination during thermal evaporation Once done all
the metallic materials are dried using a high-pressure nitrogen gun and then dipped in
89
Hydrochloric acid (HCL) solution for 2 minutes to de-oxidize the metals so that it has
minimal effect on the series resistance of the ASPAT diode
Two types of thermal evaporators were used extensively in this study both
Edwards Auto 306 (one denoted as Junior Auto 306) The latter is used to deposit alloy
type of metals while the former is used for the non-alloyed type of metals In the case of
GaAsAlAs ASPAT alloy type metals are used while for InGaAsAlAs non-alloyed
metals are used The cleaned metals are then loaded in the thermal evaporators and
placed on a resistive tungsten boat Each metal is placed on its specific tungsten boat to
avoid unnecessary mixture during the evaporation
Figure 32 Actual picture of thermal evaporator used in this study
Prior to loading the sample into the evaporator a standard fabrication process for
ASPAT diodes takes place by patterning the samples with AZ2microm negative photoresist
At the end of this step an opening area is created for the metal contact to be filled and
connected to the ohmic contact of the semiconductor The sample is also deoxidised
using a mixture of HCL and water in the ratio of 11 prior to evaporation This has to be
done in a very short time in order to avoid re-development of the native oxide layer
Inside the chamber the sample is securely placed on a chuck upside down facing the
filled tungsten boat The distance between the sample and metallic source boat is about
90
40 cm Figure 32 illustrates the actual thermal evaporation system used in this study
The thermal evaporator chamber is pumped down to reach a minimum pressure below
1times10-5
mbar before vaporizing the metal It is important that the mean free path between
metal amp sample is created and each vaporized metal stick firmly on the samplersquos surface
The normal practice in this study is to keep the vacuum pressure under 1 times10-6
bar so
that better device performance can be obtained The amount of current required to melt
down the metal is between 4 Amps to 6 Amp This amount of current is forced through
the tungsten boat and generates very high heat melting down the metallic source and
vaporizing it towards the sample surface The deposition rate for each metal can be
monitored by using a built-in film thickness monitoring (FTM) on the thermal
evaporator which proportionally depends on the amount of materials deposited The
GaAsAlAs sample is started with deposit of 55nm AuGe 13nm Ni and 500nm of Au
The reason of depositing AuGe first is due to the fact that the ohmic layer of the
ASPAT only can only be doped with a maximum doping of 4 times1018
cm-3
which is not
high enough for good conductivity Thus here Ge atoms will diffuse into the GaAs and
replaces Ga atoms during annealing process leading to higher doping levels (gt1 times1019
cm-3
) and hence improved conductivity
3351 Lift-off
The use of AZ2microm allows for the exact patterning of metals without the need for etching
using a single layer lift-off technique The negative photoresist also provides an undercut
profile which will create disjointedness between the desired metal pattern (on the
semiconductor) and undesired metal (on photoresist) The process of getting rid of the
unwanted metal from a sample surface is called lift-off The process starts once the
evaporation process is accomplished The sample is soaked into 80˚C N-Methyl-2-
Pyrrolidone (NMP) solution for usually 20 minutes (fast lift-off process) In most
instances the sample is in NMP for more than 12 hours in ambient temperature (slow
lift-off process) as the NMP solution is not destructive to the sample In this solution
the negative resist will be softened and the metal part which sticks on it will also be
eliminated from the sample As depicted in Figure 33 the lift-off process for a single
device shows the usual photoresist undercut profile observed To ensure that NMP
91
residues on the sample surface are completely removed DI water is used to rinse the
sample which is then blown dry with a nitrogen gun
Figure 33 Single layer lift-off process using negative photoresist
3352 Annealing
The alloyed (AuGeNiAu) metal stack requires a thermal treatment called annealing to
improve the ohmic contact between metal and semiconductor The sample which has
deposited top and bottom contacts is loaded into an annealing furnace at a temperature of
420˚C for 2 minutes In the case of GaAs during thermal annealing Ge atoms penetrates
into the GaAs crystal for approximately 70nm-250nm depending on evaporated
thickness of the metal layers annealing temperature as well as time [100] In this work
the total metal thickness evaporated for each contact layer is around 500nm This
thermal annealing treatment will also melt down the Au if it is too thick and is subjected
to too long a heat treatment Therefore it is not advisable to do annealing after the
sample is coated with bond pad metals as it can result in short circuited devices
sometimes
Az2micro Negative
photoresist profile
after UV exposure
and development
Evaporation to
form metal layer
(AuGe Ni Au)
Desired metal
contact
Metallisation
process
Lift-off undesired metal
92
34 GaAsAlAs ASPAT Process Optimization
As mentioned earlier this section present details two major process flows of the
fabrication process for the ASPAT diodes which utilised three stages of development of
photomasks design namely a ldquoFirst generation mask designrdquo (1st Gen) a ldquoSecond
Generation mask (2nd
Gen)rdquo and a ldquoThird Generation mask (3rd
Gen)rdquo design The 1st
and 2nd
generations mask designs are the designs that were produced in the first stage of
this work to develop the fabrication process know-how and to get familiarized with the
actual fabrication techniques in the cleanroom The difference between the 1st Gen and
2nd
Gen masks is in term of the development towards realizing Air Bridges and
Dielectric Bridges which were mostly covered by the 2nd
Gen mask design The
analyses in term of reproducibility repeatability and manufacturability for process
control and current-voltage characteristic as well as ultimately RF measurement are
obtained on relatively large size devices via these two mask designs The large area
emitter dimensions range in size from 15times15 microm2 to 100times100microm
2
The 3rd
Gen mask design was designed based on the optimization of the 2nd
Gen
mask which was to realize ASPAT diodes that are able to work at very high operating
frequencies Therefore in such design the ASPAT devices have to have a minimal
amount of capacitance and low series resistance this is can be achieved by shrinking the
emitter size of the diode to the smallest area possible as well as optimising the
fabrication process ton reduce parasitics The smallest fabricated devices designed on the
new mask has an 2times2 microm2 MESA area which also includes Ground Signal Ground bond
pads for both device and de-embedding structures (open and Short) for RF
measurements
Before the commencement of any fabrications and designing any layouts on eg
Si GaAs InP etc the epitaxial layer must be grown first to a desired design In the
University of Manchester the epitaxial layer structures are grown using one of the two
Molecular Beam Epitaxy (MBE) machines which are either the RIBER V90H or the
V100HU system Both systems are managed by Professor Missous Epitaxial wafers or
sample grown by each system are identified by a prefix and numbers that are prefix
VMBE for the V90H system and XMBE for the V100 system The epitaxial layers are
93
grown on four-inch wafer diameter The maximum diameter that can be grown on using
the V100H is 8 inches but generally single 4rdquo or 4x4rdquo wafers are used The wafers are
then diced and cut using a diamond scriber into 15mm times 15mm tiles for easy handling
and fabrication in the D12 cleanroom lab in the University of Manchester
In this section the structures fabrication and performance of the various ASPAT
diodes for both repeatability and high frequency applications will be discussed further
The ASPAT is manufactured on wafer sample XMBE304 which is a GaAsAlAsGaAs
lattice matched to a GaAs semi insulating substrate is the main focus The ground works
on this ASPAT such as the initial design and fabrication process flow optimization had
been conducted by fellow PhD colleagues in the group led by Professor Missous at the
University of Manchester
341 ASPAT Devices used in Fabrication
3411 XMBE368 and XMBE307
Table 32 Epitaxial layer of Doped substrate samples
Thickness (Aring)
Layer Material Doping (cm-3
) XMBE368 XMBE307
Top Ohmic1 GaAs (Si) 4times1018
~3000 ~3000
Buffer 1 GaAs(Si) 4times1017
~50 ~50
Spacer1 GaAs NID 50 50
Barrier AlAs NID 28 28
Spacer 2 GaAs NID 1000 1000
Buffer GaAs(Si) 4times1017
50 50
Bottom Ohmic GaAs(Si) 5times1018
~3500 ~3500
Substrate GaAs (Si) Doped 50000 50000
These two samples were the first batch of diode structures used in this work and
were grown using the RIBER V100 MBE machine A great deal of work was expanded
to ensure that it is able to produce appropriate non-linear I-V characteristics The work
carried out including finding suitable fabrication process steps mask designs process
control limitations ie etching rates etc The results obtained from processing these
94
samples mostly on large area anode and cathode sizes and their analysis included both
growth profiles and fabrication process flows These samples were grown on doped
GaAs substrates As such the finished diodes were vertical structures and the fabrication
process has marked differences compared to undoped substrate samples While
XMBE368 had similar epitaxial layer profile to XMBE307 during growth the AlAs
layer was set to be stagnant (ie no-rotation of the substrate during growth) to
investigate the effects of slight variations in barrier thickness
3412 XMBE304
The next sets of samples were all grown on semi-insulating GaAs substrates
Table 33 details the epitaxial layer profile of sample XMBE304 the main work horse
of this research work The growth of this structure was performed on a multi-wafer
platen and consisted of 9 x 2rdquo wafers (from XMBE304A to XMBE304I)
Table 33 The epitaxial layers of sample XMBE304 with barrier 10ML~28nm
Epitaxial layer Material Doping(cm-3
) Thickness(Aring)
Emitter GaAs(Si) 4e+18
3000
Emitter 2 GaAs(Si) 1e+17
400
Spacer GaAs NID 50
Barrier AlAs NID 28
Spacer 2 GaAs NID 2000
Collector GaAs(Si) 1e+17
400
Collector 2 GaAs(Si) 4e+18
4500
Substrate GaAs(SI) Semi-Insulating
For a typical ASPAT structure the emitter is essentially highly doped to
4times10+18
cm-3
to provide accumulation of electron in the emitter contact region It was
purposely highly doped to also achieve low ohmic contact with the metal The spacers
are used to avoid diffusion of dopants to the subsequent layers The ASPAT structure as
mentioned earlier has a single AlAs barrier with a very small thickness sandwiched
between two different length GaAs spacer layers
Batch XMBE304 is the main focus in these studies All activities required for
repeatability reproducibility process flow and devices as well as qualifying new or
95
optimization fabrication technique for small devices and RF performance which were
then used for high frequency were based on the set of wafers grow in this batch
342 Fabrication process of GaAsAlAs ASPAT diode toward repeatability
reproducibility and manufacturability
As the new wafer structures have to be tested and evaluated to gauge the
performance of the ASPAT diodes their uniformity also needs to be tested so as to
ensure it exhibited fully functional diode with zero bias detection in minimal variation in
IV characteristics between diodes As described previously 4rdquo wafers are always diced
up into 15mm times15 mm size for ease of handling in the cleanroom and for masks cost
purposes
3421 Doped n+ Substrate Wafers
For wafers grown on n+ substrates (XMBE368 and XMBE307) a two-level mask
set is sufficient to complete the fabrication process In this case the devices are designed
with mesa structures and top metal contact on the upper surface of the wafer and a
bottom contact on the backside of the wafer One mask plate is used for defining the
mesa structure (wet etch) and the other mask plate is used for defining the metal pad
Since the mesa is relatively large (30times30microm2
to 100times100microm2) there is no requirement to
define bond pads for measurement purposes A prior RTD mask designed by fellow
colleague Dr Md Adzhar for his PhD work was used for processing the ASPAT diodes
as well in the first instance The detail fabrication process is summarized in appendix I
for the doped substrate wafers Figure 34 shows typical IV characteristics for 30x30microm2
emitter size diodes obtained from sample XMBE368
96
The I-V measurement was taken from two different tiles (15mm times15 mm) located
on top and bottom of a 4rdquo XMBE368 wafer The location 1 marked as a blue line in
figure 34 refers to a device on a tile taken from the top of the 4rdquo wafer while location
2 (red) refers to a device on a tile taken from the bottom of 4rdquo wafer At 07V the
separation difference in current is ~228 for both tiles This shows that the device in
tile 1 is less resistive than the sample in tile 2 implying that the AlAs layer for tile
located on the top corner of the wafer is thinner and thus allows more electrons to tunnel
through it at a given bias
3422 First Generation Mask Design (1st Gen)
-0015
0005
0025
0045
0065
0085
-15 -1 -05 0 05 1 15
I C
urr
en
t (A
mp
)
V Voltage (Volt)
Current vs Voltage (XMBE368_1) for 30x30microm2
MidLeft2
MidRight3
Figure 34 Current-Voltage characteristic of sample XMBE368 used
in this study at two different locations on the wafer tile
(a) (b) (c)
Figure 35 ASPAT mask design for (a) 100times100microm2 (b) 30times30microm
2 and (c) 15times15 microm
2 diode dimensions
designed in the 1st Gen Mask
Location 2
Location 1
97
The fabrication of the GaAsAlAs ASPAT conducted in this 1st Gen mask is
followed the established generic process flow for InGaAs material which was done by
former co-worker Dr Md Adzhar Md Zawawi[101] The generic process flow is fairly
simple consisting of four mask steps as shown in Table 34 below The fabrication
process starts with the sample being cleaned in a NMP solution at a temperature of 80˚C
with Acetone and Propan-2-ol (IPA) The purpose of cleaning using NMP and Acetone
is to remove any organic material The IPA is used to remove Acetone residues
Table 34 Generic fabrication steps established by Dr Md Adzhar [101]
Step number Process
1 Top Contact
2 Mesa Etch
3 Isolation
4 Bottom Contact
In the 1st Gen mask the first step in fabricating the GaAsAlAs ASPAT diodes is
to use the first mask to define the emitter contact area The emitter has three different
sizes 100times100microm2 30times30microm
2 and 15times15microm
2 The lithography technique uses the
negative photo-resists AZ2micron with 55 second UV-photolithography to pattern the
top contact Then it is developed using MC319 developer to clear and define the
exposed area for the metals to stick to The sample is then subjected to plasma etching to
remove all organic residues and contaminants Then it is dipped into a mixture of
diluted Hydrochloric acid and water HCL H2O with a concentration of 11 for de-
oxidation This must be done in a short time right before the evaporation in order to
ensure good contact between metal and semiconductor surface with very low oxide
formation in between The ASPAT device performance depends on this step as contact
to the channel is by means of current flowing through the anode to the cathode terminals
In our lab the approach taken to achieve the Ohmic contact is by evaporation of Gold
Germanium (AuGe) Nickel (Ni) and Gold (Au) metals layers on top of the cap layer
Subsequently the metal is defined via a lift-off process using NMP
98
The next critical step is to define the MESA or island The mesa etch mask is
designed with two options with 05 microm or 10 microm tolerance The different mesa
tolerances are introduced to act as a safeguard for the emitter from producing excessive
undercut caused by lateral etching This step is to isolate and eliminate the unwanted
GaAs which will electrically link the active layers as many devices will be fabricated at
the same time on the same wafer tile (15mm times 15mm size) The lithography process in
this step uses positive resist and is developed using MC326 developer This step is
achieved using a wet etch process where a non-selective etchants mixture of
H3PO4H2O2H2O etches down the epitaxial layers until it slightly exceeds the AlAs
barrier with an etch rate of about 600Aring to 900Aring per minute The outcome of the MESA
or island step is the formation MESA active layers which are surrounded by inactive
layers of semi-insulating substrate (when using semi-insulating substrates)
The isolation mask is a step that is basically the same as the MESA etch step
eg using similar etchants mixture same lithography process but a different mask This
step is used to etch down until the GaAs substrate is reached which means that the
etching time is longer than that in the MESA etching step The purpose of this step is to
fully isolate the device from other neighboring devices hence ensuring no electrical
connection exists between each device within one sample Since these ASPAT diodes
employ an air bridge structure of size 1times5 microm the two minutes mesa etches will
simultaneously provide an initial undercut through lateral etching for the air bridge
formation
Based on the results so far obtained using the first-generation mask which
provided large mesa areas the current voltage characteristics of the ASPAT as far as the
non-linear zero bias is concerned did work very well However there was a need to
reduce the ASPAT mesa area down to very small dimensions to achieve mm-wave or
THz detection frequencies It is certainly a general rule for semiconductor device which
operate at very high frequency to have extremely small lateral dimension which
minimises the capacitance within the ASPAT device Furthermore for wider adoption of
the technology it is also important to develop a simple reproducible and low-cost
fabrication method for ASPAT diodes Details of this fabrication process are attached in
appendix II
99
3423 Second Generation (2nd
Gen) mask (ASPAT-GSG)
This work intended to enhance the 1st Gen-Large Area ASPAT photomask by
adding many features including 2 times 2microm2 mesa areas ground-signal-ground (GSG) bond
pads to enable RF measurement and three options device processing eg Air Bridge
Dielectric Bridge for semi-insulating doped substrate and dry etch-mesa Other reasons
for designing this mask was also to qualify process steps when deploying thin (1microm
width) bridge to connect small mesa area ASPAT diodes to the co-planar GSG bond pad
for DC and ultimately RF measurements
The mask was designed to fulfil the basic rules of fabricating various types of
tunnelling diode for instance RTD and ASPAT The diodes layouts were designed using
the commercial software Advanced Design Software (ADS) from Keysight
Technologies Ltd Once the design was completed it was ready to be sent to Compu-
Graphics Company for printing and patterned on a special chrome coated glass plate
The new 2nd
Gen mask design was termed ASPAT with Ground-Signal-Ground
(ASPAT-GSG) and consisted of two main designs ldquoAir Bridge and Dielectric Bridgerdquo
where each contained eight diodes with different emitter sizes (100times100μm2 50times50μm
2
30times30μm2 20times20μm
2 15times15μm
2 10times10μm
2 6times6μm
2 and 2times2μm
2) The Air Bridge
design is comprised of Design 1 (doped substrate) and Design 2 (undoped substrate)
This can be selected by changing the order of each individual layer of the mask steps
The same options are applied for Dielectric Bridge design which included processing for
doped and undoped substrates The details of the masks will be explained in the
following paragraph
(1) Air Bridge
Design 1 Contains five steps or layers mask of size 15mm times 15mm
suitable for air-bridge for undoped semi-insulating substrate
Design 2 Consist of seven layers steps mask of 15mm times 15mm size
There are 413 die chips in about 6mm times 6mm sizes in this design Figure 36 shows both
type of design for Air Bridge mask processing
(i) Mask 1- Top Contact
(ii) Mask 2- MESA
100
(iii) Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5- Collector Bond pad with GSG
(vi) Mask 2A-Dielectric
(vii) Mask 6A-Collector Bond Pad with GSG
(2) Dielectric Bridge
Design 1 Consists of seven identical steplayers masks with lateral
lengths of 15mm times 15mm each suitable for fabrication on semi-insulating
substrate
Design 2 Also has seven steps layers masked with dimension of 15mm
times15mm each suitable for doped substrate processing
There are 357 die chips in this type of mask design with an estimated size of 6mm times
6mm separately The smallest emitter size that is connected with a dielectric as the
bridge is 6times6microm2 The smallest 2times2microm
2 diodes was designed with the air-bridge
connected to the emitter bond pad due to the difficulties of opening viascavity for less
than 2 microm2 devices Figure 37 show both options for Dielectric Bridge mask processing
(i) Mask 1- Top Contact
(ii)Mask 2- MESA
(iii)Mask 3-Isolation
(iv) Mask 4- Bottom Contact
(v) Mask 5-GSG bond pad
(vi) Mask 6- Via Dielectric
(vii) Mask 7- Dielectric Bridge
(vii)Mask 5A- Via Dielectric
(ix) Mask 6A-GSG bond Pad
(x) Dielectric Bridge
Figure 36 Air Bridge design (red circle) for large mesa area (100times100microm2) device with
option for doped substrates
Figure 37 The layout of 1st design of Dielectric Bridge (green circle) mask design for 100 times
100microm2 emitter size with option for doped substrate processing
101
34231 Fabrication Process of the Air-Bridge Design
The fabrication using 1st Gen mask as mentioned in Section 3422 is less
complex however the fabrication process for Air-Bridge mask design contains a few
additional steps which are to add bond pads for the Ground-Signal-Ground radio
frequency (RF) layouts If the sample is on a doped substrate another layer needs to be
added leading to a total of six steps all together
Table 35 Standard process flow for Air-Bridge design fabrication
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa EtchDielectric
3 3 Isolation
4
5
4
5
Bottom Contact
Bond Pad
In this work the samples that have been processed so far are XMBE304
XMBE314 (GaAsAlAs base material system) and XMBE326 (InGaAsAlAs base
material system) All of them are built up on semi-insulating substrate thus the normal
process flow was followed Step 1 to step 4 follow exactly the same route as the 1st Gen-
ASPAT Large Area mask formerly discussed in Section 3422 This process is then
continued by spin coating AZ2microm on the surface Mask 5 is used to pattern the bond
pads The metallisation scheme used for bond pads is TiAu and the thickness must be at
least 1 micrometre thick This is to minimise series resistance at the pads and ensure a
robust surface is created when used for DC and RF measurements
342311 Air-Bridge Process Optimization
Since the Air Bridge design approach is focused more on developing air-bridges
which have a width of 1 microm and as the smallest device is 2 times2 microm2 the negative resist
(Az2microm) which was used in the 1st Gen design type was changed to Az1microm After spin
coating an Edge Bead Remover (EBR) is required to remove the beads at the edge of the
sample this is to ensure no gap is created between samples and mask when ldquohard-
102
contactrdquo is applied during the photolithography step The use of Az1microm and EBR are
critical to enable the fabrication of small air-bridges and emitter sizes
The exposure time during the photolithography technique also needs to be
increased to achieve a 1microm size air bridge A longer time than normal is required thus
95 seconds is used for exposure under UV light Once finished appropriate
development time must be applied to ensure the line for the air bridge is perfectly
opened for the metal to fill up To get impeccable result in this step both combination of
exposure and development have to be tuned naturally leading to trade off in both Too
long exposure and developing time will break the bridge whereas for too short exposure
time and developing the air bridge will not open
There are two types of etching method used in this fabrication wet
(H3PO4H2O2H2O) and dry (NH4H2) etching Both have their own advantages and
disadvantages Wet etching is faster than dry etching However the etching profile is
highly isotropic and causes serious undercut The smaller devices which have
dimensional sizes of 6times6microm2 and below will ldquoshrinkrdquo the effective area under the top
contact metal Even though dry etching can have highly anisotropic etching profile
which can prevent excessive undercuts it requires a lot of time for etching the
semiconductor layers The NH4 and H2 plasma that are used in this technique do not only
etch the GaAs and AlAs layers but also etch the metal contact at the same rate as the
semiconductors Thus the metal area must be covered with a photoresist or thicker metal
(~1microm) must be used to counter this issue Figure 38 shows that the emitter bond pad
which is not covered by the resist will eventually be etched away by the dry etching
Figure 38 Dry Etching for the first run in this study
As mentioned in section 333 the advantage of H3PO4H2O2H2O wet etching is
that it can be made using two solutions fast and slow The fast solution is based on a
concentration ratio of 212 while the slow solution is based on a 3150 mixture The
103
212 fast solution will produce good anisotropic etch profile but is tricky to control due
to the rather high etch rate of 1000Aring per second Both fast and slow wet etching
solutions being carried out in this experiment are replicated from successful recipes that
were developed by other co-worker from Prof Missousrsquos group
342312 Issue of Over Etch under Top Metal (Wet Etching for Air-Bridge
Design)
The first run using the solutions mentioned above started with the deposited
metal as a top contact (Top contact must be defined first to make a bridge) then Mesa
etching to remove ~7000Aring GaAs using the fast etch solution The next process to be
followed was to employ the slow etch solution to etch down the epitaxial layer to the
substrate Doing this ensured that air-bridge was open and the devices isolated
individually Unfortunately unexpected results were observed where large undercuts
still appeared for both 2times2 microm2 and 6times6microm
2 devices Figure 39 shows severe undercut
under the big device that can clearly be seen in the digital scope Most probably this
problem occurs due to excessive time used for the wet etching (10 seconds for fast
solution and 10 minutes for the slow etch solution)
Figure 39 Severe undercut of 2times2 microm2 and 6times6 microm
2 devices
The second run was employed to reduce the wet etching time in total thus dry
etching was needed As discussed above CH4 and H2 are used to etch away the GaAs
and AlAs semiconductor material while O2 is used to remove polymer residues To
reduce redundant generated polymer during dry etching the process must be separated
into several goes (runs) In this run at the mesa etch step the metal area is covered by
S1805 resist and then the plasma etches down until the heavily doped Ohmic layer is
reached For the isolation step the slow wet etching solution is used to ensure the
semiconductor under the bridge is removed The etching time is still long ie over 5
Zoomed Zoomed
104
minutes Hence this will still generate appreciable undercuts Although this run
managed to reduce the wet etching time it still did not solve the undercut Figure 310
shows undercuts under the effective mesa area still occurring in this run
Figure 310 Device with emitter area of 2times2 microm2 and 6times6 microm
2 after dry etch and wet etched
Further investigation has been made to find the root cause of this issue Scanning
Electron Microscopy (SEM) picture were taken to see deep into the completed devices to
investigate what is actually happening Figure 311 shows clearly that the semiconductor
under the bridge and effective area under the 2times2 microm2 device went missing The same
goes to for the large device where about half the size of the designed effective area under
to metal was also unintentionally removed by the solution
Figure 311 SEM Images of the GaAs sample
Since this work was also run together with an InGaAs based sample
(XMBE326) new knowledge regarding etching profile was acquired The lesson learnt
from this run is that the wet etch profile of the Gallium Arsenic (GaAs) material is
totally different from that of InGaAs Figure 312 shows the cross section of GaAs and
InGaAs materials after wet etching The evidences of these issues are also indicated by
the SEM images in Figure 313 and Figure 314 This more or less explained the reason
why the semiconductor under the top metal contact is always missing when wet
chemical etching is applied
Zoomed Zoomed
105
Figure 312 The cross-sectional view of InGaAs (left) and GaAs (right) samples used in this study
Figure 313 SEM images taken from the XMBE304 samples and a GaAs test sample
Figure 314 SEM images for InP and InGaAs taken from [56]
Furthermore previous work done by co-worker Dr Md Adzhar Md Zawawi has
optimised the process for RTD samples based on InGaAs and InAlAs heterojuction
semiconductor materials In this work Dr Zawawi found out that achieving submicron
dimensions is possible when using the soft reflow technique on InGaAs[102] However
it does not apply to GaAs when using the same technique There are few reasons to
106
believe that the work that was carried out by the previous student is not repeatable to the
XMBE304 GaAsAlAs material The main reason is due to the much thicker Ohmic
layers used in the GaAs of ASPAT structures which requires longer etch time The
sample that was used in the previous submicron work namely XMBE277 (RTD) [101]
and corresponding epitaxial layer structure is attached in appendix III The thickness
needed to be removed for the MESA step is 1421Aring compared to XMBE304 (ASPAT)
which is ~6900Aring
The fabrication results shown from the Air-Bridge design does not seem
favourable to the GaAsAlAs heterojunction sample These include unreproducible IV
characteristics and excessive undercut under the metal Therefore the GaAsAlAs
ASPAT sample cannot be processed using this type of mask (Air-Bridge approach) The
fabrication efforts were then moved to the Dielectric Bridge design described below
342313 DC measurement
Fully functional ASPAT I-V characteristics were not obtainable in this run due to
severe damages caused by the undercuts that happened underneath the top metal contact
As can be seen from Figure 315 the behaviour of the current response suggests a very
leaky diode This confirms that the air bridge approach does not work with the
GaAsAlAs ASPAT diode
Figure 315 Short circuit behaviour on one of the fabricated device in this run
-0015
-001
-0005
0
0005
001
0015
002
0025
003
0035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
mp
)
Voltage (Volt)
30x30BP
107
34232 Fabrication Process of the Dielectric-Bridge Design
Since the Air-Bridge design was not successful an alternative Dielectric-bridge
process flow was then designed to solve this issue The first run in this Dielectric-bridge
process was performed to ensure that when the fabrication was completed it was able to
produce the correct and reproducible ASPAT current-voltage characteristics The
process flow in this run is to follow the initial design which identifies the steps according
to the mask number Step 1 to step 4 in the process are exactly the same as in the 1st Gen
mask design Step 5 which is the bond pad process is then continued with spin coating
the AZ2microm After exposure and development a TiAu metal scheme with a minimum
thickness of approximately 1 microm is deposited
Table 36 Standard fabrication process flow for Dielectric-Bridge design
Mask Number Step number Process
1 1 Top Contact
22A 2 Mesa Etch
3 3 Isolation
4
5
6
7
4
5
6
7
Bottom Contact
Bond Pad
Via Etch
Bridge
Step 6 is quite complicated compared to the other steps where the introduction of
S1805 resist is used as a dielectric layer to prevent short circuit between top and bottom
contacts This includes opening the smallest via (holes within the dielectric layer) of 2times2
microm2 and 6times6 microm
2 emitter sizes This step started by spin-coating the S1805 resist and
was then followed by baking it at 150˚C for 30 minutes The longer baking time is to
ensure it is hard enough to be deployed as a dielectric layer Once the S1805 had
hardened as dielectric layer the sample was then spin-coated again with S1813 (thicker
resist) on the dielectric layer to act as a mask for vias opening (to cover the dielectric
layer from via etching damages) After the S813 was developed O2 plasma etches was
108
applied to remove the S1805 that covered the top metal and bond pads The hole on the
metal was then exposed This required only two minutersquos plasma etches time
As soon as the holes were created within the dielectric layer a quick clean to
remove S1813 was performed using Acetone and IPA This has to be fast enough to
remove the S1813 without removing the S1805 dielectric layer Mask 7 then defined the
area for the metal that will fill up into the open vias This metal connected the top
contact metal of the device to the bond pad (GSG pad) The same metal scheme as
mentioned in Section 3422 was used as the bond pad
The fabrication using the dielectric bridge approach in the 2nd
Gen mask design
appeared to work successfully when initial I-V characteristics were taken and it also
showed that the ASPAT diode was fully functional However using hardened S1805 as
a dielectric layer is not a good practise for manufacturing device since there were left
over residue on the sample surface as depicted in Figure 316 This residue comes from
the non-uniformity of S1805 resit that was formed during heat treatment Therefore the
next run was to avoid using S1805 but replacing it with a standard dielectric layer based
on Silicon nitrite (Si3N4)
Figure 316 The surface of the sample after final processing
342321 DC measurements
Given that the process of qualifying mask steps for GaAsAlAs ASPAT diodes
looked promising using the dielectric bridge approaches initial I-V characteristics
measurements were carried out for XMBE304A Figure 317 shows that the I-V
characteristics are comparable to those of the other runs ie in the 1st Gen mask
Noticeably the IV characteristic (Figure 317) between each device size does not scale
109
on a single line This is attributed to the unintentional variation in the size of the emitter
during wet etching within each sample
Figure 317 IV characteristics of sample XMBE304 for emitter sizes of 1000 microm2 2500 microm2 900
microm2 400 microm2 225 microm2 100 microm2 and 36 microm2
The current densities shown in Figure 317 are calculated based on a reduced
effective area of the devices by a factor of 08 This assumption is made as actual area
(without metal) is un-measurable Theoretically devices with small areas will have
higher resistances compared to larger devices However the opposite occurred in these
devices This problem is still under investigation It could be due to the spreading
resistance producing different values according to device sizes (smaller devices have
longer D while bigger devices have shorter D)
34233 Dielectric-Bridge Process Optimization (Si3N4)
Due to poor surface roughness of the sample when using S1805 as dielectric
layer this run was employed to improve the surface quality by using Si3N4 In order to
get the actual size of the emitter the processing needed to start by defining the
semiconductor area using either top contact mask or mesa etch mask and not to deposit
the metal first Smaller effective area will be obtained if the top contact mask is used to
define the area compared to the MESA mask since there are 05 microm and 1 microm tolerances
designed in the MESA mask
-000001
0
000001
000002
000003
000004
000005
-2 -1 0 1 2
Cu
rren
t D
en
sity
(A
mp
microm
2 )
Voltage (Volt)
Current Density vs Voltage
density36
density100
density225
density400
density900
density2500
density10000
110
Table 37 New arrangement of the mask number and step in Second Run
Mask Number Step number Process
3 1 Isolation
22A 2 Mesa Etch
4 3 Bottom Contact
6
1
7
5
4
5
6
7
Via Etch
Top Contact
Bridge
Bond Pad
The fabrication was initiated by isolating each device using Mask 3 to define
them individually Then MESA mask (Mask 2) was used to cover the area from wet
etching optical measurement were used to obtain the actual size of the emitter without
metal Figure 318 shows the process results after H3P04H2O2H2O etching for a ratio of
3150
Figure 318 Optical images after MESA etching (a) 1 microm Tolerance (b) 05 microm Tolerance
Although the mask was designed with smaller size of 6times6microm2 using the slow etchant
solution the effective emitter size can still shrink to ~3times3 microm2 and ~2times2 microm
2 as can be
seen in Figure 318 The next step was to define the bottom contact using a metal scheme
that is suitable for GaAs ohmic layer ie AuGeNiAu After lift-off the samples were
then cleaned and spin-coated with AZ2microm Then the area was defined by using Mask 6
allowing the exposed area to be filled by Si3N4 which is the dielectric layer used in the
second run However a tricky issue happened here as the Si3N4 was difficult to lift-off
especially on the smallest emitter area in this mask In this run the lift-off process was
successfully done after three days Step five which uses Mask 1 was to define the top
111
contact The same metal scheme will fill up the tiny holes within the dielectric layer to
attach on the emitter semiconductor Figure 319 below shows an optical image of a
6times6microm2
device after the top contact lift-off process Once lifted-off annealing took place
to ensure Ge diffuse into the GaAs contact layer to lower the resistance
Figure 319 After lift-off processing
Step six uses Mask 7 to define the area of metal connection between active areas
to the bond pad In this step and step seven a different metal scheme from the top and
bottom contact was used to connect metal to metal Here a TiAu scheme was used The
final step (step 7) was to define the bond pad area In this context mask 5 is used The
bond pad requires thicker metal thickness to reduce the series resistance and to increase
the robustness of the metal surface when probed with needles during measurements
This second run of 2nd
Gen mask dielectric approach went well with better samplersquos
surface when using Si3N4 as the dielectric layer compared to the previous run using
S1805 Once the bond pad were defined for each device as done in previous run the
preliminary current-voltage characteristics of the Si3N4 run were obtained This is
described in the next section
342331 DC measurements
As mentioned in the previous section the Si3N4 run started with a defined emitter
area This allows actual ASPAT dimension to be measured thus the current density
versus voltage that are plotted in the following figures are based on actual measured
sizes
112
Figure 320 The current density of XMBE304 processed using Si3N4 as dielectric layer
Although the actual area of each device is obtainable from measurement the current
density of this sample does not scale well either Figure 320 show the current density is
not scalable from 03V to 1V This probably happened due to the same issue related to
the spreading resistance for each diode varying To investigate this issue new runs were
required with intention of reducing Rsprd and were expected to lead to more scalable
devices Therefore a study of reducing the spreading resistance (Rsprd ) due to
contribution of the large D-gap was carried out using the 2nd
Gen mask with the Si3N4
dielectric bridge approach The following section discusses in detail the steps used in
reducing the gap between the top and bottom contact for the GaAsAlAs ASPAT diode
34234 Dielectric-Bridge (Si3N4) Process Optimization by varying the D-Gap
The series resistance as discussed in detail in Section 26322 is generally due to
the total contribution of specific contact resistance in particular the diode size the sum
of all doped layer resistances that sandwich the main ASPAT layer and the spreading
resistance which comes from the lateral structure diode design[33] Thus in order to
acquire better performance at high frequency these contributors must be controlled One
parameter that can be controlled through this fabrication process is to reduce the
spreading resistance by controlling the separation between top and bottom contact ie
the D-gap as indicated in Figure 321
-000001
0
000001
000002
000003
000004
000005
-1 -05 0 05 1
Cu
rren
t D
ensi
ty
(Am
pm
2)
Voltage (Volt)
Current Density vs Voltage
D36
D100
D225
D400
D900
D2500
D10000
113
Figure 321 side view of lateral ASPAT structure
Without designing a new mask at this stage the same 2nd
Gen Dielectric-Bridge
mask was used but the process flows did not follow the sequence order of mask
numbers The reason for deciding not to design a new mask to reduce the D-Gap was
because the fabrication process flow had not yet confirmed it repeatability and
reproducibility Thus the available photo mask at that moment was fully utilised
Furthermore the feature of the 2nd
Gen mask that included the mesa tolerance can be
exploited in this study Hence the initial idea was to reduce the length of D by using the
tolerance that was designed in with Mask 2 (MESA etch mask)
Table 38 New arrangement for the Third run using Dielectric-Bridge mask
Mask Number Step number Process
1 1 Mesa Etch
3 2 Isolation
3
2
3
4
Bottom Contact
Mesa Cover
6
1
7
5
5
6
7
8
Via Etch
Top Contact
Bridge
Bond Pad
The process therefore was initiated by cleaning the sample and was then
followed by spin-coating it with S1805 to cover the emitter contact and define the actual
D-gap
114
size of the diode This first step used Mask 1 with wet chemical etching using the slow
solution (H3P04H2O2H2O etch with a ratio of 3150) Once the resist was striped
optical measurements were performed to obtain the effective area of the emitter Figure
322 below shows the smallest emitter area obtained after etching
Figure 322 The measured size of the emitter area and the length D (blue color marked)
Step two was to isolate the devices individually by using Mask 3 This was
performed using the fast etch solution (H3P04H2O2H2O etch with ratio of 212) This
took about 10 seconds to remove about 10000Aring of material
Step three which involved two masks was the most complicated in this process
Firstly Mask 3 was used to define the bottom contact by covering the sample with
AZ2microm and then the sample was hard- baked at 190 ˚C for 4- 5 minutes to ensure it had
totally dried before applying Polydimethylglutarimide (PMGI) The PMGI type used in
this process is Lift-off Resist (LOR) SF11 After spin-coating the SF11 at 7000RPM for
45 seconds it was post-baked at 190 ˚C for 4 minutes This was done to ensure that the
LOR SF11 was hard enough for the S1805 to stick on it This was followed by spin-
coating S1805 at 4000RPM for 30 seconds and exposing it under i-line UV for 20
seconds and developed using Micro Dev mix with DI water (11 ratio) for one minute
When the correct shape of S1805 was formed the sample was exposed under flood UV
for 15 minutes The SF11 was developed with 101A developer for 1 minute Figure 323
below summarizes the whole process in step three The step three processes concluded
by depositing the bottom contact with alloyed metal scheme and once lift-off had taken
place the next step continues as usual
115
Figure 323 Summary of LOR technique steps
Step four as well as the subsequent steps were completed in this run by copying
from the previous run (ie second run) which was to deposit the Si3N4 as the dielectric
layer and so on All the devices that underwent fabrication using this technique were
measured under optical microscope MC60 assisted by the Walsall software tool in the
lab From the measured value obtained it was expected that reducing the length of D in
this technique would improve the spreading resistance by up to 70 from the original
2nd
Gen mask design Table 39 summarizes the calculation of original spreading
resistance and improvement using this technique The calculation method and equation
are taken from Section 26322
Table 39 The outcome of the spreading resistance before and after using LOR technique
Device Size(microm2) D-original(microm) RSprd(Ω) D-new(microm) RSprd(Ω)
100x100 4 056 163 023
50x50 14 327 194 054
30x30 19 602 163 097
20x20 21 832 212 135
15x15 22 1007 202 18
10x10 24 1293 205 252
6x6 25 1643 230 418
116
Technically from the experiment in this run it was observed that the development time
also controlled the final length of D longer development time produced shorter D
lengths while shorter time yielded larger D gap lengths Therefore in this run the
development time was kept constant because of the desired D length from the mesa
tolerance in general is only ~2microm
342341 DC measurement
As usual when wafer processing was completed early DC measurement took
place to check the diodes performance Each diode size was measured and compiled
into one graph as shown in Figure 324 It is clear that the performance was better than
that in the previous run in term of scalability and current conductivity
Figure 324 IV characteristic in 3rd run (reduced d-Gap) for each diode size on the mask
To compare the current conductivity from this run and the previous run current
density at 05V was measured for both 2nd
and 3rd
runs Assuming the contact resistances
(TLM) for both runs were constant for 50times50microm2 device size the improvement of
current in the 3rd
run is about 92 This showed that such approach to reduce the D-gap
-500E-06
000E+00
500E-06
100E-05
150E-05
200E-05
-2 -15 -1 -05 0 05 1 15 2Cu
rre
nt
De
nsi
ty (
Amicro
m2)
Voltage (Volt)
Den_100microm2
Den_225microm2
Den_400microm2
Den_900microm2
Den_2500microm2
Den_10000microm2
Den2_36microm2
117
was successful in this run A new mask design was ready to take the challenge for
processing toward millimetre and sub-millimetre wave application
343 Fabrication process of GaAsAlAs ASPAT diode toward High frequency
Applications
So far the information that can be gathered from previous processing is that the
optimum process flow is achieved through dielectric approach design The effort in
reducing the series resistance by lowering its biggest contribution was attained through
lowering the D-Gap in the structure Once everything had been optimized ie the
process flow series resistance junction capacitance etc it was time to develop a new
mask design which only focused on the development of small ASPAT devices for use in
the millimetre and sub-millimetre wave regions
3431 Third Generation (3rd
Gen) mask design
The 3rd
Gen mask design was developed by taking into the account every aspect
of parameters that can contribute to the device by means of robust devices that are able
to function properly at ultra-high frequency The device cut-off frequency is given by
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(31)
Here RS is the series resistance and Cj is the junction capacitance To obtain high cut-off
frequencies Rs and Cj must be kept as low as possible From the fabrication point of
view two parameters that can be directly and easily controlled are the device area (A)
and the D-gap (which contributes to Rs)
Therefore calculations were made to find the best option Table 310 shows the
calculated value of capacitance (eq230 in page 44) and cut-off frequencies (eq31
above) for the ASPAT diodes studied These two equations extract the cut-off frequency
of the ASPAT assuming no external effects and for fully depleted devices The
XMBE304 ASPAT sample is expected to be suitable for millimetre wave applications
if small devices are successfully made In real devices sub-millimetrewave operation
can be hard to achieve due to increased series resistance and other process related
parasitics
118
Table 310 DC and RF characteristics for XMBE304
Device Size (microm2) Fully depleted
Capacitance(fF)
Calculated Series
Resistance (Ω)
Fully depleted Cut-Off
Frequency(GHz)
10000 5490 04 72
900 490 15 216
36 198 7 1148
16 879 11 1646
4 22 29 2500
Therefore in the 3rd
Gen mask design the smallest device that can possibly be obtained
in the GaAs based material fabricated using i-line lithography which is available at the
University of Manchester is 2times2microm2 and the gap between top and bottom is 15microm at
least The connecting bridge technique applied only utilised dielectric bridge method for
GSG features Figure 325 shows the layout of actual 3rd
Gen mask used in this study
There are 344 die chips on this type of mask design It also includes the Ground-signal
ground pad with 50um pitch for each chip and six de-embedding test structures as well
as eight TLM structures
Figure 325 3rd
Gen Mask layout showing actual devices de-embedding TLM and alignment mark
structures used in this study
119
This mask is designed generally from optimizations from 2nd
Gen Mask which
deploys a dielectric bridge for connection between the devices to the bond pads
Consequently the processing steps are not being much different but mostly follow what
is shown in Table 311 below The difference only applies to the much smaller mesa
size Other features included in this mask are de-embedding structures for RF
measurements via-hole test structure TLM structures and parallel plate capacitance test
structures
Table 311 3rd
Gen Mask process step
Mask Number Step number Process
1 1 Mesa Etch
2 2 Isolation
3
4
3
4
Bottom Contact
Mesa Cover
5
6
7
5
6
7
Via Etch
Top Contact
Bond Pad
The high frequency fabrication process flow is summarized in the following section
which shows illustrations in three dimensional and cross sectional (Figure 326) views
for easy understanding
34311 Step by Step Processing
0 Wafer preparation
Cleaning using NMP and DI
water or
Acetone and IPA
120
1 Mesa Etch
2 Isolation
3 Bottom Contact
4 Mesa Cover (Dielectric Deposition)
5 Via Etch
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 3110
Etching using etchant solution
H3P04H2O2H2O etch with ratio
of 212
Metal deposition with metal
scheme AuGeNiAu for
~500nm thick
Dielectric deposition 500nm
thick Si3N4
Via etch to open holes for metal
contact using reactive ion
etching using CF4
121
6 Top Contact
7 Bridge and Bond Pad
Figure 326 Step by step device fabrication (in 3D and cross-sectional view) for semi-insulating
substrate device type used in this study
Figure 327 Example finished process device with bond pad using 3rd
Gen mask
3432 TLM measurements
Transmission Line model (TLM) measurements for this run were carried out
after annealing (ie at 420˚C for 2 minutes) for process control monitoring by extracting
contact resistance (Rc) values These values are a measure of the quality of ohmic metal
contacts for a given process As discussed in Chapter 2 the TLM technique used four-
Metal deposition with metal
scheme AuGeNiAu for ~500nm
thickness and thermal annealing
420˚C for 2 minutes
Metal deposition with metal
scheme TiAu (1microm thick)
122
point measurement on TLM test structures located around the 15times15mm2 tiles as shown
in Figure 222 (in page 55) Normally five TLM structures are measured across the tile
for both top and bottom contacts Figures 328 and 329 display graphical TLM results
for top and bottom contact respectively As can be seen both graphs exhibit excellent
uniformity
Figure 328 XMBE304 TLM measurement for the top contact after annealing
Figure 329 XMBE304 TLM measurement for the bottom contact after annealing
Based on the graphs above for the top metal contact the average contact
resistance (RC) value using the metal scheme of AuGeNiAu is found to be ~005Ωmicrom
and the sheet resistance (RSH) is 22Ω However for the bottom contact the average
value for contact resistance is 012Ωmicrom and sheet resistance obtained is 26Ω Both
values are in a very good agreement with the known doping of both ohmic contact
0
2
4
6
8
10
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins top contact
y = 02592x + 02375
0
2
4
6
8
10
12
14
0 10 20 30 40 50
Res
ista
nce
(O
hm
s)
Spacing (microm)
After 420C for 2mins bottom contact
y = 02157x + 01053
123
layers Therefore the specific contact resistance (Eq 250) that contributes to the total
series resistance can be calculated and the value obtained is 15Ωmicrom2 and 54Ωmicrom
2 for
top and bottom TLM structures respectively
3433 DC characteristic measurements
Again once the wafer processing is completed room temperature DC
characteristics are taken using an HP 414B or HP500B parameter analyser and its actual
setup is as described in Chapter 2 This initial measurement was to ensure the
functionality of the diodes For this run using the 3rd
Gen mask the I-V measurements
for mesa active area of 4times4microm2 6times6 microm
2 and 10times10 microm
2 were taken and are depicted in
Figure 330 Figure 331 and Figure 332 respectively Nine diodes were measured for
each three device sizes to check their uniformity Thus the average current and standard
deviation are taken at two voltage steps of 1V and 15V Table 312 summarizes the
standard deviation for each measured data obtained from this final run
Figure 330 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
4times4microm2 mesa size
-00005
0
00005
0001
00015
0002
00025
0003
00035
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C01_4um_1P_SI
C22_4um_1P_SI
C40_4um_1P_SI
W01_4um_1P_SI
W22_4um_1P_SI
W40_4um_1P_SI
AI01_4um_1P_SI
AI22_4um_1P_SI
AI40_4um_1P_SI
124
Figure 331 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature for
6times6microm2 mesa size
Figure 332 XMBE304 GaAsAlAs ASPAT measured IV characteristics at room temperature
for 10times10microm2 mesa size
Table 312 Standard deviation at two different voltages
Device size (um2) Standard Deviation 1V () Standard Deviation 15V ()
4times4 14 14
6times6 65 72
10times10 44 39
Noticeably the standard deviation of the device increases for the smaller size
devices This trend happened probably because the active mesa area is not uniform
causing different series resistances Since the smallest mesa active area which achieved
-0001
0
0001
0002
0003
0004
0005
0006
0007
0008
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C02_6um_1P_SI
C23_6um_1P_SI
C41_6um_1P_SI
W02_6um_1P_SI
W23_6um_1P_SI
W41_6um_1P_SI
AI02_6um_1P_SI
AI23_6um_1P_SI
AI41_6um_1P_SI
-0005
0
0005
001
0015
002
0025
-3 -2 -1 0 1 2 3
Cu
rren
t (A
)
Voltage (V)
C03_10um_1P_SI
C24_10um_1P_SI
C42_10um_1P_SI
W03_10um_1P_SI
W24_10um_1P_SI
W42_10um_1P_SI
AI03_10um_1P_SI
AI24_10um_1P_SI
AI42_10um_1P_SI
125
a good I-V characteristic is 4times4microm2
in this run these devices were used for the next step
of characterisation which is the S-parameter measurement to extract their behaviour at
different frequencies
35 Conclusions
In this chapter basic fabrication techniques of GaAsAlAs ASPAT on both doped
and semi insulating substrates using standard I-line lithography as well as step by step
descriptions to achieve reproducibility in the process fabrication flow has been
demonstrated with relevant initial measured results Two major outcomes have been
demonstrated firstly related to repeatability reproducibility and manufacturability
mostly done on large device areas (15times15microm2 to 100times100 microm
2) Secondly a successful
process flow for small emitter size devices (2times2 microm2 to 10times10 microm
2) has been
developed
Subsequently two types of designs during process optimization were developed
namely Air-Bridge and Dielectric-Bridge approaches The latter approach seems
favourable for GaAsAlAs materials but was only successful when reducing the series
resistance of the device This problem was addressed by optimising the D-gap between
top and bottom contact which resulted in good scalability of each ASPAT dimensions
improving current conductivity by 92 and achieving a reproducible process On the
other hand in the former approach issues were encountered with over etching underneath
the diode effective area and thus it was hard to achieve reproducible devices
Repeatability reproducibility and manufacturability fabrication processes based on
dielectric bridge method were successfully developed This new process provides a
highly efficient and economical solution for the fabrication of GaAsAlAs ASPAT
diode Emitter sizes down to 4times4 microm2 dimensions are routinely and reproducibly
achieved in this process Series resistance which is an important parameter in
determining high frequency application are greatly reduced by changing the gap between
top and bottom contact
With all the new improvements implemented the possibility of the proposed Dielectric
Bridge method fabrication process was successfully applied for the fabrication of
ASPAT diodes
126
4 PHYSICAL MODELLING OF THE GAASALAS ASPAT
DIODE USING SILVACO
41 Introduction
Fabricating any device or circuit requires a lot of time resources cost etc
especially elements related to the production of semiconductor devices Furthermore in
realising such a device a clean room is required Hence fabrication and processing in
wafer fab need full attention to get it done with a higher rate of success reproducibility
and manufacturability One solution that can be highlighted which will be able to reduce
all the resources that are mentioned above is by using computer simulation approaches
or to be precise physical modelling For epitaxial layer based devices physical
modelling is a good choice as it would give a better understanding and insight into each
layer and how electrical characteristics are derived A software that is most suitable for
epitaxial layer physically modelled is SILVACO This software is a very comprehensive
tool to simulate epitaxial based devices and to predict their behaviour Such software
covers many aspects starting from the first principles of physic epitaxial layer
definition as well as device layout thus making it the most powerful virtual wafer fab
tool in the market
In this chapter the SILVACO packages are discussed The discussions include the
method of defining a new material defining models and constructing the AC or DC
supply to obtain the output characteristics of the virtual device Apart from these the
focus will also be on the ASPAT diode modelling simulation and analyses of the results
which will include the ASPAT structure suitable models and DC current-voltage
characteristics The dependencies of individual structure on the I-V curves will also be
highlighted Finally the discussion of results and analyses involving a range of
operational temperatures dependency as well as from comparison made to conventional
SBD used in this study will be examined
127
42 SILVACO modelling Tools
SILVACO is a modelling software introduced in 1984 by Dr Ivan Pesic It is
purposely created for electronicsrsquo devices physical modelling and characterization This
software company has become the major supplier for most of the Electronic Design
Automation (EDA) for circuit simulation amp design of analogue Mixed-Signal and RF
circuit market This Technology Computer Aided Design (TCAD) software can predict
the simulated device performances starting from first principles It has a package which
can provide Virtual Wafer Fabrication (VWF) simulation to the device designer and
which has the capability to perform two or three dimensional physical device modelling
by using the ATLAS simulator [103] SILVACO allows all parameters such as
electrical thermal and optical characteristics of a device to be simulated under desired
bias conditions It offers cost effectiveness as well as quick prediction of results for
many semiconductor devices compared to real experiments Some hands-on experiment
may not always perform hence SILVACO can be used as an alternative
The core of SILVACO is Atlas itself which provides a platform to perform DC AC
and transient analysis for such dimensional device structure regardless of the
heterojunction material type ie binary ternary quaternary etc As the brain of
SILVACO Atlas which receives input command files containing instruction text for
execution from a runtime environment known as Decbuild will process the instruction
text and display progression error and warning via Runtime Output All the calculations
of the resultsoutcomes of the simulation are plotted via a tool called TonyPlot which is a
tool to visualise the output Figure 41 below shows how precisely the physical
modelling takes place the process of building the structure how its parameters and
variables are defined how an appropriate model statement is selected how performance
is analysed and lastly how the outcomes are displayed
128
Figure 41 SILVACO Atlas simulation process flow
As can be seen in Figure 41 the structure specification statement is used to define
any desired structure by setting the command in Deckbuid of the following parameters
a) Mesh where the structure can be defined either in 2D or 3D Cartesian grids The
unit of the coordinates used is in microns and the spacing parameters which
define the netting size can be used to improve the accuracy of the analysis at any
given position The density of netting size in this statement determines the
processing time
b) Region where the multi-layers in a structure are defined and this statement has
to outline each layer that represents a separated region independently The mesh
must be assigned to a region and the sequence of the region is arranged from low
to high
-Mesh -Region -Electrode
-Contact -Material
Structure Specification
-Model -Interface
Model Specification
Method
Numerical Method
-Log -Solve -Load -Save
Solution Specification
-Tony Plot
Display Results
129
c) Electrode are used to define the location of bias point for a designed structure
when performing the electrical analysis In this work or for the case of a diode
two electrodes are allocated as an anode and a cathode In a vertical device the
latter electrode is placed at the bottom of the device while the anode is at the top
d) Doping this statement refers to doping concentration injected into the desired
region and it normally depends on the material types
e) Materials since SILVACO was developed specifically for Silicon-based devices
default parameters are set up for Silicon properties However the use of
materials statement allows SILVACO to run for different material ie GaAs
InGaAs etc In order to make it work this parameter is defined first and then
followed by the material name and its properties such as bandgap permittivity
conductionamp valence band discontinuities mobility etc
The most crucial part is to determine whether the simulated structure of a particular
device is correct or incorrect This is done by properly choosing the specific model
statement The Specific model statement is employed to express the physic equations
that are used during the device analysis The models statement depends solely on the
structure definition Examples are device structure with double barrier use Non-
equilibrium Green function (NEGF) model and single barrier uses Semiconductor-
insulator-Semiconductor (SIS) model for effective and accurate analysis process For the
case of a single barrier in SILVACO there are many model statements that can be used
for such analysis Therefore it is recommended to check model by model in order to
ensure that all the needed parameters are defined in the material statements and results
produced are valid
SILVACO is able to calculate such models by using different numerical methods
which means semiconductor device problematic is computed to make successive
solutions by random discretisation There are three different numerical methods that are
regularly used by SILVACO to perform its calculations which are Newton Gummel and
Block Basically this is solved by using a non-linear iteration procedure which begins
from an initial guess and which then uses an iterative process to find the predicted
solution The detail of these can be found in reference [103]
130
In order to turn on the problem solution the solution specification is defined This
include log solve save and load statement All these work together to provide data for
analysis by other functions The log statement is a file type that saves in memory and can
be loaded by Atlas Any solved device will be stored in the log file Therefore it is
necessary to define the LOG before SOLVE statement and close it after the calculations
While the save statement is used to store all data point to a node in the output file the
load statement is utilised to recall all the saved data to be read by Atlas
Finally all these files can be displayed or plotted on TonyPlot it is recommended to
make SET files at plotting point for a better visualisation The plotted or displayed files
in TonyPlot can be manipulated for scaling graphs overlaying different curves and most
importantly to export the data to other files formats
43 SILVACO Implementation GaAs AlAs ASPAT Modelling
The structures play an important role in determining the terminal output
characteristics Therefore to start simulating the ASPAT device the first thing that must
be specified is its structure As mentioned earlier in Section 3412 the ASPAT diode is
a top down multilayer structure This structure which is adopted from that of Section
3412 will be used as a basis to perform the ASPAT simulation Figure 42 shows the
structure of the ASPAT in this real simulation which is exactly the same as been
discussed in Section 26322 The ASPAT diode consists of two heavily doped (up to
5x1018119888119898minus3) GaAs contact layers on top and bottom slices adjacent to lightly doped (up
to 3x1017119888119898minus3) GaAs intermediate layers In between these layers is a sandwiched
structure consisting of two different lengths of undoped GaAs spacer layers and a thin
layer of AlAs that act as a tunnel barrier In this work the simulation result will be
compared with the fabricated measurement result depending on the size of the diode
The actual device that will be used to validate the simulation is the main device used in
this study (XMBE304) which is based on a lattice matched GaAsAlAs grown on a
semi-insulating substrate Therefore the design structures that are proposed in the
fabrication are compatible with the fabricated devices and are based on lateral structures
as can be seen in Figure 42
131
Figure 42 The GaAsAlAs ASPAT structures produced from simulation based on the diode
multilayer heterostructures on the right
In the consequent simulations a key observation regarding the AlAsGaAs
heterojunction is that there are two types of tunnelling processes direct tunnelling and
indirect tunnelling Figure 43 shows the Energy-Momentum (Ek) diagram depicting the
three valleys for the AlAs conduction band namely L Γ and X points In normal
circumstances the transition of electrons happens to the X-point which is the lowest
energy in the conduction band In the case of very thin barrier the tunnelling process
occurs at the Γ point in both AlAs and GaAs materials which is the direct tunnelling
process[18] It has been reported that in the case of an ASPAT diode tunnelling which
occurs at the Γ point will be the dominant component in the tunnelling current
Therefore the actual band gap will be different from the one at the X-point which is
which 216eV[15] By contrast the energy band gap at the Γ-point is around
283eV[104] Thus this simulation uses this band gap value
Figure 43 The Energy-momentum diagram for AlAs heterojunction semiconductor
216eV
Γ
X
E
K
L
AlAs
CB
VB
283e
132
The simulation code as attached in Appendix IV and the output of the simulation with all
the input mentioned above are shown in Figure 44 (a) and Figure 44 (b) Figure 44 (a)
is the band diagram at equilibrium and Figure 44 (b) is the band diagram when a bias is
applied
Figure 44 (a) The conduction band and the valence band of the ASPAT diode structure (b) the
energy band diagram of the ASPAT diode structure when under three different biases
44 Simulation Result and Analysis
Basically the SILVACOrsquos Atlas simulation package is used to calculate the I-V
characteristics from multilayers structures In the case of GaAsAlAs heterojunctions all
details of the structure as shown in Figure 44 above are calculated based on solving the
Schrodinger time-independent equation in each layer taking into account the variation of
effective mass and conduction band offset between GaAs and AlAs
For thermionic emission and tunnelling mechanism across an abrupt heterojunction
interface the general method used in SILVACO is taken from K Y Yang work [105]
The tunnelling current of the ASPAT diode uses the equation below[74]
119869 = sum2119898lowast119864119894(1 minus 119877)119896119879
1205872ħ3
119873
119894=1ln [
1 + exp (119864119865 minus 119864119894
119896119879)
1 + exp (119864119865 minus 119881 minus 119864119894
119896119879)]
(41)
Where m is the electron effective mass E denotes the energy of the electron R is the
total resistance k represent Boltzmann constant ħ is the reduced Planck constant EF is
the fermi level V is applied voltage and Ei is the electron energy perpendicular to the
-2
-15
-1
-05
0
05
1
15
1
82
16
3
24
4
32
5
40
6
48
7
56
8
64
9
73
0
81
1
89
2
97
3
Ene
rgy(
eV
)
Thickness (microm)
VB
CB
133
barrier The important parameters that enable SILVACO Atlas to perform correct
calculations and analysis are the choice of appropriate models The suitable model that is
available for evaluating the GaAsAlAs ASPAT is based on the Semiconductor-
insulator-semiconductor (SIS) model
Thus in this run Non-local Quantum Barrier Tunnelling Model (SISEL and
SISHO) are utilized specifically semiconductor-insulator-semiconductor mode This
model enables the tunnelling current between two semiconducting regions separated by a
quantum barrier to be calculated [103] It is assumed that the charge tunnels across the
whole barrier with the source or sinks at the interface with the semiconductor regions
Under the Non-Local Quantum Barrier tunnelling model another model that can be used
is semiconductor-semiconductor-semiconductor (SS) tunnelling model if the materials
are specified By correctly inserting all parameters with the right model an excellent DC
IV characteristic match between simulation and measurement can be produced as shown
in Figure 45
441 DC Current-Voltage Characteristic
In this simulation the current at each bias step and each mesh point can be set up by the
user however the detailed calculation such as formula usage methodology and
approach that is adopted by SILVACO Atlas is unknown As mentioned above in order
to produce the energy band diagram of the ASPAT the DC characteristic of the structure
can be solved by using the Schroumldinger and Poisson equation self-consistently
To ensure that these simulations are valid one fabrication was performed on an
ASPAT diode sample XMBE304 For this sample the structure parameters are the
same as has been set in this simulation The result of the measurement and simulation
are then compared Figure 45 shows that the simulation result is in excellent agreement
with the measured data for this sample
134
Figure 45 The current-voltage characteristic of an ASPAT diode (100times100microm2) and (4times4microm
2)
using SILVACO Atlas simulator for structure device XMBE304 showing excellent agreement
between simulated and experimental data
These fitted results were performed on both a large 100times100microm2 device and the
smallest obtainable from fabrication (4times4microm2) which was to be used for the repeatability
amp reproducibility studies as well as for high-frequency applications study respectively at
room temperature In order to get a good fit a few parameters had been modified in the
SILVACO software via the Deck-built tool for example energy band effective masses
and bandgap discontinuity of GaAs spacer and AlAs barrier (The mentioned parameters
values are summarized in Table 41) The percentages of bandgap discontinuity in
SILVACO using the ALIGN parameter is given by[103]
119860119897119894119892119899 =
Δ119864119862
Δ119864119862 + Δ119864119881
(42)
Where ΔEc and ΔEv are the conduction band discontinuity and valence band
discontinuity respectively The m0 in the tables denotes the electron rest mass Once all
agreement between measurement and simulation has been met the simulation is then
carried out with structure analysis at room temperature and different temperatures
simulation
Table 41 The parameter values used in this simulation
Material Bandgap(eV) ΔEg(eV) Effective mass(kg)
GaAs 1424 03 0067m0
AlAs 2835 071 0126m0
-00002
0
00002
00004
00006
00008
0001
00012
-2 -1 0 1 2
Cu
rre
nt
I (A
mp
)
Voltage V (Volt)
Current vs Voltage
Measurment
Simulation
135
45 Structure Analysis of ASPAT Diode
Once the device structure was modelled and having successfully produced a
precise band diagram as well as validated the simulation results with experimental I-V
characteristics the next step is to further analyse the relationship between basic device
structure and its I-V characteristics This approach is used to predict what would happen
to the DC output if some of the parameters were varied especially with regards to the
AlAs barrier thickness In the subsequence simulations the thickness of each main
ASPAT (unequal spacers and barrier) layer will be studied independently as a variable in
order to determine how each parameter affects the I-V characteristic in both magnitude
and curvature The analysis will also include manufacturing tolerance where the
structure parameter which will result in a 10 difference in their I-V characteristics is
examined[59 75] This will provide an overview of how precisely to manufacture each
layer of the device The following simulation is based on the XMBE304 structure with
emitter size of 4x4microm2
451 Dependencies of current on AlAs Barrier thickness
Since the AlAs barrier is what limits the transportation of electron flow and
hence the current (which depends exponentially on the tunnelling barrier thickness)
therefore the first analysis to run on the simulation is the variation on barrier thickness
In the simulation the barrier thickness is measured in term of the monolayer Generally
one monolayer can be calculated by dividing the lattice constant of the material by two
In the case of AlAs one monolayer is calculated as follows
119900119899119890 119898119900119899119900119897119886119910119890119903(1119872119871) =
119860119897119860119904 119897119886119905119905119894119888119890 119898119886119905119888ℎ119890119889 (5666Å)
2
(43)
= 283Å
The nominal value of the AlAs barrier thickness for sample XMBE304 is 283nm
ie ten monolayers In the first simulation test the current change due to the barrier
thickness variation from 9ML to 11ML was examined first followed by the amount of
barrier thickness change that would produce a 10 change in current The simulation is
setup by fixing all other parameters and varying the AlAs barrier thickness as mentioned
136
above with a step of 02ML In order to determine what fraction of a ML would yield a
10 difference in the current the barrier thickness is slightly changed to fit the curve for
both 5 above and 5 below the original curve
Figure 46 IV characteristics of the dependencies of current on AlAs barrier
The current-voltage characteristics of the ASPAT diode do change dramatically with
barrier thickness in forward bias but not that much in reverse bias (Figure 46) The
current decreases as the barrier thickness increases For a 1ML change in layer thickness
(from 9ML to 11ML) the current changes by over ~300 at 05V
Figure 47 Example of analysis at -1 and 1V to the current
-00002
0
00002
00004
00006
00008
0001
00012
00014
-15 -1 -05 0 05 1 15
Cu
rre
nt
(A)
Voltage(V)
9ML
92ML
94ML
96ML
98ML
10ML
102ML
104ML
106ML
108ML
11ML
973E-06
0
0000005
000001
0000015
000002
0000025
000003
0000035
85 95 105 115
Cu
rren
t a
t 1V
B
ias
(Am
p)
Barrier Thickness (ML)
Current change with tunnel barrier thickness
Forward Current
5
-5
137
From the simulation result shown in Figure 46 a 9945ML barrier thickness will
give a 5 higher current and a 10056ML barrier will give a 5 lower current (Figure
47) Therefore in total 01 ML difference yields 10 current difference These indicate
that in order to control the current within 10 barrier thickness difference the growth
precision in the barrier must be precise to better than 01ML Extensive studies have
also shown that the I-V characteristic of a GaAsAlAsGaAs diode is very sensitive to
the thickness of AlAs barrier This work has been reported elsewhere[17]
452 Dependence of current on Spacer I length l1
For the longer spacer length (l1) five different values are chosen from 01microm to
03microm The lengths are changed in the order of 005microm Therefore the arrangement of
length is as follows l1=01microm l1=015microm l1=02microm l1=0 25microm and l1=03microm
respectively The results are plotted from -15V to 15V anode voltage in Figure 48 The
I-V characteristic of the ASPAT diode does not change much with the length in the
forward bias region but in the reverse bias region the current decreases as the layer
thickness increases Here the l1 layer acts as a voltage arm and a small size device
cannot sustain big changes in spacer length Changing the length at the forward region
will also change the energy states on the anode side as well changing the states
distribution on the cathode side in reverse bias
Figure 48 I-V characteristic of the dependencies current to Spacer I layer
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=01
L=015
L=02
L=025
L=03
138
By fixing the current at -1V and 1V the current and the layer thickness relationship is
illustrated in Figure 49
Figure 49 Current changes with layer thickness l1
It is noticeable that there is a dramatic change in reverse current from 01 microm to
05 microm layer thicknesses However the forward current only falls slightly from 01microm to
015microm and is stable afterwards Hence for a small size device a large change in spacer
layer at the cathode will allow more current to pass
453 Dependence of current on Spacer II length l2
Finally is the variation in the spacer II Similar to spacer I above five values are
chosen for the shorter undoped GaAs layer length l2 the thickness is varied from
00025microm to 00075 microm (steps are l2=00025microm l2=000375microm l2=0005microm
l2=000625microm and l2=00075microm respectively The results are plotted from -15V to
15V anode voltage as shown in Figure 410 In this case a slight change in I-V
characteristic in the forward bias can be seen clearly which means the I-V
characteristic depends on the length of the shorter undoped layer Therefore the l2 layer
also acts as another voltage arm due to the asymmetrical length The effect is quite
similar to the spacer l1 but this times the forward current only slight changes The reason
for the small change in current is that the length change is small and it linearly affect the
states distribution
-000002
-0000018
-0000016
-0000014
-0000012
-000001
-0000008
-0000006
-0000004
-0000002
0
0
000005
00001
000015
00002
000025
00003
000035
01 015 02 025 03
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)Reverse Current(-1V)
139
Figure 410 IV characteristic of the dependencies current to Spacer 1 layer
Fixing the current at -1V and 1V the current versus layer thickness relationship is
illustrated in Figure 411
Figure 411Current change with layer thickness l2
The I-V curve depends on the length of the shorter undoped spacer layer quite linearly
The forward current changes in increase to the layer compared to the backward current
The layer thickness l2 should be small as long as it prevents carrier diffusion Therefore
all these three layers must be kept within limit to ensure that the high performance of the
ASPAT diode can be fully utilised
-00002
0
00002
00004
00006
00008
0001
-2 -1 0 1 2
Cu
rren
t (A
)
Voltage (V)
L=75n
L=25n
L=625n
L=5n
L=375n
-2E-07
-18E-07
-16E-07
-14E-07
-12E-07
-1E-07
-8E-08
-6E-08
-4E-08
-2E-08
0
0
00002
00004
00006
00008
0001
00012
0002 0004 0006 0008
Rev
erse
Cu
rren
t (A
)
Forw
ard
Cu
rren
t (A
)
Spacer Lenght (microm)
Forward Current (1V)
Reverse Current(-1V)
140
46 Temperature Dependent Simulation
This section will discuss in detail how changes in operating temperatures influence
the IV characteristics of the ASPAT diode The same codes as in the previous
simulation with fitted results are used for this temperature dependence study but a few
parameters were changed for different temperatures
Theoretically the material parameters that are influenced by the change of
temperature are band gap electron effective mass the density of state (NC NV) light
hole mass heavy hole mass permittivity and electron amp hole mobilities However not
all mentioned parameters will have a large impact on the IV characteristic in the
SILVACO Atlas simulation The most significant factors that give appreciable impact on
the DC output current-voltage were the energy bandgap and the effective mass The
GaAs bandgap as a function of temperature is given by the equation below [106]
119864119892 = 1198641198920 minus
120572 1198791198712
120573 + 119879119871
(44)
Here Eg is the bandgap Eg0 denotes the bandgap at 0K TL is the Temperature α=
Constant (Varshni Parameter) AlAs6e-4 GaAs5405e-4 β= Constant (Varshni
Parameter) AlAs408 and GaAs204 The calculated parameters that are used in this
simulation are shown in Table 42
Table 42 The calculated values of bandgap at different temperatures
Temperature (K) GaAs Eg(eV) AlAs Eg(eV)
77 1506 2903
100 1500 2899
125 149 2893
150 1486 2887
175 1478 2879
200 1470 2871
225 1461 2863
250 1452 2854
275 1443 2844
300 1424 2835
325 1419 2824
350 1414 2814
375 1404 2803
398 1394 2793
141
The effective mass of the materials used in this simulation can be expressed by
119898119899 = 1198980119899 + 11989810 (
119879119871
300119870)
119898119901 = 1198980119901 + 1198981119901 (119879119871
300119870) + 1198982119901 (
119879119871
300119870)2
(45)
Where mn is the effective electron mass mp represents the effective hole mass m1n and
m1p are constant number for the basic GaAs material m0n
for 119898119883119898119871 119886119903119890 119892119894119907119890119899 119887119910 119905ℎ119890 119890119902119906119886119905119894119900119899 (1198981198991199052 lowast 119898119899119897)
13 while m0p is based on the
expression 1198980119901 = (11989811990111989732
+ 119898119901ℎ32
)23 The calculated parameters are shown in Table
43
Table 43 The calculated effective masses for each temperature used in this simulation
Temperatures (K) GaAs Effective Mass (kg) AlAs Effective Mass (kg)
77 00660m0 03790 m0
100 00658 m0 03788 m0
125 00655 m0 03785 m0
150 00652 m0 03782 m0
175 00649 m0 03779 m0
200 00646 m0 03776 m0
225 00643 m0 03773 m0
250 0064 m0 0377 m0
275 00637 m0 03767 m0
300 00634 m0 03764 m0
325 00631 m0 03761 m0
350 00628 m0 03758 m0
375 00625 m0 03755 m0
398 00622 m0 03752 m0
142
Figure 412 Measurement and simulation comparison result as a function of temperature range
from 100K to 398K
Figure 412 above shows excellent agreement between simulation and
measurement results at various temperatures The IV characteristics correspond to a
device of size 100times100microm2 as presented in Chapter 3
47 Temperature Dependence characteristics of GaAsAlAs ASPAT Diodes
As mentioned earlier in chapter one the tunnelling diode has many advantages
over conventional Schottky barrier diodes some of which are a large dynamic range
low power consumption and very weak temperature dependence This section will
discuss the effect of variable temperature applied to the GaAsAlAs ASPAT diode and a
similarly processed TiAu Schottky diode Two samples were fabricated together for
these studies (XMBE304 and XMBE104 representing an ASPAT and a SBD
respectively) The fabrication technique is exactly the same as has been discussed in
Chapter 3 In order to make it fair for direct comparisons as well as easy probing both
diodes were fabricated with the same emitter size (100times100microm2) The DC measurements
at different temperature were carried out using a Lakeshore Cryogenic probe station over
the range of 77K to 398K in 25K step interval
-002
-001
0
001
002
003
004
005
006
-2 -15 -1 -05 0 05 1 15 2
Cu
rren
t I
(Am
p)
Voltage V (Volt)
T=100K_Simu
T=100K_Meas
T=398K_Simu
T=398K_Meas
T=200K_Simu
T=200K_Meas
T=300K_Simu
T=300K_Meas
143
471 GaAsAlAs ASPAT diode vs TiAu SBD
Once fabrication and measurement were completed both DC outputs of the diodes
were characterised and analysed Figure 413 shows a semi-logarithmic plot for
measured current versus voltage as a function of temperature for ASPAT sample
XMBE304 In forwards bias the current changes for different temperatures from 77K
to 398K are less than 5 percent This confirms the very weak temperature dependence of
current transport as it is dominated by tunnelling through the barrier On the other hand
the backward bias shows the current changes at different temperature are slightly bigger
than in forward this due to band bending occurring faster (making the effective barrier
lower) and allowing thermionic emission to significantly contribute to transport of the
current The only other study of temperature dependence for the ASPAT was made by et
el RT Syme[15] but details were not stated in their report
Figure 413 Log Current vs voltage as a function of temperature for ASPAT sample XMBE304
The effective barrier height for the GaAsAlAs ASPAT diode is higher than that of
the SBD (See Figure 414) therefore there is an expectation of more limited thermionic
current flow in the ASPAT than the SBD As mentioned earlier the conventional
Schottky Barrier diode that is used in this study consists of a Gold Titanium and GaAs
(AuTiGaAs) interface which is the baseline for the temperature dependence study
0000001
000001
00001
0001
001
-15 -1 -05 0 05 1 15
Log
Cu
rren
t (A
)
Voltage (V)
T=77K
T=100K
T=125K
T=150K
T=175K
T=200K
T=225K
T=250K
T=275K
T=300K
T=325K
T=350K
T=375K
T=398K
144
Figure 414 The effective barrier high of the Schottky barrier diode and the ASPAT Diode [3]
The SBD epitaxial layers profile is as shown in Table 44 below Theoretically the SBD
obey thermionic emission transport[44] and its I-V characteristic is given by
119868 = 1198680[exp (
119902119881
119899119896119879) minus 1]
(46)
Where q is the electron charge V is the applied voltage across the diode n denotes the
diode ideality factor k is the Boltzmann Constant T is the absolute temperature in
Kelvin and I0 is the diode saturation current which is given by the expression
1198680 = 119860119860lowast1198792 exp (minus
119902empty1198870
119899119896119879) exp (minus120572120594119890
12120575)
(47)
here A is the area of the diode A denotes the effective Richardson constant Oslashb0 is the
barrier height at zero bias δ represents the thickness of interfacial insulator layer χ
denotes the mean tunnelling barrier and α = radic(4120587
ℎ)(2119898lowast) is a constant value The
ideality factor n is taken from the slope of the SBD current-voltage characteristic and in
this study its value varies from 1 to 2 (depending on temperature) In the case of the
ASPAT diode thermionic emission can also happen if a thicker barrier is used (~ 100Aring
or thicker) as shown by CS Kyono et el [104] who concluded that when a thicker
barrier of AlAs barrier is used the current transport is dominated by thermionic emission
145
Table 44 Epitaxial layer profile for Schottky Barrier Diode (XMBE104)
Layer Material Doping(cm-3
) Thickness(Aring) Bandgap (eV)
Schottky GaAs(Si) 500E+15 7500 14
Semiconductor GaAs(Si) 300E+16 7500 14
Semiconductor GaAs(Si) 100E+17 7500 14
Ohmic GaAs(Si) 500E+17 7500 14
Buffer GaAs(Si) 300E+18 7500 14
Substrate GaAs(Si) N+ 3000 14
The fabricated SBD was also measured and its I-V characteristic is plotted as a
function of temperature in Figure 415 Unlike the ASPAT diode the current at forward
bias for the SBD change enormously with temperature from 77K to 398K and at all
biases For the ASPAT diode the slight change in current only started after 08V bias as
the current starts to have some component of thermionic emission over barrier
Figure 415 Log Current vs voltage as a function of temperature for SBD sample XMBE104
In order to see clearly how much the current is changing in forward bias for both
ASPAT and SBDs diode a log current at different voltages versus 1000temperature is
plotted as shown in Figure 416
1E-08
00000001
0000001
000001
00001
0001
001
01
-2 -1 0 1 2
Log
Cu
rren
t (A
)
Voltage (V)
T=398K
T=375K
T=350K
T=325K
T=300K
T=275K
T=250K
T=225K
T=200K
T=175K
T=150K
T=125K
T=100K
T=77K
146
Figure 416 Influence of temperature on IV characteristic for both ASPAT diode and SBD
Semi-logarithmic plots of current (at V= 05 06 07 08V) versus inverse
temperature for both SBD and ASPAT are shown in Figure 416 When the temperature
is increased the current also increases in the SBD as a result of thermionic emission
over the barrier for sample XMBE104 This is in contrast to the temperature-
independent tunnelling through the thin AlAs barrier of sample XMBE304 ASPAT
diode where when the temperature is increased the current is almost constant
At low and high temperatures the ASPAT shows excellent temperature
independence with a constant current flow It exhibits a tunnelling current in excess of
values expected by the elastic tunnelling current calculation equation suggested by RT
Syme [16 18] above (Eq 1) using a Oslash value of 105eV (ΓGaAs to Γ AlAs tunnelling) By
contrast for the SBD at low temperature (77K-275K) the changes of currents were very
high and for every 02V there is an exponential change of more than 40 This
temperature dependent study was also reported in[68]
147
48 Conclusions
This chapter demonstrated the establishment of an excellent physical model and
comparison of room temperature I-V characteristics of GaAsAlAs ASPAT diodes for
different emitter sizes their scalability as well as an investigation of their characteristics
at different temperatures from 77K to 398K Simulation are validated on well-
characterized experimental data and excellent fitting which had been achieved in this
work permit the designer to extract all related parameters of heterojunctionmultilayer
ASPAT structures thus creating modification for future growth specification in order to
achieved precise designs
It is clear that the work which had been carried out in this chapter is able to
achieve with adequate accuracy a claim of reverse engineering capability The ability of
the GaAsAlAs ASPAT to act as a zero-bias detector has been analysed and compared
with the SBD It is clear that the temperature stability which is shown by the
GaAsAlAs ASPAT is much better than that of the SBD thus demonstrating that the
tunnelling current is dominant over the thermionic emission in ASPAT diodes
148
5 DC amp RF CHARACTERISTIC OF ASPAT DIODES
51 Introduction
To assist in circuit designs for any type of high-frequency circuits such as
millimetre wave detectors frequency multipliers and mixer circuits which are built
based on non-linear devices (diodes) an equivalent-circuit model for the diode is
required This is among the simplest and most effective method for analysing
semiconductor devices which work at high frequency where the electrical characteristics
measured obtained from the devices are extracted and presented in a circuit consisting of
lumped elements components (resistor inductor capacitor etc) However accurate DC
and RF measurement data is essential to extract the equivalent-circuit elements quickly
and correctly The extracted parameters values from the circuit that are taken into
account usually depends on bias and frequency associated with the device physically
which is also interrelated to the semiconductor material parameters device structure as
well as fabrication process flows
In this work the DC and RF data were derived from DC and S-parameter
measurements respectively These measurements were carried out both in-house and at
the University of Cambridge by a collaborator partner (Prof MJ Kelly) The I-V
characteristics of the diode obtained from DC measurements were measured from -2V to
2V while the S-parameters were carried out over a wide frequency range from 40MHz to
40GHz with eight different biases In this chapter the DC measurements for various
sizes of the diodes with analysis of their IV characteristics will be discussed The one-
port on-wafer ASPAT measurement setup as well as the de-embedding method will
also be explained Thereafter the equivalent circuit models with all lumped element
effect will be discussed This work is carried out with the help of the VNA which
principle has been described in Chapter 2 and Keysight ADS simulation tool All
technical details regarding the equivalent circuit models will be explained together with
the method used for the ASPAT diode evaluation The equivalent circuit model also will
cover the diode intrinsic elements such as Cj Rj and Rs and extrinsic elements ie CP
149
and RP Finally an equivalent circuit model with the small signal characterization of the
fabricated ASPAT diodes will be presented
52 General Analysis of Current-Voltage (I-V) characteristics of GaAsAlAs
ASPAT diodes
The recent development of state-of-art for DC measurement apparatus has led to
capabilities for high-level accuracy of measuring voltages to a few nano Volts and
current signals in the femto Amp range[107] This can easily be obtained by exploitation
of proper connections and high-quality cables connecting the equipment to the Device
under Test (DUT) In this work the DC measurements were carried out using an Agilent
B1500A Parameter analyser whose description was covered in Chapter 2
As was discussed in Chapter 3 the GaAsAlAs ASPAT diodes have been
fabricated with different mesa areas between 2times2microm2 to 100times100microm
2 but the smallest
size obtained with good I-Vs was 4times4microm2 In this section the focus will be on how the
extracted data can be expanded further for empirical modelling Figure 51 shows typical
results for measured ASPAT diodes with various dimensions to check for their
uniformity According to our standard procedure the DC measurement has to be
conducted prior to the RF to ensure the diode is in fully working order as this will later
save a lot of time during RF characterization
Figure 51 IV Characteristics of measured ASPAT diodes for emitter sizes of 4x4um2 6x6um
2 and
10x10um2 Note the good scalability
1E-10
1E-09
1E-08
00000001
0000001
000001
00001
0001-2 -1 0 1 2
Cu
rre
nt
De
nsi
ti (
Amicro
m2)
Voltage (V)
4x4microm^2
6x6microm^2
10x10microm^2
150
Figure 51 above demonstrates the IV Characteristics of measured GaAsAlAs
ASPAT diodes (XMBE304) for emitter sizes of 4times4um2 6times6um
2 and 10times10um
2 This
sample was processed using the dielectric bridge technique developed in this work It
can be observed that current per unit area for each dimension fits and scales to each
other The scalability of each diodes measurement is very important to ensure no process
related issues are hampering the devicersquos proper operations This also confirms that the
diodes are completely functional and can be used for the next stage of measurements
The advantage of having an excellent scalability of those diode sizes is that a prediction
of smaller emitter size can be made
This type of IV characteristic shows asymmetric behaviour which results from
the unequal spacer lengths of the device This behaviour is very useful for detection
application as it obeys a square law model The square law predicts that the current is
proportional to the square of the applied bias
119868 = 1198861198812 119908ℎ119890119899 119881 gt 0
119868 = 0 119908ℎ119890119899 119881 lt 0
(51)
To extract the first order effects of ASPAT diodes DC measurements which
result in asymmetric I-V characteristics are analysed The slope of the non-linear region
is used to determine the junction resistance (Rj) which is obtained from the first
derivative of voltage versus current (dVdI) The expression of Rj is given by
119877119895 =
120597119881
120597119868
(52)
In order to understand the relationship between Rj and diode sizes of the ASPAT the IV
characteristic for each diode displayed in Figure 51 is used to extract the Rj This has
been done by using the expression in equation (52) above and their response is plotted
against bias as displayed in Figure 52
151
Figure 52 Junction resistance versus voltage
As can be seen in the Figure 52 above the Rj for each device decreases strongly
when the voltage increases At zero bias the 4times4um2 devices show the highest Rj value
followed by 6times6um2 and 10times10um
2 devices The junction resistance at zero bias obtained
from the 4times4um2 diode is around 86KΩ while reducing by a third for the 6times6um
2 and
10times10um2 diodes with Rj of 27KΩ and 10KΩ respectively A diode with a smaller
forward current under the same applied voltage will exhibit a larger Rj For a good
millimetre wave detector a device with a large value of Rj is desirable since it will
provide high detection sensitivity
The slope at the IV characteristic contributes to an important parameter that is
commonly used by electronic manufacturers to describe diode specification namely the
video impedance (RV) which is also known as the non-linear resistance The RV which is
extracted from the real part of the diode small signal impedance is highly dependent on
the DC bias current and only weakly depends on the series resistance of the diode (RS)
Therefore the video impedance is given by
119877119881 = 119877119895 + 119877119878 (53)
Where RS is the series resistance of the diode whose value is normally very small and
does not contribute much to the whole slope and hence RV is dominated by Rj The RV
changes in behaviour if any DC current is flowing through the diode Practically small
DC current in the range of 1 to 10 microAmp or total zero bias is used to maintain the
appropriate RV value (1-2KΩ to several MΩ) RV will also determine the voltage
-10
10
30
50
70
90
110
130
150
-01 0 01 02 03
Rj(
KΩ
)
Voltage (V)
6x6um^2
10x10um^2
4x4um^2
152
sensitivity of the whole detector circuit This will be explained further in the next
chapter In the case of a detector with an amplifier RV of the diode acts as the RF
impedance which needs to be matched with the video amplifier ( impedance looking into
the diode from the amplifier)[108 109]
The quotient of the second order derivative to the first derivative
((d2IdV
2)dIdV)) when calculated from the whole I-V characteristic translates directly
into a curvature coefficient (k) This is the most commonly used figure-of-merit to
quantify diode nonlinearity at zero bias Figure 53 below shows the variation of k with
bias and more importantly the zero bias rectifying action for device sizes of 4times4 um2
6times6 um2 10times10 um
2 This parameter which represents the small-signal rectifying
action of the diode will affect the performance of the detector (voltage sensitivity)
Detailed discussions on how this parameter effect the detector performance will also be
discussed in the next chapter
Figure 53 The rectifying action of the diode at zero voltage which gives the ASPAT high sensitivity
near zero bias detection
Figure 53 above shows calculated curvature coefficient of the measured I-V
characteristics from the same diodes shown in Figure 51 The highest k value is
obtained from the diodes with size of 4times4um2 followed by 6times6um
2 then 10times10um
2
The curvature coefficient decreases sharply as the bias increases for each diode This can
be attributed to a significantly increasing number of electrons that tunnel through the
thin barrier which were accumulated in the 2DEG formed in the intrinsic spacer region
-5
0
5
10
15
20
25
30
-001 004 009
Cu
rvat
ure
Co
effi
cien
t(V
-1)
Voltage (V)
k(10x10 um^2)
k(6x6 um^2)
k(4x4 um^2)
153
An ASPAT diode with a smaller size will have a larger Rj with a corresponding smaller
current under the same bias condition and hence will demonstrate a larger k value In
this calculation the curvature coefficient at zero bias obtained from 4times4um2 6times6um
2
and 10times10um2 diode is 23V
-1 17V
-1 and 16V
-1 respectively
A summary of the ASPAT diodes parameters obtained from measured I-V
characteristics that have been translated into first and second order differentials are
gathered in Table 51 below and compared to other diodes in the literature
Table 51 Performance of the ASPAT diode obtained from measured IV characteristics in this work
Sample Rj(Ω) k(1volt)
ASPAT 10times10 microm2 10K 16
ASPAT 6times6 microm2 27K 17
ASPAT 4times4 microm2 86K 23
Ge Backward diode 182K[110] 159[110]
InGaAs Backward diode 154[110] 23[110]
Sb Backward diode 5K[111] 47[111]
Si-Backward diode 135K[112] 31[112]
PDB 15K[8] -
AlGaAs SBD 20-100K[113] 34-38[113]
GaN HBD - 16[114]
From Table 51 above it is clearly that the ASPAT diode has a comparable value of Rj
and k to existing detector diode in the research community and in the commercial
market Based on literature of each diodes stated in the table the key to obtaining a high
value of k at zero bias is to minimize any forward tunnelling current Furthermore the
largest ASPAT diode used here (10times10microm2) has very close performances to that of a
commercial diode ie discrete Ge backward diode (ref[110]) where both Rj and k value
are close to each other
53 RF Test Fixture Theory and Experiment
RF measurements differ from DC measurement as they are more complicated
and it is necessary to comprehend the basic measurement principles to achieve
meaningful data This is obligatory especially for on-wafer RF characterization and
154
analysis to attain precise results Most of the electronics component measurements
which have input and output for instance antenna amplifier cables etc are based on a
two-port network configuration The characteristics which can be extracted from these
components are usually used to define their impact on a more complicated system
The performance of the two-port network can be described by a few parameters
ie scattering (S-Parameter) admittance (Y-Parameter) Impedance (Z-parameter) and
Hybrid (H-Parameter) However the S-parameter approach is favoured for high-
frequency measurements as it is relatively easier to characterize the microwave
performance and is able to convert to other parameters when necessary The advantage
of S-parameters is that they can straightforwardlydirectly convert into other two-port
parameters as mentioned above in term of currents and voltages[115] In fact to obtain
the device capacitance the appropriate S-parameters needs to be transformed into Y-
parameters using specific equations Furthermore the devicersquos cut-off frequency can
also be obtained when S-parameter measurements are performed over a wide frequency
range
531 On-Wafer Measurement and Small Signal One-Port Characterizations
In this work the arrangement of the RF measurement setup is assumed to be a
linear system as small voltage amplitude signals are used this means that the signals
have only a linear effect on the network without any gain compression or attenuation
The assumption is still acceptable even though the typical ASPAT is characterised as
non-linear in nature because it is a passive device which will act linearly at any input
power level
Generally the S-Parameter measurements on a diode can be adequately and
suitably performed using a one port measurement The technique used to characterise the
output is similar to the two ports technique but only incident and reflected waves are
used to characterise the input and output ports of the device Essentially this is because
the ASPAT has only two terminals and it is a passive device like other diodes
Therefore the analysis will revolve around the S11 parameter Figure 54 below show the
S11 is a ratio of reflected wave to the incident wave
155
11987811 =
119877119890119891119897119890119888119905119890119889
119868119899119888119894119889119890119899119905=
1198871
1198861 119908ℎ119890119899 1198862 = 0
(54)
A VNA as described in Chapter 2 is used to measure the ASPAT diodes This
powerful equipment is able to measure S-parameters up to 40 GHz To conduct accurate
S-parameter measurement at the diode the measurement setup must be calibrated prior
to the actual measurements taking place
54 Device Calibration
541 Open and Short De-Embedding Technique
Further calibration to be made involves anything related or attached to the
device The co-planar waveguide (CPW) bond pad and interconnect line that are
attached to the intrinsic diode are the main contributors of the errors also are required to
be calibrated In general the bonds pad could generate a capacitance (parasitic) in
parallel with the intrinsic diode and its contribution depends on the size of the bonds pad
as well as the operating frequency Meanwhile the CPW and interconnect line may
cause a parasitic inductance in series with the diode
The method that is used to get rid of this parasitic is called de-embedding and the
most common technique to realise it is by introducing OPEN-SHORT structure[116]
This method is based on a lumped-elements model Parasitic elements of the diode
De-Embedding Structure
Incident wave
Reflected wave
One-port device
a1
b1
Figure 54 One port S-parameter measurements
156
equivalent circuit correlate directly to the access section of the CPW hence can be
derived from de-embedding structures The aim of the de-embedding technique is to
represent these parasitic elements so that the one-port characteristic of the actual diode
can be determined
The two types of de-embedding structure OPEN and SHORT are conventional
techniques that are widely used in this study The design of all structure must be
identical (in size) to the device to avoid any discrepancy It is very simple to design all
these three structures for example open structures are obtained by eliminating the diode
layout and keeping the bond pad layer only The short structure just adds a bridge and
ensures ground and signal pad are connected to each other Through structures are
realised by disconnecting both ground pad and leaving the signal pad to connect to each
other
To gain more accuracy this external effect must be removed by the implementation of
de-embedding structures on the same tile as the actual device Figure 55 shows the
fabricated de-embedding structures used in this study
Figure 55 Fabricated open short de-embedding structure and real device (zoomed) use for RF
calibration and measurements (Note Images are not to scale)
In summary the de-embedding which is used to extract out the parasitic elements
from entire single diode measurement is a very important step as normally on-wafer
measurement requires coplanar waveguide (CPW) to access the diode structure (active
region) The CPW will have some effects which will disturb the accuracy of the device
characteristics
157
55 S-Parameter Measurement Result and Analysis
This section will only present RF measurement results after all VNA setup and
calibration were performed The S-Parameter measurements were carried out on ASPAT
diodes at five different DC biases from -2 to 05 volt with a sweep frequency from
40MHz to 40GHz using a calibrated VNA and the input power was fixed at -30dBm
The measurement procedure as described in Chapter 2 was performed on the device
(on-wafer) equipped with the appropriate bond pads This is important to ensure the
results obtained are valid The reason for using different biases is to find at what voltage
the device capacitance is fully depleted This is also very important in determining the
cut- off frequency of the devices
In this research two phases of the experiment on the S-parameter measurements
were carried out The first phase is to qualify the process flow ie for manufacturability
and repeatability which can be obtained from the consistency of the result The S-
parameter measurements taken on the same wafer dies are repeated several times on
different GaAsAlAs ASPAT diodes There are three different tiles taken from 3
different wafers namely XMBE304A XMBE304B and XMBE304C carried out in
this experiment The repeatability tests are done mostly on the large devices (15times15microm2
up to 100times100 microm2) and the results are analysed based on the reflection coefficient (S11)
on Real and Imaginary measurements
In the second phase the measurement is toward producing devices that can
perform at high-frequencies This can be realised by utilising small emitter size devices
(4times4microm2 6times6 microm
2 and 10times10 microm
2) The measurement results of these devices will be
used to build the equivalent circuit models while both the intrinsic as well as the
parasitics of the device will be evaluated Hence all the values obtained from these S-
parameter measurements will be used to design the device that can be used in
millimetres-wave applications As can be seen in Figure 56 below the extracted S-
parameter measurement results comprise of a reflection coefficient (S11) for real
imaginary and Smith chart for XMBE304A While these measurement results are
extracted at zero bias voltage the other bias voltages will be used to extract the
capacitance This will be described in the final section of this chapter
158
551 Diode to diode uniformity
In order to study within tile uniformity and reproducibility statistics of the RF
performance five devices of different mesa sizes in the same tile (XMBE304A) were
measured at zero bias and represented in term of Real and Imaginary reflection
coefficient (S11) the uniformity check is carried out at three different frequencies step
under 15GHz since the cut-off frequency for these big devices is relatively low at about
~20GHz on average The variation of the reflection coefficient is taken from the
percentage of the (standard deviationmean values) for all five diodes from this run The
following figures show Real and Imaginary S11 of large mesa area ASPAT diode from
15times15microm2 up to 100times100microm
2 which are represented by lines graph in a few different
colours
Figure 56 Real S11 RF measurements for (XMBE304A) were done for four devices from
15times15microm2 to 100times100microm2 device sizes for within-wafer uniformity check
Figure 57 Imaginary S11 measurements (XMBE304A) to qualify the repeatability and
reproducibility were done on four devices from 15times15 microm2 to 100times100 microm2 at zero bias
159
The variance data extracted from the graph (Real S11) above for each device within-
wafer (device to device) uniformity study is summarize in Table 52 below
Table 52 Device to device uniformity check for large ASPAT diode
Device Size 100times100 microm2 50times50 microm
2 30times30 microm
2 20times20 microm
2 15times15 microm
2
Variation 5GHz 181 115 405 151 145
Variation 10GHz 106 133 522 424 293
Variation 15GHz 119 198 281 76 509
The majority of diodes show that the variations of S11 measurements are below
3 and only a few are below 8 These finding still can be considered as good for
manufacturing control since absolute I-V characteristics reported in [63] is set by
designerrsquos specification to be not more than plusmn10 variation Further extensive RF
measurements were carried out by the research collaboration with the University of
Cambridge on the same GaAsAlAs ASPAT diodes wafer [117] In their study they
focused on 50times50 microm2
mesa size 17 of diodes were chosen to be measured The study of
uniformity of RF characteristic only focused on frequencies below 20GHz The same
approach was used to get the variation of the reflection coefficient for all 17 diodes but
this work was carried at four different frequencies Table 53 shows the zero bias S11
result for four different frequencies and standard deviation of the devices
Table 53 The variation of reflection coefficient (S11) for GaAsAlAs ASPAT diode at four different
frequencies[117]
Frequency (GHz) 5 10 15 20
Variation () 197 243 26 276
From the results the variations of 50times50 microm2 mesa sizes measured in-house and
at the University of Cambridge are comparable with all variations showing good
uniformity ie recording variations below 3 This indicates that the RF performance
of the GaAs AlAs diode is valid and reproducible and is thus considered as a good
achievement for manufacturing Once the reproducibility and repeatability of the large
devices showed stable results the fabrication process then continued to obtain smaller
emitter size for work at high-frequencies
160
552 Wafer to wafer uniformity
Other RF measurements were conducted on sample XMBE304B which was
fabricated in-house using the same process steps but the only difference from
XMBE304A was the use of SiN3 as dielectric In this run three different mesa sizes
were measured (15times15mmicro2 20times20microm
2 and 30times30 microm
2) and Real and Imaginary S11
plotted against frequency The RF performances of both samples are gathered in one
graph as shown in Figure 58 below
Figure 58 Wafer to wafer uniformity test on 1st and 2
nd RF measurement(XMBE304B) to qualify
the repeatability and reproducibility were done for 30times30microm2 to 15times15 microm
2 device sizes (Real and
Imaginary) Note blue colour is XMBE304A and red colour is XMBE304B
For this wafer to wafer uniformity study four diodes with three different sizes as
specified previously were measured from sample XMBE304B and four diodes from
previous measurements of XMBE304A The blue line in Figure 58 represent
measurement result of real and imaginary for sample XMBE304A while the red line
161
represents XMBE304B The uniformity data is compared at three different frequencies
and gathered in the table below
Table 54 Wafer to wafer uniformity check on XMBE304A and XMBE304B
Device Size 30times30 microm2 20times20 microm
2 15times15 microm
2
Wafer A vs wafer B variation 5GHz 305 31 1 314
Wafer A vs wafer B Variation 10GHz 352 344 329
Wafer A vs wafer B Variation 15GHz 321 376 359
As can be seen in the Table 54 above the wafer to wafer uniformity is rather
large (30) on average The main reasons being that sample XMBE304A was
processed by utilizing S1805 as a dielectric layer while sample XMBE304B used
Si4N3 Although the process steps are similar for both wafer processing the use of
different dielectric layer will influence the diode parameters especially resistance and
capacitance as the dielectric constant for each materials is different Secondly the wafer
processing is not run concurrently at the same time thus the moisture and temperature in
the clean room might differ for both processing Although the wafer to wafer uniformity
test for this run might not be favourable for manufacturing tolerance at least the use of
different dielectric layer shows some significant result in term of capacitance resistance
effect to the GaAsAlAs ASPAT diode
553 Small devices RF measurements
The first objective of this study was to make smaller size mesa devices ie
1times2microm2 1times3 microm
2 2times2 microm
2 and 3times3 microm
2 However for GaAsAlAs ASPAT type this is
difficult to achieve in practise These issues were discussed in detail in Chapter 3
Hence the smallest emitter size that yields repeatable and reproducible results was
4times4um2 The final measurement which was done on sample XMBE304C focused on
small devices The measurements were done on four devices two with the diode bond
pads sitting on substrate (GaAs SI) and the other two sitting on dielectric layer (Si4N3)
Figure 59 below shows three measured results obtained from sample XMBE304C
using the 3rd
Gen Mask
162
Figure 59 RF measurement performed on device sizes of 10times10microm2 6times6mmicro
2 and 4times4microm
2 (Real and
Imaginary) Note that green red and blue colour represents 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively
Figure 510 RF measurement performed on device sizes of 10times10 microm2 6times6 microm2 and 4times4 microm2
(Smith Chart) Note that green red and blue colour represents 4times4microm2 6times6mmicro2 and 10times10microm2
diodes respectively
30MHz
40GHz
163
As can be seen in Figure 59 (Real Imaginary) and Figure 510 (Smith Chart) are
obtained from measurement of four diodes in the same tile The diode to diode
uniformity that is sitting on the same platform obtained at 35GHz frequency in this run
on average is ~15 25 and 1 for 4times4microm2 6times6mmicro
2 and 10times10microm
2 diodes
respectively On the other hand the uniformity between diode to diode sitting on
dielectric and substrate is quite high due to different capacitance value of devices on
average ~7 are attained from three different sizes of diode
From the measurement results above the Real S11 measurement of four different
sizes show the same trend for each frequency At low frequency resistances for each
diode is high as the S11 value is large At intermediate frequency the values drop
tremendously for big devices (30times30 mmicro2 and 20times20 mmicro
2) ie in Figure 57 At high
frequency all diode reach saturation limit as the value are constant Small devices
(4times4mmicro2 6times6mmicro
2 and 10times10microm
2) ie Figure 59 show S11 values that are higher than
those of large devices as smaller emitter diode have larger resistance value
The imaginary S11 value also shows the same trend as for big devices However
for small devices in this run (4times4mmicro2 6times6mmicro
2 and 10times10microm
2) the S11 value keep
dropping toward negative values at increasing frequencies This indicates that bigger
devices with positive value at high frequency are more capacitive than the smaller
devices It is worth mentioned that the capacitance and inductance values for device
sizes of 4times4microm2and 6times6microm
2 come from the CPW layouts and these are dominant while
for device sizes of 15times15 mmicro2 and above the device capacitance itself is dominant
The Smith Chart shows the reflection coefficient (S11) as a function of the
applied frequency (30MHz to 40GHz) All measurements from each mesa size follow
unique impedance circle which is that most of the lines are at the lower right outer ring
This means that the diode capacitance value is frequency dependent For the case of
10times10microm2
devices these impedance circles are mostly toward the outer ring meaning a
higher capacitance than the other two mesa dimensions All the device constantly follow
the outer ring without crossing any real axis at any frequency point meaning that the Cj
is not shorted at the maximum 40GHz measurement frequency (not reached cut-off
frequency) Therefore the entire small GaAsAlAs diodes in this run have capability to
work in the millimetre wave frequencies range
164
56 Extracting RF models of ASPAT at Zero Bias Voltage
The methodology used in the S-Parameters measurement for high-frequency
analysis must ensure that the derivation of the equivalent circuit corresponds to their port
characteristics In other words the component representing the ASPAT in the equivalent
circuit model must have physical significance otherwise the circuit will be meaningless
The fabricated ASPAT diodes as discussed in Chapter 3 have the cross section shown in
Figure 511
There are two main components that can be extracted from the fabricated
ASPAT depicted above ie intrinsic and parasitic The intrinsic refers to the main
structure of the diode itself and are represented by three bias dependent elements
namely Junction Resistance (Rj) Junction Capacitance (Cj) and diode Series Resistance
(Rs) The parasitic is the elements related to the bond pad of the anode and cathode as
well as interconnects They are represented by parasitic inductance (LP) resistance (RP)
and capacitance (CP)
The diode parameter extraction is different from the three terminal devices
(FETs) in the sense that FETs are a kind of direct extraction in which all the elements in
the transistor have linear functions to the port characteristics ie S-parameter Y-
Parameter Z-Parameter and can easily be solved by the matrix calculation method for
those particular parameters[118] The same extraction method cannot be applied to the
diodes because its elements will embroil with each other Therefore only one method is
used to extract the diode element which is optimisation by tuning the initial value toward
the measured S-Parameter values
Figure 511 Cross-sectional of fabricated ASPAT diode and the corresponding equivalent circuit
model
165
The strategy used to model the ASPAT is based on an initial fitting value of the
lumped elements to the extracted value from measurement on three S-parameter graphs
(real imaginary and Smith chart) for the reflection coefficient (S11) The refinement is
accomplished by optimisation and fine tuning of the values which result in minimum
error between extracted and modelled values Figure 517 (on page 153) shows fitted S-
parameter result for extracted and model numbers with each one fitted in a single line as
an example However to achieve this excellent fitting key prior steps have to be used
de-embedding fitting the intrinsic value and optimisation
561 Extraction of ASPAT parasitic element
Once the S-parameter measurements achieve stability repeatability and
reproducibility for each measurement in term of S11 results as mentioned above the
results of the de-embedding structure which had been measured prior to the device
structure are then extracted to form a well-defined equivalent circuit In order to build
and analyse the equivalent circuit firstly the measured data is imported into the ADS
software prior to any fitting This can be realised via the ldquoStart The Data File Toolrdquo
features provided by this particular software When successfully imported the data is
read by the function S2PMDIF (These files are a natural extension of two-port S-
parameter Touchstone files) as depicted in Figure 512 below
Figure 512 The S-parameter Touchstone file is used to read the measured files
166
For the open and short techniques after de-embedding the equivalent circuit
model which is represented by mainly a capacitor and an inductor is built The open
structure requires resistance and the capacitance values of 20KΩ and 26fF respectively
connected in parallel to be well fitted to the real imaginary and Smith chart (S11) output
On the other hand for the short structure the Real imaginary and Smith chart (S11) have
to satisfy the values of resistance and inductance elements of 1Ω and ~47pH respectively
connected in series These values strongly rely on the bond pad or CPW dimension and
length The Equivalent circuit models and fitted data as well as measurement can be
seen in Figure 513 and Figure 514 below
Figure 513 Equivalent Circuit Model of Open CPW or de-embedded structure
Figure 514 Equivalent circuit model for short de-embedded structure
To satisfy the equivalent circuit a self-consistence method introduced by
Ren[119] is utilised This approach accurately extracts the CPW capacitance (Cpad) and
inductance (Lpad) as well as intrinsic Junction capacitor (Cj) which is attained from the
one-port S-parameter measurements Therefore the pad capacitance introduced by the
self-consistence method for the open structure can be expressed by
167
119862119875 =
119868119898(11988411119874119901119890119899)
120596
(55)
Lpad which represents the short structure is given by
119871119875 =
1
120596(119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
))
(56)
Here Y is the admittance parameter (Y-parameter) converted from the S-parameter
measurement data and ω is the angular frequency The extracted measurement data
represented in the equivalent circuit fits with the simulated data in three S11 graphs as
can be seen in Figure 515 below From the Smith Chart it can be clearly seen that both
open and short S11 results are on the circumference which means the resistance of the
short structure is very small while in the open it is very large Additionally the
calculated Cpad and Lpad using Equations 55 and 56 above produce results similar to
those obtained in the equivalent circuit model for the open and short structure The
values are ~25fF and ~45pH respectively These data completely verify and validate
both results
Figure 515 Smith chart representative S-parameter measurement for short (left) and open (right)
CPW The blue lines represent simulated data and the red is measured data
Short
Open
168
562 Extraction of ASPAT intrinsic elements
Once the parasitic elements are determined it is easy to build a complete ASPAT
equivalent circuit The ASPAT is not like other tunnelling diode which their equivalent
circuit models widely studied ie RTD [120] IMPATT and PDB The only literature
which reports ASPAT equivalent circuits can be found in [15] and other RT Symersquos
journal paper[16] Fortunately its equivalent circuit model is not much different
compared to other diode video detectors Thus other literature which is based on
Schottky diode equivalent circuit model used for detector application can be referred to
The simplest form of ASPAT equivalent circuit and other video detectors intrinsically
consist of junction capacitance (Cj) series resistance (RS) and junction resistance (Rj)
First and foremost to extract the equivalent circuit one must know the theory behind
each parameter that is developedbuilt as a spine to become a complete element This is
vital to ensure the equivalent circuit is correct In the case of the ASPAT Cj is predicted
from a simple fully depleted parallel plate capacitor approximation which was discussed
previously in Eq (230)[15] Additionally for the S-parameter measurements the Cj can
also be validated by the self-consistence method mentioned earlier and thus can be
expressed by
119862119895 =
[
(1
120596)
1
1
119868119898 (11988411119905119900119905119886119897minus 11988411119874119901119890119899
)+
1
119868119898 (11988411119874119901119890119899minus 11988411119878ℎ119900119903119905
)]
(57)
This approach helps to verify both the fully depleted parallel plate capacitor in S-
parameter measurements The basic component which is responsible for the ASPAT
series resistance RS was discussed in detail in Chapter 2 RS and Cj are key contributors
to the high-frequency operation as expressed by the device cut-off frequency Equation
(58) below
119891119888119906119905minus119900119891119891 =
1
2120587119877119904119862119895
(58)
The R and C parameters must be kept as low as possible in order to obtain high cut-off
frequencies for millimetre wave applications From the fabrication point of view Cj can
169
be reduced by making as small a diode emitter size as possible while for RS reducing
the D gap is of paramount importance as it dominates the series resistance The ASPAT
contact resistance in the electrodes (contacts between metal and semiconductor) can be
reduced by using high doping in the ohmic layers
The junction resistance (Rj) of the ASPAT is taken from the 1st derivative or
slope of the current-voltage characteristics Normally the value of Rj is very large
(several kilo Ω) compared to Rs The small signals ASPAT equivalent circuit built with
intrinsic and extrinsic components is shown in Figure 516 below while the fitting
results is shown in Figure 517 and Figure 518
Figure 517 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
(Real and Imaginary) results for various small device designs
Rj
Cj
Cpad Rpad
Rs Lpad
Figure 516 Equivalent circuit of the ASPAT diode
170
Figure 518 Excellent fitting between measured (red colour) and simulated (blue colour) for S11
results (Smith Chart) for various small device designs
The equivalent circuit that was built for the ASPAT is taken from sample
XMBE304C with emitter dimensions of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 These
devices are expected to work in the millimetre-wave region and have cut-off frequencies
(intrinsic) of ~650GHz ~200GHz and ~100GHz respectively
Table 55 Comparison between calculated (fully Depleted) and extracted (different biases) values
from equivalent circuit parameters for different ASPAT mesa sizes at zero bias voltage
Parameters 4times4microm2 6times6 microm
2 10times10 microm
2
Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted Calculated
(fully
depleted)
Extracted
0V -05V -1V 0V -05V -1V 0V -05V -1V
Cj(fF) 879 23 7 6 198 55 148 139 549 171 486 46
Cpad(fF) - 15 15 15 - 15 152 152 - 15 15 15
Lpad(pH) - 45 43 42 - 50 473 473 - 51 51 46
Rj(KΩ) - 90 833 522 - 35 392 392 - 12 125 13
Rs(Ω) 99 11 11 11 67 95 8 7 41 95 45 37
fcut-off
Cj(GHz)
1828 629 2066 241
1
1208 192 1344 163
5
710 107 728 935
fcut-off
Cj+Cp(GHz)
- 380 658 688 - 151 663 781 - 98 556 705
171
The focus in this study is purposely to build ASPATs as zero bias detectors that are able
to work in the millimetre and sub-millimetre frequency range therefore all the
parameters which are obtained from equivalent circuit were extracted at zero bias
voltage Theoretically the calculations which are derived from both self-consistence amp
theory can only be solved for fully depleted device capacitance (using a parallel plate
configuration) Hence both extracted and calculated results are compiled in Table 55
Noticeably the calculation can only produce the intrinsic parameters of the
ASPAT for fully depleted capacitance On the other hand both intrinsic and extrinsic
parameters of GaAsAlAs ASPAT are obtainable from extraction and thus help to
determine at what bias the diode is start to deplete The junction and series resistance (Rj
and RS) of each dimensions shown in Table 55 above were achieved by fitting the
elements of the equivalent circuit with the three measured S11 graphs whereas the Cpad
and Lpad were extracted by utilising the self-consistent method from the S-parameter
measurements which is fitting the de-embedding structure Additionally the Cj values
are obtained via fitting the measured S11 data and employing the self-consistence
approach Results obtained from both techniques are identical
At zero bias all extracted junction capacitance from each device sizes are very
different from the calculated one while the extracted series resistance are closer to the
calculation This means that Cj is a highly voltage dependent parameter and Rs is
voltage independent but solely dependent on device structure and material used to
fabricate it The extraction at -05V and -1V shows that the values of junction resistance
is changing for most of the devices which means this parameter also rely on bias voltage
as discussed earlier in Section 52
The cut-off frequency for each calculated devices are near the THz range even
for the 100microm2 emitter area However with the introduction of parasitics elements ie
pad capacitances fcut-off is degraded tremendously Therefore it is important to make sure
all the intrinsic elements have optimum values so that the target operating frequency of
the ASPAT diode can be met Due to this it is advisable to operate the devices at no
more than 13 of fcut-off when designing detector systems
The parameters extraction at -05 and -1V also show that Cj values are closer the
calculated ones which means the ASPAT diode is reaching full depletion
172
563 Capacitances -Voltage (C-V) Extraction
Theoretically the junction capacitance of the ASPAT is calculated from the fully
depleted formula 119862119895 = 휀119900휀119903119860119889 which was also discussed in Equation (230) in Chapter
2 in page 43 Its value depends on the change of voltages to depletion at the emitter
contact[15] and make it one of the voltage dependent parameter for the diode[121]
Therefore the C-V characteristic of the GaAsAlAs must be precisely extracted
In practice the capacitance is difficult to measure due to the very low resistance at zero-
bias However alternatively it can be measured and extracted by applying different
voltage and identifying the point at which there is change which essentially represents
full-depletion Apart from these it can also be extracted from S-parameters measurement
which is then converted to Y-parameters A C-V characteristic of the GaAsAlAs
ASPAT from XMBE304C is extracted and plotted as depicted in Figure 518 below
Figure 519 Capacitance extraction showing full depletion at -025 volts (modelled capacitance vs
Voltage)
From the graph shown in Figure 518 the capacitance is extracted at eight
different biases for 4times4 microm2 6times6 microm
2 and 10times10 microm
2 The devicersquos junction
capacitance for each dimension increases and reaches a maximum value at 025V There
are additional quantum capacitance effect which comes from an increase in the negative
charges in the 2DEG region (when band bending happens creating an accumulation
0
50
100
150
200
250
-2 -15 -1 -05 0 05
Cap
acit
ance
(fF
)
Voltage (V)
Cj(4x4microm^2)
Cj(6x6microm^2)
Cj(10x10microm^2)
173
region at the barrier) This charge is imaged by the positive charge in the whole
depletion region Increasing the voltage toward positive values leads to a lowering of
the AlAs barrier and thus allowing thermionic emission to take place after certain bias
values leaving only the depletion capacitance and making the quantum capacitance
negligibly small
In the reverse bias case the device junction capacitance reaches a saturation
(fully depleted capacitance) at a voltage of -025V and remain constant up to -2V If the
reverse bias voltage is increased further the ASPAT may reach breakdown Therefore it
is important to know how far the diode can withstand applied reverse bias to ensure it
can still give full performance
57 Conclusions
In this chapter scalable DC characteristics of GaAsAlAs ASPAT diode derived
from three different emitter sizes of 4times4 microm2 6times6 microm
2 and 10times10 microm
2 was
demonstrated The current density obtained at zero bias is several microAmicrom2 These allow
1st order differential effect to exhibit high value of Junction resistance (Rj) at zero bias
However Rj is highly bias dependent The 2nd
order differential effect on IV
characteristics display a high value of curvature coefficient leading to high voltage
sensitivity when applied in millimeter wave detector applications These two parameters
are vital in the design of millimeter wave detectors and especially those operating at zero
bias
Subsequently RF measurement up to 40GHz of uniformity study for both within
wafer and wafer to wafer variance were undertaken An average uniformity below 7
was obtained for within wafer study on large device area ( 15times15 microm2 to 100times100 microm
2)
while for small device area ( 4times4 microm2 to 10times10 microm
2) a smaller 3 uniformity variance
was achieved in average However for wafer to wafer study the variant uniformity was
quite high at around 30 on average for relatively large device (15x15 microm2 to 30x30
microm2) This was mainly attributed to different dielectric layers used in the process flows
of the sample rather than fundamental MBE control of the AlAs barrier thickness
174
It was demonstrated in this chapter that careful on-wafer RF measurements of small
size GaAsAlAs ASPAT diodes allow accurate device parameter extraction of both
extrinsic and intrinsic parameters The extrinsic parameters are namely pad capacitance
and inductance with obtained values of 26fF and 47pH respectively These values were
obtained from de-embedding structure fabricated on the same tile as the real devices
The intrinsic parameters such as junction capacitor junction resistor and series
resistance had different values according to device dimensions The smallest zero bias
value of Cj obtained from 4times4 microm2 diodes was 23fF ensuring a high cut-off frequency of
380GHz and hence in the next chapter a 100GHz detector will be presented working at
slightly less than 13 of this cut off frequency
The C-V data extraction confirmed that the fully depleted capacitance started to
happen at around -025V The maximum junction resistance occurs at +025V largely
caused by the depletion region and an additional quantum capacitance effect CQ This
effect is strongly related to the size of a 2DEG which occurs under forward bias (01V to
025V) and can be reduced by having a smaller thickness AlAs barrier
175
6 MILLIMETRE WAVE GAASALAS ASPAT DETECTOR
DESIGN USING ADS
61 Introduction
The ASPAT diode having features of non-linear IV characteristics at zero voltage
make it useful for signals rectification ie detector and mixer for millimetre-wave
applications Additionally ASPAT diodes have a range of advantages such as large
dynamic range strong temperature insensitivity etc[15]over other rectifier diode This
makes ASPAT an appropriate candidate in RF detection applications Since 1940 the
only two terminals device that has been the workhorse for RF applications is the
Schottky Barrier Diode (SBD)[9] In its earliest form the SBD was built based on a
point-contact device which could not perform at high frequencies It was then developed
to work at higher frequencies by exploitation of epitaxial structures [10] and to date the
SBD remains the mainstay of two terminal devices that are able to work in the
millimetre and submillimetre-wave regions However as discussed in Chapter 4 the
performance of SBD is degraded at extremes of temperatures and these circuits
employing SBDs require temperature compensating circuitry Thus there is additional
complexity associated with technologies and applications related to SBDs
Before this work was carried out no model for the ASPAT diode as detector had
been available or developed especially using the empirical modelling ADS software
When the ASPAT diode was first introduced its function was conceptually explained it
was then built and tested to compare with other microwave detectors at X-band
frequency (95GHz) The comparisons were made in terms of detector parameters ie
sensitivity dynamic range temperature dependence etc[15] These early works lead by
RT Syme et al supplied the basic knowledge to model the ASPAT diode as a zero-bias
detector for mm-wave frequency gt100GHz For the SBD many models and equivalent
circuit approaches have been reported [122 123] The modelling of conventional SBD is
mostly implemented through fitting the S-parameter curves of the model to the
experimental one This approach is also carried out in this research since it is accurate to
predict the performance of the device under test [124]
176
This Chapter aims to introduce low cost reliable and sophisticated detector design
based on ASPAT diodes which is believed to be able to improvereplace SBD in
millimetre-wave applications especially in imaging The focus was on developing and
establishing an appropriate circuit design that suit the new ASPAT diode for such
applications The detector sensitivity as its key parameter ultimately limits the quality
and acquisition time of the detector In the subsequence section the theory of detection
including both direct and heterodyne will be discussed This is followed by definition of
detector characteristics of interest as well as noise consideration Section 65 present the
main focus of this chapter which is the development of 100GHz ASPAT detectors and
their result will be explained in term of all detector characteristic of interest
62 Detection Theory
Any incoming signal such as RF microwave or mm-wave in the form of envelope
function or single wave can be detected by rectification of the signal using a nonlinear
device ie transistor or diode The input and output signal (RF) signals are normally in
the form of amplitude as a function of time Typically the detector output is a low-
frequency signal known as the video signal which has amplitudes that are proportional to
the square of the input RF signalrsquos voltage amplitude
A complete receiver system as shown in Figure 61 below consists of receiver
antenna and a circuit designed to extract the signal and then amplify it The function of
the receiver system is the converse of the function of the transmitter side At the receiver
side the antenna is used to receive the signal it then conveys the signal to the extraction
circuit for detection as the information-bearing part of the signal (using the nonlinear
device as its heart) The signal is finally amplified to avoid any information strength
decay Additionally in a digital system the output signal which had been processed by
the detector circuit has to maintain an optimum input signal conveyed to in-phase and
quadrature (IQ) demodulators The output signal will go through a low pass filter then
to an analogue-to-digital converter (ADC) and thus a digital baseband output signals
will be produced
177
Figure 61 Block diagram represent a complete direct receiver system
There are two types of millimetre wave integrated circuit (MMIC) used for
detection purposes namely direct detectors and heterodyne detectors The direct detector
MMIC is the simplest circuit used for detector applications and has the simplest way of
extracting the RF information Due to its simplicity the direct detection method is
inexpensive and most attractive method used for measuring power in RF Laboratories
and Industries This detection scheme is also sometimes known as video detection[125]
The simplest way of explaining the detection process is that the incoming RF or
microwave signals depicted in Figure 62 below with an appropriate input power (Pin) is
rectified by using a diode and results in a corresponding output voltage (Vout) A detector
IC designed based on diodes is normally able to rectify very low levels of RF power (lt-
40dBm) then produces an output DC voltage that is proportional to the RF power A
rectifier diode can function at zero bias (which is very good for reducing noise) at very
small DC bias (003mA) and relatively high RF impedance which will produce around
600Ω This will affect the capacitance value and a low capacitance is needed to realise a
high detection sensitivity
Figure 62 The detection process of a single wave through a non-linear IV characteristic of a diode
Detector
Speakerdisplay unit Amplifier
Antenna
Vout
Pin
Tuner Amplifier
178
However this type of detector has a drawback which is itrsquos relatively low signal to
noise ratio Thus it will also rectify any incoming electrical noise at all frequencies and
up to the cut-off frequency (fC) The basics lumped components circuit as shown in
Figure 63 is used to build such detector which consists of Source impedance (Zo)
Rectifier diode (ASPAT or Schottky) wire or pad inductance and capacitance and Load
impedance (RL)
Figure 63 Lumped element illustration of microwave detector circuit
Another type of detector is the heterodyne method which mixes incoming RF or
microwave signal (fRF) with another constant signal produced by a secondary circuit
called the Local Oscillator (LO) The LO frequency (fLO) must be slightly higher than fRF
to enhance the RF signal This mixing between fRF and fLO happens in the nonlinear
device as depicted in the Figure 64 This will produce a signal at a different frequency
called the intermediate frequency (fIF) which can then be amplified and detected as
explained in the previous paragraph Theoretically a basic requirement of the mixer is to
have fIF as efficient as possible while practically the minimum conversion efficiency
obtained is around 20 The main reason for using a mixer is due to the fact that
selective amplifiers at RF frequencies are costly and hard to achieve Hence a mixer is a
good technique as it only convert the signal to a lower frequency in which good
selectivity and high gain can be more effortlessly realised[14] A good mixer diode is the
one that can produce a high cut-off frequency and reduce conversion losses (Lc) A
mixer and detector diode with a low driven input power result in reducing overall noise
figure and thus in the ideal case the fIF amplifier also should have a low noise figure for
better performance The advantage of the heterodyne method is that it has a higher
179
sensitivity compared to the direct detection method this is achieved by producing an fIF
which has a lower frequency than the incoming RF signal[14] Obviously a zero-bias
voltage diode is more favourable to be used in mixer and detector applications
Figure 64 The mixing process where the signals are processed by the non-linear I-V characteristic
to produce an intermediate frequency (fIF=fLO-fRF) when signals at fLO and fRF are applied to the
diode
To have good detection efficiency for both types of detectors the operating
frequency (fO) must be several times smaller than fC In the case of an incoming
maximum modulated signal fM the frequency that can be acquired is in the range of fO
plusmnfM and will normally come with noise The standard method that is used to reduce the
noise is using a filter of bandwidth about 2fM at the centre of fO with the condition that fO
must be smaller than fM (f0lefM) Otherwise it would be difficult to attain However in
most cases fM is smaller than fO and fO is smaller than fC thus this will make the video
impedance (RV) (or nonlinear impedance) very close to the differential resistance of the
diode (at fO) in the equivalent circuit[74]
63 Definition of Characteristics of Interest Detection Parameters in small signal
analysis
Theoretically a transfer function measurement is preferable prior to any empirical
modelling since no assumption can be made due to the detector non-linearity
Furthermore measuring voltage output at high frequency can be very low while
measuring the power incident on the detector is hard to achieve where the linearity of
180
the typical power meter is normally less than 3 over its operating range[126]
Therefore the modelling of detector output voltage vs input power (ie transfer
function) can help to determine both nonlinearity correction and appropriate operating
range for the detector itself
The performance of the diode that is often taken into account is the transfer function
(output voltage Vout versus incident power Pin) and the main parameters that is used to
characterise and determine the quality of any detector diode are the voltage sensitivity
(βV) tangential sensitivity (TSS) dynamic range (P1dB) ie under 1 dB roll off power and
variation of output voltage when examined in extreme temperature situation (ΔV(T))
The voltage sensitivity in small signal analysis can use the approach introduced by
Torrey and Whitmer [9] then βV can be expressed as
120573119881(119894119889119890119886119897) =
119877119895119877119871120581
2(119877119881 + 119877119871) (1 +119877119904
119877119895)
2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(61)
Where ω is the angular frequency (2πf) Cj is the junction capacitance of the diode
active region RL is the load resistance RV is the video impedance taken from the
expression of Rj + Rs and κ is the curvature efficiency that give small signal rectifying
action of the ASPAT diode which is given by the second order term and itrsquos expression
is
κ =
11988921198681198891198812frasl
119889119868119889119881frasl
(62)
The curvature coefficient or responsivity (κ) is translated directly from the non-linearity
of the IV characteristics of the ASPAT diode for detector application Both RV and κ are
the parameters that can be extracted directly from diode DC measurement as discussed
in Chapter 5
The voltage sensitivity is actually a quantitative relationship between input
power and detector response Meaning that it is a change in signal output over change in
input power Normally output power is measured in Volts and input signal is measured
in Watts Therefore the unit of responsivity is VW[127 128]
181
TSS is referred to the lowest or minimum signal that the detector could detect it is
determined by the diodersquos βV and total noise available in the system (from the diode and
any amplifiers in the detector circuit) For any diode with fO=10 GHz and low noise of
1MHz bandwidth amplifier the TSS is typically less than -55 dBm[74] The TSS equation
is given by
119879119878119878 =
radic[4119884119870119861119879119861(119865119886 + 119905 minus 1)]
119872
(63)
Where M is a figure of merits and is derived based on the expression M= 120573119881 radic119877119881frasl t
denotes the diode noise temperature Fa is the noise figure B T and Y are the amplifierrsquos
bandwidth temperature and power for signal-to-noise ratio respectively For a low-level
video detector ie lt10GHz the sensitivity mainly depends upon three factors firstly on
RF matching structure secondly on the rectification efficiency output impedance and
noise properties of the diode and finally the input impedance bandwidth and noise
properties of the video amplifier at the detector output The RF matching structure
controls the quantity of overall energy at the active junction for rectification The second
factor controls the reaction of the diode to incident microwave radiation and the last
factor will influence the detector sensitivity in general[109]
In practical the Tss is a direct measure of the signal-to-noise ratio of a detector and
is achieved by varying the amplitude of the input pulse (RF signal) until a point in which
the top of the noise level with no signal applied is at the same level of noise at the
bottom level of RF signal It is commonly measured on an oscilloscope as depicted in
Figure 65 below It is defined as the input power at which a signal to noise ratio of 251
is produced[109]
Figure 65 Measurement of Tangential Sensitivity[108 129]
182
The transfer function in many detector diodes is often divided into three sections
Firstly at low incident power secondly at higher input power and finally at very high
power static (continuous) In the first region the detector diode performs as a square-law
detector in which Vout is proportional to Pin This region normally is used to extract the
dynamic range of the diode detector In the second region Vout is approximately
proportional to Vin and this region is known as the linear regime Finally at higher Pin
still the transfer function or response rolls off and thus Vout ultimately become saturated
This roll-off point where Vout has dropped by 1dB below an extrapolation of the
dependence at low Pin is termed the ldquo1dB roll-off pointrdquo and this value is usually in the
range of -11 to 12 dBm[15] Therefore a dynamic range of the detector diode can be
obtained by taking the interval between TSS and 1dB roll-off point (in dBm)
Finally the temperature dependence of Vout for a detector is normally taken from
two extreme points of the temperature (-40C˚ to +80C˚) and thus can be determined
from
Δ119881(119879) = 10 11989711990011989210 |
119881(1198791)
119881(1198792)|
(64)
This Vout variation between -40C˚ and +80C˚ normally expressed in dB
64 Noise Consideration in a Detector diode
The existence of noise in a system limits the accuracy of device performance and
the precision of measurements In a detector system specifically using a diode the noise
which can reduce the sensitivity of signal encryption is called the Noise Equivalent
Power (NEP) By definition the NEP is a noise power density over the detection
sensitivity and it can be exploited to determine the overall noise performance of a
detector[130 131] In other words NEP is defined as the power from the input source
(Pin) that is required to supply a voltage output (Vout) equal to the root means square
noise at Vout [132] For an ideal lossless match and assuming only Johnson-Nyquist is
present the NEP of a zero-bias detector can be expressed as
119873119864119875119900119901119905 = radic4119896119879119861119877119881120573119900119901119905 (65)
183
Where βopt is responsivity with an optimum match which is given by1 2frasl 119877119895120581 This type
of noise appears when changing voltages across a diode and a noise voltage (Vn)
normally will arise Theoretically the NEP has units of Watts (as it is actually a power)
but it often normalized to 1Hz as it is independent of bandwidth and thus the unit
becomes WHz12
Additionally there are also several noise sources that contribute to Vn in a
semiconductor diode which are Johnson-Nyquist noise Flicker Noise and shot noise
Johnson-Nyquist noise [133 134] appears across any conductor or semiconductor at
thermal equilibrium this is due to the thermal agitation of the carriers or charges It can
be expressed in root mean square voltage as below
119881119869minus119873 = radic4119896119879119861119877119895
(66)
Where Rj is the differential intrinsic resistance B denotes the post-detection bandwidth
T is the device temperature and k is the Boltzmann constant[134]
The second noise that is taken into consideration when dealing with semiconductor
devices is Flicker noise more commonly known as 1f noise It is a group of known and
unknown noise sources that can be observed in the frequency spectrum and normally
display an opposite to the frequency power density curve[135] It comes from a variety
of different causes ie recombination effects at a defect in semiconductor mobility
fluctuation and flow of direct current as well as interface phenomena [136-138] In term
of voltage source Flicker noise can be expressed as[139]
1198811119891 = 119870119891119881119909119891119910 (67)
Where Kf denotes a device-specific constant V is the voltage and f is the frequency The
value of x and y typically used are 2 and -1 respectively This type of noise (1f noise)
will be neglected at frequencies high enough due to the fact that the NEP of the diode is
proportional to the thermal noise and resistance of the diode
Finally the noise that causes time-dependent fluctuation in a flow of electrical
current because of the carrier or electron charge crossing a potential barrier is called shot
noise Shot noise is due to the randomness in the diffusion and recombination of both
majority and minority carriers[140] The equation of shot noise term at random time is
given by[141]
184
119881119878ℎ119900119905 = 2119902119868119861 (68)
Where q is the electron charge I is the current and B is the bandwidth This type of noise
is not affected by changes in temperature or device parameters Therefore the total noise
voltage appearing in the semiconductor is found to be [141]
1198811198992 = 119881119869minus119873
2 + 11988111198912 + 119881119904ℎ119900119905
2 (69)
However a zero-bias device will greatly eliminate both shot and flicker noise
compared to a biased device This has been explained by Equation (66) and Equation
(67) above where both noises are significantly related to the current and voltage Thus
if V and I =0 in the nonappearance of incident power then Vn will also become zero For
a detection process with bias the diode will be self-biased by ΔV which causes both
flicker and shot noise to appear But the shot noise in practical situation is much smaller
and thus normally ignored [142-144] Usually the noise in a zero-bias detector is
estimated by considering the low power limit as good first order estimation in which the
presence of only Johnson-Nyquist noise and ΔV is arbitrarily low [11 145 146]
Additionally it has been reported that the noise in tunnelling type diodes displays very
low or no excess noise in the bias region of the current-voltage characteristic[147 148]
Therefore in general most of the noise specifically in tunnelling type of diode will be
neglected this is a great advantage compared to SBD or transistors
65 Modelling of a 100GHz Zero-biased ASPAT Detector
Once the DC and RF characteristics of the ASPAT diode had been accurately
obtained the next step is to model and design a detector circuit based on S-parameter
measurement results as was explained in the previous chapter The aim is to realise a
detector circuit design which can be operated at millimetre and sub-millimetre wave
regions from an accurate diode model prior to the circuit design A diode detector model
puts experimental observations into context and offers insight into future experiment
results Consequently an electrical model based on lumped element component is vital
for a deeper understanding of how and to what extent a new device like the ASPAT
diode can affect all the key detector parameters that were previously discussed The
prediction of the detector parameters mostly depends upon the ASPAT diode
185
geometrical emitter size and material parameters However for millimetre wave
operating frequency the accuracy of the model is more sensitive not only to diode size
but also to the diode periphery ie substrate as well as coplanar amp transmission line
adopted in the circuit Therefore both extracted intrinsic and parasitic element of such a
device must be taken into account
In this work an ASPAT diode with an emitter size of 4times4microm2 which is the
smallest size that could be fabricated so far was chosen to be exploited for detector
designs The important parameters related to the 4times4microm2 GaAsAlAs ASPAT which
works at 0V is summarize in table 61 below
Table 61 A summary of all the important parameters of the 4x4 microm2 diode
Device Rj(Ω) Rs(Ω) Cj(fF) Cp(fF) κ(V-1) Intrinsic_fcut-off(GHz)
4times4microm2 90K 11 21 15 23 629
The actual measured I-V characteristic is used to model the diode since the library
in the ADS simulation tool does not have an ASPAT diode model or any tunnelling
diode for that matter The procedure of realizing the diode model is by taking the I-V
characteristic obtained from the 4times4microm2 emitter size measurement results and
converting it into a10th
orders polynomial equation via MATLAB software to create a
virtual I-V characteristic Thereafter this equation is then defined as a two terminals
device namely Symbolically-defined Device (SDD1P) ie a component of the non-
linear equation provided by ADS (Figure 66) to represent the ASPAT Figure 67
shows the measured data and 10th
orders polynomial equation fit very well to each other
Hence this new component used to represent the whole ASPAT diode will be used in
this research for MMIC detector and Frequency Multiplier designs The device chosen to
be modelled (4times4microm2) has measured junction capacitance of 21fF (at 0V at 40GHz) The
detector circuit is designed to operate at 100GHz for a safe side due to the extrinsic
calculated fcut-off is around 380GHz Since there are a lot of advantages in using unbiased
detectors compared to biased one this work will discuss the performance of millimetre-
wave detector at zero-bias and their result will be compared to the current performance
of other diodes reported in the literature
186
Figure 66 The configuration circuit to verify 10th order polynomial equation extracted from
MATLAB to realize a virtual GaAsAlAs ASPAT diode
Figure 67 Verification of actual (blue measured) and virtual (red_10th order polynomial) I-V
characteristic of the 4times4 microm2 diode used in this study
To realize the ASPAT detector circuit a simple detector circuit topology as
depicted in Figure 68 was constructed Initial simulation was run to perform a
functionality check of the detector circuit utilizing the Harmonic Balance (HB)
simulation tool embedded in that particular software Such simulation tools will analyse
the detector performances in the frequency-domain as it is mostly beneficial and fully
compatible with microwave and millimetre wave problems The frequency domain is
also suitable for single and multi-tone power excitation The importance of harmonic
balance are described in [149]
-00005
0
00005
0001
00015
0002
00025
0003
-3 -2 -1 0 1 2 3
Cu
rre
nt
(A)
Voltage (V)
ADS
4x4
187
Figure 68 Direct detector circuit topology using an ASPAT diode
Initially the circuit topology that consists of P1_Tone power supply ASPAT
bypass capacitor and load resistance is simulated by setting up a fixed input frequency at
100GHz The ASPAT diode provides a DC output voltage proportional to the input
power strength depending on the absolute values of the DC terms associated with the
nonlinearity of the I-V characteristics The capacitance in the output part is a bypass
capacitor used to prevent millimetre-waves from leaking to the output The load
resistance is large enough to ensure the voltage divider between load impedance and
device impedance gives maximum voltage sensitivity This large load resistance is
achieved by creating an open circuit at the end of detector circuit terminals
Noted that this simulation was run using diode parameters that were extracted from on-
wafer one port S-Parameter measurements as described in chapter 5 To apply them in a
two port application ie detector circuit may or may not provide a very accurate
outcome it however worked adequately in the particular circuit described in this chapter
but may not work in other circuits in general Thus the one port extractions in this work
still provide adequate parameters to build and design specific MMIC detector circuits
but not in general applications
The main reason for these simulations and their results to be used in high frequency
applications is due to the fact that actual RF measurement were done up to 40GHz
Additionally the 100GHz operating frequency was obtained from extrapolation of each
ASPATrsquos component Since the on-wafer measurement that were carried out were
limited to one port characterization applying them to two port network applications may
188
have extra consequences which are unknown Therefore actual MMIC detectors are
needed to be built and test to validate this work
To find out what power the 4times4microm2 ASPAT diode can withstand the input power
is varied from -40dBm to 10dBm via control by the P1_tone As can be seen in Figure
69 the diode starts to saturate when the received input power is about -8 dBm Above
this power limit both output voltage and sensitivity drop dramatically
Figure 69 Output voltage and detector sensitivity over wide range of input power
This diode detector circuit can thus operate adequately at given input powers from -30
dBm to -8 dBm with a sensitivity of 950VW However for the best possible sensitivity
over a range of input frequencies only one optimized input power needs to be chosen
The parameters that directly influence the voltage sensitivity are the curvature
coefficients load resistance and video resistance as can be seen from Equation (61)
Therefore in the following simulation the values RL will be optimized according to the
diodes optimum input power with regards to the highest possible voltage sensitivity
Consequently five values of load resistance were chosen from few ohms to infinity
and with the same applied input power as depicted in Figure 610 For most load
resistors the sensitivity is constant at low input power and drop at the diode saturation
region (-8dBm and greater) However for an RL value of 100KΩ and below the loaded
voltage sensitivity shows a peak near 0dBm input power which corresponds to the
maximum slope of the ASPAT detector transfer function The highest voltage sensitivity
is obtained by using an Open circuit load impedance as shown in the graph The Open
circuit load impedance gives the highest voltage sensitivity due to the voltage divider
189
between source and load impedance therefore RL must be at least 5-10 times larger than
Rj to give a better sensitivity
Figure 610 Simulated dependence of Voltage Sensitivity on incident power and load resistance of
the ASPAT detector
Furthermore the value of voltage sensitivity (βV) depends on the junction
resistance of the diode and thus the large value of Rj of the ASPAT diode yields the high
βV observed Rj which was taken from the non-linear measured IV characteristic is a
voltage dependent parameter [142]and is inversely proportional to the forward bias
voltage as depicted in Figure 611 below
Figure 611 Junction resistance as a function of forward voltage
1
10
100
1000
-40 -30 -20 -10 0 10
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Incident Power Pin (dBm)
Infinity
1KΩ
10KΩ
1MΩ
100Ω
100KΩ
0
20
40
60
80
100
0 001 002 003 004 005 006 007 008 009 01
Ju
nct
ion
Res
ista
nce
(k
Ω)
Bias Voltage (V)
190
In fact the expression of (120597119881120597119868frasl ) contribute to the video impedance expression via the
expression RV=Rj+RS (nonlinear resistance) As RS is very small compared to Rj thus it
was ignored when calculating RV Although the large value of Rj will increase the
voltage sensitivity it will also make matching difficult to achieve Therefore there will
be a compromise between the size of the matching circuit and voltage sensitivity to
attain the correct value of Rj Additionally a very high Rj (around ~1MΩ) will also
increase the detectorrsquos noise equivalent power (NEP in Eq(65)) Thus an average value
of RJ typically around 100kΩ is satisfactory[150] By having a large value of RJ one can
benefit from a low input power to drive the diode into the non-linear region and thus the
detector can work at very low RF input power The NEP for GaAsAlAs ASPAT diode
is then calculated based on parameters obtained from this simulation at room
temperature The values are compared to other diode detector available in the literature
as shown in Table 62 below
Table 62 Noise Equivalent Power (NEP) for zero bias detector diode
Device NEP (pWHz12) RJ(KΩ) Frequency(GHz)
ASPAT (4times4 microm2) 188 92 100
Tunnel Diode (08times08 microm2)[150] 370 26 220-330
Zero bias SBD[11] 15 3 150
Sb-Heterojunction Backward Diode[145] 024 32 94
VDI Zero bias SBD[151] 2 18 110
From the Table 62 above the NEP of the ASPAT is calculated based on RF input power
which is required to obtain an output signal-to-noise ratio of unity in a 1Hz at detector
output[142] and also the assumption of only Johnson-Nyquist (thermal noise) is
dominant for small incident power (-25dBm)[152 153] The prediction of NEP for the
ASPAT is comparable to the VDI Zero bias detector since the value of their junction
resistance is much lower than that of the ASPAT Therefore it is very important to
obtain a reasonable value of junction resistance From this it is clear that a trade-off of
high voltage sensitivity and low junction resistance is best to obtain low noise
191
Finally the curvature coefficient at specific operating voltages also influences
the voltage sensitivity of the detector Figure 612 shows the calculated curvature
coefficient of the 4times4microm2 ASPAT diode used in this work
Figure 612 Curvature coefficient for the measured I-V characteristic with a device size of 4times4μm2
The high zero-bias curvature (23V) is reached from the mutual effect of the intra-band
tunnelling in the GaAs-AlAs-GaAs and the highly doped GaAs at the anode and cathode
(Rs amp Rj) This was shown in the numerical simulation in[154] where the combined
effects of the optimum anode AlAs composition increases the curvature coefficients by
thinning the energy tunnelling window (intraband tunnelling process)
Other approaches that can lead to a large curvature is using smaller device area
with minimum series resistance [155] as was also discussed in Section 52 Having a
better curvature coefficient leads to increased voltage sensitivity as seen from Equation
(61) above and βV is also proportional to κ [111] The curvature coefficient calculated
using the above formula is nearly 23V at 1mV peak and high voltage sensitivity can be
achieved by having large value of curvature coefficient But one needs to remember that
this will also decrease with increasing input power because RJ which will also decrease
Therefore for a safe operating region the incident power that can be applied through the
diode is in between -30dBm to -8dBm for a 100GHz operating frequency
In this simulation -25dBm is chosen to simulate the GaAsAlAs ASPTAT diode
detector working at 100GHz input frequency By fixing the P1_Tone to this input power
-5
0
5
10
15
20
25
30
-001 001 003 005 007 009
Cu
rva
ture
Co
effi
cien
t(V
-1)
Voltage (V)
k(4x4 um^2)
192
the frequency is varied from 90GHz to 110GHz and the results are depicted in Figure
613 below
Figure 613 Voltage Sensitivity against frequency at -20dBm fixed input power
Noticeably the voltage sensitivity of the diode detector decreases linearly with
increasing input frequency At 100GHz a sensitivity of around 540VW is obtained
However the sensitivity in this case is roughly estimated from the Equation (61) above
and will not be sufficiently accurate because of the effect of other key factors such as
reflective power which was not included This parameter must be taken into the account
due the P_1Tone power source which provides a 50 Ω impedance source (Zin) which
does not match the load impedance (ZL) which consists of JωL 1JωC and Z and which
mainly comes from the ASPAT diode itself In order to determine the load impedance at
the diode a typical ohmrsquos law (Z=VI) equation must be used at the input side of the
diode with regards to the applied frequency (100GHz)
As a result the total load impedance obtained from the simulation is 11055-
j69057Ω which is clearly not matched to the 50Ω impedance source The mismatch
between source and load leads the available power from the source to be not fully
delivered to the load and hence there is loss of power leading to a lower detector
sensitivity Therefore actual calculation must take into the account the reflection impact
as expressed in the equation below
193
120573119881(119886119888119905119906119886119897) =
119877119869119877119871120581(1 minus |Γ|2)
2(119877119881 + 119877119871) (1 +119877119904
119877119895)2
[1 +1205962119862119895
2119877119878119877119895
1 + 119877119904 119877119895frasl]
(610)
Where the term (1-|Г|2) refers to the normalized power absorption by the ASPAT diode
and Г is the reflection coefficient due to discrepancy between 50Ω input impedance (Zin)
of the input port and the diode Consequently the calculation of reflection coefficient
(eq611) is carried out by using this expression and the result is shown in Figure 614
Γ =
119885119871 minus 119885119894119899
119885119871 + 119885119894119899
(611)
Figure 614 Reflection Coefficient versus operating frequency without matching circuitry
As can be seen in Figure 614 without the matching circuit the S11 is decrease
linearly with frequency but only very slowly This means that most of the RF power
transmitted from the source is reflected back (by that ratio) when it went through the
diode Therefore in order to resolve the mismatch a matching circuit is introduced in
between the source and load of the detector circuit as shown in Figure 615 (red
rectangular) This matching circuit works by transforming the load impedance into an
impedance that is identical to the source or input impedance Note that for any
impedance matching circuit the main purpose is usually to obtain maximum power
transfer to the load however in some cases (ie oscillators) the matching circuit is to
achieve a lower noise figure Hence in a broad sense the introduction of the matching
194
circuit in a detector circuit can be defined as a circuit that convert available impedance
into wanted impedance by obeying the maximum power transfer theorem [156]
Figure 615 Detector circuit with impedance matching circuit placed in between diode and source
There are many type of matching circuit that can be used to achieve both
objectives above such as circuits using lumped element transmission-line-impedance
matching circuit single and double-stub tuners as well as a quarter-wavelength In this
design the technique used to match source and load impedance is the single open and
short stub (in red rectangular) as it is simple convenient and very efficient in ADS
simulation The important parameter that needs to be tuned in both stubs is the electrical
length (E) at any designed frequency ie 100GHz in this case The E tuning is realized
by using the Smith Chart features available in the ADS simulation tools Figure 616
shows the reflection coefficient with matching circuit modelled over a broad frequency
band and it is clearly shown that at the desired operating frequency the reflection is very
low Note that it is difficult to obtain wide frequency band matching
Matching circuit
195
Figure 616 Reflection Coefficient over wide frequency band with matching
The simulation is continued to find the effect of the matching circuit placed in
the detector circuit on the voltage sensitivity The same input power (-25dBm) is applied
to the diode and the voltage sensitivity is plotted against frequency as depicted in Figure
617 Obviously at the desired operating frequency (100GHz) the sensitivity rises up to
a maximum value of 2100VW with this value obtained without any reflection and the
input port being completely matched with the ASPAT diode model used in this work
Figure 617 Simulated voltage sensitivity of GaAsAlAs ASPAT detector at W-band frequency
Once the matching circuit to be used for 100GHz operating frequency was confirmed
further simulations were made by applying a series of low input power to find the
tangential sensitivity (Tss) of the detector diode When determining the Tss it is very
important to include the matching circuit as it will minimize any power losses through
the diode thus a very small input power can be detected
196
Figure 618 Lowest detectable signal at 100GHz operating frequency
The transfer function depicted in Figure 618 shows incident power of -80 dBm
to -50 dBm applied and the lowest detectable signal that can be obtained with 4times4microm2
mesa size ASPAT diode is around 138microV at -68dBm Although a typical value of Tss is
normally not more than ~-55dBm as in ref [74] the lower value obtained in the
simulation is because the device is operated at zero bias operation and does not use any
amplifier therefore the noise and values related to amplifier as in Equation 63 have been
neglected Even though the TSS appeared very low it is most likely very dependant to
the 10th
order polynomial equation embedded into SDD in ADS software Therefore in
near future the TSS value has to be determined in real fabricated MMIC ASPAT detector
As discusses in Section 63 other important parameter that can be extracted from
the diode transfer function is the Dynamic Range of the diode It can be obtained in a
region called square law region which is a region where the Vout of the ASPAT diode is
proportional to the square law of the input power signal From Figure 619 the square
law region is in between -68dBm and -12dBm and the linear region or in this case
saturated region is above -12dBm Taking to the account the roll-off point where Vout
has dropped 1dB below the extrapolation of the dependence at low input power and
therefore the dynamic range of the detector diode can be obtained by taking the interval
between TSS and the 1dB roll-off point (in dBm) which is ~55dBm
197
Figure 619 The dynamic range of the ASPAT diode obtained from linear region of diode operation
The figure of Merit (M) of the detector (ie equation 63) is 2100 (90K) 12
where 2100 is the sensitivity and 90K is the value of RJ at zero bias which is equivalent
to 652 W The M value should be large however in this case due to RJ being very
large it has dropped tremendously when compared to the voltage sensitivity obtained in
this simulation The results obtained indicate a reasonably successful design of the
MMIC detector using the 4times4microm2
emitter size GaAsAlAs ASPAT diode The results
obtained lead to the design of other MMIC detector using the other fabricated diode
sizes (6times6microm2 and 10times10microm
2) A Similar procedure to the one used for the 4times4microm
2
diode was followed The only difference was the use a slight higher input power (-
20dBm) than in the 4times4microm2 design Hence the simulation results obtained are then
compiled and compared as depicted in Figure 620
Saturated
Region
198
Figure 620 Simulation result of diode sensitivity for three devices geometries obtained from the
fabricated ASPAT in this work
The graph plotted for each dimension was taken after matching circuits were included
As can be seen in Figure 620 the highest sensitivity is achieved using the smallest
device size as this has the highest cut off frequency Table 63 below summarises the
performances of the 100GHz ASPAT detectors obtained from the simulation in this
work
Table 63 Summary of characteristic of interest for GaAsAlAs ASPAT detector
Device Tss(dBm) fcut-
off(GHz)
Bv
(VW)
Dynamic range dB(dBm) M(W-12
)
4times4microm2 -68 380 2100 55 65
6times6microm2 -50 151 1445 48 45
10times10microm2 -40 98 247 40 21
From table 63 above it is clear that a lower cut-off frequency will affect the
voltage sensitivity The dynamic range between each ASPAT is different because larger
size area will allow more power to go through the diode as a result of high current that
such a device can handle before reaching the saturation their lowest detectable is higher
Small diode size will detect lowest voltage but cannot handle high power On the other
hand a large diode size is able to receive high power however can only offer lower
voltage output Therefore there is a trade-off between small diode size and receiving
input power which will directly affect Tss and 1dB roll off Once again all the
100
1000
10000
90 95 100 105 110
Vo
lta
ge
Sen
siti
vit
y (
VW
)
Frequency (GHz)
10times10microm^2
6times6microm^2
4times4microm^2
199
parameters obtained in this simulation are just estimation from the 10th
order polynomial
equation thus real ASPAT detector has to be fabricated for verification
The best device performance among all GaAsAlAs ASPAT diodes was obtained
with the 4times4microm2 mesa area size diode which was compared to other exiting millimetre
wave detector diode available in the literature Since the 100GHz is located in the W-
band spectrum frequency therefore the comparison will be performed in this frequency
band but with low input power The parameters for the-state-of-the-art zero bias
detectors are gathered in Table 64 below
Table 64 Comparison 4times4microm2 GaAsAlAs ASPAT diode to the-state-of-the-art zero bias detector
at W-band (75GHz-110GHz)
Device Size(microm2) Tss(dBm) βv (VW) Pin (dBm) f (GHz)
GaAsAlAs ASPAT 4times4 -68 2100 -25 100
GaAs SBD HSCH-
9161[157]
- -49 2200 94
HBD[158] 15x15 2540 -20 95
Planar SBD[159] - -68 2100 -25 100
Note that the ASPAT diode retains its favourable temperature stable characteristics
which are not the case for all the diodes used for comparison in Table 64
66 Conclusions
In this chapter all theory regarding RF detection using diodes ie parameters of
interest noise consideration etc have been discussed The aim to design and develop a
low cost reliable and sophisticated zero bias 100GHz detector circuit was achieved
through exploitation of a 4times4microm2 GaAsAlAs ASPAT diode The design was performed
with the aid of Keysight ADS modelling software utilizing harmonic balance simulation
The effect of load resistance junction resistor to the detector voltage sensitivity was also
discussed in details The 90KΩ Rj value and open circuit load resistance was chosen for
high sensitivity
200
A step by step design of a W-band ASPAT detector was presented The effect of
matching circuit was discussed in detail and where an unmatched sensitivity of 843VW
is obtained which then increases to 2100VW after matching Through RF
characterization simulation a detection at 100GHz (W-band) was successfully achieved
with a relatively large device mesa area (4times4microm2) at an input power of -25dBm
(8microWatt) leading to a 2100VW voltage sensitivity a -68dBm TSS and 55dBm dynamic
range All these values are comparable to others fabricated diodes in the literature
The zero bias ASPAT detectors based on the GaAsAlAs material system in this
work are still at an early stage of development a lot of work is still required to realize
high yielding integrated millimeter and sub-millimeter wave (MMIC) detector circuits
However as this work is on-going at Manchester it is expected that fabricated ASPAT
MMICs with even higher voltage sensitivity will be fabricated in the near future through
collaborating bodies involved in this research especially the University of Cambridge
and ICS Limited
201
7 FREQUENCY MULTIPLIERS (DOUBLER) DESIGN USING
GAASALAS ASPAT DIODES
71 Introduction
Originally the key application for the ASPAT diode was for use as microwave and
millimetre wave detectors[18] This is due to the fact that such diode demonstrates
strong non-linearity low noise and high cut-off frequency features as described in the
previous chapters However these features are not only beneficial for detection purposes
but also allow them to be used and designed as microwave and millimetre wave sources
The only way to generateenhance continuous wave (CW) power using a non-linear
device is through frequency multiplication techniques It is known that the frequency
multiplier is the alternative approach (to 3 terminal transistors) using non-linear devices
that are used to generate high frequency low phase noise signals Any high quality low
frequency signal that goes through a frequency multiplier circuit can be generated to any
desired high output frequency[160] Therefore the main objective of this chapter is to
demonstrate the feasibility of the ASPAT diode as a compact source of microwave and
millimeter-wave receiver for imaging applications[161]
The study of the ASPAT diode as a power source begins with a brief explanation
of the importance of a frequency source and the lack of compact device and technologies
at high-frequency signals The state-of-the-art for frequency multiplier will also be
discussed In the next section (Section 74) the fundamentals of the frequency multiplier
architecture ie the principle of operation and appropriate devices will be presented
Since this is the first attempt at using GaAsAlAs ASPAT diodes a simple multiplier
circuit design and topology was built This will be discussed in detail in the subsequent
sections where simulation results are discussed The focus of the discussion will be to
demonstrate the possibility of a GaAsAlAs ASPAT diode functioning as a frequency
multiplier and comparison with other state-of-the-art varistor mode frequency
multipliers
202
72 Motivation and Background
Typically continuous wave (CW) sources generating below 100 GHz can be
obtained through oscillators amplifiers and pin diode comb generator Below 10THz
the sources can be made from RTD IMPATT diodes and Gunn oscillators and above 10
THz it is commonly done by photonic mixing quantum cascade laser (QCL) and gas
lasers [162] Both types of sources and their performance are plotted in Figure 71
However these conventional ways of generating millimetre and sub-millimetre waves
have their own limitations ie high cost complexity and sometimes requirement for
cryonic cooling The most effective way to tackle the limitations of conventional mm-
wave and THz sources is by implementing frequency multiplication technique using
solid state nonlinear diodes [163-165] such as SBD and ASPAT diodes
Figure 71 performance of state-of the-art millimetre wave source [166]
Twenty years ago there were only two types of diodes (SBD and P-N junction
diodes) often used for frequency multiplication To date besides the SBD there are
many types of diode that have been used as frequency multipliers These include the
high electron mobility varactor (HEMV) single barrier varactor (SBV) [167] and hetero-
structure barrier varactor (HBV) (270GHz with 90mW input power and Conversion
Efficiency of 72)[168 169] Other variants that have developed to enhance the
frequency multiplier performance of the classic SBD [170] include the Barrier-intrinsic-
203
n+ (BIN)diode and Barrier N-layer N+ (BNN) diode [171] Other diodes for use in such
applications are the planar doped barrier diode (PDB) Resonant tunnelling diode (RTD)
amp it families ie Quantum well diode (QWD) and step recovery diode which is a
modification of the P-N junction diode
Although three terminal devices ie FET GaAs MESFET and HEMT had
shown better performance and are capable of achieving greater efficiency and
bandwidth as well as having additional conversion gain features [160] two terminal
devices (ie varactor diodes) which are passive multiplier are still preferred This is due
to their simplicity and most importantly their ability to generate very little noise Among
these types of device technologies the SBD is preferable as it is mature and has been
shown to be very suitable for high-frequency applications [172 173]
The ASPAT diode is exploited to investigate the possibility and the feasibility of
generating microwave and millimetre-wave power through well-known frequency
multiplication methods The utilisation of the ASPAT in frequency multiplication will
also aid in generating local oscillator sources which are critical components in
heterodyne receivers The ASPAT diode will work in resistive I-V mode (varistor mode)
and has features to work also at zero bias condition thus offering low power handling
than traditional high-efficiency varactor diode since the varactor diode requires a large
reverse bias supply of several tens of volts
73 Frequency Multiplier Architecture the Basics
In principle a frequency multiplier is an electronic circuit that gives an output
frequency that is a multiple integer of its input frequency signal pumped from a local
oscillator as depicted in Figure 72 The ability to generate any desired multiple output
signals is realised by a nonlinear device ie diode or transistor Such devices though
also can give distortion or cause sudden change to the input frequency Additionally
these devices generate multiples of the input frequency (fout) The distortion of the
sinusoidal signal refers to an abruptsudden change versus amplitude or time which thus
generates higher frequency with lower amplitudes of the input signal Usually a
frequency multiplier circuit will include a bandpass filter to select the desired harmonic
204
frequencies and deselect undesired harmonic frequencies especially fundamental
harmonic at the output for further processing
Any non-linear device either in symmetricalantisymmetric current-voltage or
capacitance-voltage can be utilised to realise a frequency multiplier source [168 174]
Figure 73 describes the method where a nonlinear resistance is utilised to convert a
harmonic input signal into periodic output signal containing components at multiples of
the input frequency Both non-linear resistance and reactance characteristics can be
extended into power series methods
Figure 73 Principle of operation for frequency multiplier utilising a non-linear resistance [10]
The operating principle of the frequency multiplier is shown in Figure 73 where
the I-V curve converts a harmonic frequency input into a periodic frequency output
including components at multiples of the input frequency The non-linear I-V
characteristic can be explained in term of a power series at the operating fixed point of
bias voltage (VB) [174]
Frequency
Multiplier Circuit
finput
foutput
= nfinput
Figure 72 Frequency multiplier has the property that foutput is an integer multiple of fin
205
119868(119881119861 + ∆119881) = 1198860 + 1198861∆119881 + 1198862∆1198812 + 1198863∆1198813 helliphellip (71)
For a given input voltage as below
∆119881 = 119881119904 cos120596119878119905 (72)
The input signal harmonics will become
119868(119905) = 1198680 + 1198681 cos120596119904119905 + 1198682 cos 2120596119904119905 + 1198683 cos 3120596119904119905 (73)
Where t and ω are the time and angular frequency respectively based on equation (73)
the output contains both signal source and harmonics Therefore a complete frequency
multiplier circuit has to have non-linear device and filter to allow the selection of any
frequency components needed
731 Types of frequency multipliers
Frequency multipliers can be classified into passive and active multipliers This
classification is based on the ability of the frequency multiplier to yield any conversion
gainlosses The passive multiplier is the one that only produces conversion losses In
other words it can be described as a multiplier that generates an output power level
lower than the excitation input power and it is mostly dominated by passive nonlinear
devices ie Diodes On the other hand the active multipliers refer to a device that would
produce an output signal with a power level that is greater than the input signal power
This conversion of power is termed as conversion gain These types of multipliers attract
much attention as they do not only increase the frequency at the output but also the
signal power
Passive frequency multiplier can be formed by using diodes that are classified as
being of the varistor (non-linear I-V) or varactor (non-linear C-V) type [160 174] The
varistor type will influence the frequency multiplication with a non-linear resistance or
conductance (resistive diodes) and this results in a very large potential bandwidth at the
output but poor conversion efficiency The varactor diode type where the frequency
multiplications are affected by the non-linear capacitance (reactive diode) as their
reactive element typical result is high conversion efficiency A diode that is used in this
206
application must have strong nonlinearity stable electrical characteristic repeatable and
has fast enough response to an applied frequency Therefore multipliers are classified
into Doubler Tripler quintuple and so forth depending on the highest power of output
harmonic signal
In general all varactor type diodes with such characteristics will produce high
power at odd-order harmonic oscillation if any microwave signal is pumped into them
The benefit of having odd-order in multiplier design is that it reduces the complexity of
the overall circuit ie it eliminates even-order idler frequencies [175] The varactor type
diode had been shown by Manley-Rowe to a get maximum 100 conversion efficiency
for generating an ideal harmonic [176] compared to the varistor type where the
maximum efficiency achievable ideally is 1 1198992frasl where n is the multiplication factor
(output harmonics number) [174] In the case of power handling (input excitation power)
for multipliers varactor mode diode required greater power (several milli Watt) than the
varistor mode due to the fact that reverse applied voltages are very large (many tens of
volts) Therefore these types of frequency multipliers may not be suitable for the case of
high input power excitation There no report in the literature of varistor based
multipliers working with high power excitations
74 Parameters of interest for Frequency Multipliers
The simplest way to describe an equivalent circuit for a complete frequency
multiplier is by setting a Source impedance (ZS) at the input side and load impedance
(ZL) at the output side as depicted in Figure 74 below This circuit usually has the same
properties as described in the previous chapter and most of the others two ports
networks However in this case the purpose is different and is the conversion of a sine
wave signal source (Vs) with angular frequency ωs to an output signal with frequency
nωs where n is the multiplication integer or the order of multiplication
207
Figure 74 A standard system for two port frequency multiplier circuit
Referring to Figure 74 above there are few sets of parameters for the frequency
multiplier to be taken out and compared Examples are the conversion loss maximum
input signal power Impedance at source and load Bandwidth multiplication factor or
harmonic amp subharmonic content and noise conversion properties The conversion loss
(CL) is described by the ratio of available power at source (Ps) to the output harmonic
power delivered to load resistance (PL) and is normally expressed in dB It occurs due to
the nature of passive semiconductor diodes and the electronic circuit itself that are lossy
and dissipate energy On the other hand the conversion efficiency (ηn) is a ratio of the
output power at load (PL) to the available power at the input (Ps) This is often expressed
in percentage () The conversion efficiency can be determined as
120578 =
119875119878
119875119871
(74)
while the conversion loss is expressed as[174]
119871119899[119889119861] = 10 log
119875119904
119875119871= 10 log (
|1198811199042|
4 119877119890 |119885119904||1198681198712|119877119890|119885119871|
) (75)
Where Vs is the input voltage and IL is the output current amplitude Besides this the
conversion efficiency is often referred to as the inverted value of the Ln In designing a
frequency multiplier it is crucial to minimise the conversion loss and maximise the
conversion efficiency value
To achieve a perfect multiplier with minimum conversion loss the impedance of
source and load must be at an optimum level This implies that the source impedance
Frequency
Multiplier Z
L
Zout
Z
in
V
Z
SWR Г
208
(Zs) must be very close to the complex conjugate of the multiplier input impedance
(Zin) hence minimum reflection loss will occur at the input side This can be realised by
introducing an impedance matching circuit between the diode and source The power
transfer between the source and the multiplier is quantitatively described by the value of
the multiplier input reflection coefficient (Ѓ) with source Zs assumed to represent a
reference impedance This specification also can be explained in the standing wave ratio
(SWR) Both relationships are described below respectively [174]
Γ =
119885119894119899 minus 119885119904lowast
119885119894119899 + 119885119904
(76)
119878119882119877 =
1 + |Γ|
1 minus |Γ|
(77)
Where the asterisk () represents the complex conjugate of the Zs impedance
On the other hand the situation of the load impedance is different when a standard
or an optimum value is provided by the designer This will either increase the conversion
loss or decrease the output power Thus one has to keep in mind that frequency
multipliers are non-linear devices and power transfer condition both at the input and the
output depend on each other and the input signal level[174]
75 20GHz40GHz Varistor Mode ASPAT Diode Frequency Doubler
In this work a similar ASPAT diode (4times4microm2) to that in designing millimetre
wave detector in the previous chapter is used The main objective of designing the
frequency multiplier circuit was first to investigate the performance of the ASPAT
diode as a microwave or millimetre wave signal source A design is deemed successful
when the diode physical parameters are optimised and the suitable impedance matching
network is produced for each desired harmonic as well as maximising the output power
These goals however are hard to achieve when a higher frequency operation is targeted
for use
There are many types of multiplier circuit topologies that can be implemented
using GaAsAlAs ASPAT diode in varistor mode to achieve high order of multiplication
209
Examples are single diode multiplier series or parallel connected diode multiplier anti-
parallel amp anti-series connection diode pair multiplier anti-parallel-series connected
diode multiplier and bridge frequency multiplier as well as nonlinear transmission line
frequency multiplier [174] Before designing a circuit there is one most important
consideration to make Prior to choosing any mentioned circuits to be used for frequency
doubler the design considerations are made based on the capability of ASPAT diode to
receive an optimum amount of input excitation RF power From the discussions in
Chapter 6 the ASPAT diode will reach saturation level (linear regime) at power ~
-10dBm for a device size of 4x4microm2 Once the optimum input power was confirmed the
circuit topology was carefully chosen to balance between the requirements of the
ASPAT to work at high frequencies ie low Rs and Cj amp high diode cut-off frequency
as well as the desired output signal frequency that needs to be produced
To realise the first attempt of an ASPAT diode as a signal source a simple circuit
topology of a frequency doubler was deployed as depicted in Figure 75 below The
frequency doubler circuit consists of a voltage source (can be power source) input
filtering with matching network ASPAT diode output filtering with matching network
and load impedance (ZL)
Figure 75 Block diagram of frequency doubler with series ASPAT mounted diode
In order to investigate the doubler performance the Keysight ADS simulation
tool and similar procedure to obtain accurate ASPAT model using a 10th
order
polynomial equation as in Section 65 was used The circuit in Figure 75 is translated
into ADS format as illustrated in Figure 76 Once the circuit was constructed the
analysis was performed using the Harmonics Balance (HB) simulator The circuit
requirements are matched terminations at the input and output frequencies open
Input Filtering
and matching network
Output Filtering
and matching network
Zs
Vs
ZL
Pin
fin
Pout
nfout
210
circuited terminations at the higher harmonics and optimum reactive terminations (an
inductance which resonates with the junction capacitance) at the output frequencies
Figure 76 Empirical modelling of ASPAT doubler utilising Keysight ADS tool
The circuit in Figure 76 is the simplest way of constructing a frequency doubler
circuit which consists of the signal source (P_1Tone) input matching circuit (Stubs)
filter (Short stub) ASPAT diode low pass filter output matching circuit(Stubs) and ZL
(load resistance) The utilisation of the stubs is an ideal case of simulation since in the
real fabrication stubs are normally formed in large sizes Therefore a proper design such
as using CPW instead of stubs is essential in real fabrication
Again this simulation works for this particular circuit in this chapter as all the diode
parameters were extracted from on-wafer one port S-Parameter measurement described
in chapter 5 To apply them in such two ports applications may not very accurate
however it still provides adequate parameters to build and design particular frequency
multipliers but not in general applications These simulations and results are adequate for
high frequency applications due to the fact that the actual RF measurements on the
diodes were carried out up to 40GHz and the target operating frequency in this multiplier
design does not exceed 40GHz
Since the on-wafer measurement that were carried out were limited to one port
characterization applying them to two port network applications may have extra
consequences which are unknown Therefore actual MMIC frequency multiplier is
needed to be built and test to validate this work
Input Matching
Output Matching
211
To find the optimum output power initial simulation without matching circuit
was performed This simulation was run by varying the input power from -35dBm to
20dBm but fixing the input frequency at 20GHz As can be seen in Figure 77 the lowest
point in the conversion loss (CL) and the highest point of the conversion efficiency (CE)
are obtained from an input power of -1dBm However this amount of input power is too
high for the ASPAT diode The lowest CL at -1dBm may not be accurate since it was
applied without matching Note that it is difficult to achieve a matching between source
impedance and load impedance when varying the input power Therefore a lower input
power of -10dBm is chosen for this frequency doubler operation Figure 77 shows the
Conversion Loss and Conversion Efficiency as a function of the available power of the
given input source
Figure 77 Conversion loss and conversion efficiency as a function of input power
The circuit in Figure 76 works with a -10dBm input power and 20GHz centre
frequency input signal is pumped from the power source (P1_tone) to the ASPAT diode
and distortionabrupt change of input waveform occurs at the fundamental frequency (f0
in this case 20GHz) Such abrupt change produces harmonics and these harmonics can
be classified into desired frequency component by placing two-quarter wavelength (λ4)
stubs (90˚) at both sides of the ASPAT diode At the input side of the diode short circuit
stubs are utilised to permit the f0 tone to reach the ASPAT diode and block the second
harmonics (2f0 in this case 40GHz) back to the input side and pushes it towards the
load resistance On the contrary at the output side of the diode the open circuit stubs are
used to ldquoopen circuitrdquo the 2f0 signals while ldquoshort circuitrdquo the f0 component Thus 2f0
212
signal will not be affected due to the open circuit stubs being half wave (λ2) long The
function of both stubs is basically to isolate the input and output signal from mixing each
other Therefore the design of input and output matching circuit can be achieved easily
The input matching circuit was designed based on the mentioned input frequency
(f0=20GHz) for an available input power (Ps=-10dBm) which is set up at the power
source by using two stubs with the same configuration as used in Chapter 6 Such
configuration is purposely deployed to increase the 50Ω coming from the P1_tone
source impedance to the conjugate thus reducing the reflection coefficient to the
ASPAT diode From the simulation without matching the input impedance to the diode
is 551Ω in magnitude for an available input power of -10dBm
On the output side of the diode output matching circuit is available to transform the 50Ω
port impedance in the optimum load impedance which provides minimum conversion
loss for the ASPAT diode The output matching circuit is designed based on expected
output frequency which is in this case 2f0 =40GHz Other than this optimum
impedance between load impedance and ASPAT will not be achieved thus resulting in
higher conversion loss
To ensure the proposed circuit is valid and suitable for the specific ASPAT diode
mesa size the response of conversion loss and efficiency are plotted as a function of
output frequency from 20GHz to 100GHz The results of both conversions are illustrated
in Figure 78
Figure 78 Conversion loss and Conversion efficiency as a function of output frequency
213
As can be seen in Figure 78 the conversion loss is obtained at the lowest point where
the output frequency is needed Meanwhile the conversion efficiency is maximum at the
same output frequency Therefore this indicates that the first attempt of an ASPAT
Doubler frequency source works well However the values obtained for Ln from this
simulation is 28dB which is rather high On the contrary the η achieved in this study is
very low with a value less than 1
Since the ASPAT is in varistor mode with no bias applied the conversion
efficiency is expected to be low due to resistive losses Another factor that may
contribute to lower η is the diode model itself as it is taken from a 10th
order polynomial
equation not from a diode model provided in the ADS software tools Thus some
properties of such tunnelling diode may not be included Hence it is necessary in due
course to fabricate and build such a compact frequency doubler in the future to verify
the simulation results
From the simulation point of view the less than 1 Conversion Efficiency
obtained is still good enough for a first attempt at a frequency doubler which utilises the
new ASPAT tunnelling diode The frequency doubler obtained from this work is suitable
for use in zero bias varistor modes for low power application The varistor mode doubler
performances from this simulation work are gathered and compared to other in the
literature as summarized in Table 71 below where fout is 40GHz η is 015 Ln is 28dB
and Pi is -10dBm
Table 71 Comparison parameter obtained from this simulation to the state-of-the-art multiplier
diode
Device fout (GHz) η() Ln(dB) Pi (dBm)
ASPAT 40 015 28 -10
SBD (Si)[177] 104 2 134 -10
SBD (GaAs)[178] 13 2 137 -16
214
The performance of the 2040GHz is compared to the literature based on their input
power below -8dBm since the ASPAT is only capable of working at low power To the
best of the author knowledge very few diodes operating in varistor mode at low power
excitation can be found in the field of research and industry Therefore this 2040GHz
ASPAT Doubler might a first for tunnel diodes if it can be fabricated and test at Ka band
and above
76 Conclusions
In this chapter another alternative application based on non-linear features of
GaAsAlAs ASPAT has been presented The simulation of a frequency multiplier
(doubler) was carried out utilizing the 4times4microm2 size ASPAT diode The theory and the
ability of the ASPAT diode to operate as a frequency source were explained in detail
A unique varistor mode frequency multiplier circuit topology for the 2040GHz
ASPAT doubler has been demonstrated and briefly discussed The details and step by
step simulation technique utilizing harmonic balance from Keysight ADS has been
presented Even though the conversion efficiency is very small at 015 and large
conversion loss of 28dB there is still space for improvement in term of design ie
different circuit topology optimized input and output matching circuit etc This design
can be a good reference for a doubler operating at very low power but produce high
frequencies in Ka band
215
8 CONCLUSION AND FUTURE WORK
81 Conclusion
The main focus of this research was the development of a new tunneling diode
namely the asymmetrical spacer layer tunnel (ASPAT) diode for process repeatability
manufacturability and reproducibility The broad study undertaken was to improve the
microwave performance technology by introducing a new type of tunneling diode
For years the asymmetrical spacer layer tunnel diode was unable to be manufactured
due to the high sensitivity of the tunneling current to the barrier thickness This changed
dramatically when the MBE method was carefully optimized to precisely control the
growth to sub-monolayer precisions When stability repeatability and reproducibility in
the epitaxial growth was achieved the next step was to qualify the fabrication process of
the diodes themselves thus ensuring high performance device can be delivered to the
market
For this purpose GaAsAlAs ASPAT diodes made of two different types of
substrates were grown The first batch was grown in the Riber V100HU SSMBE and
used doped substrates Samples XMBE307 and XMBE368 were successfully grown
and fabricated from that batch The DC characterization obtained from measurement
proved that this first batch had fully functional reproducible and manufacturable
devices Later a second batch using semi insulating substrates improvement in spacer
layer and doping concentration were grown This set of samples (9 x 2rdquo wafers grown
simultaneously) and denoted as XMBE304 also showed fully functional DC
characteristic and was used for RF characterization and detector integrated circuits
The conventional GaAsAlAs ASPAT diode structures grown on doped
substrates and developed previously in our lab were not suitable for high frequency RF
characterizations Therefore a major contribution of this work was to develop a new
fabrication technique for a new GaAsAlAs ASPAT structure using semi insulating
substrates to achieve repeatability manufacturability and reproducibility in term of
process flow DC characteristics and ultimately RF characteristics Apart from the
enhancement of the epitaxial layer the other important contribution of this research was
216
the optimization of the small 4times4microm2 emitter size by incorporating both vertical and
lateral structure based purely on low cost I-line optical lithography
To obtain a repeatable and manufacturable fabrication process of lateral
GaAsAlAs ASPAT structures the key issue was to solve the over etching of the
effective mesa area when qualifying the Air Bridge technique This issue caused all
semiconductors under the metal contact to be completely lost thus leaving the metal
contact hanging without connection to any bond pad area However the developments of
the Dielectric Bridge technique realized the true performance of the GaAsAlAs ASPAT
diode structures The samplersquos surface cleanliness as well as DC and RF performance
showed significant improvement when using Si3N4 as a dielectric layer Due to the
highly isotropic etching profile and thicker GaAs layer in XMBE304 samples and
although the smallest emitter size designed on the mask was 2times2microm2 only 4times4microm
2 were
reproducible and showed good uniformity in I-V characteristics
Upon successful optimization in the fabrication process flow of the small emitter
size diodes (4times4microm2 6times6microm
2 and 10times10microm
2) a good uniformity of better than 91
was obtained for DC measurement results within a tile containing over 1000 devices
This confirmed that the lateral GaAsAlAs ASPAT diode structure can only be realized
through the Dielectric Bridge technique These devices were further characterized with
S-parameter measurements and their intrinsic and extrinsic parameter values and
junction capacitances series resistances and junction resistances were extracted leading
to intrinsic cut-off frequencies of 600GHz 429GHz and 100GHz for the three device
sizes respectively
Temperature dependence measurements and simulations were also carried out in
order to confirm that the ASPAT diodersquos characteristics were temperature insensitive
showing less than 5 change in current at both extremes of temperatures 77K to 400K
By comparison the SBD I-V characteristics variations with temperature span orders of
magnitude Physical modelling agreed very well with measured data confirming good
and validated models that can also describe temperature effects
For the realization of the integrated ASPAT millimeter wave detector empirical
modelling using ADS simulation tools was carried out This was performed to predict
the detector performance at 100GHz to comply with the initial objective to develop a
217
millimeter wave detector circuit The simulations using the 4times4microm2 diode models led to
a successful 100GHz circuit design able to detect 100GHz incoming frequency with
2100VW voltage sensitivity
The first ever GaAsAlAs ASPAT diode frequency multiplier design was also
attempted A reasonably good result was obtained for a 20 to 40GHz frequency doubler
operating in varistor mode However the conversion efficiency obtained was less than
1 Further research on this is required to improve the efficiency by using other circuit
topology ie using a balun or other Co-planar waveguides Ultimately fabricating and
testing the actual multiplier circuits are essential to validate the simulation data
82 Future Work
This work has provided a foundation for a reproducible and repeatable GaAsAlAs
ASPAT (SI substrate) wafer fabrication process and recommendations for design and
simulation of ASPAT diode MMIC detectors and frequency source has also been
provided However the GaAsAlAs ASPAT diodes still remain immature and there are
many ways to improve its DC and RF performances both experimentally and in
simulations which will directly affect the detection performances
In term of fabrication process smaller size diodes ie submicron level can be
achieved using dry etching technique with proper calibration For wet etch technique the
etched profile still can be improved by thinning the doped layers so that etching time
will be reduced and hence dimensions down to 2times2microm2 or even 15times15microm
2 can be
reproducibly made
For simulations advanced AC and RF modelling utilizing physical device
simulation available software (SILVACO) must be include in future research hence
holistic study can be conducted to improve the understanding of the ASPAT
For MMIC detector and multiplier design it is vital to produce actual MMIC
devices so that the simulation results can be validated Ultimately tested devices with
good performances can be realized and manufactured
218
REFERENCES
1 Laeri F U Simon and M Wark Host-Guest-Systems Based on Nanoporous
Crystals 2006 John Wiley amp Sons
2 Łukasiak L and A Jakubowski History of semiconductors Journal of
Telecommunications and information technology 2010 p 3-9
3 Song H-J and T Nagatsuma Present and future of terahertz communications
IEEE Transactions on Terahertz Science and Technology 2011 1(1) p 256-
263
4 Hu B and M Nuss Imaging with terahertz waves Optics letters 1995 20(16)
p 1716-1718
5 Smith PR DH Auston and MC Nuss Subpicosecond photoconducting
dipole antennas IEEE Journal of Quantum Electronics 1988 24(2) p 255-260
6 Nagatsuma T Terahertz technologies present and future IEICE Electronics
Express 2011 8(14) p 1127-1142
7 Kumar S et al A 18-THz quantum cascade laser operating significantly above
the temperature of [planck][omega]kB Nature Physics 2011 7(2) p 166-171
8 Phillips T and D Woody Millimeter-and submillimeter-wave receivers Annual
Review of Astronomy and Astrophysics 1982 20(1) p 285-321
9 Whitmer HCTaCA Crystal Rectifiers McGraw-Hill book Company
London 1948
10 Young D and J Irvin Millimeter frequency conversion using Au-n-type GaAs
Schottky barrier epitaxial diodes with a novel contacting technique Proceedings
of the Ieee 1965 53(12) p 2130-2131
11 Liu L et al A broadband quasi-optical terahertz detector utilizing a zero bias
Schottky diode IEEE microwave and wireless components letters 2010 20(9) p
504-506
12 Sankaran S Schottky barrier diodes for millimeter wave detection in a foundry
CMOS process IEEE Electron Device Letters 2005 26(7) p 492-494
13 Chattopadhyay G Submillimeter-wave coherent and incoherent sensors for
space applications in Sensors 2008 Springer p 387-414
14 Anand Y and WJ Moroney Microwave mixer and detector diodes
Proceedings of the Ieee 1971 59(8) p 1182-1190
15 Syme RT Microwave Detection Using GaasAlas Tunnel Structures Gec
Journal of Research 1993 11(1) p 12-23
16 Syme RT et al Asymmetric superlattices for microwave detection in Physical
Concepts of Materials for Novel Optoelectronic Device Applications 1991
International Society for Optics and Photonics
17 Missous M MJ Kelly and J Sexton Extremely uniform tunnel barriers for
low-cost device manufacture IEEE Electron Device Letters 2015 36(6) p 543-
545
18 Syme RT et al Novel GaAsAlAs tunnel structures as microwave detectors in
Semiconductors 92 1992 International Society for Optics and Photonics
19 Schwierz F and JJ Liou Semiconductor devices for RF applications evolution
and current status Microelectronics Reliability 2001 41(2) p 145-168
219
20 HayasHi H Development of Compound Semiconductor DevicesmdashIn Search of
Immense Possibilitiesmdash SEI TECHNICAL REVIEW 2011(72) p 5
21 Mead C Schottky barrier gate field effect transistor Proceedings of the Ieee
1966 54(2) p 307-308
22 Hooper W and W Lehrer An epitaxial GaAs field-effect transistor Proceedings
of the Ieee 1967 55(7) p 1237-1238
23 Drangeid K R Sommerhalder and W Walter High-speed gallium-arsenide
Schottky-barrier field-effect transistors Electronics Letters 1970 6(8) p 228-
229
24 Pillarisetty R Academic and industry research progress in germanium
nanodevices Nature 2011 479(7373) p 324-328
25 Oxley TH 50 years development of the microwave mixer for heterodyne
reception IEEE transactions on microwave theory and techniques 2002 50(3)
p 867-876
26 Baca AG and CI Ashby Fabrication of GaAs devices 2005 IET
27 Cho AY and J Arthur Molecular beam epitaxy Progress in solid state
chemistry 1975 10 p 157-191
28 Cho A Growth of IIIndashV semiconductors by molecular beam epitaxy and their
properties Thin Solid Films 1983 100(4) p 291-317
29 Kiehl RA and TG Sollner High speed heterostructure devices 1994
Academic Press
30 Feiginov M et al Resonant-tunnelling-diode oscillators operating at
frequencies above 11 THz Applied Physics Letters 2011 99(23) p 233506
31 Chang LL L Esaki and R Tsu Resonant tunneling in semiconductor double
barriers Applied Physics Letters 1974 24(12) p 593-595
32 Kasjoo SR Novel Electronic Nanodevices Operating in the Terahertz Region
2012
33 Kanaya H et al Structure dependence of oscillation characteristics of
resonant-tunneling-diode terahertz oscillators associated with intrinsic and
extrinsic delay times Japanese Journal of Applied Physics 2015 54(9) p
094103
34 Chattopadhyay G Technology capabilities and performance of low power
terahertz sources IEEE Transactions on Terahertz Science and Technology
2011 1(1) p 33-53
35 Betz A and R Boreiko A practical Schottky mixer for 5 THz in Proceedings of
the 7th International Symposium on Space Terahertz Technology 1996
36 Yu D et al Ultra high-speed 025-spl mum emitter InP-InGaAs SHBTs with
fsub maxof 687 GHz in Electron Devices Meeting 2004 IEDM Technical
Digest IEEE International 2004 IEEE
37 Das MB Optoelectronic detectors and receivers speed and sensitivity limits in
Optoelectronic and Microelectronic Materials Devices 1998 Proceedings 1998
Conference on 1999 IEEE
38 Rodwell MJ et al Submicron scaling of HBTs IEEE Transactions on Electron
Devices 2001 48(11) p 2606-2624
220
39 Bouloukou A and S Missous Novel High-breakdown Low-noise InGaAs-
InA1As Transistors for Radio Astronomy Applications 2006 University of
Manchester
40 Bean J Materials and technologies 1990 John Wiley amp Sons New York p
13
41 Swaminathan V and A Macrander Materials aspects of GaAs and InP based
structures 1991 Prentice-Hall Inc
42 Vurgaftman I J Meyer and L Ram-Mohan Band parameters for IIIndashV
compound semiconductors and their alloys Journal of applied physics 2001
89(11) p 5815-5875
43 Dingle R W Wiegmann and CH Henry Quantum states of confined carriers
in very thin Al x Ga 1minus x As-GaAs-Al x Ga 1minus x As heterostructures Physical
Review Letters 1974 33(14) p 827
44 Sze SM and KK Ng Physics of semiconductor devices 2006 John wiley amp
sons
45 Tyagi MS Introduction to semiconductor materials and devices 2008 John
Wiley amp Sons
46 Schubert E Delta doping of IIIndashV compound semiconductors Fundamentals
and device applications Journal of Vacuum Science amp Technology A Vacuum
Surfaces and Films 1990 8(3) p 2980-2996
47 Rhoderick EH Metal-semiconductor contacts IEE Proceedings I-Solid-State
and Electron Devices 1982 129(1) p 1
48 Piotrowska A A Guivarch and G Pelous Ohmic contacts to IIIndashV compound
semiconductors A review of fabrication techniques Solid-State Electronics
1983 26(3) p 179-197
49 Rideout V A review of the theory and technology for ohmic contacts to group
IIIndashV compound semiconductors Solid-State Electronics 1975 18(6) p 541-
550
50 Baca A et al A survey of ohmic contacts to III-V compound semiconductors
Thin Solid Films 1997 308 p 599-606
51 Higman T et al Structural analysis of AundashNindashGe and AundashAgndashGe alloyed
ohmic contacts on modulation‐doped AlGaAsndashGaAs heterostructures Journal of
applied physics 1986 60(2) p 677-680
52 Chen KJ et al High-performance enhancement-mode InAlAsInGaAs HEMTs
using non-alloyed ohmic contact and Pt-based buried-gate in Indium Phosphide
and Related Materials 1995 Conference Proceedings Seventh International
Conference on 1995 IEEE
53 Berlin L The man behind the microchip Robert Noyce and the invention of
Silicon Valley 2005 Oxford University Press
54 Goodhue W et al Large room‐temperature effects from resonant tunneling
through AlAs barriers Applied Physics Letters 1986 49(17) p 1086-1088
55 Kerr A and Y Anand Schottky diode MM detectors with improved sensitivity
and dynamic range Microwave Journal 1981 24 p 67-71
56 Davies R Simulations of the current-voltage characteristics of semiconductor
tunnel structures Gec Journal of Research 1987 5(2) p 65-75
221
57 Kelly M Tunnel structures and devices over the coming decade Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2291-2293
58 Wilkinson V and M Kelly Manufacturability of quantum semiconductor
devices in High Performance Electron Devices for Microwave and
Optoelectronic Applications 1995 EDMO IEEE 1995 Workshop on 1995
IEEE
59 Wilkinson V M Kelly and M Carr Tunnel devices are not yet
manufacturable Semiconductor Science and Technology 1997 12(1) p 91
60 Eaves L and MJ Kelly The current status of semiconductor tunnelling devices
Philos trans of the Roy soc of London Ser A Math phys and eng sciences
1996 354(1717)
61 Billen K V Wilkinson and M Kelly Manufacturability of heterojunction
tunnel devices further progress Semiconductor Science and Technology 1997
12(7) p 894
62 Kelly M The engineering of quantumndashdot devices Philosophical Transactions
of the Royal Society of London A Mathematical Physical and Engineering
Sciences 2003 361(1803) p 393-401
63 Kelly M New statistical analysis of tunnel diode barriers Semiconductor
Science and Technology 2000 15(1) p 79
64 Hayden R et al Ex situ re-calibration method for low-cost precision epitaxial
growth of heterostructure devices Semiconductor Science and Technology
2002 17(2) p 135
65 Dasmahapatra P et al Thickness control of molecular beam epitaxy grown
layers at the 001ndash01 monolayer level Semiconductor Science and Technology
2012 27(8) p 085007
66 Hayden R M Missous and M Kelly Precision growth for the manufacture of
semiconductor heterostructure devices Semiconductor Science and Technology
2001 16(8) p 676
67 Shao C et al Highly reproducible tunnel currents in MBE-grown
semiconductor multilayers Electronics Letters 2012 48(13) p 792-794
68 Abdullah MR et al GaAsAlAs tunnelling structure Temperature dependence
of ASPAT detectors in Millimeter Waves and THz Technology Workshop
(UCMMT) 2015 8th UK Europe China 2015 IEEE
69 Ariffin KZ et al Asymmetric Spacer Layer Tunnel In0 18Ga0 82AsAlAs
(ASPAT) Diode using double quantum wells for dual functions Detection and
oscillation in Millimeter Waves and THz Technology Workshop (UCMMT)
2015 8th UK Europe China 2015 IEEE
70 Liboff RL Introductory quantum mechanics 2003 Addison-Wesley
71 Esaki L Discovery of the tunnel diode IEEE Transactions on Electron Devices
1976 23(7) p 644-647
72 Landau LD LEM Quantum Mechanics Non-relativistic Theory Pergamon 3
73 Landau LD et al Quantum Mechanics Non‐Relativistic Theory Vol 3 of
Course of Theoretical Physics 1958 AIP
222
74 Syme R Tunnelling devices as microwave mixers and detectors Philosophical
Transactions of the Royal Society of London A Mathematical Physical and
Engineering Sciences 1996 354(1717) p 2351-2364
75 Syme R et al Tunnel diode with asymmetric spacer layers for use as
microwave detector Electronics Letters 1991 27(23) p 2192-2194
76 Brown E W Goodhue and T Sollner Fundamental oscillations up to 200 GHz
in resonant tunneling diodes and new estimates of their maximum oscillation
frequency from stationary‐state tunneling theory Journal of applied physics
1988 64(3) p 1519-1529
77 Reddy M Schottky-collector resonant tunnel diodes for sub-millimeter-wave
applications 1997 University of California Santa Barbara
78 Cox R and H Strack Ohmic contacts for GaAs devices Solid-State Electronics
1967 10(12) p 1213IN71215-1214IN81218
79 Valdes LB Resistivity measurements on germanium for transistors
Proceedings of the IRE 1954 42(2) p 420-427
80 Schroder DK Semiconductor material and device characterization 2006 John
Wiley amp Sons
81 Klootwijk J and C Timmering Merits and Limitations of Circular TLM
structures for contact resistance determination for novel 111-V HBTs Proc
fEEE 2004
82 Marlow GS and MB Das The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance Solid-State
Electronics 1982 25(2) p 91-94
83 Murrmann H and D Widmann Current crowding on metal contacts to planar
devices IEEE Transactions on Electron Devices 1969 16(12) p 1022-1024
84 Berger H Models for contacts to planar devices Solid-State Electronics 1972
15(2) p 145-158
85 Reeves G and H Harrison Obtaining the specific contact resistance from
transmission line model measurements IEEE Electron Device Letters 1982
3(5) p 111-113
86 Shur MS GaAs devices and circuits 2013 Springer Science amp Business
Media
87 Popescu D and B Odbert The Advantages Of Remote Labs In Engineering
Education Educatorrsquos Corner-Agilent Technologies-application note 2011 p
11
88 DataSheet Karl Suss- PM5 Probe System Datasheet 2013
89 Keysight IC-CAP Device Modeling Software 2016 Available from
httpwwwkeysightcomenpc-1297149ic-cap-device-modeling-software-
measurement-control-and-parameter-extractioncc=USamplc=eng
90 DataSheet Anritsu 37369A Vector Network Analyzer Datasheet 2016 Available
from httpwwwtestequipmenthqcomdatasheetsANRITSU-37397D-
Datasheetpdf
91 Packard H HP 4142B Modular DC SourceManual Operation Manual 1992
Available from httpcpliteratureagilentcomlitwebpdf04142-90010pdf
223
92 Microtech C Cascade Microtech- Wincal High Performence RF calaibration
Software (Official Website) 2016 Available from
httpswwwcascademicrotechcom
93 Singh J Electronic and optoelectronic properties of semiconductor structures
2007 Cambridge University Press
94 Whyte W Cleanroom design 1999 Wiley Online Library
95 Vieu C et al Electron beam lithography resolution limits and applications
Applied Surface Science 2000 164(1) p 111-117
96 La Fontaine B Lasers and Moorersquos law SPIE Professional October 2010 p
20
97 Madou MJ Fundamentals of microfabrication the science of miniaturization
2002 CRC press
98 Serway R Physics for Scientists and Engineers 1996 Saunders Publ
Philadelphia
99 Jalali B and S Pearton InP HBTs growth processing and applications 1995
Artech House Publishers
100 Shih YC et al Effects of interfacial microstructure on uniformity and thermal
stability of AuNiGe ohmic contact to n‐type GaAs Journal of applied physics
1987 62(2) p 582-590
101 Zawawi M Advanced In0 8Ga0 2AsAlAs Resonant Tunneling Diodes
forApplications in Integrated mm-waves MMIC Oscillators 2015
102 Zawawi MAM et al Fabrication of Submicrometer InGaAsAlAs Resonant
Tunneling Diode Using a Trilayer Soft Reflow Technique With Excellent
Scalability IEEE Transactions on Electron Devices 2014 61(7) p 2338-2342
103 Silvaco I ATLAS Users Manual Device Simulation Software 2010 Santa
Clara CA
104 Kyono C et al Dependence of apparent barrier height on barrier thickness for
perpendicular transport in AlAsGaAs single‐barrier structures grown by
molecular beam epitaxy Applied Physics Letters 1989 54(6) p 549-551
105 Yang K JR East and GI Haddad Numerical modeling of abrupt
heterojunctions using a thermionic-field emission boundary condition Solid-
State Electronics 1993 36(3) p 321-330
106 Varshni YP Temperature dependence of the energy gap in semiconductors
Physica 1967 34(1) p 149-154
107 Handbook LLM Precision DC Current Voltage and Resistance
Measurements Keithley Instruments Inc[online] 6th revision Ohio 2004
108 Lipsky SE Microwave passive direction finding 2004 SciTech Publishing
109 Howell CM and SJ Parisi Principles Applications and Selection of Receiving
Diodes MACOM Semiconductor Products Division Application note AG314
110 Schulman J D Chow and D Jang InGaAs zero bias backward diodes for
millimeter wave direct detection IEEE Electron Device Letters 2001 22(5) p
200-202
111 Zhang Z et al Sub-Micron Area Heterojunction Backward Diode Millimeter-
Wave Detectors With 018$ rm pWHz^12 $ Noise Equivalent Power IEEE
microwave and wireless components letters 2011 21(5) p 267-269
224
112 Jin N et al High sensitivity Si-based backward diodes for zero-biased square-
law detection and the effect of post-growth annealing on performance IEEE
Electron Device Letters 2005 26(8) p 575-578
113 Shashkin VI et al Millimeter-wave detectors based on antenna-coupled low-
barrier Schottky diodes International journal of infrared and millimeter waves
2007 28(11) p 945-952
114 Zhao P et al GaN Heterostructure Barrier Diodes Exploiting Polarization-
Induced $delta $-Doping IEEE Electron Device Letters 2014 35(6) p 615-
617
115 Pozar DM Microwave engineering 2009 John Wiley amp Sons
116 Koolen M J Geelen and M Versleijen An improved de-embedding technique
for on-wafer high-frequency characterization in Bipolar Circuits and
Technology Meeting 1991 Proceedings of the 1991 1991 IEEE
117 Cao M et al RF characteristics uniformity of GaAsAlAs tunnel diodes in
Infrared Millimeter and Terahertz waves (IRMMW-THz) 2016 41st
International Conference on 2016 IEEE
118 Gao J RF and microwave modeling and measurement techniques for field effect
transistors 2010 SciTec
119 Ren T et al A 340-400 GHz Zero-Biased Waveguide Detector Using an Self-
Consistent Method to Extract the Parameters of Schottky Barrier Diode Applied
Computational Electromagnetics Society Journal 2015 30(12)
120 Fobelets K et al High‐frequency capacitances in resonant interband tunneling
diodes Applied Physics Letters 1994 64(19) p 2523-2525
121 Diebold S et al Modeling and Simulation of Terahertz Resonant Tunneling
Diode-Based Circuits IEEE Transactions on Terahertz Science and Technology
2016 6(5) p 716-723
122 Yong Z et al Design of a 220 GHz frequency tripler based on EM model of
Schottky diodes JOURNAL OF INFRARED AND MILLIMETER WAVES
2014 33(4) p 405-411
123 Louhi JT and AV Raisanen On the modeling and optimization of Schottky
varactor frequency multipliers at submillimeter wavelengths IEEE transactions
on microwave theory and techniques 1995 43(4) p 922-926
124 Guo J Z Zhang and C Qian Modeling of commercial millimeter wave
Schottky diodes in Microwave and Millimeter Wave Technology (ICMMT) 2016
IEEE International Conference on 2016 IEEE
125 Schneider M Metal-semiconductor junctions as frequency converters Infrared
and Millimeter Waves 1982 6 p 209
126 Muth C et al Advanced technology microwave sounder on NPOESS and NPP
in Geoscience and Remote Sensing Symposium 2004 IGARSS04 Proceedings
2004 IEEE International 2004 IEEE
127 Putley E Thermal detectors in Optical and Infrared Detectors 1977 Springer
p 71-100
128 Martin DH Spectroscopic techniques for far infra-red submillimetre and
millimetre waves in Spectroscopic Techniques for Far Infra-red Submillimetre
and Millimetre Waves 1967
225
129 Lucas W Tangential sensitivity of a detector video system with RF
preamplification in Proceedings of the Institution of Electrical Engineers 1966
IET
130 Balocco C et al Low-frequency noise of unipolar nanorectifiers Applied
Physics Letters 2011 99(11) p 113511
131 Benford D T Hunter and TG Phillips Noise equivalent power of background
limited thermal detectors at submillimeter wavelengths International journal of
infrared and millimeter waves 1998 19(7) p 931-938
132 Papoušek D Vibration-rotational Spectroscopy and Molecular Dynamics
Advances in Quantum Chemical and Spectroscopical Studies of Molecular
Structures and Dynamics Vol 9 1997 World Scientific
133 Nyquist H Thermal agitation of electric charge in conductors Physical review
1928 32(1) p 110
134 Turner CS Johnson-Nyquist Noise url httpwww claysturner
comdspJohnson-NyquistNoise pdf(Letzter Abruf Juli 2012)
135 Voss RF 1f (flicker) noise A brief review in 33rd Annual Symposium on
Frequency Control 1979 1979 IEEE
136 McWhorter AL 1f noise and related surface effects in germanium 1955
137 Hooge FN 1ƒ noise is no surface effect Physics letters A 1969 29(3) p 139-
140
138 Van der Ziel A Noise Sources characterization measurement Prentice-Hall
Information and System Sciences Series Englewood Cliffs Prentice-Hall 1970
1970
139 Hooge F 1f noise sources IEEE Transactions on Electron Devices 1994
41(11) p 1926-1935
140 Der Ziel A Theory of shot noise in junction diodes and junction transistors
Proceedings of the IRE 1955 43(11) p 1639-1646
141 Schottky W Small-shot effect and flicker effect Physical review 1926 28(1)
p 74
142 Cowley A and H Sorensen Quantitative comparison of solid-state microwave
detectors IEEE transactions on microwave theory and techniques 1966 14(12)
p 588-602
143 Schulman J et al 1$f $ Noise of Sb-Heterostructure Diodes for Pre-Amplified
Detection IEEE microwave and wireless components letters 2007 17(5) p
355-357
144 Lynch JJ et al Passive millimeter-wave imaging module with preamplified
zero-bias detection IEEE transactions on microwave theory and techniques
2008 56(7) p 1592-1600
145 Su N et al Sb-heterostructure millimeter-wave detectors with reduced
capacitance and noise equivalent power IEEE Electron Device Letters 2008
29(6) p 536-539
146 Westlund A Self-Switching Diodes for Zero-Bias Terahertz Detection 2015
Chalmers University of Technology
147 Yajima T and L Esaki Excess noise in narrow germanium pn junctions
Journal of the physical society of Japan 1958 13(11) p 1281-1287
226
148 Sommers H Tunnel diodes as high-frequency devices Proceedings of the IRE
1959 47(7) p 1201-1206
149 Miraftab V and A Abdipour Harmonic balance analysis of a microwave
balanced power amplifier in Electrical and Computer Engineering 2001
Canadian Conference on 2001 IEEE
150 Patrashin M et al GaAsSbInAlAsInGaAs Tunnel Diodes for Millimeter Wave
Detection in 220ndash330-GHz Band IEEE Transactions on Electron Devices 2015
62(3) p 1068-1071
151 Hesler JL and TW Crowe Responsivity and noise measurements of zero-bias
Schottky diode detectors Proc ISSTT 2007 p 89-92
152 Su N et al Temperature dependence of high frequency and noise performance
of Sb-heterostructure millimeter-wave detectors IEEE Electron Device Letters
2007 28(5) p 336-339
153 Lynch J et al Unamplified direct detection sensor for passive millimeter wave
imaging in Proc of SPIE Vol 2006
154 ZHANG Z et al A physics-based tunneling model for Sb-heterostructure
backward tunnel diode millimeter-wave detectors International Journal of High
Speed Electronics and Systems 2011 20(03) p 589-596
155 Bahl IJ and P Bhartia Microwave solid state circuit design 2003 John Wiley
amp Sons
156 Yeom K-W Microwave Circuit Design A Practical Approach Using ADS
2015 Prentice Hall Press
157 Xie L et al A W-band detector with high tangential signal sensitivity and
voltage sensitivity in Microwave and Millimeter Wave Technology (ICMMT)
2010 International Conference on 2010 IEEE
158 Fay P et al High-performance antimonide-based heterostructure backward
diodes for millimeter-wave detection IEEE Electron Device Letters 2002
23(10) p 585-587
159 Hrobak M et al Planar zero bias Schottky diode detector operating in the E-
and W-band in Microwave Conference (EuMC) 2013 European 2013 IEEE
160 Maas SA Nonlinear microwave and RF circuits 2003 Artech House
161 Appleby R and RN Anderton Millimeter-wave and submillimeter-wave
imaging for security and surveillance Proceedings of the Ieee 2007 95(8) p
1683-1690
162 Crowe TW et al Opening the terahertz window with integrated diode circuits
IEEE Journal of Solid-State Circuits 2005 40(10) p 2104-2110
163 Raisanen AV Frequency multipliers for millimeter and submillimeter
wavelengths Proceedings of the Ieee 1992 80(11) p 1842-1852
164 Erickson NR Diode frequency multipliers for terahertz local-oscillator
applications in Astronomical Telescopes amp Instrumentation 1998 International
Society for Optics and Photonics
165 Mehdi I et al Terahertz local oscillator sources performance and capabilities
in Astronomical Telescopes and Instrumentation 2003 International Society for
Optics and Photonics
166 Tonouchi M Cutting-edge terahertz technology Nature photonics 2007 1(2)
p 97-105
227
167 Nilsen SM et al Single barrier varactors for submillimeter wave power
generation IEEE transactions on microwave theory and techniques 1993 41(4)
p 572-580
168 Xiao Q et al A 270-GHz tuner-less heterostructure barrier varactor frequency
tripler IEEE microwave and wireless components letters 2007 17(4) p 241-
243
169 David T et al Monolithic integrated circuits incorporating InP-based
heterostructure barrier varactors IEEE microwave and wireless components
letters 2002 12(8) p 281-283
170 Lieneweg U B Hancock and J Maserjian Barrier-intrinsic-N+(BIN) diodes
for near-millimeter wave generation in Conference Digest for the Twelft
International Conference on Infrared and Millimeter Waves 1987
171 Lieneweg U et al Modeling of planar varactor frequency multiplier devices
with blocking barriers IEEE transactions on microwave theory and techniques
1992 40(5) p 839-845
172 Chattopadhyay G et al An all-solid-state broad-band frequency multiplier
chain at 1500 GHz IEEE transactions on microwave theory and techniques
2004 52(5) p 1538-1547
173 Maestrini A et al A 17-19 THz local oscillator source IEEE microwave and
wireless components letters 2004 14(6) p 253-255
174 Faber MT J Chramiec and ME Adamski Microwave and millimeter-wave
diode frequency multipliers 1995 Artech House Publishers
175 Frerking MA and JR East Novel heterojunction varactors Proceedings of the
Ieee 1992 80(11) p 1853-1860
176 Penfield P and RP Rafuse Varactor applications 1962
177 Palazzi V et al Low-power frequency doubler in cellulose-based materials for
harmonic RFID applications IEEE microwave and wireless components letters
2014 24(12) p 896-898
178 Presas SM Microwave frequency doubler integrated with miniaturized planar
antennas 2008
228
APPENDICES
Appendix I Doped substrate process details
Mask Stage Process Stage Process step Process detail Equipment
Mask 1 (Mesa
Etch)
Sample clean NMP 10 min 80˚C Beaker
Acetone 5 min Beaker
Isopropanol (IPA) 5 min Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist S1805 - Program 4 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
1 min 09mW iline
(Compensation error set to 1)
MA4 Mask
aligner
Develop MIF 319 for 1 min Beaker
Post Exposure
Bake Oven or Bake 120C for 15
minutes Hotplate
Etch Etch Cal Cal Sample - etch for 2 minutes Beaker
Etch
H3PO4H2O2H2O 3150
time is determined by the etch cal Beaker
Resist Strip Acetone - 5 min and IPA - 5 min Beaker
Mask2 (Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3 Beaker
Acetone ultrasonic for 5 Min Power 3 Beaker
Isopropanol (IPA) ultrasonic for 5 Min Power 3 Beaker
Apply Resist Prebake Bake for 5mins 150C Hotplate
1st Resist AznLoF - 2um grade - Program 6 Laurell Spinner
Post bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Expose
55 seconds 09mW i-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 326 for 1 mins Beaker
Clean O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
Surface De-oxide HCLH2O 11 40 sec Beaker
Metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Anneal 420˚C 2min Furnace
229
TLM
Measurement ICCAP
Measurement
Bench
Mask 3
(BottomBacks
ide Contact)
Sample clean Acetone Optional Beaker
Isopropanol (IPA) Optional Beaker
Apply Resist Prebake
Bake for 5mins 150C to dry
the sample Hotplate
Resist (top side) S1813 - Program 6 Laurell Spinner
Soft bake 110C for 1 Min Hotplate
Photolithography Mask Align mask to wafer
MA4 Mask
aligner
Exposure
10 seconds 09mW I-line
(Compensation error set to 1)
MA4 Mask
aligner
Post Exposure bake 110C for 1 Min Hotplate
Develop MIF 319 for 2 mins Beaker
De-scum O2 Plasma Etch
20sec 100W forward (340)
60mTorr Plasma Tech
De-oxidise
Surface De-oxide
HCLH2O 11 40
sec Beaker
metallisation Evaporation Clean trays + metals Beaker
Load sample and metals
Edward
Evaporator
AuGe (100mg) deposits 55nm
Edward
Evaporator
Ni (1cm) deposits 15nm
Edward
Evaporator
Au (10cm) deposits 200nm
Edward
Evaporator
Lift-off
NMP1165 for 24 hours (25C) or
20 min 80C Beaker
Clean Water 3min Beaker
TLM
Measurement ICCAP
230
Appendix II Four Mask step Process Flow
Mask Stage Process Stage Process step Process detail
Mask1 Top
Contact)
Sample clean NMP ultrasonic for 15 Min Power 3
Acetone ultrasonic for 5 Min Power 3
Isopropanol (IPA) ultrasonic for 5 Min Power 3
Apply Resist Prebake Bake for 5mins 150C
1st Resist AznLoF - 2um grade - Program 6
Hot Plate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 55 seconds 09mW iline (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 1 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
Mask 2 (Mesa
Etch)
Sample clean NMP Optional
Acetone Optional
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C
1st Resist S1805 - Program 4
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 1 min 09mW i-line (Compensation error set
to 1)
Develop MIF 319 for 1 min
Post Exposure Bake Oven or Bake 120C for 15 minutes
Etch Etch Cal Cal Sample - etch for 2 minutes
Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Measure TLM
Resist Strip Acetone - 5 min and IPA - 5 min
Mask 3(Isolation) Sample clean Acetone Optional
Isopropanol (IPA) Optional
231
Apply Resist Prebake Bake for 5mins 150C
Resist S1828 - Program 4
Hot Plate 115C for 1 mins
Photolithography Mask Align mask to wafer
Expose 9 mins 09mW iline (Compensation error set
to 1)
Develop MF 319 3 mins
Post Bake Oven Bake 120C for 15mins
Etch Etch Cal Refer to Etch Cal instr tab
Sub-collector Etch H3PO4H2O2H2O 3150 time is
determined by the etch cal
Resist Strip Acetone 5mins + IPA 5 mins in ultrasonic bath
power 1
inspection Microscope
Sample clean Acetone Optional
Mask 4 (Bottom
Contact)
Isopropanol (IPA) Optional
Apply Resist Prebake Bake for 5mins 150C 1st
Resist AznLoF - 2um grade - Program 6
HotPlate 110C for 1 Min
Photolithography Mask Align mask to wafer
Expose 10 seconds 09mW i-line (Compensation
error set to 1)
Post Exposure bake 110C for 1 Min
Develop MIF 326 for 2 mins
Clean O2 Plasma Etch 20sec 100W forward (340) 60mTorr
Surface De-oxide
HCLH2O 11 40 sec
Metalisation Evaporation Clean trays + metals
Load sample and metals
AuGe (100mg) deposits 55nm
Ni (1cm) deposits 15nm
Au (10cm) deposits 200nm
Lift-off NMP1165 for 24 hours (25C) or 20 mnt 80C
232
Appendix III Epitaxial Layer XMBE277
TABLE I The epitaxial structure for sample XMBE277
Layer Thickness (nm) Doping Concentration (cm-3)
n+- In053Ga047As 45 200 x 1019
n- In053Ga047As 25 300 x 1018
In053Ga047As 20 undoped
AlAs 13 undoped
In08Ga02As 45 undoped
AlAs 13 undoped
In053Ga047As 20 undoped
n- In053Ga047As 25 300 x 1018
n+- In053Ga047As 400 100 x 1019
Semi-insulating InP
233
Appendix IV SilVaco (Atlas) Simulation Code
go atlas
---------------------------------------------------------
Structure parameter definition (Constants) values in um
---------------------------------------------------------
Thicknesses
set t_contact1=0
set t_ohmic1=03
set t_emitter=004
set t_spacer1=0005
set t_barrier=000283
set t_spacer2=02
set t_collector=004
set t_ohmic2=045
Doping concentrations
set d_ohmic1=4e18
set d_emitter=2e17
set d_collector=2e17
set d_ohmic2=4e18
set d_gap=2
set d_mesa=4
set d_device=10
set d_etch=008
Layers
set I=$t_contact1
set A=$I+$t_ohmic1
set B=$A+$t_emitter
set C=$B+$t_spacer1
set D=$C+$t_barrier
set E=$D+$t_spacer2
set F=$E+$t_collector
set G=$F+$t_ohmic2
-------------------------------------
Mesh generator
-------------------------------------
mesh diagflip width=45
xmesh location=0 s=1
xmesh location=1 s=1
xmesh location=2 s=1
xmesh location=4 s=1
xmesh location=5 s=1
xmesh location=6 s=1
xmesh location=7 s=1
xmesh location=8 s=1
xmesh location=$d_mesa s=1
xmesh location=$d_mesa+$d_gap s=1
xmesh location=$d_device s=1
Ohmic1
ymesh l=0000 s=005
ymesh l=$I s=005
234
ymesh l=$A s=0005
ymesh l=$B s=0005
ymesh l=$C s=00005
ymesh l=$D s=00005
ymesh l=$E s=0009
ymesh l=$F s=0005
ymesh l=$G s=0005
-----------------------------------
SECTION 2 Regions Structure definition
-----------------------------------
region num=1 name=contact1 material=Gold ymin=0 ymax=$I
region num=2 name=ohmic1 material=GaAs ymin=$I ymax=$A
region num=3 name=emitter material=GaAs ymin=$A ymax=$B
region num=4 name=spacer1 material=GaAs ymin=$B ymax=$C
region num=5 name=barrier material=AlAs ymin=$C ymax=$D xmin=0 xmax=$d_mesa
calcstrain qtregion=1
region num=6 name=spacer2 material=GaAs ymin=$D ymax=$E
region num=7 name=collector material=GaAs ymin=$E ymax=$F
region num=8 name=ohmic2 material=GaAs ymin=$F ymax=$G
region num=9
name=etch material=Air ymin=0 ymax=$F+$d_etch xmin=$d_mesa xmax=$d
_device
---------------------------------
Electrodes
---------------------------------
electrode num=1 name=anode xmin=0 xmax=$d_mesa ymin=0 ymax
=$I material=Gold
electrode num=2 name=cathode xmin=$d_mesa+$d_gap xmax=$d_device ymin=$F+
$d_etch ymax=$F+$d_etch material=Gold
--------------------------------
Doping
--------------------------------
doping uniform ntype conc=$d_ohmic1 Region=2 ymin=$I ymax=$A
doping uniform ntype conc=$d_emitter Region=3 ymin=$A ymax=$B
doping uniform ntype conc=$d_collector Region=7 ymin=$E ymax=$F
doping uniform ntype conc=$d_ohmic2 Region=8 ymin=$F ymax=$G
--------------------------
Contacts
--------------------------
interface sc region=1
interface ss region=2
interface ss region=3
interface si region=4
interface si region=5
interface ss region=6
interface ss region=7
interface sc ymin=$F ymax=$F xmin=$d_mesa+$d_gap xmax=$d_device
interface tunnel region=5 dytunnel=0001
contact name=cathode
contact name=anode
235
------------------------------------------
SECTION 3 Material amp Models Definitions
------------------------------------------
material material=AlAs
permittivity=10 eg300=28 mc=004 affinity=305 nc300=4e19 nimin=1e1
material material=GaAs permittivity=139 eg300=14 mc=0067
affinity=407 nc300=09e17 nimin=1e6
BAND DIAGRAM
output tquantum bandparam qfn qfp valband conband charge polarcharge flowlines
STRUCTURE GRAPHIC
solve init
save outf=XMBE304+real2str
tonyplot XMBE304+real2str
------------------------------------------
SECTION 4 ANALYSIS
------------------------------------------
trap acceptor structure=top elevel=03 density=48e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$A ymax=$C xmin=0 xmax=$d_mesa
trap acceptor structure=BOTTOM elevel=035 density=47e17 degenfac=10 sign=284e-17 sigp=1e-17
ymin=$E ymax=$F xmin=0 xmax=$d_mesa
models sisel sisnlderivs qtregion=1 print
method climit=1e-4 itlimit=50 maxtraps=20
DC ANALYSIS
log outf=XMBE304log
solve init
solve vanode=0 name=anode vstep=001 vfinal=15
save outf=XMBE304str
log off
tonyplot XMBE304str
tonyplot XMBE304log
