generic ic emc test specification

Generic IC EMC Test Specification

IMPRESSUM

Title: Generic IC EMC Test Specification© ZVEI copyright 2010

Published by: ZVEI - Zentralverband Elektrotechnik und Elektronikindustrie e.V. (ZVEI – German Electrical and Electronic Manufactures' Association) Electronic Components and Systems Devision Lyoner Straße 9 60528 Frankfurt am Main Fon 069 6302-465 Fax 069 6302-407 Mail [email protected] www.zvei.org

Contact in the ZVEI:

Dr. Rolf Winter

Authors:

Joester, Michael Continental Automotive GmbH

Klotz, Dr. Frank Infineon Technologies AG

Pfaff, Dr. Wolfgang Robert BOSCH GmbH

Steinecke, Thomas Infineon Technologies AG

Photo (Cover):

Adam Opel GmbH Infineon Technologies AG

This document may be reproduced according to the copyright and liability chapter free of charge in any format or medium providing it is reproduced accurately and not used in a misleading context. The material must be acknowledged as ZVEI copyright and the title of the document has to be specified. A complimentary copy of the document where ZVEI material is quoted has to be provided.

Every effort was made to ensure that the information given herein is accurate, but no legal responsibility is accepted for any errors, omissions or misleading statements in this information.

The Document and supporting materials can be found on the ZVEI website at: www.zvei.org/ecs under the rubric "Publikationen"

Revision: January 2010

Based on BISS Version 1.2 of November 2007

TABLE OF CONTENT

T A B L E O F C O N T E N T 1. Scope ....................................................................................................................................... 6 2. General and objective ............................................................................................................... 6 3. Normative reference ................................................................................................................. 7 4. Definitions ................................................................................................................................ 8 5. Splitting ICs into IC function modules ...................................................................................... 13

5.1 Matrix for splitting ICs ......................................................................................................... 13 5.2 Example of an IC built up with IC function modules ............................................................. 14

6. Test definitions ....................................................................................................................... 15 6.1 Test methods ..................................................................................................................... 15 6.2 Test parameters ................................................................................................................. 15 6.3 DUT Monitoring .................................................................................................................. 17

7. Test and measurement selection guide ................................................................................... 18 7.1 Workflow for selection and test ........................................................................................... 18

7.1.1 Conducted tests ............................................................................................................ 19 7.1.2 Identification of IC function modules .............................................................................. 19 7.1.3 Pin Selection for Emission and Immunity ........................................................................ 19 7.1.4 IC function module and the coupling or injection points .................................................. 20 7.1.5 Selection guide emission ............................................................................................... 20 7.1.6 Selection guide immunity ............................................................................................... 21

7.2 Radiated tests .................................................................................................................... 22 7.2.1 Criteria for performing radiated Emission and Immunity Tests ........................................ 22 7.2.2 Selection guide emission ............................................................................................... 22 7.2.3 Selection guide immunity ............................................................................................... 22

8. Test and measurement networks ............................................................................................. 23 8.1 Port module ........................................................................................................................ 24

8.1.1 Line Driver .................................................................................................................... 24 8.1.2 Line Receiver ................................................................................................................ 25 8.1.3 Symmetrical Line Driver ................................................................................................. 26 8.1.4 Symmetrical Line Receiver ............................................................................................ 27 8.1.5 Regional Driver ............................................................................................................. 28 8.1.6 Regional Input ............................................................................................................... 29 8.1.7 High Side driver ............................................................................................................ 30 8.1.8 Low Side driver ............................................................................................................. 32

8.2 Supply module ................................................................................................................... 34 8.3 Core module ....................................................................................................................... 35 8.4 Oscillator module ............................................................................................................... 35 8.5 Signal decoupling- and monitoring setup ............................................................................. 36 8.6 Entire IC ............................................................................................................................. 38

9. Functional Configurations and Operating Modes ..................................................................... 39 9.1 Emission test configuration for ICs without CPU .................................................................. 39 9.2 Immunity test configuration for ICs without CPU .................................................................. 41 9.3 Emission test configuration for ICs with CPU ...................................................................... 44

9.3.1 Test initialization software module for cores containing a CPU ....................................... 44 9.3.2 Immunity test configuration for ICs with CPU ................................................................. 47 9.3.3 Test loop software module for cores containing a CPU ................................................... 48

10. Test board ............................................................................................................................ 49

Introduction

Normative References

Definitions

Test and Measurement Selection Guide

Test and Measurement Networks

Functional Configurations and

Operating Modes

Test Board

TABLE OF CONTENT

4

11. “Preliminary” IC EMC limits for Automotive ............................................................................ 50

11.1 Emission .......................................................................................................................... 50 11.1.1 Emission level scheme ................................................................................................ 50 11.1.2 General emission limit classes ..................................................................................... 51 11.1.3 Dedicated emission limits for 'external digital bus systems' .......................................... 53

11.2 Immunity .......................................................................................................................... 54 11.2.1 General immunity limit classes ..................................................................................... 54

12. IC EMC Specification ............................................................................................................ 55 13. Test report ............................................................................................................................ 57 14. Copyrights and Liability ......................................................................................................... 58 15. Contacts and authors ............................................................................................................ 59 Annex A Layout Recommendation, (informative) ......................................................................... 60 Layout Example of 150 Ω networks on 2 layer and multi layer PCB ............................................. 60 Layout Example of 1 Ω network on 2 layer and multi layer PCB .................................................. 60 Layout Example of DPI network on 2 layer and multi layer PCB ................................................... 61 Layout Example of a TEM cell test board .................................................................................... 62 Layout Example for Digital systems built with IC types microcontrollers, RAMs ............................ 63 Annex B Test network modification (emission, normative) ........................................................... 69 Annex C Trace impedance calculation (informative) .................................................................... 71 Annex D Modulation definition (immunity, informative) ................................................................. 73 Annex E Example of an IC EMC specification (general, informative) ............................................ 74 Annex F Calculation of pin specific limits (general, informative) ................................................... 76

IC EMC Test Limits

Testing Documents

Terms of Usage

Annexes

INTRODUCTION

5

Conditions of use

The use of the Generic IC EMC Test Specification is subject to the conditions of use as stated in chapter 14.

By making use of the Generic IC EMC Test Specification the user acknowledges to have taken notice of chapter 14 and to have agreed to the conditions of use stated in chapter 14.

INTRODUCTION

6

1. Scope

The document is the technical basis to define common tests characterising the EMC behaviour of Integrated Circuits (ICs) in terms of RF emission and immunity in the frequency range from 150 kHz to 1GHz. It contains all information to evaluate any kind of ICs in the same way. In this document general information and definitions of IC types, pin types, test and measurement networks, pin selection, operation modes and limit classes are given. This allows the user to create an EMC specification for a dedicated IC as well as to provide comparable results for comparable ICs.

2. General and objective

The objective and benefit of the document is

to obtain relevant quantitative measuring results

to reduce the number of test methods to a necessary minimum

to strengthen the acceptance of IC EMC test results

to minimize test effort to get comparable test results for IC suppliers and users

to release ICs based on IC level results

NORMATIVE REFERENCE

7

3. Normative reference

International IC EMC standards The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.

Emission:

[1] IEC 61967-1 Ed 1: 2002, Integrated circuits Measurement of electromagnetic emissions 150 kHz to 1 GHz – Part 1: General conditions and definitions

[2] IEC 61967-2 Ed 1: 2005, Integrated circuits Measurement of electromagnetic emissions 150 kHz to 1 GHz – Part 2: Measurement of radiated emissions – TEM cell and wideband TEM cell method

[3] IEC 61967-4 Ed 1: 2002, Integrated circuits Measurement of electromagnetic emissions 150 kHz to 1 GHz – Part 4: Measurement of conducted emissions - 1 Ω/150 Ω direct coupling method

IEC 61967-4/A1/Ed 1: 2006, Amendment 1 to IEC 61967-4: Integrated circuits – Measurement of electromagnetic emission, 150 kHz to 1 GHz - Part 4: Measurement of conducted emissions – 1 Ohm/150 Ohm direct coupling method

[4] CISPR 25: Limits and methods of measurement of radio disturbance characteristics for the protection of receivers used on board vehicles – second edition 2002-08

[10] IEC 61967-4-1/TR/Ed 1: APPLICATION GUIDANCE TO IEC 61967-4, Integrated circuits - Measurement of electromagnetic emissions, 150 kHz to 1 GHz - Part 4: Measurement of conducted emissions - 1 Ohm/150 Ohm direct coupling method

Immunity:

[5] IEC 62132-1 Ed 1: 2006, Integrated circuits Measurement of electromagnetic immunity 150 kHz to 1 GHz – Part 1: General and definitions

[6]* IEC 62132-2 (47A/774/CD), Integrated circuits Measurement of electromagnetic immunity 150 kHz to 1 GHz – Part 2: Measurement of radiated immunity - TEM Cell and Wide Band TEM Cell Method

[7] IEC 62132-4 Ed. 1: 2006, Integrated circuits Measurement of electromagnetic immunity 150 kHz to 1 GHz – Part 4: Direct RF Power Injection Method

Other relevant documents

[8] IEC/TS 62228 Ed 1: 2007: Integrated circuits - EMC evaluation of CAN transceivers

[9]*** LIN EMC Test Specification, Version V1.0 (01.08.2004)

*) Working draft within IEC SC47A WG9 ***) Working draft within German national working group DKE 767.13.5

DEFINIT IONS

8

4. Definitions

• analog

"Pertaining to the representation of information by means of a physical quantity which may at any instant within a continuous time interval assume any value within a continuous interval of values. Note. - The quantity considered may, for example, follow continuously the values of another physical quantity representing information."

[IEV 101-12-05]

• Core

An →IC function module without any connection to outside of the IC via pins. (Note: The supply is connected via the IC function module supply to pins, signals to pins are connected via IC function module driver)

• digital

"Pertaining to the representation of information by distinct states or discrete values."

[IEV 101-12-07]

• EMC pin type

global pin

A 'global' pin carries a signal or power, which enters or leaves the application board

local pin

A 'local' pin carries a signal or power, which does not leave the application board. It remains on the application PCB as a signal between two components with or without additional EMC components.

• Fixed Function Unit (FFU)

Functional core sub-unit of the →IC function module 'Core', designed to perform one fixed function without instruction decoding and executing capability.

• IC type

IC with a characteristic set of functions built in. These functions are realized with →IC function modules.

DEFINIT IONS

9

• IC function module

An IC function module is a device functional part of an IC with at least one function and its supply connection, if needed.

Passive IC function module: No supply system for function

Active IC function module: A dedicated supply connection needed for function.

Note: The supply connection is handled as a separate input/output pair as it has a dedicated EMC behavior.

• Integrated Circuit (IC)

An integrated circuit (IC) is a set of implemented →IC function modules in one die or package.

• Pin

is an interface between an IC and its circuit environment.

• Port

An →IC function module containing minimum one Driver and/or minimum one Input each connected to a signal pin.

• Active port:

An active port is initialized to a defined configuration or connected to a →fixed-function module unit and is in operating mode during EMC measurements.

• Inactive port:

An inactive port is initialized to a defined configuration or connected to a →fixed-function module unit and remains in a defined static mode.

• Test port:

A port selected for IC EMC tests.

• Printed Circuit Board (PCB):

A piece of isolating material with fixed metal traces to connect electronic components.

• Supply pin pairs

Supply pin pairs are all supply voltage pins of the same supply voltage system with their related ground pin(s) of an IC supply module.

supply connection

supply referenceconnection

inputs outputsIC FunctionModule

Figure 1, Common definition of an IC function module

DEFINIT IONS

10

IC function modules Port module

It is a set of minimum one port module 'Driver' and/or minimum one port module ´Input´.

Port modules are:

a) Line Driver

drives signals leaving the application board (global pin).

Examples: ISO9141 outputs, LIN outputs

b) Line Receiver

receives signals from outside of the application board (global pin).

Examples: ISO9141 inputs, LIN inputs

c) Symmetrical Line Driver

drives differential signals leaving the application board with two phase-correlated outputs (global pin)

Examples: CAN outputs, LVDS outputs

d) Symmetrical Line Receiver

receives differential signals from outside of the application board with two phase-correlated inputs (global pin)

Examples: CAN inputs, LVDS inputs

e) Regional Driver

drives signals not leaving the application board (local pin).

Examples: serial data outputs, operational amplifier outputs

f) Regional Input

receives signals from the application board (local pin).

Examples: serial data inputs, Input stages of operational amplifiers, Analog-Digital-Converter (ADC) inputs

g) High Side driver

drives power into loads. The current flows out of the driver (local or global pin).

Examples: High side switch, Switched mode power supply current output (buck converter)

h) Low Side driver

drives power into loads. The current flows into the driver (local or global pin).

Supply module

CoreSupply

Core

PortSupply module

PortSupply

Driver orInput

Driver orInput

Driver orInput

Driver orInput

Digital Logicor analogFixed-function Unit




Oscillator(PLL)

Supply module

OscillatorSupply

PLL factor

DEFINIT IONS

11

Examples: Low side switch, Switched mode power supply current input (boost converter)

Supply module

distributes supply current to at least one IC function module (local or global pin).

It is an IC function module with at least one current input pin of same supply system and minimum one current output pin. It may contain active elements like voltage stabilization and/or passive elements like internal charge buffering, current limiting elements etc.

Core module

It is an IC function module without any connection to outside of the IC via pins. The core is supplied via the IC function module supply. It contains a set of minimum one core module described below.

Core modules are:

a) Central Processing Unit (CPU)

A CPU decodes and executes instructions, can make decisions and jump to a new set of instructions based on those decisions.

Sub-units within the CPU decode and execute instructions (Sub-Unit CU (Control Unit)) and perform arithmetic and logical operations (Sub-Unit ALU (Arithmetic/Logic Unit)), making use of small number-holding areas called registers.

b) Digital Logic Fixed-Function Unit

Functional core sub-unit, designed to perform one fixed core digital logic function without instruction decode and execute capability.

Examples: Clock distribution, Memory logic and arrays, Registers, Timer, Watchdog Timer, State Machines, Programmable Logic Arrays (PLA).

Supply module

CoreSupply

Supply module

PortSupply

Driver orInput

Driver orInput

Driver orInput

Driver orInput





Oscillator(PLL)

Supply module

OscillatorSupply

PLL factor

Supply module

CoreSupply

Core

Supply module

PortSupply

Driver orInput

Driver orInput

Driver orInput

Driver orInput





Oscillator(PLL)

Supply module

OscillatorSupply

PLL factor

DEFINIT IONS

12

c) Analog Fixed-Function Unit

Functional core analog sub-unit, clocked or unclocked, designed to perform one fixed core analog function without instruction decode and execute capability.

Examples: Analog-to-digital-converter (ADC), Digital-to-analog-converter (DAC), Sample-and-hold-circuits, Switched capacitor filter, Charge Coupled Devices (CCDs).

Dedicated Analog Fixed Function Unit: Sensor element

A sensor element is a converter of an environmental value into an electrical value and therefore a FFU.

Examples: Hall sensor element for magnetic field sensing, E-field sensing, Acceleration sensing. It can be combined with a precision amplifier (FFU), a supply module and a line driver to realize an IC type "sensor".

Oscillator module

generates a periodic signal internally as a charge pump or clock generator by using a combination of a fixed function module of the core with regional drivers and regional inputs. Due to the EMC behaviour it is dedicated to be defined as a separate IC function module.

A fixed-frequency-oscillator may be part of a Phase Locked Loop (PLL) circuit with Voltage Controlled Oscillator (VCO), Low pass filter, Frequency Divider and Phase Detection. All pins related to these circuits (for example divider, digital logic input pins) are part of this IC function module.

Supply module

CoreSupply

Core

Supply module

PortSupply

Driver orInput

Driver orInput

Driver orInput

Driver orInput





Oscillator(PLL)

Supply module

OscillatorSupply

PLL factor

SPLITTING ICS INTO IC FUNCTION MODULES

13

5. Splitting ICs into IC function modules

5.1 Matrix for splitting ICs Functional module

supply connection

supply referenceconnection

inputs outputsIC FunctionModule

IC type examples

connection external circuit via pin no pin local external circuits

Driver (Outputs) Inputs Supplies Core Core/Inputs Li

ne D

river

Sym

met

rical

Lin

e D

river

Reg

iona

l Sig

nal D

river

Hig

h Si

de D

river

Low

Sid

e D

river

Line

Rec

eive

r

Sym

met

rical

Lin

e R

ecei

ver

Reg

iona

l Inp

ut

All I

C F

unct

ion

Mod

ule

Supp

lies

Dig

ital F

ixed

Func

tion

Uni

t

Anal

og F

ixed

Fun

ctio

n U

nit

Cen

tral P

roce

ssin

g U

nit (

CPU

)

Osc

illato

r

Dig

ital I

Cs Microcontrollers • • • • • • •

RAM, ROM, Bus Drivers • • • •

Logic Gate ICs • • • •

Anal

og IC

s Operational Amplifier (•) (•) • • • •

VCOs • • • • • Sensor Circuit • (•) (•) • •

Pow

er d

river

High Side Switch (•) • • • • (•) (•)

Low Side Switch (•) • • • • (•)

Bridge (•) • • • • • (•) (•)

Inte

rface

driv

er

symmetrical communication

(e.g. CAN, LVDS)

• • • • • • (•) (•)

asymmetrical communication (e.g. LIN, Single

Wire CAN)

• • • • • • (•) (•)

voltage regulator, linear (•) • • (•) • (•) (•)

voltage regulator, switch mode (•) • (•) • (•) • (•) (•) (•)

ASICs any combination

• = typical configuration (•) = additional or alternative configuration

Table 1: Matrix showing which typical IC function module is integrated in several well known IC’s.

SPLITTING ICS INTO IC FUNCTION MODULES

14

5.2 Example of an IC built up with IC function modules

Cor

e

Supply Module

I/OSupply

Supply Module

I/OSupply

Data/AdressRegisters

Digital LogicFixed Function Unit:

ClockDistribution

DATABus

ADDRESSBus

Supply Module

I/OSupply

Sele

ctio

nSi

gnal

s

Clockinput

Address selection logic

Supply Module

ProgramVoltageSupply

AnalogFixed Function Unit:

Step upConverter

Supply Module

CoreSupply

Flash MemoryProgramming

Flash / EPROM Type of memory

Memory (RAM/ROM) Arrays

ReginalInput





Port Module

ReginalInput

Port Module

RegionalDriver

Port Module

ReginalInput

Port Module

Port

Port

ReginalInput

Port Module

Figure 2, Example of a Memory IC built up with the IC function modules

TEST DEFINIT IONS

15

6. Test definitions

6.1 Test methods Conducted test methods

The conducted tests have to be performed for all ICs.

Test type Coupling Method Method name Reference Conducted Emission Direct coupling via 150 Ω / 1 Ω network 150 Ω / 1 Ω

method IEC61967-4

Conducted Immunity

Direct RF-power injection via DC block capacitor

Direct Power Injection (DPI) IEC62132-4

Table 2: Conducted test methods Radiated test methods

The radiated tests have to be performed only for dedicated ICs.

Test type Coupling Method Method name Reference Radiated Emission E- and H-field radiation of entire IC TEM-cell

method IEC61967-2

Radiated Immunity E- and H-field radiation on entire IC TEM-cell

method IEC62132-2

Table 3: Radiated test methods

6.2 Test parameters Test conditions

Environment: Temperature 23°C +/-5°C

Supply: nominal Voltage +/- 5%

Emission bandwidths and frequency step sizes related to frequency ranges For all measurements the noise floor must be minimum 6dB below the limit.

Method Frequency range Receiver Analyzer BW Step size RBW Sweep time**

1 Ω

150 Ω

TEM

150 kHz to 30 MHz 9 kHz 5 kHz 9/10kHz

RBWFRLTNPts

⋅⋅=

30 MHz to 200 MHz

120 kHz*** 60 kHz 100/120kHz*** * 200 MHz to 1000 MHz

*) Note: Upper frequency range of 1 Ω method is critical to handle, see layout recommendations **) Note: NP=Number of Points; LT=Loop time or minimum period; FR=Frequency range ***) Note: Instead of 120 kHz / 100 kHz a bandwidth of 10 kHz / 9 kHz (with appropriate step size) can be used to reduce the

noise level in case of no difference of the disturbances.

Table 4: General test parameters: Emission Detector type: Peak detector

Measurement time: The emission measurement time at one frequency shall be minimal the period or test software loop duration.

TEST DEFINIT IONS

16

Immunity test parameters to perform immunity tests Frequency step sizes: Frequency step sizes related to frequency ranges are shown in

Table 5. Critical frequencies such as clock frequencies, system frequencies of RF devices etc. should be tested using smaller frequency steps agreed by the users of this procedure. Deviations have to be stated in the test report.

Method Frequency range Step size linear

DPI

TEM

150 kHz to 1 MHz 100 kHz 1 MHz to 10 MHz 0.5 MHz

10 MHz to 100 MHz 1MHz 100 MHz to 200 MHz 2MHz 200 MHz to 400 MHz 4MHz 400 MHz to 1000 MHz 10MHz

Table 5: General test parameters: Immunity Dwell time: The dwell time at each frequency should be minimal 1000 ms. If shorter or longer dwell times are used, the deviation has to be stated in the test report

DPI Immunity characteristic: The immunity diagram shows maximum RF forward power without any monitored failure measured with increasing power up to the required limit.

TEM Immunity characteristic: The immunity diagram shows maximum field strength calculated from the forward power (substitution method) without any monitored failures measured with increasing field strength up to the required limit.

Modulation definition: Continuous Wave (CW) is mandatory.

An Amplitude Modulation (AM) test is optional and has to be performed only on special request. Parameters: 1 kHz, 80%, according ISO automotive specifications: reduced carrier for same peak CW and AM (see Annex D).

same peak value

reduced carriercarrierAM = carrierCW / 1.8

AM 80 %reducedcarrier

am_mod_reduced_carrier.xls

CW

Figure 3: General test parameters: Immunity, definition of AM modulation

carrier

TEST DEFINIT IONS

17

6.3 DUT Monitoring The pins to be monitored shall be specified in the dedicated IC EMC test specification.

Generally, all DUT functions, which are decided to be monitored, have to be checked. For conducted immunity the DUT functions can be monitored direct or indirect at output ports. For radiated immunity tests the distinction between direct and indirect monitoring is not possible. All monitored signals shall be within the failure criteria of the IC EMC test specification.

Direct monitoring: The signal of the functional module at the injection point where the RF power is applied is monitored.

Indirect monitoring: The signal of another functional module output port where the RF power is not directly applied is monitored.

RF decoupling: RF filter are necessary to prevent the monitoring device from the disturbance RF.

Monitoring device: The monitoring can be realized e.g. by a microcontroller (µC) test application with a cycling test program, an oscilloscope with a programmable signal tolerance mask, a multimeter.

An example how the monitored signals can be combined to a logical sum "within specification or out of specification” is shown in Figure 4

Failure criteria: For monitored signals failure criteria have to be defined in the dedicated IC EMC test specification. A failure criterion is defined by its nominal signal values and allowed tolerances. An example of a failure criteria table with typical signals is shown in Table 6.

Inje

ctio

n Po

int Monitored pin Failure criteria

Analogue output 2.5 Volts ± 0.2V

'Status' output digital signal '1'

… …

Table 6: Example of a failure criteria table

functionoutput signal

function



DUT

DUT within spec.

orone or more functionsout of spec.

failure criteria

indirec t monitoring

direct monitoring

RF decoupling

RF decoupling

RF decoupling

Monitoring device

pass fail

pass fail

pass fail

RF injection

ORfunction

function

Figure 4: DUT monitoring for immunity tests

TEST AND MEASUREMENT GUIDE

18

7. Test and measurement selection guide

7.1 Workflow for selection and test The following workflow shows in sequential order the steps required to generate a dedicated IC EMC specification and to perform the EMC measurements. A template of the IC EMC specification is provided in Chapter 12.

EMC Specification

Identification of all IC function modules and selection of the EMC relevant modules (as defined in chapter 5)

Listing of all related pins and classification in local and global pins

(as defined in chapter 5)

Selection of pins to be measured (7.1.1) and monitored (6.3)

Selection of functional configuration, operation mode and software requirements


Selection of test- and measurement networks


Add radiated test methods, if criteria are met (see chapter 7.2)

selection of the test limits and monitoring definition

(as defined in chapter 11 and 6.3)

EMC - Test

Design of test schematic and board layout (see chapter 10)

Performing measurements according EMC specification (see chapter 7, 12)

Test Report (see chapter 13)

Figure 5: Workflow to perform IC EMC measurements


19

7.1.1 Conducted tests The pin, test and measurement selection guide for conducted tests describes typical selection criteria for the coupling and injection points to be tested, the configurations and the operating functions of the IC under test for the characterization of its EMC behavior (relevant pins). The dedicated selection, configuration and function have to be defined by the typical application of the IC or by a dedicated IC EMC test specification.

7.1.2 Identification of IC function modules To define the relevant IC function modules influencing the EMC behavior of an IC significantly all integrated functions have to be classified according to the definitions in Chapter 6.

7.1.3 Pin Selection for Emission and Immunity If an IC function module has a related IC pin it has to be checked if this pin is relevant for the EMC behavior of the IC application according the following selection criteria. The classifications of IC function modules and pins have to be listed.

Port modules

All global pins have to be measured.

At a global driver pins the emission and immunity of the direct pin function, the crosstalk behavior pin to core and the crosstalk behavior port to pin can be measured.

At a global receiver pin only the crosstalk core to pin and port to pin can be measured.

Local pin measurements are not mandatory.

Local pin measurements are optional and should be performed only on special request or if no pin could be defined as a global pin for measurements.

Supply modules

All supply pins have to be measured.

Core modules

The core cannot be measured directly only by crosstalk at global or local pins.

Oscillator modules

The emission of the oscillator should be measured only by crosstalk at global or local pins.

Immunity measurements can be performed optional directly at the oscillator.


20

7.1.4 IC function module and the coupling or injection points

IC function module Coupling and injection point Port Pin Supply Pin Core Oscillator (Pin)

Port module • • Supply module • Core module • •

Oscillator module • • (•)

Table 7: Conducted tests: Coupling and injection points

7.1.5 Selection guide emission The following table provides the necessary details to apply the selection part of the workflow for a dedicated IC. It starts with the selection of function modules with the related pin types, defines the measurement networks to be connected and it shows the operation modes and the expected coupling mechanisms in order to select the correct functional configuration and software if necessary.

Coupling point Coupling mechanism Functional Configuration

Direct Indirect Without CPU (see chapter 9.1)

With CPU (see chapter 9.3)

IC function module

Pin type

Measurement network (see chapter 8)

Operation mode *

Functional signal

Crosstalk core module to

Crosstalk port module to

Crosstalk oscillator module to

Port module

Core module

Oscillator module

Port module

Core module

Oscillator

Line Driver global 8.1.1 T • PM1 C1-S3 H • CM1 C4-S2 H • OM1 C6-S0

Line Receiver global 8.1.2 IA (•) CM1 C4-S2

Sym. Line Driver global 8.1.3 T • PM3 C1-S3 IA • CM1 C4-S2 IA • OM1 C6-S0

Sym. Line Receiver global 8.1.4 IA (•) CM1 C4-S2

Regional Driver local

8.1.5 A T • PM5 C1-S3 H, L • CM1 C4-S2 H, L • OM1 C6-S0

8.1.5 B H, L • PM5 C1-S2 C1-S3

Regional Input local 8.1.6 IA (•) CM1 C4-S2

High Side Driver local, global 8.1.7

T • PM7 C1-S3 H • CM1 C4-S2 H • OM1 C6-S0

Low Side Driver local, global 8.1.8

T • PM8 C1-S3 H • CM1 C4-S2 H • OM1 C6-S0

Supply local, global 8.2

H • SM1 C1-S3 H • CM1 C4-S2 H • OM1 C6-S0

* Note: T = Toggle; H = static high potential, L = static low potential IA = defined inactive, realized with internal or external pull up or pull down (•) = Test is optional

Table 8: Selection guide emission


21

7.1.6 Selection guide immunity The following table provides the necessary details to apply the selection part of the workflow for a dedicated IC. It starts with the selection of function modules with the related pin types, defines the measurement networks to be connected and it shows the operation modes in order to select the correct functional configuration, the software if necessary and the kind of monitoring.

Injection point

Functional configuration

Kind of monitoring without CPU

(see chapter 9.2)

with

CPU

(see c

hapte

r 9.3)

IC fu

nctio

n mod

ule

Pin t

ype

Test

netw

ork

(see c

hapte

r 8)

Oper

ation

mod

e*

Port

modu

le

Core

mod

ule

Oscil

lator

mod

ule

Port-

, Cor

e-, O

scilla

tor

modu

les

Dire

ct

Indire

ct

Line Driver global 8.1.1 T PM9 CM2 OM2 C10-S3 • • H PM9 CM2 OM2 C10-S3 • • IA CM3 • •

Line Receiver global 8.1.2 A PM10 CM2 OM2 C10-S3 • IA CM3 • •

Sym. Line Driver global 8.1.3 T PM11 CM2 OM2 C10-S3 • • IA PM11 CM2 OM2 C10-S3 • • IA CM3 • •

Sym. Line Receiver global 8.1.4 A PM12 CM2 OM2 C10-S3 • • IA CM3 • •

Regional Driver local 8.1.5 A

T PM13 CM2 OM2 C10-S3 • • (H) PM13 CM2 OM2 C10-S3 • • (L) PM13 CM2 OM2 • • IA CM3 • •

Regional Input local 8.1.6 A PM14 CM2 OM2 C10-S3 • • IA CM3 • •

High Side Driver local, global 8.1.7

T PM15 CM2 OM2 C10-S3 • • (H) PM15 CM2 OM2 C10-S3 • • (L) PM15 CM2 OM2 C10-S3 • • IA CM3 • •

Low Side Driver local, global 8.1.8

T PM16 CM2 OM2 C10-S3 • • (H) PM16 CM2 OM2 C10-S3 • • (L) PM16 CM2 OM2 C10-S3 • • IA CM3 • •

Supply local, global 8.2 H SM2 CM2 OM2 C10-S3 • •

H SM2 CM3 • • Oscillator local 8.4 T PM9 CM2 C10-S3 • •

* Note: T = Toggle; H = static high potential, L = static low potential A = defined active; IA = defined inactive, realized with internal or external pull up or pull down ( ) = Test is optional

Table 9, Selection guide immunity


22

7.2 Radiated tests

7.2.1 Criteria for performing radiated Emission and Immunity Tests Emission:

• the IC has a CPU, or

• the IC has a digital logic FFU or an oscillator module with an operating frequency higher than 10MHz and a package diagonal dimension greater than 25mm

Immunity:

• the IC has an analogue FFU as sensing element working with electrical or magnetic fields, or

• the IC has an analogue or digital FFU with charge coupled devices (CCD) for filtering

7.2.2 Selection guide emission

Coupling structure Test setup Functional configuration without CPU with CPU

entire IC chapter 8.6 CM1 C1-S2

Table 10, Selection guide emission

7.2.3 Selection guide immunity

Injection structure Test setup Functional configuration without CPU with CPU

entire IC chapter 8.6 CM2 C10-S3 CM3 C11-S3

Table 11, Selection guide immunity

TEST AND MEASURMENT NETWORKS

23

8. Test and measurement networks

This chapter describes the coupling, injection and monitoring networks for the emission measurements and immunity tests. All pins not used for emission measurement, immunity test or monitoring have to be set in a defined state and configuration according to the IC data sheet and documented in the test report. The electrical characteristics (power dissipation, voltage, current, frequency properties) of the passive components on the test PCB have to meet the functional and RF requirements.


24

8.1 Port module

8.1.1 Line Driver For line drivers type LIN refer to specification 'EMC-Evaluation of LIN-Transceivers' [9]

IC

Lin

e D

rive

r

Cor

e

R2

(Ztrace = 50 Ω)

C1

R1

© 2007 BISS

Configuration A: Single Line Driver port

IC

Lin

e D

rive

r

Cor

e

RA1

R2

(Ztrace = 50 Ω)

CB1

RA2

RAn

CB2

CBn

© 2007 BISS

Configuration B: Multiple Line Driver port*

*) Use circuit B, if more than one driver should be tested simultaneously (means: all driver are active) of a multiple Line Driver port.

Emission setup component variation R1 120 Ω R2 51 Ω C1 6.8 nF or less as max. load capacitance according IC data sheet RA1= RA2=..=RAn

nRA ⋅Ω=± 120%5 n = number of Line Drivers Select a resistor according resistor standard set within tolerance of 5%

CB1= CB2=..= CBn

nCCB 1

%5 =± n = number of Line Drivers

Select a capacitor according capacitor standard set within tolerance of 5%

Immunity setup component variation R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2 open C1 6.8 nF or less as max. load capacitance according IC data sheet RA1= RA2=..=RAn

nRRA ⋅=± 1%5 n = number of Line Drivers Select a resistor according resistor standard set within tolerance of 5%

CB1= CB2=..= CBn

nCCB 1



Table 12: Emission and immunity setup for IC module line driver


25

8.1.2 Line Receiver For line receivers type LIN refer to specification 'EMC-Evaluation of LIN-Transceivers' [9]

C

Cor

e

Cdd

Lin

e R

ecei

ver

Zdd

R1

R2

C2

(Ztrace = 50 Ω)

Decoupling Device

Inpu

t Sig

nal

© 2007 BISS

Configuration A: Single Line Receiver port

IC

Lin

e R

ecei

ver

Cor

e

RA1

R2

(Ztrace = 50 Ω)

CB1

RA2

RAn

CB2

CBn

© 2007 BISS

Configuration B: Multiple Line Receiver port*

*) Use circuit B, if more than one driver are tested simultaneously of a multiple Line Receiver port.

Emission setup component variation For receiver ports emission tests are not mandatory

Immunity setup component variation R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2 open C1 6.8 nF or less as max. load capacitance according IC data sheet Zdd > 400 Ω Cdd 10 nF or acc. max. frequency of input signal RA1= RA2=..=RAn

nRA ⋅Ω=± 120%5 n = number of Line Drivers Select a resistor according resistor standard set within tolerance of 5%

CB1= CB2=..= CBn

nC

CB1



Table 13: Immunity setup for IC module line receiver


26

8.1.3 Symmetrical Line Driver For symmetrical line drivers type CAN refer to specification 'EMC-Evaluation of CAN-Transceivers' [8]

IC

Sym

met

rica

l L

ine

Dri

ver

Cor

e

(Ztrace = 50 Ω)

CB

CB

RA

RARB

R2

© 2007 BISS

Setup component variation

Item Value Bus system type with separate termination1 with termination

RB acc. Bus specification open •

Emission setup component variation RA 240 Ω Note: : the resistors shall be matched with tolerance better than 0.1% R2 51 Ω

CB 6.8 nF or max. load capacitance according IC data sheet Note: the capacitors shall be matched with tolerance better than 1%

Immunity setup component variation

RA 0 Ω as default, up to 100 Ω for load current limitation according data sheet Note: the resistors shall be matched with tolerance better than 0.1%

R2 open

CB 6.8 nF or less as max. load capacitance according IC data sheet Note: the capacitors shall be matched with tolerance better than 1%

Table 14: Emission and immunity setup for IC module symmetrical line driver

1 Termination not part of the test network, but may be needed for the symmetrical line driver


27

8.1.4 Symmetrical Line Receiver For symmetrical line receivers type CAN refer to specification 'EMC-Evaluation of CAN-Transceivers' [8]

IC

Sym

met

rica

l L

ine

Rec

eive

r

Cor

e

(Ztrace = 50 Ω)

CB

CB

RA

RARB

R2

© 2007 BISS


Item Value Bus system type with separate termination2 with termination

RB acc. Bus specification open •

Emission setup component variation For symmetrical line receiver ports emission tests are not mandatory


RA 0 Ω as default, up to 100 Ω for load current limitation according data sheet Note: the resistors shall be matched with tolerance better than 0.1%

R2 open

CB 6.8 nF or less as max. load capacitance according IC data sheet Note: the capacitors shall be matched with tolerance better than 1%

Table 15: Immunity setup for IC module symmetrical line driver

2 Termination not part of the test network, but may be needed for the symmetrical line receiver


28

8.1.5 Regional Driver R

egio

nal D

rive

r

Cor

e

R1

R2

(Ztrace = 50 Ω)

C1

Vcc

RPullup

1 Ω

1 Ω Probe 2

49 Ω

1RPulldown

© 2007 BISS

IC

Cor

e R1

R2

C1

CLOAD

RPullup/PulldownVDD/ GND

R3

R4

(Ztrace = 50 Ω)

Reg

iona

l Por

ts

C2

(Ztrace = 50 Ω)VDD/ GND

VDD/ GND

Z=f(Cload, RPullup/Pulldown) © 2007 BISS

Configuration A Configuration B: Set up for Crosstalk measurement pin to pin

General setup component variation

RPullup

Digital signal: according IC data sheet (typical value), if it is needed for external pull up (default 3300 Ω)

Analog signal: signal connection to functional required circuit RPulldown according IC data sheet (typical value) Cload max. load capacitance according IC data sheet or Z=f(Cload, RPullup/Pulldown)

real loads (e.g. memory) or passive substitution networks according IC data or application sheet

Emission setup component R1 120 Ω R2 51 Ω C1 6.8 nF or less as max. load capacitance according IC data sheet Test network

1 RPullup-down ≤ 30 Ω or DC mode 2 RPullup-down > 30 Ω

Immunity setup component

R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2 open C1 6.8 nF or less as max. load capacitance according IC data sheet

Table 16: Emission and immunity setup for IC module regional driver


29

8.1.6 Regional Input

IC

Cor

e

Cdd

Reg

iona

l Inp

ut

Zdd

R1

R2

C2

(Ztrace = 50 Ω)

Decoupling Device

Inpu

t Sig

nal

© 2007 BISS

Emission setup component variation For input ports emission tests are not mandatory


R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet C1 6.8 nF or less as max. load capacitance according IC data sheet) Zdd > 400 Ω Cdd 10 nF or acc. max. frequency of input signal

Table 17: Immunity setup for IC module regional input


30

8.1.7 High Side driver • Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the

load impedance are decoupled by a 5 µH coil (LBAN), to get results independent from the load impedance.

• Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a 5 µH coil (LBAN) and a 150 Ω matching network (RBAN , CBAN) for impedance fixing is added.

reference

outputIC

Hig

h Si

de D

rive

r

Cor

e

R1

R2

(Ztrace = 150 Ω)

(Ztrace = 50 Ω)

C1

LBAN

C2

RLoad

supply

1

RBAN

CBAN

© 2007 BISS Configuration high side driver / linear voltage regulator

reference

outputIC

Hig

h Si

de D

rive

r

Cor

e

R1

R2

(Ztrace = 150 Ω)

(Ztrace = 50 Ω)

C1

LBAN

C2

RLoad

D1

supply

1

1 Ω

1 Ω Probe 2

L1

Decoupling and coupling network decoupling network

49 Ω

1 2

RBAN

CBAN

© 2007 BISS

Configuration switched mode power supply


31

General setup component variation

Item Value Circuit type

high side driver linear voltage regulator

switched mode power supply (Buck converter)

LBAN 5 µH independent of load current (no saturation effects) L1 acc. IC data sheet shorted shorted • D1 acc. IC data sheet open open • C2 acc. IC data sheet open • •

RLoad According Imes* Conthmes RR

TI°⋅

∆=

150,

(∆T = 65 K, Imes ≤ 10 A) Imes = 80% of Inom Imes = 80% of Inom

*) The IC dissipation power Pdissipation is basically limited by Rth of the housing and the maximum temperature Tmax of the semiconductor at a maximum ambient temperature Tamb according data sheet. With the definitions Tmax = 150°C at Tamp = 85°C a ∆T = 65K is given. The typical dissipation power is additionally given by Ron,150*C and a typical load current ILoad:

ConLoadndissipatio RIP °⋅= 150,2 and

thndissipatio RPT ⋅=∆ .

Emission setup component variation R1 120 Ω • • • R2 51 Ω • • • C1 6.8 nF • • •

Test network

1 RLoad ≤ 30 Ω or DC mode • • 2 RLoad > 30 Ω open open

RBAN 150 Ω open open open CBAN 6.8 nF open open open

Immunity setup component variation R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2 open C1 6.8 nF or less as max. load capacitance according IC data sheet

RBAN 150 Ω • • • CBAN 6.8 nF • • •

Table 18: Emission and immunity setup for IC module high side driver


32

8.1.8 Low Side driver • Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the

load impedance are decoupled by a 5 µH coil (LBAN), to get results independent from the load impedance.

• Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a 5 µH coil (LBAN) and a 150 Ω matching network (RBAN , CBAN) for impedance fixing is added.

output

Low

Sid

e D

rive

r

Cor

e

R2

(Ztrace = 150 Ω)(Ztrace = 50 Ω)

C1

supply

1 Ω

1 Ω Probe

49 Ω

2

1

reference

Decoupling and coupling network 1Ω decoupling network

12

RLoad,1

VSupply

LBAN1

RBAN1

CBAN1

R1

© 2007 BISS Configuration Low Side Driver

outputC

Low

Sid

e D

rive

r

Cor

e R3

R4

(Ztrace = 150 Ω) (Ztrace = 50 Ω)

C2

supply

1

reference

L1

D1

C4RLoad,2

VSupply

LBAN1

C3

LBAN2

RBAN2

CBAN2

RBAN1

CBAN1

R1

R2

(Ztrace = 50 Ω)

C1

1

(Ztrace = 150 Ω)

© 2007 BISS Configuration switched mode power supply


33


Item Value Circuit type

Low Side Driver switched mode power supply (Boost converter)

L1 acc. IC data sheet shorted • LBAN1 5 µH independent of load current (no saturation effects) LBAN2 5 µH shorted •

D1 acc. IC data sheet shorted • C3 acc. IC data sheet open • C4 acc. IC data sheet open •

RLoad,1 According Imes* Conthmes RR

TI°⋅

∆=

150,

(∆T = 65 K, Imes ≤ 10 A) shorted

RLoad,2 According Imes Imes = 80% of Inom

*) The IC dissipation power Pdissipation is basically limited by Rth of the housing and the maximum temperature Tmax of the semiconductor at a maximum ambient temperature Tamb according data sheet. With the definitions Tmax = 150°C at Tamp = 85°C a ∆T = 65K is given. The typical dissipation power is additionally given by Ron,150*C and a typical load current ILoad:

ConLoadndissipatio RIP °⋅= 150,2 and

thndissipatio RPT ⋅=∆ .

Emission setup component variation R1, R3 120 Ω • • R2, R4 51 Ω • • C1, C2 6.8 nF • •

Test network 1 RLoad ≤ 30 Ω or DC mode • 2 RLoad > 30 Ω open

RBAN1, RBAN2 150 Ω open open CBAN1, CBAN2 6.8 nF open open

Immunity setup component variation R1, R3 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2, R4 open C1, C2 6.8 nF or less as max. load capacitance according IC data sheet

RBAN1, RBAN2 150 Ω • • CBAN1, CBAN2 6.8 nF • •

Table 19: Emission and immunity setup for IC module low side driver


34

8.2 Supply module Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the load impedance are decoupled by a 5 µH coil (LBAN), to get results independent from the load impedance.

Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a 5 µH coil (LBAN) and a 150 Ω matching network (RBAN , CBAN) for impedance fixing is added.

R1

R2

(Ztrace = 50 Ω)

C1

Func

tion

mod

ule

Func

tion

mod

ule

supp

ly

VSx

VS1

VGND1

VGNDx

Vsupply

LBAN1

CD1

RBAN1

CBAN1 © 2007 BISS

Configuration A: All supplies combined

IC

Func

tion

mod

ule

Func

tion

mod

ule

supp

ly

VSx

VS1

VGND1

VGNDx

Vsupply(x)Vsupply(1)

LBAN1 LBANx

CDX

CD1

C1

(Ztrace = 50 Ω)

VGND2..n

VS2..n

C2

(Ztrace = 50 Ω)

RBAN1

RBANx

CBAN1

CBANx

R3

R1

R2

R4

© 2007 BISS

Configuration B: Supplies partly combined

IC

Func

tion

mod

ule

Func

tion

mod

ule

supp

ly

VSx

VS1

VGND1

VGNDx

Vsupply(x)Vsupply(1)

LBAN1 LBANx

CDX

CD1

C1

(Ztrace = 50 Ω)

C2

(Ztrace = 50 Ω)

RBAN1

RBANx

CBAN1

CBANx

R3

R1

R2

R4

© 2007 BISS

Configuration C: All supplies separated

1 Ω

1 Ω Probe

49 ΩIC

Func

tion

mod

ule

Func

tion

mod

ule

supp

ly

VSx

VS1

VGND1

VGNDx

Vsupply(X)Vsupply(1)

LBAN1 LBANX

CDXCD1

© 2007 BISS

Configuration D: All supplies combined 1Ω method

General setup component variation CD1…CDx Supply Decoupling Capacitor acc. IC data sheet

LBAN1...LBANx 5 µH independent of load current (no saturation effects)

Emission setup component variation R1, R3 120 Ω R2, R4 51 Ω C1, C2 6.8 nF or less as max. load capacitance according IC data sheet


R1, R3 0 Ω as default, up to 100 Ω for load current limitation according data sheet R2, R4 open C1, C2 6.8 nF or less as max. load capacitance according IC data sheet

RBAN1…RBANx 150 Ω CBAN1…CBANx 6.8 nF

Table 20: Emission and immunity setup for IC module supply


35

8.3 Core module The conducted emission and immunity of the core module cannot be measured directly. All emission or immunity tests shall be performed by using cross talk effects between

• core and supply

• core and port

• core and oscillator

8.4 Oscillator module The emission of the oscillator should be measured only by crosstalk at global or local pins.

Immunity measurements can be performed optional directly at the oscillator.

IC

Osc

illat

or

Inpu

t O

utpu

t

Cor

e

quartz

C2

(Ztrace = 50 Ω)

C1

(Ztrace = 50 Ω)JMP1

JMP2

R1

R2

R3

R4

© 2007 BISS

General setup component variation R1, R2 0 Ω C1, C2 Oscillator capacitors: 33 pF or according data sheet

JMP1, JMP2 Jump plug (50 Ω) in case of no injection (immunity test) R3, R4 50 Ω

Emission setup component variation

For oscillator module emission tests are not required

Immunity setup component variation JMP1, JMP2 Jump plug (50 Ω) connected to the not used injection point3

Table 21: Immunity setup for IC module oscillator

3 The internal impedance of the connected RF system substitutes the 50 Ω of the jumper plug.


36

8.5 Signal decoupling- and monitoring setup The signal decoupling- and monitoring setup with or without external filter elements should not affect the functional signal of the function module and not reduce the RF power at the monitored pin. It is recommended that the impedance of the filter is higher than 400 Ω in the test frequency range. An example for filter definition is shown in Figure 6.

in-/outputIC

Por

t/Sup

ply/

Osc

illat

ore

Mod

ule

Cor

e

R1

supply

reference

C1Ulowpass, outUlowpass,in

to load network /from signal source

to supply network

1

2

© 2007 BISS

Configuration 1: Monitoring network at input or output Configuration 2: Monitoring network supply

Figure 6, General setup for a decoupling network for monitoring

Base of calculation:

Transfer ratio: 11,

,

211

CfRjUU

ainlowpass

outlowpass

⋅+==

π

Magnitude of the transfer ratio in dB

41

1log202

12

122

,

,

CRfUU

ainlowpass

outlowpass

π+⋅==

Limit for the magnitude of the transfer ratio < -20 dB, requires R1 > 400 Ω in the test frequency range

Note: Reflection coefficient for R1 ≥ 400 Ω in a 50 Ω system ≥ 0.8


37

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0,01 0,1 1 10 100 1000

frequency f / MHz

tran

sfer

ratio

/ dB

R=400Ohm, C=0.5nFR=400Ohm, C=10nFR=1kOhm, C=1nFR=6.8kOhm, C=2nFR=10kOhm, C=6.8nF

transfer function chart for examples for different values of R1, C1

for direct and indirect monitoring

Figure 7, Decoupling network for monitoring: transfer function charts for low pass circuitry

examples


38

8.6 Entire IC The measurement of radiated electromagnetic fields and the immunity against electromagnetic fields are measured according [2], [6] with the (G)TEM cell.

With the (G)TEM Cell the field coupling between the IC structure and the (G)TEM cell septum is measured. Therefore the IC is mounted on one side of the test board, which is oriented to the septum of the (G)TEM cell. All the other circuit elements are located on the other side of the test board and therefore outside of the (G)TEM Cell.

(G)TEM cell measurements have to be performed in minimum two orientations with 90° difference in the x- and y- plane. The data sets shall be documented separately for each direction.

Pin 1

Direction X

© 2007 BISS

Pin 1

Direction Y

© 2007 BISS

Figure 8: Example of "Direction X" and "Direction Y" of TEM cell test PCB

FUNTIONAL CONFIGURATIONS AND OPERATING MODES

39

9. Functional Configurations and Operating Modes

The functional configuration of the FFUs describes the operation of the sources and sinks in a FFU during the emission measurement or immunity test period. The pin loading is given by the test and measurement networks described in chapter 8. Any deviations of the functional or hardware configuration have to be noted in the test report.

9.1 Emission test configuration for ICs without CPU

Port

mod

ules

PM1

Line Driver To measure the direct switching noise of a line driver the driver shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. If there is a function integrated to use EMC optimized operation modes they should be measured additionally. If more than one driver is tested simultaneously all drivers have to be controlled synchronously. For core cross coupling noise measurement the line driver has to be set in a permanent high state. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected. LIN communication drivers have to be tested according to EMC-Evaluation of LIN transceivers [9].

PM2

Line Receiver To measure the core cross coupling emission at a line receiver the receiver has to be set in the normal receiving mode. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected. LIN communication receivers have to be tested according to EMC-Evaluation of LIN transceivers [9].

PM3

Symmetrical Line Drivers To measure the direct switching noise of a symmetrical line driver the drivers shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. If there is a function integrated to use EMC optimized operation modes they should be measured additionally. For core cross coupling emission measurement the line driver has to be set in a permanent high state. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected. CAN symmetrical line drivers have to be tested according to specification EMC-Evaluation of CAN-Transceivers [8].

PM4

Symmetrical Line Receiver To measure the core cross coupling emission of a symmetrical line receiver the receiver has to be set in the normal receiving mode. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected. CAN communication receivers have to be tested according to EMC-Evaluation of CAN transceivers [8].

Table 22, Emission test configuration for ICs without CPU

Port

mod

ules

PM5

Regional Driver To measure the direct switching noise of a regional driver the driver shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. If there is a function integrated to use EMC optimized operation modes they should be measured


40

additionally. For core cross coupling noise measurement the regional driver has to be set in a permanent high state to measure effects caused by internal periodical sources. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected. To measure the pin to pin cross coupling noise caused by the neighborhood pins the measured pin shall be set at high level and the neighborhood pins shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%.

PM6

Regional Input For core cross coupling noise measurement the regional input shall stay in the default state to measure effects caused by internal periodical sources. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected.

PM7

High Side driver To measure the direct switching noise of a high side driver the driver shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The switching time should take less than 1% of the switching period. The duty cycle should be set to 50%. If there is a function integrated to use EMC optimized operation modes they should be measured additionally with the same frequency as before. For core cross coupling noise measurement the high side driver has to be set in a permanent high state to measure effects caused by internal periodical sources. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected.

PM8

Low Side driver To measure the direct switching noise of a low side driver the driver shall operate with the maximum frequency and the shortest switching time as specified in the IC Data Sheet. The switching time should take less than 1% of the switching period. The duty cycle should be set to 50%. If there is a function integrated to use EMC optimized operation modes they should be measured additionally with the same frequency as before. For core cross coupling noise measurement the low side driver has to be set in a permanent high state to measure effects caused by internal periodical sources. This measurement should be performed only if a cross coupling by internal periodical sources with frequencies above 1MHz is expected.

Supp

ly m

odul

e

SM1 To measure the emission on the supply the IC shall be powered as for normal operation. All modules shall operate as defined for normal operation according data sheet. All internal periodical sources shall be active and operate with maximum frequency and power.

Core

m

odul

e

CM1 The core module shall operate as defined for normal IC function. All internal periodical sources shall be active and operate with maximum frequency and power.

Oscil

lator

m

odul

e

OM1 If an oscillator is used it has to be activated and operate with maximum frequency and power as specified.

Table 22, Emission test configuration for ICs without CPU, continued


41

9.2 Immunity test configuration for ICs without CPU

Port

Modu

les

PM9

Line Driver To measure the immunity of a line driver two functional operation modes have to be tested. In the first mode the driver shall operate with a typical frequency and the typical switching time as specified in the IC data sheet. The duty cycle should be set to 50%. In the second mode the driver has to be set in a permanent high state. For both operation modes the functionality shall be monitored directly at the line driver pin and indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. If there is a function integrated to use EMC optimized operation modes they should be measured additionally. If more than one driver is tested simultaneously all drivers have to be controlled synchronously. LIN communication drivers have to be tested according to EMC-Evaluation of LIN transceivers [9].

PM10

Line Receiver To measure the immunity at a line receiver the receiver has to be set in the normal receiving mode. The monitoring shall be done indirectly at another FFU functional module output port of the IC to detect cross coupling effects to other FFUs. There is no possibility to distinguish between the immunity behavior of the receiver and cross coupling effects into other FFUs. LIN communication receivers have to be tested according to EMC-Evaluation of LIN transceivers [9].

PM11

Symmetrical Line Driver To measure the immunity of a symmetrical line driver two functional operation modes have to be tested. In the first mode the driver shall operate with a typical frequency and the typical switching time as specified in the IC data sheet. The duty cycle should be set to 50%. In the second mode the driver shall be deactivated and stay in the default state. For both operation modes the functionality shall be monitored directly at the line driver pin and indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. If there is a function integrated to use EMC optimized operation modes they should be measured additionally. CAN communication drivers have to be tested according to EMC-Evaluation of CAN transceivers [8].

PM12

Symmetrical Line Receiver To measure the immunity of a symmetrical line receiver the receiver has to be set in an active receiving mode. The monitoring shall be done indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. There is no possibility to distinguish between the immunity behavior of the receiver and cross coupling effects into other FFUs. CAN communication receivers have to be tested according to EMC-Evaluation of CAN transceivers [8].

Table 23, Immunity test configuration for ICs without CPU


42

Port

Modu

les

PM13

Regional Driver To measure the immunity of a regional driver three functional operation modes are possible. The test shall be performed at least in the toggling mode with a typical frequency and the typical switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. Optionally the driver can be tested in a permanent High state and/or Low state. For all operation modes the functionality shall be monitored directly at the regional driver pin and indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. If there is a function integrated to use EMC optimized operation modes they should be tested additionally.

PM14

Regional Input To measure the immunity of a regional input the input has to be set in an active mode. The monitoring shall be done indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. There is no possibility to distinguish between the immunity behavior of the input and cross coupling effects into other FFUs.

PM15

High Side Driver To measure the immunity of a High Side driver three functional operation modes are possible. The test shall be performed at least in the toggling mode with a typical frequency and the typical switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. Optionally the driver can be tested in a permanent High state and/or Low state. For all operation modes the functionality shall be monitored directly at the High Side driver pin and indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. If there is a function integrated to use EMC optimized operation modes they should be tested additionally.

PM16

Low Side Driver To measure the immunity of a Low Side driver three functional operation modes are possible. The test shall be performed at least in the toggling mode with a typical frequency and the typical switching time as specified in the IC Data Sheet. The duty cycle should be set to 50%. Optionally the driver can be tested in a permanent High state and/or Low state. For all operation modes the functionality shall be monitored directly at the Low Side driver pin and indirectly at another functional module output port of the IC to detect cross coupling effects to other FFUs. If there is a function integrated to use EMC optimized operation modes they should be tested additionally.

Supp

ly m

odul

e SM2

To measure the immunity of the supply the IC shall be powered as for normal operation. All modules shall operate as defined for normal operation according data sheet. All internal periodical sources shall be active and operate with maximum frequency and power. The monitoring shall be done indirectly at the supplied FFUs of the IC.

Table 23, Immunity test configuration for ICs without CPU, continued.


43

Core

mod

ule CM2

Core active mode The core module shall operate as defined for normal IC function. All internal functions shall be active and operate with typical frequency and power.

CM3 Core sleep modes If it is possible to set the IC in other modes different to the normal mode such as sleep mode, standby mode etc. they should be tested additionally.

Oscil

lator

m

odul

e OM2 If an oscillator is used it has to be activated and operate with typical frequency and power as specified.

Table 23, Immunity test configuration for ICs without CPU, continued.


44

9.3 Emission test configuration for ICs with CPU

9.3.1 Test initialization software module for cores containing a CPU Configuration Software Module

Description and definition of test initialization software module Nu

mbe

r

Nam

e

Shor

t De

scrip

tion

C1

Refe

renc

e

‘Wor

st ca

se’ s

ettin

g System clock: - frequency = fmax CPU: - active FFUs: - all Fixed-function Units active, if

available: system clock output active Active ports: - all multifunction ports switched to FFU

function - fastest slew rate of drivers

Inactive Ports: - all other ports Memory access: - choose the memory access for the loop

software module with highest emission potential available, for example:

- synchronous access from external memory (burst mode)

- asynchronous access from external memory

- internal access from on-chip memory

C2

Bus m

ode

1 Pr

ogra

m ex

ecut

ion w

ith

sync

hron

ous b

us a

cces

s/ s y

stem

cloc

k

System clock: - frequency = fmax CPU: - active FFUs: - all Fixed-function Units inactive, except

the memory interface Active ports: - buses

- bus clock (system clock output active) - fastest slew rate of drivers

Inactive Ports: - all other ports Memory access: - memory access for the loop software

module: synchronous access from external memory (burst mode)

Table 24, Test initialization software module for cores containing a CPU


45

C3 2 Pr

ogra

m ex

ecut

ion w

ith

asyn

chro

nous

bus a

cces

s/ s y

stem

cloc

k


the memory interface Active ports: - buses

- fastest slew rate of drivers Inactive Ports: - all other ports

- bus clock (System clock output inactive) Memory access: - memory access for the loop software

module: asynchronous access from external memory

C4 3

On-c

hip e

xecu

tion

with

out

syste

m cl

ock o

utput

System clock: - frequency = fmax CPU: - active FFUs: - all Fixed-function Units inactive Active ports: - none Inactive Ports: - all ports (Buses and all other ports)

- bus clock (System clock output inactive) Memory access: - memory access for the loop software

module: internal access from on-chip memory

C5

Drive

r

Drive

r slew

rate

test


the FFU corresponding to a tested driver (if system clock output is available, its test is required)

Active ports: - driver slew rate switched to I. Required: fastest slew rate II. Optional: slower slew rates

Inactive Ports: - all other ports Memory access: - choose the memory access for the loop

software module with lowest emission potential (low, medium, high) available, for example: low internal access from on-

chip memory medium asynchronous access from

external memory high synchronous access from

external memory (burst mode)

Table 24, Test initialization software module for cores containing a CPU, continued.


46

C6

Oscil

lator

Idle

(Osc

illato

r) M

ode

System clock: - frequency = fmax CPU: - inactive ('wait' mode, 'hold' mode), if

available FFUs: - all Fixed-function Units functionally

inactive and unclocked Active ports: - none Inactive Ports: - all ports Memory access: - memory access for the loop software

module: none

C7

Cloc

k Tre

e

Activ

e Cl

ock T

ree

Mod

e

System clock: - frequency = fmax - maximum clock tree frequency in clock

tree distribution CPU: - inactive ('wait' mode, 'hold' mode), if

available FFUs: - all Fixed-function Units clocked, but

functionally inactive Active ports: - none Inactive Ports: - all ports Memory access: - memory access for the loop software

module: none

C8

Sing

le FF

U

Test

single

FFU

System clock: - frequency = fmax CPU: - minimum required activity FFUs: - all Fixed-function Units inactive, except

the FFU under investigation Active ports: - controlled ports by FFU under

investigation Inactive Ports: - all other ports Memory access: - choose the memory access for the loop

software module with lowest emission potential (low, medium, high) available, for example: low internal access from on-

chip memory medium asynchronous access from

external memory high synchronous access from

external memory (burst mode)

C9

Redu

ced

syst

em

frequ

ency

On

-chip

exe

cutio

n at

re

duce

d sys

tem

fre

quen

c y

System clock: - frequency < fmax

combined with Configuration Modules C1..C8

Notes: 1. The measurement should start after finishing the initialization. . 2. This table may be extended by further tests agreed between the customer and IC supplier

Table 24, Test initialization software module for cores containing a CPU, continued.


47

9.3.2 Immunity test configuration for ICs with CPU Configuration Software Module

Description and definition of test initialization software module

Num

ber

Nam

e

Shor

t De

scrip

-tio

n

C10

Imm

unity

Ref

eren

ce

Func

tiona

l ‘Wor

st ca

se’ s

ettin

g

System clock: - frequency = fmax CPU: - active FFUs: - all Fixed-function Units active, if

available: system clock output active Active ports: - all multifunction ports switched to FFU

function - fastest slew rate of drivers

Inactive Ports: - all other ports Monitor pin: - a pin of a non-multifunction port without

FFU function, toggle signal with fixed relation to system clock (constant frequency), CPU-driven

Error detection: - all possible error detections should be active (e.g. watchdog, oscillator loss of lock, internal/external bus errors / FFU-errors, traps, interrupts)

- load/compare/store loop inside internal/external memory

- each error case should stop the toggling signal on the monitor pin

Memory access: - choose the memory access for the loop software module with highest functional potential (high, medium, low) available, for example: high synchronous access from

external memory (burst mode) medium asynchronous access from

external memory low internal access from on-chip

memory

C11

Oscil

lator

Idle

Mod

e (O

scilla

tor t

est-m

ode)

System clock: - frequency = foscillator CPU: - inactive ('wait' mode, 'hold' mode), if

available FFUs: - all Fixed-function Units functionally

inactive and unclocked OSC: - all different Oscillator-driver-settings

must be tested on a typical crystal (e.g. according data sheet like 4/16 MHz)

Active ports: - clock output or a toggling port for monitoring

Inactive Ports: - all ports Memory access: - memory access for the loop software

module: none Notes: 1. The measurement shall start after finishing the initialization. 2. This table may be extended by further tests agreed between the customer and IC supplier

Table 25, Immunity test configuration for ICs with CPU


48

9.3.3 Test loop software module for cores containing a CPU The test software should be developed with respect to the expected measuring time. The loop time should not exceed 100 ms.

Loop Software module Description and definition of test loop software module Number Short description

S0 Idle None S1 Fastest instruction loop label: jump(unconditional) label

S2 RAM copy

Copied data range is equal or more than 10% of available RAM. Data pattern is alternating $AA.. and $55.. (length depending on data bus width) in consecutive RAM access. Source memory area and destination memory area shall differ by the maximum number of address bits

Upper memory limit

Lower memory limit

10 % Uppermemory

area

101010101...010101010...

10 % Lowermemory

area

101010101...010101010...

memory vector-1 decrement

memory vector+1 increment

S3 Driver output action Toggling driver outputs

S4 IEC Increment

[IEC 61967-1, annex B]: "This simple routine implements a counter function using a single 8-bit port. Every 100 µs, the port output is incremented or decremented. After 10 count cycles (256 ms) an LED output is complemented. This will provide a blinking light indication with a frequency of about 2 Hz. For consistency, equivalent loop times shall be maintained."

S5 FFU dedicated software

CPU runs at minimum required activity for FFU controlling, target is autonomous running mode of the FFU under investigation. All FFU parameters: Adjust to EMC worst case condition

S6 Read Receiver/Input Read receiver/input register Note: Take care of software loop times according emission measurement dwell time.

Table 26, Test loop software module for cores containing a CPU

TEST BOARD

49

10. Test board

The minimum requirement for the test PCB is a two-layer board with a common ground plane on the bottom side used as reference ground.

In general all ground areas have to be connected to a common ground system with low impedance.

For conducted measurements the geometry of the board may have any rectangular or circular shape. This is dependent on the IC specific application and necessary additional components, measuring- and decoupling networks. The DUT and all mandatory components needed to operate the DUT, as described in the data sheet or application note should be mounted onto the topside of the test board. As much wiring as possible should be routed in the top layer. The device under test should be placed in the centre of the PCB, while the needed matching networks should be placed around this centre. The wiring between the IC pins and the matching network should be as short as possible. A trace length equal to 1/20 of the shortest wave length (1 GHz) applied is a reasonable target. The wiring of the outputs of the matching networks should be designed to have a line impedance of 50 Ω connected with a RF-connector (e.g. SMA or SMB) at the end. In case that the 1Ω -Method is used a socket for the RF current probe should be used. The shield of the RF current probe tip shall be connected to RF- peripheral ground by the socket, while the measured IC Pin is connected to the current probe tip. The connection between the IC Pin and the probe tip should be as short as possible. In any case the trace length should not exceed 15 mm (at 1 GHz upper frequency range limit).

In general the transfer characteristic of each RF measurement point at the test board including all functional, decoupling and measuring components without the DUT shall be measured and documented in the test report. The DUT has to be substituted by 50 Ω resistors to ground at the DUT pin pads.

For radiated measurements the geometry of the board is given by the hole in the TEM cell where the board has to fit in. To fulfill the requirements of the application on such a limited board a more layer board should be used. In any case the DUT has to be mounted onto the bottom side with the common ground plane.

In “Annex-A” some examples of board layouts for 150 Ω -, 1 Ω - , DPI- and TEM-cell testing are shown.

IC EMC L IMITS

50

11. “Preliminary” IC EMC limits for Automotive

All relevant pins of an IC shall be classified according to the limits given in the following chapters. Mandatory components are regarded as part of the IC and shall be added for the test.

The currently defined limits are based on a small data base and must be updated if more experience is collected. Therefore they are for orientation at the moment.

The limit classes are different depending on the requirements given by the application. The application EMC effort is defined by the application itself, ECU housing, number of layers, filters elements etc.

Limit class Description I high application EMC effort II medium application EMC effort III low application EMC effort C customer specific

C-BS customer specific: external bus systems

11.1 Emission

11.1.1 Emission level scheme The following level scheme can be used to describe the emission of ICs in a simplified way.

0

6

12

18

24

30

36

42

48

54

60

66

72

78

84

0,01 0,1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

A

B

C

D

E

F

G

H

I

K

L

M

N

O19

1817

1615

1413

1211

109

87

65

43

2 1

yz

x wv

u ts r

qp o

nm l

ki h

gf

e d cb

a

Figure 9, Emission level scheme according IEC61967-2 and IEC61967-4

By selecting the right emission level and defining a limit class for a dedicated IC pin the desired functionality and operation mode has to be considered.

Toggling digital data pins, periodically switching analogue power outputs etc. generate switching harmonics as a matter of principle. This may violate emission requirements in terms of standard limit classes but cannot be avoided by IC design measures for functional reasons.

IC EMC L IMITS

51

The resulting spectrum can be calculated by Fourier transformation of the functional specified signal waveform as described in Annex F. This calculated spectrum describes the limitation of the minimal emission and has to be considered to define superimposed specific limits for those pins.

11.1.2 General emission limit classes

Limit class 150 Ω method 1 Ω method TEM cell method global local global local I 8-H 6-F 10-K 8-H I II 10-K 8-H 12-M 10-K L III 12-M 10-K 14-O 12-M N C customer specific

Table 27, General emission limit classes

IC EMC L IMITS

52

Conducted emission 150Ω method limit line set for all IC function modules

6121824303642485460667278849096

102

0.1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

H

K

M

10

8

0,15

12Class I

Class II

Class III

Figure 10: Limit line set for global pins

6121824303642485460667278849096

102

0.1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

H

K

6

8

0,15

F10

Class I

Class II

Class III

Figure 11: Limit line set for local pins

Conducted emission 1Ω method limit line set for all IC function modules

06

121824303642485460667278849096

0.1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

O

K

M

12

10

14

0,15

Class I

Class II

Class III


06

121824303642485460667278849096

0.1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

K

M

12

10

8

0,15

H Class I

Class II

Class III


Radiated emission TEM cell method limit line set for dedicated IC types (see chapter 7.1.1)

0

6

12

18

24

30

36

42

48

54

60

66

72

78

84

0,1 1 10 100 1000[frequency] MHz

[Vol

tage

] dB

µV

L

0,15

I

N

Class I

Class II

Class III

Figure 14: Limit line set for TEM cell

IC EMC L IMITS

53

11.1.3 Dedicated emission limits for 'external digital bus systems' Adapted limits C-BS for bus communication of microcontrollers with RAM or flash in configuration C1 and software loop S2.

Background: The performance of current 'digital systems' built of IC types microcontrollers, RAMs and flashes, connected via busses, leads to higher emission values. To attend this technical phenomenon, other emission values are allowed for this kind of IC type combination. In the case of applying such an IC type combination in an application, all other IC types used in the same application shall fulfill the limit of the agreed region.

Figure 15, Conducted emission 150 Ω limit Port Pins

0

10

20

30

40

50

60

70

80

90

0,1 1 10 100 1000[frequency] MHz

[val

ue] d

BµV

0.15 MHz69.31 dBµV

10 MHz45 dBµV

100 MHz45 dBµV 300 MHz

39 dBµV

600 MHz30 dBµV

0.15

Figure 16, Conducted emission 150 Ω limit Supply pins

0

10

20

30

40

50

60

70

80

90

0,1 1 10 100 1000[frequency] MHz

[val

ue] d

BµV

0.15 MHz59.3 dBµV

10 MHz35 dBµV


29 dBµV

600 MHz20 dBµV

0.15

Figure 17, TEM cell limit Microcontroller

0

10

20

30

40

50

60

70

80

90

0,1 1 10 100 1000[frequency] MHz

[val

ue] d

BµV

0.15 MHz35 dBµV


29 dBµV

600 MHz20 dBµV

0.15

IC EMC L IMITS

54

11.2 Immunity

11.2.1 General immunity limit classes

Immunity limit classes DPI

[forward power] dBm TEM

[E-field] V/m global pin local pin entire IC

I 18 0 200 II 24 6 400 III 30 12 800 C customer specific

Table 28, General immunity limit classes

Conducted immunity DPI method limit line set for all IC function modules

-30369

1215182124273033363942

0,1 1 10 100 1000[frequency] MHz

[fore

war

d po

wer

] dB

m

0,15

Class I

Class II

Class III30 dBm

24 dBm

18 dBm


-30369

1215182124273033363942

0,1 1 10 100 1000[frequency] MHz

[fore

war

d po

wer

] dB

m

0,15

Class I

Class II

Class III12 dBm

6 dBm

0 dBm


Radiated immunity TEM cell method limit line set for dedicated IC types (see chapter 7.2.1)

0

100

200

300

400

500

600

700

800

900

1000

0,1 1 10 100 1000[frequency] MHz

[E-fi

eld]

V/m

0,15

Class I

Class II

Class III

Figure 20: Limit line set for TEM cell

IC EMC SPECIF ICATION

55

12. IC EMC Specification

The IC EMC Specification contains the EMC requirements and the EMC Test Specification for a dedicated IC. It is either provided by the customer or by the IC supplier. The IC EMC Specification contains the pin selection, functional configuration, measurement method and limits (EMC requirements) for emission and immunity tests as defined in Table 29 and Table 30. Additionally the test board’s schematic and special agreements may be included. An example is given in Annex E.

Emission

Coupling point Coupling mechanism Test method selection

with limit (Class I-III,C,C-BS)

Pin (if available)

IC fu

nctio

n m

odul

e

Pin

Type

(g

loba

l/loca

l)

Func

tiona

l Co

nfig

urat

ion

Oper

atio

n Mo

de*

dire

ct

port

cros

stalk

core

cros

stalk

osc.

cros

stalk

150 Ω

1 Ω

TEM

No.:

Nam

e

Function

Example:

System clock output

Regional driver local C1-S2 T III

Data bus Regional driver local C1-S2 T III

Address bus Regional driver local C1-S2 T III

ALE signal pin Regional driver local C1-S2 T III

All Chip select (CS)

Regional driver local C1-S2 T III

Read (R) Regional driver local C1-S2 T III

Write (W) Regional driver local C1-S2 T III

* Note: T = Toggle; H = static high potential, L = static low potential A = defined active; IA = defined inactive, realized with internal or external pull up or pull down

Table 29, Structure of an IC EMC specification, part emission

IC EMC SPECIF ICATION

56

Immunity

Injection point Monitoring Test method

Pin

Pin

Type

(glo

bal/lo

cal)

Func

tiona

l Con

figur

atio

n

Oper

atio

n Mo

de*

Monitoring pins

Failu

re cr

iteria

DPI

TEM

No.

Nam

e

Func

tion

Port

IC fu

nctio

n m

odul

e

No.

Nam

e

Func

tion

CW AM CW AM

Example:

Reset Regional Input local

C1-S2 A I/O Port 1 III C1-S2 A Reset 2 III

PLL-freq1..x Regional

Input local C1-S2 A CLK out or toggling port 1

III III III

* Note: T = Toggle; H = static high potential, L = static low potential A = defined active; IA = defined inactive, realized with internal or external pull up or pull down

Table 30, Structure of an IC EMC specification, part immunity (1)

Failure criteria

No. Description Tolerance 1 Toggling port toggling, constant frequency 2 Voltage at pin as specified in data sheet

Table 31, Structure of an IC EMC specification, part immunity (2)

TEST REPORT

57

13. Test report

Following items shall be part of the test report:

• Reference to used EMC specification

• Schematic diagram of test board

• Picture of test board layout or parts of it

• Transfer characteristics of RF coupling paths

• Functional configurations of FFUs and description of implemented software modules for ICs with CPU

• Description of test equipment

• Description of monitoring points and failure criteria for immunity tests

• Description of any deviation from previously defined test parameters

• Result diagrams (Emission: scaled in dBµV and all limit lines, Immunity: scaled in dBm for DPI or V/m for TEM with target value lines, as shown as figures in chapter 11)

COPYRIGHTS AND L IABIL ITY

58

14. Copyrights and Liability

Copyrights:

§1 With respect to the Specification Document sent in the form of either paper or data, the companies Bosch, Continental and Infineon provide this specification to their respective business partners and any other third parties according to the following conditions. All interested users may:

§1.1 use the Specification Document in terms of the specification for the compilation and implementation of the IC Tests and incorporate the Specification Document into their respective in-house specifications with the existing copyright notices;

§1.2 publish, subject to the protection of the copyright notices, the Specification Documentation free of charge;

§1.3 revise or further develop the Specification Documentation. In this case, any changes have to be made visible as such; and

§1.4 make the Specification Document available to their respective business partners (in the form of paper or data) subject to the aforementioned conditions.

§2 Any user shall point out to its respective business partners or any interested third party that the copyright notices which are found on the Specification Document and which exist for the benefit of the Bosch, Continental and Infineon, may not be removed or modified by such business partners or any other third party; this also applies in cases of revisions or further developments thereto.

§3 Any user shall point out to its respective business partners or any interested third party that utilization of the Specification Document by them or by their respective business partners or any other third party on a remunerative basis is not permitted.

Liability:

§ 1 Bosch, Continental and Infineon are liable without limitation for deliberate acts and acts committed with gross negligence.

§ 2 With the exception of injuries to life, body and health, Bosch, Continental and Infineon are liable for acts committed with slight negligence only insofar as principal obligations with regard to the providing of the Specification Document are infringed. Also, liability is restricted to the typical and foreseeable damages.

§ 3 Liability for indirect and unforeseeable damages, for standstill of production and recovery for loss of use, loss of data, lost profits as well as expenses incurred for development, supplementary labour or product recall as well as pure economic loss due to third-party claims are excluded in the event of slight negligence.

§ 4 Further liability in excess of what is specified herein is excluded regardless of the legal nature of the claim asserted.

ANNEXES

59

15. Contacts and authors

The following table shows company contact persons listed in alphabetic order:

Name Company Email address

Michael Joester

Continental Automotive GmbH AQL RBG 42 P.O. Box 10 09 43 93009 Regensburg

[email protected]

Dr. Frank Klotz

Infineon Technologies AG Automotive Power – EMC Center ATV PTS PD EMC 81726 München

[email protected]

Dr. Wolfgang Pfaff

Robert Bosch GmbH AE/EMC-G P.O. Box 300240 70442 Stuttgart

[email protected]

Thomas Steinecke

Infineon Technologies AG Automotive Microcontrollers ATV MC D IPI EMC 81726 München

[email protected]

Table 32, List of contact persons The specification was created by a working group with experts and members of the german national standardization organization DKE from Bosch, Infineon and SiemensVDO. The Authors are listed in alphabetical order by Companies:

Robert Bosch GmbH:

Dr. Joerg Brueckner, Dr. Wolfgang Pfaff, Herman Roozenbeek, Andreas Rupp

Infineon Technologies AG:

Dr. Frank Klotz, Christoph Schulz-Linkholt, Thomas Steinecke, Markus Unger

Continental:

Michael Joester, Hartwig Reindl, Christian Roedig, Gerhard Schmid

ANNEXES

60

Annex A Layout Recommendation,

(informative) Several networks

Layout Example of 150 Ω networks on 2 layer and multi layer PCB

IC

6.8 nF

120 Ω

51 Ω

SMA or SMBconnector

R1

R2

C1

Conducted Emissionconfiguration

R1 C1

R2

50 Ω micro striplinelength < λ/20

Signal or supply to IC pin

CX

CX

ZX

ZX

51Ω

120Ω 6.8nF

CX e.g.: Output mode load capacitor or supply buffer capacitor

IC-Pin

ZX e.g.: 0 Ω for connection to circuit or pullup resitor for input mode

= top layer

= bottom layer circuit ground TEM cell RF ground plane

DUT on bottom side Components as closetogether as possible

SMA or SMB connectoron top side

150 Ω network on 2 layer PCB

IC

6.8 nF

120 Ω

51 Ω

SMA or SMBconnector

R1

R2

C1

Conducted Emissionconfiguration

R1 C1

R2



CX

CX

ZX

ZX

51Ω

120Ω 6.8nF


IC-Pin

ZX e.g.: 0 Ω for connection to circuit or pullup resitor for input mode

= top layer

.

.

.

.= 1st inner layer

= other inner layer

= bottom layer reserverd for TEM cell RF ground plane

DUT on bottom side Components as closetogether as possible


150 Ω network on multi layer PCB

Notes:

• The impedance of the signal island at the IC pin is not 150 Ω, but can be neglected as it is as small as possible. • This layout recommendation can be configured to perform Direct Power Injection (DPI) according IEC62132-4. • The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum twice of the

distance between the 50 Ω trace and the ground plane underneath the trace.

Figure 21, Layout recommendation 150 Ω network

Layout Example of 1 Ω network on 2 layer and multi layer PCB

IC

1 Ω

1 Ω Probe

Conducted emission1 Ω method


DUT on bottom side SMA or SMB connectoron top side

CDecoupling

IC-ground-pin

= top layer


IC sum ground island

VSupply Pin

IC-ground-pin

IC-ground-pin

Groundisland Signal

ground

CDecoupling

VSupply Pin

.

. inner layers

Figure 22, Layout recommendation 1 Ω network

NOTES

61

Layout Example of DPI network on 2 layer and multi layer PCB

IC

6.8 nF

0 Ωor value forcurrent reduction

SMA or SMBconnector

R1

C1

Direct Power Injectionconfiguration

R1 C1

R2


Components as closetogether as possible

DUT on bottom side



CX

CX

ZX

ZX

0Ω 6.8nF


IC-Pin

ZX e.g.: Inductance or resistor for supply/ signal line/circuit decoupling

= top layer


DPI network on 2 layer PCB

IC

6.8 nF

0 Ωor value forcurrent reduction

SMA or SMBconnector

R1

C1

Direct Power Injectionconfiguration

R1 C1

R2


Components as closetogether as possible

DUT on bottom side



CX

CX

ZX

ZX

0Ω 6.8nF


IC-Pin

ZX e.g.: Inductance or resistor for supply/ signal line/circuit decoupling

= top layer

.

.

.

.= 1st inner layer

= other inner layer

= bottom layer reserverd for TEM cell RF ground plane

DPI network on multi layer PCB

Notes: • The impedance of signal island at the IC pin is not 50 Ω, but can be neglected as it is as small as possible. • This layout recommendation can be configured to perform Conducted Emissions according IEC61967-4. • The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum twice of

the distance between the 50 Ω trace and the ground plane underneath the trace.

Figure 23, Layout recommendation DPI network

ANNEXES

62

Layout Example of a TEM cell test board The layout requirements for a TEM cell test board are described in detail in [1] and [2].

DUT

GND-Vias

GND Tin-coated

GND

103,00 mm

GND-Vias are always plated through all layers and all other Vias are partial plated or buried only.

Figure 24, TEM cell test PCB shape

NOTES

63

Layout Example for Digital systems built with IC types microcontrollers, RAMs In the following figure a required 6 layer stack is shown used for digital systems built with IC types microcontrollers, RAMs and flashes:

µ-Via: hole diameter = 100 µm and pad diameter = 300 µm Small Via: hole diameter = 250 µm and pad diameter = 500 µm Standard Via: hole diameter = 300 µm and pad diameter = 800 µm

Min. trace width 160 µm and Cu-thickness 35 µm

Figure 25, Recommended layer stack up of a test board for digital systems built of IC types microcontrollers, RAMs and flashes

Multi method test board

For combined test boards for radiated and conducted tests (conducted emission and DPI) the conducted measurement points and adaptation networks with RF connectors at port pins and supply lines should be realized on the component side of the PCB. Every port pin and every independent power supply that has to be measured needs an adaptation network and a RF connector (e.g. SMA or SMB). Add the conducted test method networks to this board according the previous chapter.

DUT- or TEM-Side

1

2

3

4

5

6

0.063 mmComponent Side

Inner 1

Inner 2

Inner 3

Inner 4

Solder Side

Insulation

Insulation

Insulation

Insulation

Insulation

0.063 mm

0.053 mm

0.053 mm

0.035 mm

0.035 mm

0.250 mm

0.250 mm

0.200 mm

0.200 mm

0.200 mm

components + wiring

wiring

ground plane

empty (optional) plane

DUT-supplies only

DUT and groundplane

Component-side

u-Via

u-Via

ANNEXES

64

Digital system built with IC types Microcontrollers, RAM and Flash: PCB requirements and some layout hints for combined radiated and conducted methods test board.

Component side:

To prevent unwanted resonances in the supply system, the wiring recommendation of the different PCB-layers should be followed. Every supply-island is connected with two SMB-jackets. One jacket is used for measuring the supply voltage according to the 150 Ohm method in our example BUVDD2V6 for the external-bus/Flash supply-island and BUVDD1V5 for the core supply-island. The other jacket which is directly connected with the corresponding supply-island is used for measuring the impedance of the supply-island and the transfer impedance between the supply-islands. In our example BVDD2V6 for the external-bus/Flash supply-island and BVDD1V5 for the core supply-island.

Figure 26, Component side

NOTES

65

An integrated voltage regulator has to be placed on the test-board too. Separated supply-lines to the different islands and component units should be used. Only plated-through holes through all layers and no partial vias shall be used for ground connections. For all other connections only partial vias are allowed. Bus wiring should be limited on component- and innerlayer1 only. Any wiring between core decoupling capacitors at the component side should be prevented.

Figure 27, Detail of component side layer

The supply-islands are connected by a special land to the supply-line at the component side, which makes it possible to separate the island from the supply line very easily. Such a land is shown below in a picture detail of the component side layer.

Inner layer 1 (i1):

The core supply-island and the core supply-line from the voltage regulator to the core-island should be at layer i1 only. Above layer i1 should be no wiring of external address- data- and bus control-signals

Figure 28, Inner layer 1

ANNEXES

66

Inner layer 2 (i2): (Ground layer)

Inner layer 2 should be a ground layer only without any exceptions. Ground vias are basically connected with all layers as far as possible.


Inner layer 3:

The external-bus/Flash supply-island can be placed more favorable at the inner layer 3 as at inner layer 4, because at i4 a little bit of wiring has to be done caused by the use of partial vias.


NOTES

67

Inner layer 4:

A minimum of wiring should be under the supply-island of i3. The wiring of the clock out signal should be between two ground areas in this layer only. USB-Bus traces for communication purposes are shown in this layer also.


Solder Side (SS):

Only absolute minimum of wiring should be performed at this layer. Only the DUT in our example a microcontroller should be mounted at this layer.

Figure 32, Solder side

ANNEXES

68

Summary of the placement of components and wiring of the combined TEM cell/conducted emission-Test board:

Components + Buswiring + Mainwiring

Solder Side-Ground +Microcontroller

I1- Buswiring + Supply-Island forMicrocontroller +Mainwiring

I2 - Groundplane only

I3 - Supply-Island external Bus only

I4 - Clockout + Communication with Microcontroller

Component-side

DUT-or TEM-side

Figure 33, Layer stack

NOTES

69

Annex B Test network modification

(emission, normative)

Calculation of new start frequency in case of modifying the coupling capacitor of the 150 Ω measuring network

Base of calculation:

transfer ratio highpass voltage divider out

in

inhighpass

outhighpass

ZZ

UU

a ==,

, ; limit definition 2

13 =− dBa

. (A1)

Magnitude of transfer ratio of 150 Ω network, see Figure 34:

2222,

,

41)5051120(

)5051(log20

CfUU

ainhighpass

outhighpass

π+ΩΩ+Ω

ΩΩ⋅== ,

transfer ratio for: ∞→f : dB 2.15−=∞→fa (A2)

Equation for limit frequency (highpass -3dB point)

FdB C

fMHz

µ⋅≈− Ω 844

13 (A3)

-27

-24

-21

-18

-15

0,1 1 10 100 1000

[frequency] MHz

[|tra

nsfe

r rat

ion|

] dB

6.8 nF1 nF100 pF50 pF

120 Ω

51 Ω 50 Ω

fX C π2

1=Uin

Uout

- 3 dB

Figure 34, 150 Ω network, attenuation chart of some example capacitor values

ANNEXES

70

Table of useful capacitor values:

Value of 150 Ω network DC block capacitor Lower limit frequency (-3 dB) 6.8 nF * 174 kHz

1 nF 1.2 MHz 100 pF 12 MHz

68 pF 17 MHz 50 pF 24 MHz 33 pF 36 MHz

*) Note: (default value according IEC standard)

Table 33, Limit frequencies of modified DC block capacitor values in 150 Ω network

NOTES

71

Annex C Trace impedance calculation

(informative)

Equations for calculating Micro Stripline impedances (informative)

Source of this annex part: Hall/Hall/McCall, 'High Speed Digital System Design', issue 2000, ISBN 0-471-36090-2

"These equations should be used only when a field simulator is not available. A field simulator is required for the most accurate results."

Microstrip

⎟⎠⎞

⎜⎝⎛

++≈

TWHZ

r 8.098.5ln

41.187

0 ε (B1)

Valid when 151 and 0.21.0 <<<< rHW ε

εr

WT

H

Figure 35, Micro strip line

Note: The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum twice of the distance H between the 50 Ω trace and the ground plane underneath the trace.

Please consider furthermore that in case of ground copper edges on the same layer the impedance is influenced if varnish is on the PCB surface, too.

Symmetric Stripline

⎟⎟⎠

⎞⎜⎜⎝

⎛+

≈)8.0(67.0

4ln60,0 WT

HZr

sym πε (B2)

Valid when 25.0 and 35.0 <<HT

HW

εr

THW

Figure 36, Symmetric stripline

ANNEXES

72

Offset Stripline

"The impedance for an offset stripline is calculated from the results of the symmetrical strip line formulas. The reader should note that this formula is an approximation and the accuracy of the results should be treated as such. For more accurate results, use a filed solver."

( ) ( )( ) ( )rr

rr

TWBZTWAZ

TWBZTWAZZ

symsym

symsym

offset εε

εε

,,,2,,,2

,,,2,,,22

00

000 +

⋅= (B3)

εr

TA

WB

Figure 37, Offset Stripline

Note: The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum of the same distance as the distance H/2 (Figure 36) or B (Figure 37) between the 50 Ω trace and the ground plane underneath/above the trace.

NOTES

73

Annex D Modulation definition

(immunity, informative)

Source: According ISO 11452-1, Annex B (informative):

This annex explains the principle of constant peak test level. The electric filed strength of a continuous wave signal, ECW, may be written in the form )cos( tEECW ω×= where E is the peak value of ECW. The mean power may be calculated

2

2EPCW =

The electric field strength of an amplitude modulated signal, EAM, may be written in the form

)cos()cos1(' ttmEEAM ψϑ×+×= where the peak value,

)1(' mEEAMpeak +×=

The mean power,

221

2'2 EmPAM ×⎟⎟⎠

⎞⎜⎜⎝

⎛+=

In all these formulae, m is the modulation index; other symbols are explained in the relevant parts of ISO 11452.

Note: The total power is the sum of the power in the carrier component and the power in the side-frequency component. The peak test level conversation may be written AMpeakCWpeak EE =

The relation between CW power and AM power is then

=⎥⎦

⎤⎢⎣

⎡×⎟⎟

⎠

⎞⎜⎜⎝

⎛+

=

2

221

2

2'2

E

Em

PP

CW

AM

2

2

'2

)1(2

1

21

m

m

EEm

+

⎟⎟⎠

⎞⎜⎜⎝

⎛+

=⎟⎟⎠

⎞⎜⎜⎝

⎛×⎟⎟

⎠

⎞⎜⎜⎝

⎛+

Therefore

2

2

)1(22

mmPP CWAM +

+×=

For m=0.8 (AM 1 KHz 80%) this relation gives CWAM PP ×= 407.0

ANNEXES

74

Annex E Example of an IC EMC specification (general, informative)

IC type with CPU, Emission

Coupling point Coupling mechanism Test method selection

with limit (Class I-III,C,C-BS)

Pin (if available) IC

func

tion

mod

ule

Pin

Type

(g

loba

l/loc

al)

Func

tiona

l Co

nfig

urat

ion

Oper

atio

n M

ode*

dire

ct

port

cros

stal

k

core

cr

osst

alk

osc.

cro

ssta

lk

150

Ω

1 Ω

TEM

No.:

Nam

e

Function

All signals for external (synchronous and asynchronous) memory access

System clock output Regional driver local C1 S2 III

Data bus Regional driver local C1 S2 III Address bus Regional driver local C1 S2 III ALE signal pin Regional driver local C1 S2 III

All Chip select (CS) Regional driver local C1 S2 III

Read (R) Regional driver local C1 S2 III Write (W) Regional driver local C1 S2 III

Other Memory access signals Regional driver local C1 S2 III

Digital ground GNDD1..x Supply global C1 S2 III III

Supplies Vcc_core1..x Supply global C1 S2 • III III Vcc_osc Supply global C6 S1 • III III Vcc_I/O Supply global C1 S3 • III III Supply global III III

Synchronous serial bus (e.g.SPI, I2C)

Communication Clock out (e.g.

SPI CLK) Regional driver local C1 S3 • III III

Com. Data out (e.g. MOSI) Regional driver local C1 S3 • III III

I/O port with highest driver strength

Digital I/O port in output mode Regional drivers local

C5-S3 T • III III C5-S3 H,L • III III C1-S2 H,L • • III III

Line drivers and Line receivers

Relay drivers Line drivers global C5-S3 T • III III

C5-S3 H,L • III III C1-S2 H,L • • III III 'Wake up' signal Line receivers global C1-S2 IA • • III III

Asynchronous serial bus (e.g. CAN)

CAN driver Symmetrical line drivers global

C5-S3 T • III III

C5-S3 H,L • III C1-S2 H,L • • III

CAN receiver Symmetrical line

receivers global C1-S2 IA • • III III

* Note: T = Toggle; H = static high potential, L = static low potential A = defined active; IA = defined inactive, realised with internal or external pull up or pull down

Table 34, IC EMC specification, IC type with CPU, Emission

NOTES

75

IC type with CPU, Immunity

Injection point Monitoring Test method Pin

Pin

Type

(g

loba

l/loc

al)

Conf

igur

atio

n M

ode*

Oper

atio

n M

ode*

Monitoring pins

Failu

re c

riter

ia

DPI

TEM

No.

Nam

e

Func

tion

Port

IC fu

nctio

n m

odul

e

No.

Nam

e

Func

tion

CW AM C

W AM

Reset Regional Input local

C1 S2 I/O Port 1 III C1 S2 Reset 2 III PLL configuration pins

PLL-

freq1..x Regional

Input local C1 S2 CLK out or

toggling port

1 III

III III

Oscillator Xtal1

Osc local

C12 S3 CLK out or

toggling port

1 III

Xtal2 local III

Supplies

Vcc_core1..x Supply global C1 S2 I/O Port 1 III

Vcc_osc Supply global C12 S3 CLK out or

toggling port

1 III

Vcc_I/O Supply global C5 S3 I/O Port 1 III Supply global

* Note: T = Toggle; H = static high potential, L = static low potential A = defined active; IA = defined inactive, realised with internal or external pull up or pull down

Table 35, IC EMC specification, IC type with CPU, Immunity

Failure criteria

No. Description Tolerance 1 Toggling port toggling, constant frequency 2 Voltage at pin as specified in data sheet

Table 36, IC EMC specification, IC type with CPU, Failure criteria

ANNEXES

76

Annex F Calculation of pin specific limits (general, informative)

Fourier transformation of time domain signals

Toggling digital data pins or periodically switching analogue power outputs generate switching harmonics as a matter of principle defined by the functional necessary and specified signal waveform.

The resulting harmonics of those wanted signal waveforms can be calculated with Fourier-transformation. For trapezoidal periodic signals as shown in Figure 38, the envelope of the resulting amplitude versus frequency spectrum can be subdivided into 3 sections. From the fundamental frequency of the signal up to the first corner frequency fg1 the spectral response is parallel with the frequency axis. After the first corner frequency fg1 the amplitudes diminish by 20dB/decade up to the second corner frequency fg2, from which point the spectrum falls off at 40dB/decade, as shown in Figure 39. The simplified equations to calculate amplitudes and corner frequencies of the spectrum are depicted for the sections in Figure 39. AO is defined as the amplitude of original signal (I or V), ti as the signal pulse width, ts as the switching time, TO as the period of the fundamental frequency and n as the multiples of the fundamental frequency.

Figure 38, periodical trapezoidal signal, time domain

Periodical Trapezodial Signal - Frequency Domain

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

0,1 1 10 100 1000

Frequency

[Am

plitu

de] d

B

0 dB

-20 dB

-40 dB

fg1

fg2

Figure 39, Fourier Analysis of periodical signals (simplified calculation)

sn

tT

nAA 0

220

12π

≈

sg

tf

π1

2 =i

gt

fπ1

1 =

nAAn 12

0π

≈

0

02TtAA i

n ≈

NOTES

77

Notes:

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