George Mason University ECE 448 FPGA and ASIC Design with VHDL FPGA Design Flow based on Aldec Active-HDL FPGA Board George Mason University ECE 448 FPGA and ASIC Design with VHDL FPGA Design Flow 3ECE 448 FPGA and ASIC Design with VHDL Design flow (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds.. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis 4ECE 448 FPGA and ASIC Design with VHDL Design flow (2) Implementation Configuration Timing simulation On chip testing 5 Tools used in FPGA Design Flow Synplicity Synplify Pro Synplicity Synplify Pro Design Synthesis Implementation Xilinx ISE VHDL code Netlist Bitstream Xilinx XST Functionally verified VHDL code George Mason University ECE 448 FPGA and ASIC Design with VHDL Synthesis 7ECE 448 FPGA and ASIC Design with VHDL Synthesis Tools and others Synplify Pro Xilinx XST 8ECE 448 FPGA and ASIC Design with VHDL architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1 n67, A => D1, B => D0); U32 : IV port map( Z => n68, A => n67); U33 : EOP port map( Z => n69, A => D6, B => D7); U34 : EO3 port map( Z => n70, A => D3, B => D2, C => D4); U35 : EO port map( Z => n72, A => D5, B => n70); U36 : EOP port map( Z => XOR8, A => n72, B => n71); U37 : FA1A port map( S => n73, CO => n76, CI => D3, A => D2, B => FF); U38 : EO3 port map( Z => n74, A => n68, B => n73, C => D4); U39 : EOP port map( Z => FF_COMB_OUT, A => D5, B => n74); end structural; George Mason University ECE 448 FPGA and ASIC Design with VHDL Celoxica RC10 FPGA Board 40ECE 448 FPGA and ASIC Design with VHDL 41ECE 448 FPGA and ASIC Design with VHDL 42ECE 448 FPGA and ASIC Design with VHDL 43ECE 448 FPGA and ASIC Design with VHDL 44ECE 448 FPGA and ASIC Design with VHDL 45ECE 448 FPGA and ASIC Design with VHDL Joystick needs to be debounced (you can use circuit from experiment 2) input output DD clock cycles 47ECE 448 FPGA and ASIC Design with VHDL Piezo Buzzer Outputted signals should be 50% duty square waves, meaning the signal is high and low for equal amounts of time. 48 Demo 49 Exp.2: Part 2 Programmable (joystick) timer (counter + clock divider) with alarm (buzzer). 50ECE 448 FPGA and ASIC Design with VHDL Questions? 51ECE 448 FPGA and ASIC Design with VHDL Hands-on Session Enough Talking Lets Get To It !!Brace Yourselves!!