takeshi miyajima, aldec japan k.k. · pdf file•uvm/hdl training ... . 11 . design and...

Takeshi Miyajima, Aldec Japan K.K.

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Agenda

Aldec Overview Co-verification with algorithm and system

development environment (simulator and actual hardware)

Documentation and graphical design entry Functional verification with simulator and hardware

assisted environment Utilization of RTAX/RTSX prototyping board

© 2012 Aldec, Inc. Company Confidential.

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Aldec Overview

Founded 1984

Privately Held, Profitable

Employees 190+

Over 34,000 Licenses Worldwide

Several Key Technology Patents

Markets Segments: Military/Defense Aerospace Telecommunications Safety Critical (Avionics/Nuclear/Automotive/Rail) Industrial

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Customers


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Market/Product Roadmap


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Design/ Simulation

VHDL and Verilog

Design Entry, Requirements

Traceability and Simulation

Active-HDL Riviera-PRO

ALINT

Functional Verification

SystemVerilog, HDLs, PSL

ABV, UVM, FC, Constrained

Randomization, HW Acceleration

Riviera-PRO HES-DVM

Platform Validation

System Hardware and Software co-

validation

Emulation, HW Prototyping and Virtual Platforms

HES-DVM HES-7

RTAX/RTSX

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Design/ Simulation

VHDL and Verilog

Design Entry, Requirements

Traceability and Simulation

Active-HDL Riviera-PRO

ALINT

› Target Customer › FPGA graphical design entry and HDL simulation › Tests are FPGA and Unit level to validate the RTL code › Mapping Design Requirements to the HDL code and System Level › HDL Code quality checking (linting)

› Typical Designs › VHDL, Verilog or Mixed (Text or Graphical) › IP Cores or FPGA system

Hardware (HDL)Designer

Software (C/C++)Programmer


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Functional Verification

SystemVerilog, HDLs, PSL

ABV, UVM, FC, Constrained

Randomization, HW Acceleration,

Riviera-PRO HES-DVM

› Target Customer › System Level Testing – batch and GUI modes › Functional Verification – Assertions › Functional Coverage (FC) with Constrained Randomization (CR) › Hardware-assisted Verification (RTL Acceleration - HW in the Loop)

› Typical Designs › VHDL, Verilog testbench › SystemVerilog testbench with CR and FC › UVM, OVM and VMM › OS-VVM for VHDL › Assertions based triggers › FPGA and ASIC




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Platform Validation

Hardware and Software co-

validation

Emulation, Prototyping and Virtual Platforms

HES-DVM HES-7

RTAX/RTSX

› Target Customer › System Integrators and Firmware engineers › Require At-Speed Prototyping (real time inputs, MHz requirements,

Virtual platforms and processors) › C/C++ designers seeking early access to the HW Design

› Typical Design › SoC (processor based) › ASIC › Space




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Vertical Markets 10

Compliance/ Standards

• Avionics (DO254/ED80)

• Nuclear (IEC61508)

• Automotive • Rail Roads

Prototyping

• ASIC (Virtex7/2000T’s Boards)

• Space (RTAX/RTSX Adaptors)

Services

• SCEMI Transactors

• Customer Design

• UVM/HDL Training


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Design and Verification Flow 11

VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping

System Specification

System Validation

System Partitioning


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Co-verification with algorithm and system development environment

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VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping


System Validation

System Partitioning


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Aldec provide 3 types MATLAB interface


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Simulink interface

MATLAB direct interface

MATLAB to Hardware in loop test

MATLAB

Simulink PCI-Driver HES-API MATLAB-API

Run MATLAB from AHDL/RPRO

Run AHDL/RPRO from Simulink

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Simulink interface

Compare simulation result of HDL design accuracy in Simulink environment

Ability to analysis and visualization of simulation result in Simulink

Direct connection to Synplify DSP and Xilinx System Generator blocks Test of HDL source generated from

both tools Generate testbench for standalone

HDL simulation

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Simulink interface use case

Rich Simulink libraries to generate input stimulus and testbench for HDL block

Compare, Analysis and visualization of each simulation results Reuse HDL source to Simulink block Compare Simulink floating point operation

vs. FPGA hardware fixed point operation Control HDL simulation run/stop at Simulink environment Reuse test vectors generated by Simulink for standalone HDL

simulation Automatic rerun by batch file, when HDL source code changed

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MATLAB direct Interface

Exchange of scalar and array data between Riviera-PRO/Active-HDL – MATLAB Visualization of HDL Simulation

(statistics/Spectrum analysis) Generate complex stimulus

for HDL testbench Described high level abstraction

for a part of design unit Post-processing by MATLAB

after HDL simulation Provide VHDL procedure and Verilog function for

MATLAB direct Interface

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MATLAB direct Interface use case

Call MATLAB m file from HDL testbench Create complex input data/stimulus

Display and analysis in MATLAB for output Analog/Image/Video data

Use MALTLAB model instead of HDL model Run System Level Simulation before HDL creation

Available rich HDL debug features Assertion, code coverage, Waveform

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MATLAB Hardware in Loop Test MATLAB as testbench for FPGA Prototyping

DUT and TB Computing intensive algorithm implemented in the FPGA (running at MHz) MATLAB works as a testbench

INTERFACE MATLAB files wrappers for HES-Proto API

BENEFITS RTL IP (VHDL/Verilog) acceleration in FPGA while the rest of the system is

simulated in MATLAB Early prototype validation in FPGA with power of MATLAB

Hardware Board

C/C++ low level API

Algorithm

in FPGA

SW/HW

Wrapper

MATLAB files wrappers

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MATLAB Hardware in Loop Test use case

Fastest HDL Simulation Direct test vector input from MATLAB to FPGA Accessible FPGA board(PCIe) on PC via network Quickly change FPGA design by bit data download Hardware in Loot Test for high reliability apprications

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Documentation and graphical design entry 20

VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping


System Validation

System Partitioning


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Documentation and graphical design entry 21

VISUALIZE • Abstract design intelligence and convert it to schematic. • Create a textual and graphical representation of your

workspace or design.

LEARN • Design status report – collect detailed information about a user

workstation, design, libraries, statistics of line count, flow manager settings, synthesis and/or implementation results

SHARE • Auto-generate HTML & PDF documentation with all the design

details. Export waveform to graphics for easy sharing between peers


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Design Documentation

Entire workspace, individual designs or files can be printed or exported to vector PDF

The HTML document closely Resembles Active-HDL environment layout

Vector graphics and other advanced PDF options available

Graphical Design Entry documents can be accompanied by generated code

Ideal solution for design documentation

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Code2Graphics Converts HDL code into graphical representation: Block Diagrams Finite Sate Machine Editor files

Creates perfect documentation for HDL designs

Helps with debugging of large designs

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Block Diagram Editor Multi-page hierarchical

block diagrams Multidimensional arrays and

record signals supported Bottom-up and top-down

design methodologies supported

Allows mixed structural and behavioral elements

Cross probing with generated code

Handles mixed HDL designs Customizable design rules

checking Imports schematics Customizable symbols

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Finite State Machine Editor

Multiple State Machines on a single diagram

Full-Moore machines support

Hierarchical states and junctions provided for legibility

Delay states simplify control of machine timing

Advanced code generation settings

Automatic testbench generation

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Active-HDL – FPGA Vendor-Independent IDE 26


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Functional verification with simulator and hardware assisted environment

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VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping


System Validation

System Partitioning


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Traditional Hardware Verification Traditional Hardware Verification Real-time data is streaming through the design inputs Design outputs (FPGA) are connected to other components

on the board No test headers on the FPGA I/Os


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Board Under Test

FPGA

DSP

RAM

uP

Test Vectors

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Traditional Hardware Verification Challenges Ensuring RTL and Hardware

simulation results match Development of input data to

cover all the design requirements (time!)

Limited visibility and controllability on the FPGA I/Os

Preserving documentation of results

How to automate the testing environment for many test cases?

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FPGA Level Verification with DO-254 CTS At-speed verification in the target device Reusing testbench as test vectors for

in-target testing No changes in the design and testbench FPGA design and verification can be

performed immediately without the final board

Robustness testing is simplified. The DUT can be exercised with stimuli that might not be possible to re-create in the target board

Easy results capturing, analysis and documentation


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DO-254 CTS Components

COTS Mother Board

Customized Daughter Board

• Provides test vectors into daughter board “at speed”

• 1-environment to test all FPGA requirements • Samples FPGA outputs “at speed” • PCI/e interface to PC

• FPGA level verification • Customized to target FPGA and DUT • Contains target FPGA and DUT

DO-254 CTS CVT (Software) • Converts final testbench into test vectors • Controls In-Hardware Verification • Writes hardware results to a waveform file

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Traditional Hardware Testing Methods vs. DO-254 CTS

Traditional Hardware Verification

Aldec’s DO-254 CTS Approach

Input Type Real Data RTL Test Vectors

Verification Type At Speed At Speed

Target Device Yes Yes

Test Data Generation Manual engineering time required Automatic, no additional development required

Test Environment Setup Manual connections of wires and cables

PCIe based Hardware Boards

FPGA I/O Access Limited controllability Complete controllability and visibility

Output Format From Logic Analyzer, Oscilloscope RTL Simulator Waveform Format

RTL and Hardware Results Comparison

Limited Easy and automated

Result Documentation Manual documentation Automatically generated waveform and PDF export

FPGA Device Verification Time

Manual Process and takes months to complete, thus development cost is very high

Automated process and only takes weeks to complete, thus development cost is reduced substantially

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Aldec’s Additional DO-254 Solutions

• Common-Kernel Mixed Language Simulator • VHDL 2008 • Graphical Entry - Block Diagram and State Machine • Coverage and Assertions

Active-HDL RTL Design and Simulation

• DO-254 Best Practice HDL Design Rules • Custom Rules creation • Tracking, Results Analysis, Reporting • Design and library management

ALINT Design Rule Checking

• Tool Qualification Package for Active-HDL Code Coverage

• Including Test Cases and Documentation (Tool Operational Requirements, Tool Test Plan, etc)

Code Coverage Tool Qualification

Package

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Utilization of RTAX/RTSX prototyping board 34

VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping


System Validation

System Partitioning


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HES-7 ASIC Prototyping HES-7 with Virtex-7 Utilizes industry’s largest FPGAs – V7 2000ts Dual HES-7 can accommodate up to 24m ASIC gates! Using a conservative 6x logic cell to ASIC gate conversion Competition has over-inflated capacity – we use the same FPGAs

Offers scalable configuration and flexible expansion With four single-board capacity product configurations 4m to 24m ASIC gates

Using non-proprietary backplane connector for expansion to: Daughter boards Multi-HES-7 boards (expands capacity to 96m ASIC gates)

Aggressive product prices Reduces design partitioning 2 FPGAs can be used instead of 6 FPGAs Which produces higher performing designs Enables lower cost of “bring-up” effort


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HES-7 Top View


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HES-7 Bottom View


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JTAG Connector

Micro SD Socket

SO-DIMM DDR3 Memory Socket

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Utilization of RTAX/RTSX prototyping board

Ability to prototype RTAX-S/SL and RTSX-SU designs using re-programmable Microsemi Flash ProASIC®3E FPGA family chips

Adaptor board is footprint-compatible with the final RTAX-S/SL and RTSX-SU device

Programming connector (JTAG) allows on-the-fly reprogramming of the device without detaching the adaptor from the target PCB

EDIF netlist converter allows to migrate from RTAX-S/SL and RTSX-SU to ProASIC 3E FPGA easily

Design efficiency is achieved, saving Development Time and Costs

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Aldec Complementary Design Flow 39

No throwaways!

Synthesize and Implement for flight FPGA

Final Hardware Tests

Y

Synthesize and Implement for ProASIC3 FPGA

Test in Hardware: Results OK?

Modify and Verify Design Code

N

Preferred flow for PURE HDL Designs

Create and Verify Design Code


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Sample RTAX-S/SL Adaptor Board

ACT-H3K-CG624 Adaptor Adaptor size: 32.5mm x 34mm The following elements reside on

the top part of the adaptor Microsemi ProASIC3E FPGA

device, A3PE3000-FGG896 (or A3PE3000-2FGG896I)

JTAG connector Capacitors, resistors

The following elements reside on the bottom part of the adaptor Leads that mimic CG624 package

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Capacitors

A3PE3000-FGG896

JTAG Connector

Ball grid array that mimics CG624 package


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Sample RTSX-SU Adaptor 41

Mother Board of ACT-RTSX-CQ256 adaptor: • Top side with visible Microsemi ProASIC3E device

(A3PE600-FGG484 or A3PE600-2FGG484I) • Bottom side with leads mimicking CQ256 package

Mother board and daughter board of ACT-RTSX-CQ256 adaptor in stacked configuration


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Available Adaptors

ALDEC is constantly extending the assortment of adaptors RTAX-S/SL adaptor boards are available in the following

footprint layouts: Commercial grade: CQ208, CQ256, CQ352, CG624, CG1272 Industrial grade: CQ208, CQ256, CQ352, CG624

RTSX-SU adaptors are available in the following footprints: Commercial grade: CQ208, CQ256, CG624 Industrial grade: CQ208, CQ256, CG624

Save Development Time – “Re-Programmability” Footprint compatible adaptors Customer proven with over 300 units shipped worldwide

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Summary Aldec fill in the gap for Radiation Tolerant FPGA design

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VHDL/Verilog HDL

FPGA Compile

Simulation

C/C++

ASM

MATLAB Production

System Integration

FPGA Prototyping


System Validation

System Partitioning


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Q & A 44

Riviera-PRO™ Advanced Verification Platform

Active-HDL™ FPGA Design and Simulation

ALINT™ Design Rule Checking

HES™ Hardware Emulation Solutions

DO-254/CTS™ FPGA Level In-Target Testing

HES-7™ ASIC Prototyping

Microsemi™ Prototyping RTAX/RTSX

Aldec Japan K.K. Stella Shinjuku 7F 2-1-9 Shinjuku, Shinjuku-ku, Tokyo, Japan

+81-3-5312-1791 [email protected] N. America [email protected] Europe [email protected] Israel [email protected] Japan [email protected] China [email protected] India [email protected] Taiwan [email protected]

www.aldec.com/jp

www.youtube.com/AldecInc www.twitter.com/Aldec_Japan


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http://www.aldec.com/jp

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takeshi miyajima, aldec japan k.k. · pdf file•uvm/hdl training ... . 11 . design and...

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