Upload File

gpu design on fpga

61
CSIR-NAL MTech Project Review 1 CSIR-NAL By SG Ramanathan MTech Thesis Project Final Submission External Review

Upload: ramanathan-sg

Post on 21-Feb-2017

143 views

Category:

Design


3 download

Report

TRANSCRIPT

PowerPoint Presentation

BySG Ramanathan MTech Thesis Project Final Submission External Review

CSIR-NAL

CSIR-NALMTech Project Review#

9/04/2015

Title of Project Thesis Design and Development of Graphics Processing Unit (GPU) Framework on FPGATarget FPGA - Spartan-6 XC6SLX45T-3FGG484Internal GuideMr. JAYAKUMAR EPAsst. ProfessorDepartment of ECENIT, CalicutExternal GuideDr. ANANDA CMSr. Principal ScientistHead, Aerospace Electronics Systems DivisionCSIR-NAL, Bangalore

CSIR-NALMTech Project Review# AgendaScope & Objective of the ProjectSystem OverviewTriple Video BuffersDDR3 Memory Controller IntegrationHost Application DevelopmentResults & ConclusionSummaryRendering AlgorithmVideo DemonstrationDesign Blocks Interface

CSIR-NALMTech Project Review# Scope & Objective Of ProjectDevelop GPU Frame Work FunctionalitiesFPGA VHDLTriple Video Buffer Mechanism Display Graphics Controller DesignDevelop Rendering AlgorithmHost Application C ProgramCommand Generation

LCD DisplayDesign OutputSocket ProgrammingUDP Packet Decoder

CSIR-NALMTech Project Review#

UDP DecoderPixel Color/Command HandlerDDR3 MemoryTriple Buffer HandlerDisplay Controller

Typical GPU InterfacesTop-Level FPGA BlocksHost MachineDisplay System

Frame Rendering: Converting Numeric Coordinates into bitmapsGraphics Controller: Converting Bitmaps into signals for screen with control signals based on the chosen resolution

Buffer Management: Frame Buffering using Triple Display Buffers

CSIR-NALMTech Project Review# System OverviewTEMAC CoreFIFO[FWFT]

UDP Decoder

ARP Packet Transmitter

Colour Data/ CommandHandler [MIG Wrapper]

MIG Core

Flush Buffer Logic

FIFO[FWFT]

Display Buffer Logic

FIFO[STD]XGA Display Controller

DDR3 Memory

Rasterization Programming in Host MachineTEMAC InterfaceCommand MemoryInterfaceMIG Interface & Triple Buffer ImplementationDisplay ControllerReview#1Review#2Review#3

Xilinxs TEMAC - Tri-Mode Ethernet Media Access Controller

CSIR-NALMTech Project Review# Display Controller Design & its Simulation Results

CSIR-NALMTech Project Review# XGA_GeneratorClk_65RGB

HSyncVSync

DDR3 Memory

RGB with control signals generated for fixed pattern/colorDisplay pixels has been feed from DDR3 memory

Graphics Controller: Converting Bitmaps into signals for screen with control signals for chosen resolutionPixel Mapping: Each Pixel of the screen mapped to a DDR3 memory locationActive Data

CSIR-NALMTech Project Review# Simulation Result#1: Display Controller Design

RGB Data in Active Region

CSIR-NALMTech Project Review# DDR3 Memory Controller Integration & its Simulation Results

CSIR-NALMTech Project Review# DDR3 Memory Read & Write BlocksInput WrapperOutput Wrapper

Spartan6 FPGA MIG WrapperMemory Controller CORECmd_FIFODATAFIFO

DDR3 Memory

Memory Interface is a free software tool used to generate memory controllers and interfaces forXilinxFPGAs

Top Design

Read & Write LogicsXilinxs Memory Interface Controller

Physical Component in BoardCommand FIFO holds Starting Address & Length of DataData FIFO holds Pixel color (RGB)

CSIR-NALMTech Project Review# FSM for DDR3 Memory AccessSTARTInitialize all Counters/RegisterMemory Calibration StatusSend Command to Controller for Writing to DDR3Controllers Data FIFO EmptyWrite into Data FIFOIncrement Address to Next LocationWrite Finish StatusSTOPCompletedNot CompletedEmptyNot EmptyFinishedNot FinishedSTARTInitialize all Counters/RegisterMemory Calibration StatusSend Command to Controller for Reading DDR3Controllers Data FIFO FullRead Data FIFO ContentIncrement Address to Next LocationRead Finish StatusSTOPCompletedNot CompletedFULLNot FULLFinishedNot FinishedWRITEREAD

CSIR-NALMTech Project Review#

Simulation Result#2: DDR3 Memory Write Sequence

64 colorsCommand64 colorsCommand64 colorsCommand

CSIR-NALMTech Project Review# Simulation Result#3: DDR3 Memory Read Sequence

Command

64 colors

Command

64 colors

CSIR-NALMTech Project Review# Triple Video Display Frame Buffer Design

CSIR-NALMTech Project Review# DDR3 Memory

GPU Engine

1 Operational BufferWhat is Triple Display Frame Buffer?

Frame BufferDisplay

3 Display Buffers

Operational Buffer: Dedicated Buffer for drawing the frame contentDisplay Buffers: Buffer the frame for display

CSIR-NALMTech Project Review# Triple Display Buffer Design How It Works?

Operational Buffer Memory RegionDisplay Buffer1Display Buffer2Display Buffer3

Port 2Colour Data/ Command Handler

Port 5Tri-Buffer Display Wrapper

Port 3Port 4Flush Logic WrapperOn Vsync_TriggerOn Flush TriggerXGA VideoGenerator

Operational Buffer: Dedicated Buffer for drawing the frame contentDisplay Buffers: Buffer the frame for display

CSIR-NALMTech Project Review# Generally, GPU generates 24 FPS, its very hard to witness the function of triple buffer operation.9/04/2015

Top DesignPORT_2

PORT_3

PORT_4

PORT_5

RGB

Input WrapperTri_Buffer_DisplayOutput FIFOFlush LogicClock Infrastructure

Spartan 6FPGA WrapperMemory Controller CORECmd_FIFODATAFIFO

Clk_200

All Clock Signals for Memory Controller DesignClock Gen IPClk_125Clk_65Clk_333.33DDR3 MemoryClk_333.33

XGA_Generator

FLUSH

Latest Buffers Base AddressVsync_Pulse

Integrated Design with Triple Buffer - FPGA

CSIR-NALMTech Project Review# Once Vertical Sync. Triggered from controller, display buffers gets read by tri_buffer_display logic. Triple Buffering to prevent FPS drops related to enabling Vsync; help to both remove tearing while also preventing the significant FPS drop encountered when VSync is enabled9/04/2015

Host Machine Interface & Application Development

CSIR-NALMTech Project Review# Host Software Application Design FunctionsUser Inputs/Commands Rendering AlgorithmSlice PacketsChop-OffSocket ProgramCoordinates, ColourDot, Line, Arc Primitives64 Word CountIgnore Over shoot pixelsEthernet Protocol

UDP DecoderPixel Color/Command HandlerDDR3 Memory

CSIR-NALMTech Project Review# Host FPGA Ethernet InterfaceHost Machine

UDP Packet

ARP PacketFPGAHost Machine & FPGA are bonded with IP & MAC IDs

Ethernet Data Payload Structure

CSIR-NALMTech Project Review# Drawing Pixel Dots

On Screen

CSIR-NALMTech Project Review# Line is a Stair-Case

CSIR-NALMTech Project Review# Bresenhams Line Algorithm

23452435(xk, yk)(xk+1, yk)(xk+1, yk+1)

yykyk+1xk+1

dlowerdupper

Algorithm finds pixel closer to original line0


FPGA Design Automation

Computing Performance Benchmarks among CPU, GPU, and FPGA

RESEARCH Open Access Real-time tone mapping on GPU and FPGA · RESEARCH Open Access Real-time tone mapping on GPU and FPGA Raquel Ureña*, Pablo Martínez-Cañada, Juán Manuel Gómez-López,

TWO-DIMENSIONAL GRAPHICS CARD (GPU) ON AN ALTERA FPGA

FPGA Design - IIHE

CPU, GPU und FPGA - eti/Vorlesung/WS1718/Informationsmaterial/... · Maximilian Bandle CPU, GPU und FPGA CPU • Bisher in Vorlesung betrachtet • Über Assembler/Maschinensprache

Cooperative CPU, GPU and FPGA Heterogeneous …...Cooperative CPU, GPU and FPGA Heterogeneous Execution with EngineCL 3 not always followed by a reduction in energy consumption, for

Accelerated ML on cloud FPGAs · CPU vs GPU vs FPGA 23 A GPU is effective at processing the same set of operations in parallel – single instruction, multiple data (SIMD). An FPGA

Making the most out of Heterogeneous Chips with CPU, GPU and FPGA

West Coast Spectrometer Team Mark Wagner, Berkeley project manager, FPGA designer Terry Filiba, data transport: FPGA --> CPU --> GPU Suraj Gowda, boosting

GPU VS FPGA: EXAMPLE APPLICATION ON WHITE-LIGHT … · FPGA vs. GPU implementations Architectural concepts for WLI processing GPU VS FPGA: EXAMPLE APPLICATION ON WHITE-LIGHT INTERFEROMETRY

3D Tomography back- projection parallelization on FPGAs using … · GPU vs FPGA with OpenCL An embedded GPU is more energy efficient Algorithm inadequacy implies longer FPGA execution

LabVIEW FPGA and GPU

Computing Performance Benchmarks among CPU, … Performance Benchmarks among CPU, GPU, and FPGA MathWorks Authors: ... multicore CPUs, general purpose GPU computing and an FPGA, we

Accelerating a random forest classifier: multi-core, GP-GPU, or FPGA? 1

Cygnus: GPU meets FPGA for HPC - RIKEN R-CCS · 2020. 2. 27. · FPGA-GPU DMA (FPGA ← GPU) FPGA-GPU DMA (FPGA → GPU) direction via CPU FPGA-GPU DMA GPU→FPGA 17 1.44 FPGA→GPU

High performance FPGA and GPU complex pattern matching over spatio-temporal streamsnajjar/papers/2014/Geoinformatica-2014.pdf · 2014-10-27 · High performance FPGA and GPU complex

FPGA GPU Co-Design - SwissT.net...FPGA GPU Co-Design Philipp Huber ZHAW, Institute ofEmbedded Systems [email protected] nModerne Computer sind Heterogene Systeme •Verwendung von verschiedenen

FPGA Acceleration of LFRic - EMiT · • “GPU vs FPGA Performance Comparison”, Berton White Paper •GPU: 0.07-0.12 vs. FPGA: 0.23 €/Gflop/s/W •GPU: 20 vs. FPGA: 70 Gflops/W

From FPGA design to FPGA programming · 2008-11-07 · • Move from FPGA design to FPGA programming – using FPGAs “the software way” • Exploit inherent concurrency of FPGA

Accelerating Robot Dynamics Gradients on a CPU, GPU, and FPGA

Gpu vs fpga

FPGA based system design Programmable logic. FPGA Introduction FPGA Architecture Advantages & History of FPGA FPGA-Based System Design Goals

LabVIEW FPGA and GPU - Universitetet i oslo · FYS3240 PC-based instrumentation and microcontrollers LabVIEW FPGA and GPU Spring 2011 –Lecture #11 Bekkeng, 11.5.2011

FPGA Accelerated Computing Using AWS F1 Instances · 2017-09-07 · FPGA Accelerated Computing Using AWS F1 Instances. Applications and development environment. F1. ... GPU and FPGA

Synthesis of Data-Parallel GPU Software into FPGA Hardware · FPGA hardware (VHDL, ISE) GPU code (DX9) X64 multicore SSE4. universal language? embedded high level software FPGA GPU

Fpga Gpu Soc Mejorado

Convolutional Neural Networks on FPGA and GPU on the ...1447576/FULLTEXT01.pdfConvolutional Neural Networks on FPGA Linus Pettersson and GPU on the Edge: A Comparison Uppsala University

Design Fpga Modulation

5g, gpu and fpga

GPU VS FPGA: EXAMPLE APPLICATION ON WHITE …...gate arrays (FPGA) receive a growing interest as implementation platforms, hybrid implementation on FPGA and GPU for image stack processing

Computing Performance Benchmarks among CPU, GPU, and FPGA · 2.2.2. GPU Architecture and Parallelism..... 12 2.3. FPGA Background ... astonishing performance using the hundreds of

Basic Implementation of FPGA-GPU Dual SoC Hybrid

A GPU-Outperforming FPGA Accelerator Architecture for ... · 18 A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks YIXINGLI,ArizonaStateUniversity

Accelerating FPGA/ASIC Design and Verification - …matlabexpo.com/in/.../accelerating-fpga-asic-design-verification.pdf · Accelerating FPGA/ASIC Design and ... Streamline a time-consuming