Group M3Nick MarwahaCraig LeVanJacob ThomasDarren ShultzProject Manager: Zachary Menegakis February 28, 2005

MILESTONE 7 Component Layout

DSP 'Swiss Army Knife'

Overall Project Objective: General Purpose Digital Signal Processing Chip

STATUS

Design Proposal (Done) Architecture (Done) Size Estimates/Floorplan/Verilog (95%) Gate Level Design (99%) Component Layout (Done) Functional Block (50%) To Be Done

Complete layout of functional blocks• Wallace Tree Multiplier, etc.• Layout of Adder and div remain

Schematic• Make remaining adjustments for comb/Wallace• Top-level

Verification• Test adjusted blocks

DESIGN DECISIONS

LayoutRe-did XOR and FA (and others) using M2

to reduce sizeGoing to need all four layers for the fp_mult

• Not a big issue because we don’t route over them

Wallace Tree MultiplierFully implemented booth encodingAll blocks for wallace tree done to conform

to aspect ratio

MENTAL BREAK

OLD WALLACE TREE

NEW WALLACE TREE

Wallace Tree Mult

Booth Encoding – PP_Gen

TRANSISTOR COUNT

LAYOUT UPDATE - FA

LAYOUT UPDATEREG

BO

OT

H D

EC

OD

ER

LAYOUT UPDATE3

:2 C

OM

PR

ES

SO

R

CO

MP

AR

AT

OR

FLOORPLAN BEFORE

FLOORPLAN AFTER

UPDATE – TEXT VERSION

Since Wednesday @ 3pm:Craig – Worked on Booth Recoding

and floorplanDarren – Got in a car…Jake – Worked on layout (only 13hrs

straight this time)Nick – ditto

PROBLEMS & QUESTIONS

Booth Recoding Still walking through

Problem: Timing issues with top level design. Haven’t tackled yet (fixing lower blocks to avoid complications*)

Problem: Spring break We want one

* scientific method: only test one variable at a time