half and full adder using vhdl
TRANSCRIPT
Experiment No : 2
Aim: To design half adder using VHDL.
Apparatus: Xlinx 10.1 software , RAM : 512 MB
Theory:
Logical Symbols
Half Adder:
Full Adder:
HALF ADDER:
TRUTH TABLE
A B S C0 0 0 00 1 1 01 0 1 01 1 0 1
FULL ADDER:
TRUTH TABLE
A B C S1 C20 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 0
Program Code:
Half Adder
Dataflow Code
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:44:43 01/27/2011
-- Design Name:
-- Module Name: ha1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ha1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end ha1;
architecture Behavioral of ha1 is
begin
s<= a xor b;
c<= a and b;
end Behavioral;
Behavioral Code
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:44:43 01/27/2011
-- Design Name:
-- Module Name: ha1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ha1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end ha1;
architecture Behavioral of ha1 is
begin
process ( a, b)
begin
s<= a xor b;
c<= a and b;
end process;
end Behavioral;
RTL View:
Program Code:
Full Adder
Data Flow Code
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:07:02 01/27/2011
-- Design Name:
-- Module Name: FA1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FA1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S1 : out STD_LOGIC;
C2 : out STD_LOGIC);
end FA1;
architecture Behavioral of FA1 is
begin
S1<= A XOR B XOR C;
C2<= (A AND B) OR (B AND C) OR (A AND C);
end Behavioral;
Behavioral Code
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:07:02 01/27/2011
-- Design Name:
-- Module Name: FA1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FA1 is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
S1 : out STD_LOGIC;
C2 : out STD_LOGIC);
end FA1;
architecture Behavioral of FA1 is
begin
process (A,B,C)
begin
S1<= A XOR B XOR C;
C2<= (A AND B) OR (B AND C) OR (A AND C);
End process;
end Behavioral;
RTL View:
RESULT:
HENCE HALF ADDER AND FULL ADDER HAS BEEN DESIGNED USING VHDL.
RESULT:
HENCE ALL THE GATES HAVE BEEN CREATED AND STUDIED USING VHDL.