hardware description languages digital logic design instructor: kasım sinan yildirim
TRANSCRIPT
Introduction• A drawing of a circuit, or schematic,
contains graphical information about a design– Inverter is above the OR gate,
AND gate is to the right, etc. • Such graphical information may not
be useful for large designs• Can use textual language instead si
gtocontr
atapa
DoorOpener
c
hp
f
Computer-Readable Textual Language for Describing Hardware Circuits: HDLs
• Hardware description language (HDL) – Intended to describe circuits textually, for a computer to read– Evolved starting in the 1970s and 1980s
• Popular languages today include:– VHDL –Defined in 1980s by U.S. military; Ada-like language– Verilog –Defined in 1980s by a company; C-like language– SystemC –Defined in 2000s by several companies; consists of libraries in
C++
Describing Structure in VHDLDoorOpener
c
h
p
f
AND2_1OR2_1
Inv_1
n2
n1
(a)
(b) (c)
We'll now describe a circuit whose name is DoorOpener. The external inputs are c, h and p, which are bits. The external output is f, which is a bit.
We assume you know the behavior of these components: An inverter, which has a bit input x, and bit output F. A 2-input OR gate, which has inputs x and y, and bit output F. A 2-input AND gate, which has bit inputs x and y, and bit output F.
The circuit has internal wires n1 and n2, both bits.
The DoorOpener circuit internally consists of: An inverter named Inv_1, whose input x connects to external input c, and whose output connects to n1. A 2-input OR gate named OR2_1, whose inputs connect to external inputs h and p, and whose output connects to n2. A 2-input AND gate named AND2_1, whose inputs connect to n1 and n2, and whose output connects to external output f.That's all.
library ieee;use ieee.std_logic_1164.all;entity DoorOpener isport ( c, h, p: in std_logic;
f: out std_logic );end DoorOpener;
architecture Circuit of DoorOpener iscomponent Invport (x: in std_logic;
F: out std_logic);end component;component OR2port (x,y: in std_logic;
F: out std_logic);end component;component AND2port (x,y: in std_logic;
F: out std_logic);end component;signal n1,n2: std_logic; --internal wires
begin Inv_1: Inv port map (x=>c, F=>n1); OR2_1: OR2 port map (x=>h,y=>p,F=>n2); AND2_1: AND2
Describing Combinational Behavior in VHDL
• Describing an OR gate's behavior– Entity defines input/output ports– Architecture
• Process – Describes behavior– Behavior assigns a new value to
output port F, computed using built-in operator "or"
library ieee;use ieee.std_logic_1164.all;
entity OR2 isport (x, y: in std_logic;
F: out std_logic );
end OR2;
architecture behavior of OR2 isbegin
process (x, y)begin
F <= x or y;end process ;
end behavior;
• Describing a custom function's behavior– Desired function: f = c'*(h+p)
architecture beh of DoorOpener isbegin
process (c, h, p) begin
f <= not (c) and (h or p);end process ;
end beh;
Testbenches• Testbench
– Assigns values to a system's inputs, check that system outputs correct values
– A key use of HDLs is to simulate system to ensure design is correct
SystemToTest
Testbench
Set input values, check
output values
Testbench in VHDL• Entity
– No inputs or outputs• Architecture
– Declares component to test, declares signals
– Instantiates component, connects to signals
– Process writes input signals, checks output signal
• Waits a small amount of time after writing input signals
• Checks for correct output value using "assert" statement
library ieee;use ieee.std_logic_1164.all;
entity Testbench isend Testbench;
architecture behavior of Testbench iscomponent DoorOpener
port ( c, h, p: in std_logic; f: out std_logic );
end component;signal c, h, p, f: std_logic;
begin DoorOpener1: DoorOpener port map (c,h,p,f);
processbegin
-- case 0 c <= '0'; h <= '0'; p <= '0';
wait for 1 ns;assert (f='0') report "Case 0 failed";
-- case 1 c <= '0'; h <= '0'; p <= '1';
wait for 1 ns;assert (f='1') report "Case 1 failed";
-- (cases 2-6 omitted from figure) -- case 7 c <= '1'; h <= '1'; p <= '1';
wait for 1 ns;assert (f='0') report
SystemToTest
Testbench
Set input values, check
output values
process
DoorOpener1
Describing a Full-Adder in VHDL• Entity
– Declares inputs/outputs• Architecture
– Described behaviorally (could have been described structurally)
– Process sensitive to inputs– Computes expressions, sets
outputs
library ieee;use ieee.std_logic_1164.all;
entity FullAdder isport ( a, b, ci: in std_logic;
s, co: out std_logic );end FullAdder;
architecture behavior of FullAdder isbegin
process (a, b, ci)begin
s <= a xor b xor ci; co <= (b and ci) or (a and ci) or (a and
s = a xor b xor cico = bc + ac + ab
co
ciba
s
Full adder
9
Describing a Carry-Ripple Adder in VHDL
• Entity– Declares inputs/outputs– Uses std_logic_vector for 4-bit
inputs/outputs• Architecture
– Described structurally by composing four full-adders (could have been described behaviorally instead)
– Declares full-adder component, instantiates four full-adders, connects
• Note use of three internal signals for connecting carry-out of one stage to carry-in of next stage
library ieee;use ieee.std_logic_1164.all;
entity CarryRippleAdder4 isport ( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0); ci: in std_logic; s: out std_logic_vector(3 downto 0); co: out std_logic );end CarryRippleAdder4;
architecture structure of CarryRippleAdder4 iscomponent FullAdder
port ( a, b, ci: in std_logic; s, co: out std_logic );
end component;signal co1, co2, co3: std_logic;
begin FullAdder1: FullAdder
port map (a(0), b(0), ci, s(0), co1); FullAdder2: FullAdder
port map (a(1), b(1), co1, s(1), co2); FullAdder3: FullAdder
a3
co s
FA
co
b3 a2 b2
s3 s2 s1
ciba
co s
FA
ciba
a1 b1
co s
FA
ciba
s0
a0 b0 ci
co s
FA
ciba
co1co2co3
Describing a 4-bit Register in VHDL• Entity
– 4 data inputs, 4 data outputs, and a clock input
– Use std_logic_vector for 4-bit data• I: in std_logic_vector(3 downto 0)• I <= "1000" would assign I(3)=1, I(2)=0,
I(1)=0, I(0)=0
• Architecture– Process sensitive to clock input
• First statement detects if change on clock was a rising edge
• If clock change was rising edge, sets output Q to input I
• Ports are signals, and signals store values – thus, output retains new value until set to another value
library ieee;use ieee.std_logic_1164.all;
entity Reg4 is port ( I: in std_logic_vector(3 downto 0); Q: out std_logic_vector(3 downto 0); clk: in std_logic );end Reg4;
architecture behavior of Reg4 isbegin
process(clk)begin
if (clk='1' and clk'event) then Q <= I;
end if
11
Describing an Up-Counter in VHDL
• Described structurally (could have been described behaviorally)
• Includes process that updates output port C whenever internal signal tempC changes– Need tempC signal because
can't read C due to C being an output port
ld4-bit register
Ctc
4
4 4
4
cnt
4-bit up-counter
+1
library ieee;use ieee.std_logic_1164.all;
entity UpCounter isport ( clk: in std_logic;
cnt: in std_logic; C: out std_logic_vector(3 downto 0); tc: out std_logic );end UpCounter;
architecture structure of UpCounter iscomponent Reg4
port ( I: in std_logic_vector(3 downto 0); Q: out std_logic_vector(3 downto 0); clk, ld: in std_logic );
end component; component Inc4
port ( a: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0) );
end component;component AND4
port ( w,x,y,z: in std_logic; F: out std_logic );
end component;signal tempC: std_logic_vector(3 downto 0);signal incC: std_logic_vector(3 downto 0);
begin Reg4_1: Reg4 port map(incC, tempC, clk, cnt); Inc4_1: Inc4 port map(tempC, incC); AND4_1: AND4 port map(tempC(3), tempC(2),
tempC
Describing an Oscillator in VHDL
• Entity– Defines clock output
• Architecture– Process
• Has no sensitivity list, so executes non-stop as infinite loop
• Sets clock to 0, waits 10 ns, sets clock to 1, waits 10 ns, repeats
library ieee;use ieee.std_logic_1164.all;
entity Osc isport ( clk: out std_logic );
end Osc;
architecture behavior of Osc isbegin
processbegin
clk <= '0';wait for 10 ns;
clk <= '1';wait for 10 ns;
Describing a Controller in VHDL
Inputs: b; Outputs: x
On2On1 On3
Off
x=1x=1x=1
x=0
b’
b
library ieee;use ieee.std_logic_1164.all
entity LaserTimer isport (b: in std_logic;
x: out std_logic; clk, rst: in std logic );end LaserTimer;
architecture behavior of LaserTimer istype statetype is
(S_Off, S_On1, S_On2, S_On3);signal currentstate, nextstate:
statetype;begin statereg: process(clk, rst)
beginif (rst='1') then -- intial state
currentstate <= S_Off;elsif (clk='1' and clk'event) then
currentstate <= nextstate;end if;
end process;
comblogic: process (currentstate, b)begin
case currentstate iswhen S_Off =>
x <= '0'; -- laser offif (b='0') then
nextstate <= S_Off;else
nextstate <= S_On1;end if;
when S_On1 => x <= '1'; -- laser on nextstate <= S_On2;
when S_On2 => x <= '1'; -- laser still on nextstate <= S_On3;
• FSM behavior captured using architecture with 2 processes
– First process models state register• Asynchronous reset sets state to "S_Off"• Rising clock edge sets currentstate to nextstate
– Second process models combinational logic• Sensitive to currentstate and FSM inputs• Sets FSM outputs based on currentstate• Sets nextstate based on currentstate and present
FSM input values– Note declaration of new type, statetype
Combinationallogic
State register
s1 s0
n1
n0
xb
clkFS
Min
puts
FSM
outp
uts
Summary• Hardware Description Languages (HDLs) are widely used in
modern digital design– Textual rather than graphical language sufficient for many
purposes– HDLs are computer-readable– Great for simulation
• VHDL, Verilog, and SystemC are popular• Introduced languages mainly through examples• Numerous HDL books exist to teach each language in more
detail