hardware summary - oregon state universityoregonstate.edu/instruction/ece573/hw_summary.pdf · •...

ECE473/573Microprocessor System Design, Dr. Shiue

1

Hardware Summary


2

Introduction

• The MCS-51 is a family of microcontroller ICs developed, manufactured, and marketed by Intel. Other IC manufacturers are – Siemens, Advanced Micro Devices (AMD), Fujitsu, Philips are licensed

‘second source’ suppliers of devices in the MCS-51 family.

• The generic MCS-51 IC is the 8051, the first device in the family offered commercially. Its features are summarized – 4KB ROM (64KB external code memory space)– 128B RAM (64KB external data memory space)– 8-bit I/O ports (4EA)– 16-bit timers (2EA)– Serial interface– Boolean processor– 210 bit-addressable locations– 4 ? s multiply/divide


3

Comparison of MCS-51 ICs

3256B8K EPROM8752

3256B8032

3256B8K ROM8052

2128B4K EPROM 8751

2128B8031

2128B4K ROM8051

TimersRAMROM/EPROMPart No.


4

8051 Block Diagram

Oscillator

CPU

Interrupt Control

INT1INT2

Timer 1Timer 0

Serial port

Other registers

128B RAM

4KB ROM

Timer 1

Timer 0

Bus Control

I/O ports Serial port

T1

T0

ALEPSEN

RSTEA

P0 P1 P2 P3 TXD RXD

Address/data

Note: bold-faced pin assignments for P1 and P3.


5

8051 Pinouts

VSS(20)

VCC (40)

P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

RD(17)WR(16)T1(15)T0(14)INT1(13)INT0(12)TXD(11)RXD(10)

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0

AD7(32)AD6(33)AD5(34)AD4(35)AD3(36)AD2(37)AD1(38)AD0(39)

P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0

(8)(7)(6)(5)(4)(3)(2)(1)

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0

A15(28)A14(27)A13(26)A12(25)A11(24)A10(23)A9(22)A8(21)

PSENALEEARST

(29)(30)(31)(9)

XTL1 (19)

XTL2 (18)

30pF

30pF

8051

Port 0

Port 1

Port 2Port 3


6

I/O Ports

• 32 of the 8051’s 40 pins function as I/O port lines. However, 24 of these 32 lines are dual-purpose. – Dual purpose: can operate as I/O, control line, or part of

address/data bus.– The 8-line in a port can be treated as a unit in interfacing to parallel

devices such as printers, A/D converters, and so on. – Or, each line can operate independently in interfacing to single-bit

devices such as switches, LEDs, transistors, motors, and loudspeakers.


7

I/O Ports• Port 0

– Is a dual-purpose port on pins 32-39 of the 8051 IC. – In minimum-component designs,

• It is used as a general purpose I/O port.

– For larger designs with external memory, • It becomes a multiplexed address and data bus.

• Port 1– Is a dedicated I/O port on pins 1-8. – The pins are available for interfacing to external devices as required.

• Port 2– Is a dual-purpose port on pins 21-28 of the 8051 IC. – As a general purpose I/O port – Or as the high-byte of the address bus for designs with external ROM or

more than 256B of RAM.


8

I/O Ports• Port 3

– Is a dual-purpose port on pins 10-17 of the 8051 IC.– As a general purpose I/O port – These pins are multifunctional, with each having an alternate purpose related

to special features of the 8051.

Timer/counter 2 capture/reload91HT2EXP1.1

Timer/counter 2 external input90HT2P1.0

External data memory read strobeB7HRDP3.7

External data memory write strobeB6HWRP3.6

Timer/counter 1 external inputB5HT1P3.5

Timer/counter 0 external input B4HT0P3.4

External interrupt 1B3HINT1P3.3

External interrupt 0B2HINT0P3.2

Transmit data for serial portB1HTXDP3.1

Receive data for serial portB0HRXDP3.0

functionsBIT addressNAMEBIT


9

Control Signals

• PSEN (Program Store Enable)– Is an output signal on pin 29.– It is a control signal that enables external program (code) memory

(ROM).– It usually connects to an EPROM’s output enable (OE) pin to

permit reading of program bytes.– The PSEN signal pulses low (active stage) during the fetch stage of

an instruction, which is stored in external program memory. – The binary codes of a program (opcode) are read from EPROM,

travel across the data bus, and are latched into the 8051’s instruction register (IR) for decoding.


10

Control Signals

• ALE (Address Latch Enable)– Is an output signal on pin 30.– It is used for demultiplexing the address and data bus.– When port 0 is used in its alternate mode – as the data bus and

low-byte of the address bus – ALE is the signal that latches the address into an external register during the first-half of a memory cycle. This done, the port 0 lines are then available for data input or output during the second-half of the memory cycle, when the data transfer takes place.

– The ALE signal pulses at 1/6th the on-chip oscillator frequency and can be used as a general-purpose clock for the rest of the system.


11

Control Signals

• EA (External Access)– Is an input signal on pin 31.– Is generally tied high (5V) or low (ground). – If high

• The 8051 executes programs from internal ROM when executing in the lower 4K/8K of memory.

– If low• Programs execute from external memory only (and PSEN pulses low)

• RST (Reset)– Is an input signal on pin 9.– When this signal is brought high for at least 2 machine cycles, the

8051 internal registers are loaded with appropriate values for an orderly system start-up.

– For normal operation, RST is low.


12

Memory Organization

• Most microprocessors implement a shared memory apace for data and programs. Both the data and programs reside in the system RAM. Microcontroller, on the other hand, the control program must reside in ROM.

• The internal memories consist of ROM and RAM. The RAM contains a rich arrangement of general-purpose storage, bit addressable storage, register banks, and special function registers.


13

RAM

00

1F20

2F30

7F

Bank registers

(32 bytes)

Bit-addressable locations (16 bytes)

General-purpose RAM (80 bytes)

80

FF

Special Function Registers (SFR)


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General-Purpose RAM

00

1F20

2F30

7F

Bank registers

(32 bytes)

General-purpose RAM (80 bytes)

Ex: To read the contents of internal RAM address 5FH into the accumulator.

Solution1:(direct address mode)

MOV A, 5FHSolution2:(immediate addressing & indirect address mode)

MOV R0, #5FH

MOV A, @R0


15

00

1F20

2F30

7F

Bit-addressable locations (16 bytes)

(128 bits)

210 (128+82) Bit-Addressable RAM

80

FF

Special Function Registers (SFR)

(82 bits)

The idea of individually accessing bitsthrough software is a powerful feature of most microcontroller.


16

128 General-Purpose Bit-Addressable Locations

Ex: to set bit 67HSolution: (in Microcontroller)

SETB 67H

Solution: (in Microprocessor)

MOV A, 2CH

ORL A, #10000000B

MOV 2CH, A

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

0001020304050607

08090A0B0C0D0E0F

1011121314151617

18191A1B1C1D1E1F

2021222324252627

28292A2B2C2D2E2F

3031323334353637

38393A3B3C3D3E3F

4041424344454647

48494A4B4C4D4E4F

5051525354555657

58595A5B5C5D5E5F

6061626364656667

68696A6B6C6D6E6F

7071727374757677

78797A7B7C7D7E7F


17

128 General-Purpose Bit-Addressable Locations

Ex: What instruction would be used to set bit 3 in byte address 25H?

Solution: (in Microcontroller)

SETB 2BH

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

0001020304050607

08090A0B0C0D0E0F

1011121314151617

18191A1B1C1D1E1F

2021222324252627

28292A2B2C2D2E2F

3031323334353637

38393A3B3C3D3E3F

4041424344454647

48494A4B4C4D4E4F

5051525354555657

58595A5B5C5D5E5F

6061626364656667

68696A6B6C6D6E6F

7071727374757677

78797A7B7C7D7E7F


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Register Banks

Ex: Read the contents of address 05H into the accumulator.Solution: (Register address mode)

MOV A, R5 (only 1-byte) Solution: (direct address mode)

MOV A, 05H (2-byte instruction)

0700

0F08

1710

1F18

R7~R0

R7~R0

R7~R0

R7~R0

Bank 3 (8 bytes)

Bank 2 (8 bytes)

Bank 1 (8 bytes)

Bank 0 (8 bytes)

Data values used frequently should use one of these registers.


19

Register Banks

Ex: What location of the following instruction writes the contents of accumulator into?

SETB RS1

SETB RS0

MOV R0, A

Solution: (Register address mode): 18H

0700

0F08

1710

1F18

R7~R0

R7~R0

R7~R0

R7~R0

Bank 3 (8 bytes)

Bank 2 (8 bytes)

Bank 1 (8 bytes)

Bank 0 (8 bytes)

Select the register bank 3


20

Register Banks

Ex: What is the address of register 5 in register bank 3?

Solution: (Register address mode): 1DH

18 19 1A 1B 1C 1D 1E 1F

R0 R1 R2 R3 R4 R5 R6 R7

0700

0F08

1710

1F18

R7~R0

R7~R0

R7~R0

R7~R0

Bank 3 (8 bytes)

Bank 2 (8 bytes)

Bank 1 (8 bytes)

Bank 0 (8 bytes)


21

21 Special Function Registers (SFR)

TMODNot bit addressable89

TL1Not bit addressable8B

TL0Not bit addressable8A

TH1Not bit addressable8D

TH0Not bit addressable8C

SBUFNot bit addressable99

80

88

90

98

A0

A8

B0

B8

D0

E0

F0

80

81

82

83

87

88

90

98

A0

A8

B0

B8

D0

E0

F0

P081828384858687

SPNot bit addressable

DPLNot bit addressable

DPHNot bit addressable

PCONNot bit addressable

TCON898A8B8C8D8E8F

P191929394959697

SCON999A9B9C9D9E9F

P2A1A2A3A4A5A6A7

IEA9AAABAC--AF

P3B1B2B3B4B5B6 B7

IPB9BABBBC---

PSW-D2D3D4D5D6 D7

ACCE1E2E3E4E5E6 E7

BF1F2F3F4F5F6 F7


22

21 Special Function Registers (SFR)

E0

F0

E0

F0

ACCE1E2E3E4E5E6 E7

BF1F2F3F4F5F6 F7

Some SFRs are both bit-addressable and byte-addressable.

SETB 0E0H (bit-addressable)

P1909192939495969790

SCON98999A9B9C9D9E9F98

The bits within Port 1 have addresses 90H to 97H. 10010xxxB


23

Program Status Word (PSW)

PSWP-OVRS0RS1F0AC CYD0

D0D0 PSW-D2D3D4D5D6 D7

• Carry flag (CY)– Is a dual-purpose. Carry out of bit 7 during add, or borrow into

bit 7 during a subtract.– EX: MOV A, #FFH

ADD A, #1– What is the state of the carry flag and the content of the

accumulator after execution of the following instruction sequence? MOV R5, #55H; MOV A, #0AAH; ADD A, R5;

• Solution: – A=FFH and CY=0 (No Carry)

A=00H and sets the carry flag in the PSW (ie CY=1).


24




• Auxiliary Carry flag (AC)– When adding a BCD values, the AC is set if a carry was

generated out of bit 3 into bit 4. – What is the state of the AC and the content of the accumulator

after execution of the instruction sequence below?• MOV R5, #1; MOV A, #9; ADD A, R5; • Solution:

A=10H (BCD) =1010 = 00010000B ? AC=1


25




• Register bank select bit (RS1 and RS0)RS1 RS0 Register Bank #0 0 00 1 11 0 21 1 3– SETB RS1; CLR RS0; ? Register Bank 2– SETB RS1 (= SETB 0D4H)– SETB RS0 (=SETB 0D3H)


26




• Overflow Flag (OV)– When signed numbers are added or subtracted,

software can examine this bit to determine if the result is in the proper range ( -128 < X < 127).

– If X >=127 and X <=-128 ? OV=1– MOV R7, #0FFH; MOV A, #0FH; ADD A, R7;– Solution

• R7=11111111 (00000000+1=-00000001B=-1)• A=00001111 (15)• A=-1+15=14 =0EH< 127 ? OV=0 (No overflow)


27




• Parity bit (P)– The P is set or cleared each machine cycle to

establish even parity accumulator. – MOV A, #55H– A=01010101B ? numbers of 1-bit = 4 ? P=0


28

B Register and Stack Pointer

80

F0

80

81

F0

P081828384858687

SPNot bit addressable

BF1F2F3F4F5F6 F7

• B register or B accumulator – MUL AB

• Results of low-byte in A and high-byte in B.

– DIV AB • Integer results in A and remainder in B.

– It is bit-addressable thru bit addresses F0H to F7H.

• Stack Pointer (SP)– The SP is an 8-bit register at address 81H.


29

Data Pointer (DPL, DPH)

82

83

DPLNot bit addressable

DPHNot bit addressable

• Data pointer (DPTR) is used to access external code or data memory (16-bit register) – DPH: Data Pointer High-byte) at 83H– DPL: Data Pointer Low-byte) at 82H– EX

• MOV A, #55H ? A=55H• MOV DPTR, #1000H ? DPTR=1000H (16-bit)• MOVX @DPTR, A ? Move the content of A to the external RAM

location whose address is in DPTR (1000H)


30

Port Registers

P1909192939495969790

80

A0

B0

80

A0

B0

P081828384858687

P2A1A2A3A4A5A6A7

P3B1B2B3B4B5B6 B7

• Ports 0, 2, and 3 may not be available for I/O if external memory is used or if some of the 8051 special features are used (interrupt. Serial port etc.)

• Nevertheless, P1.2 to P1.7 are always available as general purpose I/O lines. – SETB P1.7 (=SETB 97H)? might turn the motor ON– CLR P1.7 (=CLR 97H)? might turn the motor OFF.


31

Timer Registers

TMODNot bit addressable89

TL1Not bit addressable8B

TL0Not bit addressable8A

TH1Not bit addressable8D

TH0Not bit addressable8C

8888 TCON898A8B8C8D8E8F

• The 8051 contains two 16-bit timer/counters for timing intervals or counting events. Timer 0 is TH0 and TL0, timer 1 is TH1 and TL1.

• Timer operation is set by the timer mode register (TMOD) and timer control register (TCON).

• The TCON is bit-addressable.


32

Serial Port RegistersSBUFNot bit addressable99

9898 SCON999A9B9C9D9E9F

• The 8051 contains an on-chip serial port for communicating with serial devices such as terminals or modem, or interfaces with other ICs with a serial interface (A/D converters, shift registers, nonvolatile RAM, etc.)

• The SBUF (serial data buffer) at address 99H holds both the transmit data and receive data.

• SCON (serial port control register) is used for various modes of operation.

• SCON is a bit-addressable.


33

Interrupt Registers

A8B8

A8B8

IEA9AAABAC--AFIPB9BABBBC---

• Interrupts are disabled after a system reset and then enabled by writing to the interrupt enable register (IE) at address A8H.

• The priority level is set through the interrupt priority register (IP) at address B8H.

• Both registers are bit-addressable.


34

Power Control Register

IDL87

87

PCONPDGF0GF1---SMOD

PCONNot bit addressable

• SMOD: Double baud rate bit; when set, baud rate is doubled in serial port modes 1, 2, and 3.

• GF1 & GF0: General-purpose flag bits 1 and 0.• PD: Power down; set to activate power down mode; only exit is reset.

– The oscillator is stopped, all functions are stopped, all RAM contents are retained, port pins retain their logic levels, and ALE and PSEN are held low. VCC is 2V.

• IDL: Idle mode; set to activate idle mode; only exit is an interrupt or system reset. – The internal clock signal is gated off to the CPU. The CPU status is

preserved and all register contents are maintained. Port pins also retain their logic levels. ALE and PSEN are held high.


35

External Memory

• When external memory is used, Port 0 is not available as an I/O port. It becomes a multiplexed address (A0-A7) and data (D0-D7) bus, with ALE latching the low-byte of the address at the beginning of each external memory cycle. Port 2 is usually employed for the high-byte of the address bus.

Address

Data

A0-A15

D0-D7

Non-multiplexed (24 lines)

Address

Data

A8-A15

AD0-AD7

Multiplexed (16 lines)

Address

Memory Cycle


36

Accessing External Code Memory

• Here’s how the multiplexed arrangement works: during the first half of each memory cycle, the low-byte of the address is provided on Port 0 and is latched using ALE.

• A 74HC373 latch holds the low-byte of the address stable for the duration of the memory cycle.

• During the second half of the memory cycle, Port 0 is used as the data bus, and data are read or written depending on the operation.

8051

D Q

G

Port 0

ALE

EA

Port 2

PSEN

D0-D7

A0-A7

A8-A15

OE

EPROM

74HC373

hardware summary - oregon state universityoregonstate.edu/instruction/ece573/hw_summary.pdf · •...

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