Hardware Support for Clock Synchronization in Distributed Systems

Martin Horauer

University of Technology ViennaDepartment of Computer Technology

Objectives

LANs (hardware)

Internal Clock Synchronization:

| Cp(t) - Cq(t) |

External Clock Synchronization:

| Cp(t) - t | 1ns

distance10m 100m 1 km

1s

1ms

precision,accuracy NTP

LANs (software)

GPS

PLL

LANs (hardware)

Requirements Hardware Clock

small oscillator drift good stability fine grained rate and state adjustable

Access to an external time reference

Timestamp Messages tight coupling of timestamp mechanisms to the network medium

Hardware Support

OCXOor

XO + Rate Synchronization

Clock ASICUTCSU

Ts = Cp(t)

TRmin

= Cq(t)

end-to-endmin

end-to-endmax

t

t

TransmitterNode p

ReceiverNode q

TRmax

= Cq(t)

Queing delay, NetworkController FIFOs, etc.

Overload, NetworkController FIFOs, etc.

Software Timestamping

Cq(t) - Cp(t) TR – TS - [ - ]

= max - min

Ts = Cp(t)

TRmin

= Cq(t)

min

t

t

TransmitterNode p

ReceiverNode q

Timestamping with HardwareSupport

min max

t

t

TransmitterNode p

ReceiverNode q

TRmax

= Cq(t)

Ts = Cp(t)

Timestamping with HardwareSupport

Cq(t) - Cp(t) TR – TS - [ - ]

= max - min

Hardware Support for Clock Synchronization

U TC SU

NetworkController

T im estam pLogic

PhysicalLayer

Device

C PU M EM O R Y

PC I Bus

PC I-PC IBridge

PC ITarget

local PC I Bus

Clock Synchronization PacketTimestamping

Preamble SFD Dest. Addr. Src. Addr. TF User Data FCS

Transmit TS FCSTransmit Timestamping:

Preamble SFD Dest. Addr. Src. Addr. TF User Data FCSTransmit TS

FCSReceive TS

Receive Timestamping:

Transmit TS FCS

Dest. Addr. Src. Addr. TF User DataTransmit TS FCS

Receive CRC check:=

FCSReceive TS

Hardware Support for Clock Synchronization

UTCSU

Netw orkContro ller

Physica lLayer

Device

C PU M EM O R Y

PC I Bus

Prototype Implementation