marchal.jean.free.frmarchal.jean.free.fr/datasheets/uociii hercules... · restricted, contains nda...

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1Introducing UOC-III “ HERCules ” :“SIMPLY COMPLETE”“SIMPLY COMPLETE”

File: Herc_1.ppt = Introduction, v1.2 29-09-2003 by E.Arnold

Presented by:

&

E. Arnold

P. Schepers

© Philips Electronics N.V. 2003All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The

presented information does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey

nor imply any license under patent- or other industrial or intellectual property rights. Diagrams in this presentation are intended to explain the functional behavior of a TV receiver with UOC-III “Hercules” concept, not necessarily in accordance with the actual IC

implementation.

Start this presentationwith a mouse-click

& read the “Notes Pages”

?

Contains items that require NonDisclosureAgreement

TV System Design, ICE, Eindhoven

RESTRICTED, contains NDA items

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1-2UOC-III “ Hercules ” TV course, part 1:

1. Objectives of this course

2. Introduction:

• Market positioning of Hercules

• Sub-division of low- and mid-end TV market

• Family overview

3. Block diagrams

4. Intake open questions


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1-3UOC-III “ Hercules ” TV course, part 2:

5. The Guard Ring approach

6. Application aspects:

• Do’s and don’ts with TDA110xx

• System Example: Global TV Receiver

7. Answering questions


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1-5

Development

TVSDICE

Eindhoven

? !

! ?

Hamburg

Ap

plic

atio

n

IC d

esig

n

Nijmegen

?

I2C

TVSD (HW) + SDCE (SW)Innovation Center

Eindhoven

IPMNijmegen

+ Shanghai

GTV

$$$ !!

Training TV Systemarchitecture

PC menuI2C driver

GTV platformSW libraries

Herc

ReferenceHW

SystemArchitecture& Definition

Spec &ApNote

EmulatorDebugger

From Idea to Product:


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1-6

IC application

TV system, EMC

Software

RSO

RSO

IPM/RSO

TV Proc. : Nijmegen

µP + Emulator: Hamburg

Ref. Designs, EMC:Eindhoven

GTV + Business Partners:Eindhoven+Southampton

Sound DSP I.P. RSO Hamburg

Technical support:


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• Faster design-in cycle = higher efficiency for all

• Make information easier accessible for all levelsof experience (engineers, software writers, QA)

• Share I.C. & system application information

• Share layout & EMC experience

• STANDARD solutions (libraries, basic cell, IP-blocks)

Objectives:

Philips Semiconductors’ approach for customer support aims to make our customers “self-supporting”. That is more efficient for both parties.

Software has become a substantial part of the total design effort. Philips Semiconductors understands that our technical information will be used by experienced TV developers, but ALSO by “fresh” engineers. We are now adding more (basic) functional descriptions to our (detailed) technical application notes.


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Old

• Technology driven(sell what we can make)

• Application assistanceat first design

• Technical description (how we’ve done it)

• Description I2C-bus bits

• TV know-how required

New

• Market driven(make what we can sell)

• Training before design starts(saves time)

• Functional descriptions(how functions are intended)

• TV functions & algorithms

• Higher abstraction level

Design-in approach:

With this IC training course we want to present you a COMPLETE system in a short time frame.

Please use the documentation of this course together with our technical Application Notes and it should be easier to:- understand how certain functions should be operated- find the link between a function and its I2C-bus control bits- prevent errors in TV chassis design

In the IC’s Application Note you can find descriptions of each pin and the I2C-bus control bits. In this training course we will show how TV functions use the I2C-bus bits.

The diagrams in this presentation are intended to explain the functional behavior. The actual IC implementation may be different.


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ü Total integration for 50/60Hz TV chassis

ü All-in-one IC, one design for Mono & Stereo

ü Picture & sound enhancements

ü Many I/O pins & switches, but less components

ü Faster time-to-market

ü Faster factory throughput

What set makers want:

The “truly-global” TV capabilities of the UOC-III “Hercules” IC, makes it possible to cover more market with less chassis designs. The application overhead of the maximum versus the minimum version is small. Leaving out some components is often cheaper than having different PCB designs.


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• The next step of integration: UOCIII

- Less versions (keep cost effectiveness)

- More features (= more pins : QFP128)

• Make TV design aseasy as possible

• Optimal process combination (MCM of CMOS + BIMOS)

The platform:

Available as I/O pins:- 4x ADC/IO- 2x Int/IO- 6x PWM/IO- 2x IO- 2x IO (no UART used)- 5x Output (no I2S used)- 1x Swo (no YUVoutput used)- 1x SwIo/Vguard (p12)= 23 lines, excluding I2C


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“Face-down” QFP-package:

• Two variants = easier choice for PCB layout

⇓

1

32

33 64

96

128

97

65

“Old” face

⇓• Same physical IC,but legs bent the other way

• Type number printedon the new “top” of the “flipped” - IC

Old pinning(IC-top view)

128

97

96 65

33

1 32

64

New, reversedpinning

(IC-top view)

• Existing QFP128 SMDpackage SOT-320-2

“New” face


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The highlights:

• One IC for everything: Control, small-signal, mono/stereo, extensive Audio/Video

• Upgrade with digital sound & video processing

• Alignment free IF, including SECAM-L/L1 + AM

• FM sound, no external filters (traps/band-pass 4.5/5.5/6.0/6.5)

• Full multi-standard colour decoder

• One Xtal reference for all functions (micro processor, RCP, TXT, CC, RDS, colour decoder & stereo sound processor)

Modern PLL techniques are used to eliminate alignments.

The IF frequency can simply be chosen from:

- 58.75 MHz (Japan),

- 45.75 MHz (America),

- 33.4 or 33.9 MHz (SECAM-L1 only in France),

- 38.0 MHz (China)

- 38.9 MHz (Europe)

Mono version:

The FM sound carrier is demodulated using a “Narrow-Band-PLL”, enhanced with internal band pass filters. Since the Narrow-Band-PLL is automatically calibrated, a multi-standard implementation can be made WITHOUT external switching.

Stereo versions:

Addition of a sound-DSP offers stereo decoding for all terrestrial stereo standards. Audio processing includes Dolby Pro-Logic, Virtual Dolby and many other features to enhance the TV sound.


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The highlights:

• Only 3.3V, 10mA needed in TV-standby (PowerDown mode)

• Low stress by innovative slow start/stop of HOUT

• Separate adjusted colour temperature hi/low-light

• Selectable I/O pin configuration:ADC / PWM / Push-Pull / Open-Drain …

• Byte-level hardware, multi-master I2C-bus:Transmit/receive up to 400kHz (Normal/Fast-mode I2C),“In-System” (re)Programming up to 2MHz (Hs-mode I2C)

All 3.3V supply pins should be permanently connected to the Standby supply. Including peripheral components, the start-up current is less than ??100mA.

During standby mode the device’s power consumption can be reduced to ??12mA, by bringing the software in Power Saving mode (improved POWERDOWN and IDLE modes).


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1-14

The highlights:

• Enhanced 80c51 micro processor core

• (re)programmable program memory 64 .. 128KB, same type for OSD + TXT + CC character sets

• High performance OSD :- Italics, Underline, ShadowingShadowing- Soft ccoolloouurrss- Soft scroll- Reduced-intensity background- Dynamic Redefinable Characters (DRCs)

Normal 8051 core can address up to 64KB of ROM. The address space is enhanced with bank-switching.

Characters can also be modified in (re)programmable-ROM, allowing customer logo’s, special characters etc.

With the inclusion of Closed Captioning (American subtitling) the same attributes also become available for On Screen Display.

DRCs make it possible to add dynamic animations to the OSD. They can also be used to extend the number of OSD character fonts.


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1-15

TDA8361 +TDA4665 +PCA84C441

TDA8362 +TDA4665 +TDA8395 +PCA84C641

TDA8362 +TDA4665 +TDA8395 +SAA5244 (1p TXT) +PCA84C841

TDA8362A +TDA4665 +TDA8395 +SAA5281 (8p TXT) +P83C055

TDA8840 +SAA5290 (uP + TXT)

TDA935x/6x/8x - FM Ultimate One Chip

Mono

Y PR PB

TDA8842 +SAA5291 (1p TXT)

TDA8844 +SAA5296 (10p TXT)

TDA8854 +SAA5497 (10p TXT)

TDA9801 + TDA8376A +TDA4665 + TDA8395 +SAA5497 (10p TXT)TDA935x/6x/8x - QSS Ultimate One Chip

Stereo

• TDA935x/6x/8x-FM for mono, -QSS for stereo• TDA95xx provides both QSS & FM/AM demod.

Classification of TV receivers:

• UOC-III “Hercules“ for Mono and Stereo• UOCIII “Hercules“ for Mono and Stereo

PHILIPS

Low-PHILIPS

LowPHILIPS

Low+

PHILIPS

Low++

PHILIPS

Mid--2 Speaker Mono

PHILIPS

Mid-Playback Stereo

PHILIPS

Mid

PHILIPS

Mid+

PHILIPS

Mid++

The largest production volume is found in the Low-end segment. The UOC-III “Hercules” IC makes it possible to build a very compact TV chassis, including extensive audio/video I/O switching.

The Mid-end segment is dominated by stereo sets. This is usually a larger cabinet with two speakers and a stronger power supply. The on-board stereo DSP processor adds attractive sound features to the concept.


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• Suitable for “real-flat” and 16:9 CRT displays

ParabolaUpperCorner

Parabola

Horizontal Parallelogram

LowerCorner

Parabola

TrapeziumHorizontal Bow

Suitable for Small AND Big screen:

Vert.Linearity

For 110º applications UOC-III has an East-West modulator output, suitable to handle large screen picture tubes. Especially for completely flat picture tubes, controls for Horizontal Bow, Parallelogram and Vertical Linearity are added.

For more precise alignment, the corner parabola’s can be set independently for the upper and lower corners.


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1-17

Hor.Driver

• 1V8, 3V3STANDBY and +VB needed to start line drive

• Secondary +5V and +8V can be generated by FBT

UOC-IIIHercules

SMPS

+5V

+3V3 +VB

Pulse

HorizontalDrivePulses

ϕ2-loopH-flyback

LH

CBCS

Linearitycorrection

CF

CDIV

+VB

LP

FBT

+8V

TDR

RDR

LLEAK

+8V

EHT

BeamCurr.

+5V

Shaper

TD + D1

Low voltage Start-Up:

LSU, MSU = NOT yet available in ≤ ES7.2D samples+5V and 1V8EXT must be ON during IC-reset ??

The IC can start generating HOUT line-drive pulses from only its 3.3V Standby supply voltage. This is called “Low voltage start-up”.

The +VB for the FBT is normally well-stabilized (1%) by the SMPS (determines picture width). Secondary supplies that are scan-rectified from the FBT need NO stabilizers. Also the +5V second power supply for the IC can be generated in this way.


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New features: Video

Full YUV-loop interfaceYPbPr inputTint and Peaking on peripherals (CVBS, Y/C, RGB, YPbPr)

Scavem on ALL peripherals, plus independently for TXT/OSD Integrated 4H Comb filter (2D, time-discrete using digital techniques)

Sound trap integrationEconomy histogram: ”White-Stretch" & "DC-transfer ratio"Programmable Black stretch function ("depth" and "area selection")

Pseudo auto Y/C detector3-bit Signal-to-Noise ratio measurementIntegration of White Stretch capacitor


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New features: Micro / TXT 0,10 or 100p Txt with embedded memoryTwin TXT Double window (Video/TXT - all inputs)Linear and non Linear H-Scaler (all inputs)Flash-programmable ROMImproved power downHigh-speed I2C Bus64 DRCS, 32 four-colour charactersUp to 16x18 font sizeRDS (Radio Data System)Character smoothing


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Global Stereo-TV processing & stereo FM radio (look TV, listen radio)BTSC with DBX noise reduction [Trademark of THAT Corporation]

DDEP = Demodulator + Decoder Easy ProgrammingASD = Auto Standard DetectionSSS = Static Standard SelectionBBE = High definition BBE sound [Trademark of BBE sound, Inc]

DBE = Dynamic Bass EnhancementDUB-II = Dynamic Ultrabass-2SRS = surround + bass effects VDS = Virtual Dolby Surround (VDS422/423)Dolby Pro Logic Delay & Pseudo Hall / Matrix functionI2S out for Sub-Woofer or full 5-channel DPL [Trademark of Dolby Laboratories]

Smooth volume control, soft mute, loudness, bass, treble, Incredible mono / Incredible stereoProgrammable beeperAV Stereo playback

New features: Sound


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type selection:

Type Number Sound N

um

ber

of

TX

T

pag

es

Co

mb

filt

er

Co

lou

r d

eco

der

DW

Pan

oram

a

FM

rad

io

RD

S/R

DB

S

DB

X

Do

lby

Pro

Lo

gic

Vir

tual

Dol

by

SR

S 3

D s

tere

o S

RS

Tru

Su

rro

un

d

BB

E

RO

M [k

B]

Use

r R

AM

[kB

]

Multi stereo

BTSC Audio DSP

Mono 0 10 NTSC only

Multi Stereo Mono 256 128

8 4

TDA110xx - - - √ TDA120xx √


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CombFilter

PeakingSaturationContrast YUV

F

YUV

Vref

TXTOSDCC

RDSColour

Decoder

UOCIII “Hercules”

“Picasso”“Cosmic”

RG

Bsw

itch

RGBF

BrightnessRGB out

Sync

StereoSound

Micro+

Flash

inside:

Spl

it -

scre

enP

anor

amaDA

CA

DC

DA

C

SwitchIF

YU

Vsw

itch

• Mixed process: BiMos + CMos = best of both worlds

• Easy: “GTV” software takes care of all initialisations


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1-23Control BIT Name, e.g: “VSW”

FUNCTION Short descriptionI/O Input = control bit, Output = status bitMACRO The device macro, where the bit is related to:- VIF&SIF Vision IF and Sound IF- Mono/stereo FM/AM demodulation & audio processing- Sync&Geo Horizontal and Vertical synchronisation & geometry- Power Power and Protection- In/Out Input / output for audio & video- Colour Colour decoder & filters- YUV Video control- RGB RGB output and control- Micro TCG Teletext, Control and Graphics

FU Function class- SU Start-Up, set before switching-on from stand-by- AL Alignment, aligned during production, values set before switching on- SC Setmaker Control, controlling normal operation- UC User Control, accessible for the customer like contrast, brightness, etc.- TK Tool Kit, can help to improve performance under difficult working conditions

like RF phase modulation, wrong burst/chroma ratio, etc.

GTV Function Function call within the GTV software Platform

I2C-bit naming convention:

In the Application Notes we are now using these naming conventions.

E.G. a “TK”-bit is a bit that should typically be implemented in software as an optional bit. It can help the set maker to handle difficult problems in the field. E.g. by selecting a different compromise of time-constants for weak-signal areas.

Note:Be careful with using TK-bits as they may have side-effects. Only use them in specific situations, disable them in all other situations.


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DVD (YPBPR) or RGB+FBL

IF-PLL, AGCLockdet, AFCVideo-Amp.

-Ident-Vsw Mute

GroupdelaySoundtrap

QSS

CVBS,Y/C,YUV/RGB, matrix

Peak, CoringSaturation,Hue

ScavemDigital processingDouble window

Combfilterchroma-trap, -BP, Y-delay

PAL,NTSC,SECAMBaseband-delay

2nd Sound IFAM, NBPLL-FM

demodulatorFM Lock Det.FmMute, AVL

H-Osc.LV-start-up

IBLACK

RGB

I2S

+5V

H+V

Y/C

CVBS

EHT

Teletext,CCControlGraphics,OSD

Int

ADC

PWMI/O

24.576MHz

E/W

VIF & SIFVIF & SIF

In/OutIn/Out

PowerPower MicroMicro

CRTcalibrationBeamCurrent White Limit,SoftclippingStretchingBrightnessContrast

RGBRGB

AGC

VIF

Osc

TunerSIF

NICAM, A2, MPX, RDS

Digital Audio Features

StereoStereo ColourColour

MonoMono

YUVYUV

Audio Switch, 2x Volume

SVM

IBEAM

YUVloop

UOCIII

“Hercules” Φ1+2 Sync

SyncSync

1.8V

+3.3V

Goto

Dictionary

H+V GeometryV divider, zoom

Functional blocks:

GeometryGeometry

QSS,IFOUT

Mono

TuningTuning


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Video- and sound-IF:

In/OutIn/Out

MicroMicro

RGBRGB

StereoStereo

ColourColour

MonoMono

YUVYUV

PowerPower Sync & Sync & GeometryGeometry

VIF & SIFVIF & SIF

File: Herc_2.ppt = Analogue part, v2.8, 30-09-2003 by E.Arnold

The diagrams in this presentation are intended to explain the functional behavior of a TV receiver with UOC-III “Hercules” concept.

© Philips Electronics N.V. 2003All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The presented information does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Authors: Philips Semiconductors, BL-MTS

E.C.P. ArnoldInnovation Center Eindhoven, the Netherlands

Stereo part: Ulf Buhse, Peter Schöning, Matthias Meyer S&A, Hamburg, Germany


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IF:

• Multi-Standard alignment free PLL-IF, including SECAM L / L’(Positive Modulation)

• Integrated IF-AGC time constant (SW selectable)

• Integrated sound band-passes & traps (4.5 / 5.5 / 6.0 / 6.5 MHz)

• Group delay compensation (for “flat” multi-standard NTSC/PAL SAW filters)

• QSS versions with digital Second-Sound-IF SSIF (AM demodulator for free)

• FM mono operation possible: Inter-Carrier or QSS

The IF frequency is calibrated, using the X-tal reference oscillator.

A choice can be made for different IF frequencies.

Positive and negative modulation are supported.

Four different IF-AGC time constants can be chosen via I2C-bus, for optimal performance under various conditions. For positive modulation the AGC time constant is automatically adapted to a larger value.

GTV Function: ptun_SetIFAGCSpeed

The UOC-III family makes no difference anymore between QSS- and Inter-Carrier-IF, nearly all types are software-switchable between the two SAW-filter constructions.


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SSIF(INTCO)

FMRO

Optional BP

IF modes:

Inter-Carrier Sound Quasi-Split Sound

Tune

r

TV SAWVIF+SIF

TV SAWVIF

TV SAWSIF

VIFVIF

SIF

FM-10.7 radio (mono/stereo)

FM-Eco-radio (low cost add-on, re-using TV tuner)

Tuner-AGC coupled to S-AGC

AGC

Tune

r

AGC

S-AGC

DVB-hybrid

TV VIF(SIF)

DVBIF

DV

B-T

uner

AGC

TV SIF

SAWD-IF

DVBadd-on

(S-AGC)

AGCin

(INTCO)

DVBO

(SSIF)

REFin

TV SIFRADIO-IF

SwFM T

uner

SSIFBP 10.7 MHz

TV-IF modes:

The cheapest IF mode is “Inter-Carrier”, using one SAW filter for both video and sound. Better separation of video and sound is achieved, using “Quasi-Split Sound”. The sound SAW is now optimised and passes > 10dB more sound carrier. This results is better sound sensitivity and higher quality video.

FM-Radio modes:

Adding a special FM-radio tuner plus 10.7MHz band pass gives the best result (FM tuner = optimised for phase-noise & selectivity). A QSS configurationallows double-use of the TV tuner for low-cost FM-Eco-radio implementation. The selectivity of the sound-SAW filter should be switched (FM radio = narrower than TV-FM-sound). Various mixing frequencies can be used (e.g. RIF=37.5MHz mixed with 43.008 gives 5.5MHz → FM-demodulator).Extra selectivity can be added externally, but is usually not needed.

DVB mode:

The IF spectrum (36MHz) is mixed-down to a “low-IF” frequency (4.5MHz) , that can be handled by an add-on DVB demodulator. If the fixed down-mix frequency does not match the DVB concept, the DVB part can deliver a reference carrier to the UOC-III.


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39MonoOUT +DeEmphasis

15K

Mono

NB-PLL

SSIFIN33

41

IF-PLL loop filterIn-lock-detector& AFC

VIF

2425

AutomaticGain Control

Tuner AGC 31

28PC

SAW

IF & sound path:

GroupDelay

55 CVBS258,59 Y/C351,52 Y/C472,70 Y/C564 CVBSO

Colourdecoder

IFVO43

48 SVO

I/O s

witc

h

Combfilter

HP62,63

LS60,61Stereo

46SSIF-AGC

SSD

DAC1 DAC2ADC

AV356,57

34,35

53,54

AV1

AV2

36,37

49,50 AV4

Mono-FM

SoundCross

bar

IF-PLL,Xtal

calibrated

102..106I2SIN/OUT

Video AM demodulator

Sound down mixer

Narrow-Band-PLLFM demodulator

Tune

r

Soundtrap

IF video

SIMPLIFIED

SIMPLIFIED

SSIFAGC

The embedded Comb Filter function (some UOC-III type numbers) improves the video decoding performance significantly.

A single, combined video + audio SAW filter is known as “Inter carrier”. With the same UOC-III “Hercules” device, also a “QSS” construction can be made, using separate VIF (Video-IF) and SIF (Sound IF) SAW filters. Selection between QSS or IntC is done via software.

Although all required traps & band-pass filters are integrated, we maintain flexibility to route the signals through external filters. This is useful for testing and/or for unforeseen field conditions (see next slide).

GroupDelay

TunerExternal trap

Front-End out


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FM radio mode uses thevideo mixer-path, to keepthe Tuner-AGC operational

VSW mutes Front-End,but also connects tuner AGC to ground

Narrow-Band-PLL mono-FM demodulator

Stereo demodulator and audio processing

IFA..D,FFI41IF-PLL loop filter

LockDet.

LOCK AFC

MODVIF

2425

Video AGCdetector

MOD,AGC0/1

AGC

Tuner AGC 31VSW,TOP

I / V

28

LPF

IFS

PCSAW

Gating

AFN

IF & sound:

FMR

SIF2930

SoundAGC

SCSAW

42

AMdemod.

SIF-AGCMOD

QSS

AM

MOD

QSS

48

IFVO

55 CVBS258,59 Y/C351,52 Y/C472,70 Y/C564 CVBSO

43

SVO/CVBSI

VideoIdentSID

YCD

Colourdecoder

Comb

INA..D,CS1A..D,SD2..0

I/O s

witc

h

HPVOL

62,63

Digitaldemod+decoder

DigitalSound

Processor

DAC1

LS

105 I2SOUT1

60,61106 I2SIN

104 I2SOUT2103 I2SCLK102 I2SWS

swap

perStereo

DSP

5x I/O

DAC2ADC

AV356,57

34,35

53,54

AV1

AV2

36,37

49,50 AV4

AM/FM

SoundCross

bar

SC2..0,HP2..0

Mute

L,ExtMONO

IF-PLL

VSW

BPB

FMA..B,BPB2

SVO1/0Soundtrap

CV2

GroupDelay

FMA..D GD

IFO2..0

Black-DCDVB/FMR

Mute

39

38Decoupling

E2D,FMI

MonoOUT +DeEmphasis

NB-PLL

L,ExtMONO

15KMute

SM0/1,AM

FMI,FMWSFMA..E

+6dB

FML/W

Mono

SSIFIN

AM

33

QSS

AGN

CMB2..0

FMR

46SSIF-AGC

SSIFAGC

For European SCART TV sets the tuner-part must always remain active, but in Asia-Pacific the tuner can be shut-off ( bit VSW=1) when an external source is viewed. Please note that VSW also shorts the Tuner AGC output to ground. The DC-range (max. and min.) must be limited by external resistors, otherwise the Tuner AGC voltage may take very long to settle.

GTV Function: pimg_SetVideoMute

For flexibility you can take the Front-End signal outside the IC (IFVO, before or after the internal sound trap). An additional, external sound trap can be added in series with the signal path. Then it can be re-inserted via CVBSI or CVBS2. Doing so via CVBS2 keeps the option to have Front-End output at pin SVO.

Further a 2-tuner system can be supported (e.g. one to “cable” plus another for “antenna”). The base-band-output of a secondary (PIP) tuner+IF can be cross-linked to the UOC-III : output via IFVO and input via CVBSI (or CVBS2). This avoids an antenna switch.Sound band-passes for FM mono demodulation are available at 4.5, 5.5, 6.0 and 6.5MHz. Other band-pass filters can be added outside the IC (4.72, 5.74). Frequency of internal trap/band pass is determined by FMA..FMD.

GTV Function: psys_GetFMDemodulatorCentreFrequency, psnd_SetFMDemodulatorSelection

FM radio IF (RIF) internally uses the part of the video mixer (FMR=1), so that the Tuner-AGC output remains operational during (Eco-) FM radio mode.

GTV Function: ptun_SetTVFMMode


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Below Reference Above Reference

Calibration tolerance 25kHz

FIF set by IFA/B/C

IF: AFC window:

RF too low,IF too high

RF too high,IF too low

Resolution 25kHz/step (AFC7..0)

• Large AFC detection range (+/- 3.2MHz) allows fast & proportional tuning corrections (25kHz resolution)

• AFC only valid when IF-PLL in-lock,practical range = -2MHz .. +500kHz (including SAW filter characteristic)

• Switch AFC detection off when not needed (improves sound cross talk)

The frequency of the IF-PLL is calibrated with a tolerance of 25kHz. This same tolerance is applicable to the AFC-readout.

Because the AFC read-out is very precise, it is possible to correct tuning deviations with ONE, proportional step. E.g when the transmitter is drifted away by 375kHz, it will take SW only one action to correct the tuning. We advice to keep such proportional jumps smaller than 800kHz; larger deviations can better be corrected in more than one step.

When AFC indication is not needed, you can switch-off the detection mechanism via AFN=1. For critical applications this can help to improve frame-synchronous cross-talk to the sound. SW can e.g. randomize reading back the AFC information.GTV Function:ptun_StartSearch / ptun_CancelSearchptun_IsSearchActiveptun_TransmitterFoundptun_GetIdents ptun_SetAFCSwitch (Note: this sets AFN to 0)


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Normal modulation:Normal PLL time constant

Phase modulation:Fast PLL time constant(follow carrier frequency variations)

Over modulation:Slow PLL time constant(don’t follow 180º jump)

Fast FiIter IF-PLL (FFI):

For normal modulation, the standard loop filter is a good balance for most situations, with sufficient reserve.

Phase modulation:

When a high level of phase modulation (~FM modulation) of the AM carrier occurs, it helps to reduce the external filter time constant. This enables the IF-PLL to follow the phase modulation faster.

Over-modulation:

When the modulation depth exceeds 100%, the phase of the AM carrier suddenly changes 180 degrees. The IF-PLL tries to follow this phase jump but this is NOT wanted. Performance can be improved by increasing the external filter time constant. This prevents the IF-PLL from over-reacting on these temporary phase inversions.


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High carrier amplitude:Adapted PLL time constantBetter for phase modulation (FM)

Low carrier amplitude:Normal PLL time constantBetter for over modulation

FFI=1 : PLL time constant automatically adapted to carrier levelBetter behaviour for phase modulation (FM) and over modulation

FFI=1: auto-adapt to level

When both phase modulation and over-modulation occur, the requirements for the IF PLL loop filter are contradictory.

Bit FFI adapts the time constant of the IF-PLL loop filter, depending on the IF-amplitude of that moment:- Normal time constant for high modulation (= low carrier amplitude)- Fast time constant for low modulation (= high carrier amplitude)

This can improve the reception performance under difficult conditions (both FM- and over-modulation of the picture carrier).

When FFI is set to 1, the PLL time constant for low carrier levels is kept normal, while for higher carrier levels the PLL speed is increased. In this way, a better compromise between phase modulation and over- modulation is possible. GTV Function: ptun_SetFastFilterIFPLL

Remarks:- FFI=1 has no influence on e.g. search-tuning speed- Use FFI only for negative modulation (MOD=0)- Use toolkit bit FFI=1 only if you really have to, we advice to implement it as

a service-mode option


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BITS FUNCTION SETTING I / O MACRO FU REM LOCK IF PLL LOCK indication 1: IF PLL in lock O IF SC AFC7..0 AFC outputs C4HEX < –1.5MHz

00HEX = centre value 3CHEX > +1.5MHz

O IF SC 2-complement notation, resolution = 25kHz/step

AFN AFC Not active 1: not active I IF SC Non-IF mode FFI Fast Filter IF-PLL 0: normal, 1: fast I IF TK IFS IF Sensitivity 1: low sensitivity I IF SC STM Search Tuning Mode 1: less sensitive SL-bit I Sync SC During AutoStore

IFD IFA IFB IFC FMD FMR IF freq. selection AREA 0 0 0 0 x 0 58.75 MHz Japan 0 0 0 1 x 0 45.75 MHz USA 0 0 1 0 x 0 38.9 MHz Europe 0 0 1 1 x 0 38.0 MHz China 0 1 0 0 x 0 33.4 MHz Secam L1 with 5.5 MHz shift 0 1 1 0 x 0 33.9 MHz Secam L1 with 5 MHz shift

1 x x x x 0 External reference Flexible DVB down-mix FM-Radio modes

0 x x x 1 x 10.7 MHz FM-Radio mode (independent of VIF) 0 1 0 1 0 1 43.008 MHz 0 1 1 1 0 1 49.152 MHz

Eco-FM-Radio mode

IF related bits (1):

During eco-FM-radio mode the IF-PLL has no picture-carrier to lock-onto, instead it will be set to a fixed frequency (derived from Xtal).

• fXTAL/4 * 7 = 24.576/4 * 7 = 43.008 MHz , or

• fXTAL/4 * 8 = 24.576/4 * 8 = 49.152 MHz

With a customized RIF-SAW it is also possible to use 10.7 MHz inter-carrier:

• 43.008 – 10.7 = 32.308 MHz as RIF-SAW center-frequency, or

• 49.152 – 10.7 = 38.452 MHz (→ check IF-frequency range of your tuner)

Many other down mix possibilities are e.g. 43.008 - 37.508 = 5.5MHz.

For 10.7MHz selectivity you can use a band-pass filter like e.g.:Murata “SFE 10.7 MS3 A 20 G”.- MS3=bandwidth 180kHz (needed with fully occupied FM-band), MS2=230kHz - A=accuracy center frequency is exactly 10.7- 20=tolerance of +/-20kHz, 10=10kHz, 30=30kHz- G=flat group delay time, best for low distortion & large FM swing

GTV Function:LOCK: ptun_GetIfPllLockAFC,AFN: ptun_SetAFCSwitch (Note: sets AFN to 0)FFI: ptun_SetFastFilterIFPLLIFS: ptun_SetIFSensitivitySTM: ptun_SetFEIdentSensitivity


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BITS FUNCTION SETTING I / O MACRO FU REM IFLF IF Lock Forced 1: do not calibrate I IF SC For high modulation SID Video Signal IDent 1: video identified O IF SC VA1..0 Video output signal Amplitude 00: no correction

10: –5% 11: +5%

I IF SC Level-out amplitude differences due to filtering or standard

VAI Video output Amplitude system I 1: +12% I IF SC VIM Video Ident Mode, input selection for

SID-circuit 0: CVBS1INT input, 1: output source switch

I IF SC

VSW Video mute SWitch 1: mute I IF SC Tuner AGC also off

MOD MODulation standard 1: positive I IF SC French SECAM-L/L1

GD Group Delay correction 1: on I IF SC For IF signal AGC1..0 AGC time constant,

sets the IF-AGC speed 00: 0.7x, 01: normal 10: 3x , 11: 6x normal

I IF SC 20x slower when MOD=1

AGC AGC readout 1: tuner AGC active O IF SC AGC below TOP RDS Demodulated Audio to RDS decoder 0: not active I IF SC

BITS FUNCTION STEPS RANGE MACRO FU REMTOP AGC Take-Over-Point 63 0.4..80 mV IF ALOIF Offset IF-PLL 63 Small DC-offset IF AL 20H = neutral

IF related bits (2):

• IF-PLL offset does NOT change calibrated centre-value(a slight offset can improve e.g. S/N ratio for QSS-sound or SECAM weak-signal performance)

IFLF=1 prevent the IF oscillator from being re-calibrated. This is useful only in European TV sets, where the Scart plug definition requires continuous tuner-CVBS output. Normally IF calibration is vertically synchronised. But when external video is selected, the vertical is no longer synchronous to the tuner-CVBS. If e.g. by over modulation the IF-PLL accidentally gets out of lock (LOCK=0), there is no need for a re-calibration, that might be visible in the tuner CVBS output signal. Keep IFLF=0 during channel-change & at start-up; the rest of the time it can be set to IFLF=1.

GTV Function → IFLF: sys_SetCalibrationIFPLLDemodulator

With OIF the IF-PLL can be given a small offset, for improved PLL behavior under noisy signal conditions. This depends on tuner + SAW filter, so OIF can best be a factory alignment (or set to 20HEX for no offset).

Bit SID is an independent line-frequency detector, indicating valid CVBS signal. SID can be connected to CVBS1-internal (tuner signal), to improve catch / hold performance of the Front-End (see bits: SD2..0, VID, VDXEN, VDX).

GTV Function → SID: ptun_GetIdents, ptun_GetVideoIdent,psys_GetVideoInputSignalIdent

TV & VCR-combi:It is possible to keep the IF-part functional, while the H&V deflection is put into standby (STB=0). Simply maintain the +5V and set IFLF=1. In this situation the indication IFL (IF in-Lock) is less reliable, so please use SID instead (coupled to CVBS1-front-end).


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IF related bits (3):BITS FUNCTION SETTING I / O MACRO FU REM AM AM or QSS/FM selection 0: QSS/FM, 1: AM I Sound SC AM-mono AMLOW AM LOWer amplitude 1: reduce with 6dB I Sound SC MONO MONO FM demodulator on/off 1: NB-PLL active I Sound SC Save power FMI QSS amplifier connects FM demod.

Internal (mono or stereo) 0: to QSS-output 1: to demod.

I Sound SC For test or external demod.

SSIF External Second Sound IF input 1: from external input I Sound SC See I/O switching QSS Output connection of QSS amplifier 0: not active

1: to QSSO / FM demod I Sound SC Sound via VIF

sound via SIF VDXEN, VDX

Coupling of gating functions between VIF and synchronisation circuit

0x: coupled if INA..D=0001 10: coupled 11: not coupled

I IF SC Improves performance

IFO2..0 Pin 43 function Pin 44 function Remark

000 Mute Mute High Ohmic output 001 IFOUT Mute Without Sound Trap or Group Delay

010 IFOUT after SndTrap Mute Including GD for flat SAW filter 011 FMROUT / DVBOUT,P FMROUT / DVBOUT,N Balanced DVB

100 FMROUT / DVBOUT,SE Mute

110 Mute FMROUT / DVBOUT,SE

FM radio-IF output when bit FMR=1 Single ended DVB

111 Black DC Black DC Black-level-DC = mute without DC jump

??ES7.2D: IF-AGC set at 6x (max) can be too fast (see below)

Bit AM=1 also selects between AM and FM mono Front-End-sound (AM is used only in France).

??Temporary for ES7.2D:When IF-AGC is set at 6x speed, it can get stuck when sync fails. SW cansolve this by checking for IVWF & reduce IF-AGC speed to 4x when IVWF=0.

GTV Function:AM: psnd_SetQssAm, psys_SetQssAmOutSelectAMLOW: psnd_SetAMDemodulatorGainMONO: psys_SetActivateFMmonoDemodulatorFMI: psnd_SetQSSAmplifierOutputSelection,

psys_SetConnectionOutputQSSAmplifierSSIF: psys_SetCombFilterControlQSS: psnd_SetQSSAmplifierMode,

psys_SetQSSAmpModeVDXEN: psys_SetEnableVDXVDX: psys_GetModeIFSyncInterface


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DVB related bits:

BITS FUNCTION SETTING I / O MACRO FU REM AGCM DVB AGC Mode 0: internal mode

1: external mode I IF SC Ext = AGC from

DVB add-on EPVI Enable Preset Value IF-PLL 1: value can be loaded I IF SC DVB down-mix

BITS FUNCTION STEPS RANGE MACRO FU REMPVI1 Preset Value IF-PLL-1 255

PVI2 Preset Value IF-PLL-2 255

IF SC Load while EPVI=1 andExternal reference IFE=1

Proper AGC control requires feedback from a digital DVB demodulator. With AGCM=1, the SIFAGC pin 42 becomes an input for an analogue AGC control voltage (generated by DVB add-on).

The Down-Mix function of UOC-III does not have a complete synthesizer. If a certain DVB add-on requires a different mixing frequency, the add-on can supply a reference into pin 33. The frequency of that reference should be programmed in PVI2/1 and latched after a strobe on bit EPVI.

GTV Function:AGCM: ptun_SetAGCModeEPVI: psys_SetIFPLLOscillatorPresetValueIFE:PVI1: psys_SetIFPresetValue1PVI2: psys_SetIFPresetValue2


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Mono sound:

In/OutIn/Out

MicroMicro

RGBRGB

StereoStereo

ColourColour YUVYUV


VIF & SIFVIF & SIF

MonoMono

This “Mono” sound section refers to the mono sound decoder in the analoguepart of UOCIII.

The sound demodulator in the digital part (mono & stereo) is described in section “Stereo”.


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• FM mono Inter-carrier or QSS operation

• AM mono demodulator in QSS operation

• Integrated sound band pass (4.5 / 5.5 / 6.0 / 6.5 MHz)

• Alignment free (Narrow-Band) PLL FM demodulator, switchable: (4.5 / 4.72 / 5.5 / 5.74 / 6.0 / 6.5 MHz)

• Second-Sound-IF-input (SSIF) and INTer-Carrier-Output (INTCO) for additional selectivity

(4.72 / 5.74MHz & FM-radio modes)

Mono sound & demodulator:

The IF frequency is stabilised using the X-tal reference oscillator. Sound band pass filters are integrated, although for extremely critical signal circumstances it is still possible to add one externally.


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VOUT

fi = 360o

LPF

SIF

0o

Multiplier

Synchronous AM demodulation:

Clipper

AGCExternal BPF (SAW)

The Multiplier in an AM sound demodulator folds the IF frequency spectrum back to zero Hz. Together with a Low-Pass-Filter this has the same effect as a bandpass filter in the IF stage.

The incoming AM signal is rectified. After integration (LPF) the result is the amplitude variation (LF) of the IF spectrum.


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90o

Multiplier

fi = 360o

AGC

OSC

Set fOSC

Narrow-Band PLL frequency range = fOSC +/- 150 kHzTYPICAL

Loop Filter

InternalBPF

No filters neededNo external filters needed (internally added for enhanced FM performance)

VOUT = 0 at 90o

VOUT = -1/2 at 45o

VOUT = +1/2 at 135o

SSIF

Narrow-Band PLL FM demodulator:

The narrow PLL loop filter is especially optimized for selectivity. Therefore the external bandpass filter can be omitted. The PLL frequency is selected via I2C-bus (gives improved sensitivity), making the NB-PLL solution multi-standard.

To optimize the sound performance with extreme, non-standard signals it is still possible to add an external filter.

Sound distortion, due to video contents:

Before SAW, video modulation is purely AM. Due to Nyquist-slope, upper IF frequencies are attenuated. Result is AM-to-PM conversion. The IF-PLL will lock to this (PM-modulated) Picture Carrier and thus the PM can couple to audio: via the audio down-mixing (multiply FM with PM-distorted carrier).

With black or full-white (or gray) video, the PM has a rhythm of mainly 16kHz. But when e.g a cross-hatch is applied, the video frequencies introduce extra side-bands around the PM distortion. This again pollutes audio demodulation.

Audio THD should be measured with equipment that filters out only the applied audio modulation plus its harmonics. Otherwise you include noise into the THD measurement.


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De emphasis level

10 100 1k 10k 100k

Soundoutput

[mV]

Volume

1400

1000

500

100

0.3

+ 12 dB

0 dB

- 64 dB

De emphasis level

MIN. sound volume (mute)

C=3n9

T=54µs

C=33p forBTSC stereo

f [Hz]

f 1 f 2

38Decoupling

39Mono output+ DeEmphasis SM0/1

15K2.5V

NB-PLL

Audio frequency response NB-PLL:AGN=0 : 125mVAGN=1 : 250mV

(nominal 27 kHz swing, 54% modulation)DSG=0 : SCARTOUT = 1VRMS

(8V required) DSG=1 : SCARTOUT = 2VRMS

MAX. sound volume (DSG=1)

10 100 1k 10k 100k

+ 6 dB/oct - 6 dB/oct

AGN

The high frequency roll-off is determined by the de-emphasis capacitor on pin DeEmph.

The low frequency cut-off is determined by the value of the external decoupling capacitor on pin DecsDem. The capacitor value should remain < 22µF, to allow fast enough DC-settling, after the +5V is applied.


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FM-Window & Band pass:

Band Pass

NarrowWindow

WiderWindow

FM-SoundCarrier

• Digital acquisition helper brings FM-PLL back in range, when it loses lock to the FM carrier

(set auto-mute: SM1,0=0,1 to limit noise from acquisition helper)

Bits FMWS1..0

Bit BPB

SM1,0 = 1,0 permanently mutes the FM demodulator output.Software can select between SM1,0=1,0 and SM1,0=0,1 to mute or de-mutethe Front-End FM-mono sound (NB-PLL).

GTV Function: mono/av-stereo: psnd_SetMute()


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BITS FUNCTION SETTING I / O MACRO FU REM

FMA/B/C FM sound carrier selection I Sound SC Mono FMD 10.7 MHz radio (overrules FMA..C) 1: 10.7 MHz carrier I Sound SC

FMR TV mode or FM Radio mode 1: FM radio mode I Sound SC Video blanked

Mono Sound related bits (1):

FMA FMB FMC FMD FMR FM - DEMOD. BP SOUND TRAP REM 0 1 0 x 0 4.5 MHz Intern 4.5 MHz NTSC-M, PAL-M/N 0 1 1 x 0 4.724 MHz Extern 4.5 MHz 2nd language Korea 0 0 0 x 0 5.5 MHz Intern 5.5 MHz PAL-BGIDK, SECAM-BG 0 0 1 x 0 5.74 MHz Extern 5.5 MHz 2nd language A2 1 0 0 x 0 6.0 MHz Intern 6.0 MHz PAL-I 1 1 0 x 0 6.5 MHz Intern 6.5 MHz PAL-DK, SECAM-DK

Als

o us

able

for

Eco

-FM

rad

io

mod

es

x x x 1 x 10.7 MHz Extern x FM radio mode 1 0 1 x 1 7.902 MHz Extern Video blanked Eco FM radio USA 1 1 1 x 1 9.608 MHz Extern Video blanked Eco FM radio Euro

• Eco FM radio uses narrow-RIF-SAW + fixed SIF-mixing frequency:

- Euro : (Sound = 38.9 -5.5 =) 33.4MHz, mixed with 43.008MHz = 9.608MHz- USA : (Sound = 45.75 -4.5 =) 41.25MHz, mixed with 49.152MHz = 7.902MHz⇒ Alternatives : 43.008 -37.508 = 5.5MHz or 49.152 -44.652 = 4.5MHz

The available functionality depends on the IC type number.

In general, un-used bits have no effect, but they should be written “0” for compatibility with future versions.

During eco-FM-radio mode the IF-PLL has no picture-carrier to lock-onto, instead it will be set to a fixed frequency (derived from Xtal).

• fXTAL/4 * 7 = 24.576/4 * 7 = 43.008 MHz , or

• fXTAL/4 * 8 = 24.576/4 * 8 = 49.152 MHz

By using (narrow) SIF-SAW filters (for TV sound), the Narrow-Band PLL can directly demodulate mono FM-radio.

GTV Function:FMR: ptun_SetTVFMModeFMA..FMD: psys_GetFMDemodulatorCentreFrequency


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BITS FUNCTION STEPS RANGE MACRO FU REM VOLL VOLume control Left 127 -70..0 dB Sound UC Device without DSP VOLR VOLume control Right 127 -70..0 dB Sound UC QFP128 only

BITS FUNCTION SETTING I / O MACRO FU REM AVL Automatic Volume Levelling mono 1: on I Sound UC AVLE AVL capacitor or East-West output 0: EW, 1: AVL available I Sound SC Shared pin AVLM AVL gain Maximal 1: maximal I Sound SC Fast settling FML Narrow-Band FM PLL Lock 1: PLL in lock O Sound SC FMW FM PLL in Window (see FMWS) 0: PLL in window O Sound SC Digital acq. FMWS1..0 FM PLL Window Select 00: 100kHz narrow

01: 225kHz normal 10: 450kHz wide 11: 900kHz

I Sound SC For FM radio, for selectivity, for high mod. for overmodulation

BPB By-Pass sound Band pass filters 1: filters bypassed I Sound TK BPB2 By-Pass Band filter 2 0: high-Q filter

1: 2nd filter bypassed I Sound TK More range for

overmodulation MONO MONO FM demodulator on/off 1: active I Sound SC Off during stereo CMCA Complete Mono Channel Active,

mono out on HP outputs 0: not active 1: active

I Sound SC 1=No mono AVL, 0=AVL on HP-L

AGN Adapted Gain for Ntsc mono sound 1: +6dB gain I Sound SC SM1..0 Sound Mute 00: no mute

01: Auto-mute FM audio 10: mute FM/AM audio

I Sound SC “Auto” limits noise from digital acquisition-helper

Mono Sound related bits (2):

For areas where over-modulation is expected, FMWS1,0 can enlarge the FM-PLL window to 900kHz (effective after the acquisition is complete).The 100kHz narrow window is only intended for FM-radio. The 225kHz window can be used for areas where over modulation never occurs. Use 450kHz for all other circumstances.

GTV Function: FMWS: psnd_SetFmWindowSelect

We advice to use SM1,0=0,1 for automatic muting of the mono FM-PLL demodulator (fast attack and slow decay of 20..40ms). Position SM1,0=1,0 can be used to mute the sound during channel switching.Position SM1,0=1,1 will not mute at all and is reserved for test purposes.

Normally transmissions with standard “M” (=4.5MHz) sound have an FM swing of 25kHz, only half of the 50kHz of other FM sound standards. To obtain equal sound output level, the signal can be amplified by +6dB via AGN=1.

During channel-change you can set AVLM=1 to get faster settling of the mono-AVL-circuit to the new selected audio signal.GTV Function: AVL: psnd_SetAVL

AVLE: psnd_SetAVLEnabledOnEastWestOutputPinAVLM: psnd_SetAVLGain


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Audio Carrier Search:Mono: Narrow-band FM-PLLFM-PLL carrier search

BPB=1, sound band pass offFollow SAW filter switching of the

video-colour-search M-SAW selected ? yes

NarrowSAW filter

FMA,B,C= 5.5/6.0/6.5MHz

Read FML

Found: De-Mute

> 5x FML=1 ?

BPB=0, band pass on

yes

BP-off makes FML more sensitive

= 4.5MHz

FMD=1, wait 3ms, FMD=0 Best order: 6.5→5.5→6.0→4.5

Read FMW

Max 10 times ?yes

Wait 20ms

BP-on makes FMW more reliable

Need SW integration of FML bit

> 5x FMW=0 ? no

FMW=0 means FM-NBPLL in window

Max 10 times ?no 5 out of 10 or earlier

5 out of 10 or earlier

Wait 10ms

?? Toggling FMD necessary for ≤ ES7.2D, to “unstick” mono NB-PLL at: power on cycle,search tuning and changing system or channel

The Narrow-Band-PLL mono FM demodulator has a digital acquisition helper, with a frequency window around its calibrated center value (FMA/B/C).

With the help of some software, an audio carrier search can be implemented.

1- Simply select an FM frequency.2- Then wait and see if the PLL demodulator can lock (bit FML).3- Finally check if the PLL-FM demodulator is in window (bit FMW).

With BPB=1 the sound band passes are off. This makes FML more sensitive.With BPB=0 bit FMW is more reliable. A solution is to integrate FML and FMWby software over several read-outs.

To avoid a false lock on other carriers (4.43 MHz colour, 5.85 MHz NICAM), the search order should be: 6.5 → 5.5 → 6.0 → 4.5 MHz.

GTV Function: mono/av-stereo: psnd_DetectStandard

After an FM carrier is found, the NB-PLL will try to stay locked. If the carrier goes outside the frequency window (FMWS1,0), the digital acquisition helper will quickly bring the NB-PLL back into the window.

We advice to select FMWS1,0=1,0 (=450kHz) as best compromise between selectivity and over-modulation.


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Stereo sound:

In/OutIn/Out

MicroMicro

ColourColour YUVYUV


VIF & SIFVIF & SIF

MonoMono

RGBRGB

StereoStereo

The digital demodulator can handle stereo and mono standards, independent of the analogue mono-NB-PLL demodulator.


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Stereo audio processing:

SSIF

I2SOUT2

I2SIN/OUT3

I2SOUT1

AM/FM

InL,R4InL,R3

InL,R2

SAS2..0

ADC

Dual 5 : 1

Dem Dec

DAC1

AM/FM

InL,R4InL,R3

InL,R2

HP2..0

Dual 8 : 1

SC2..0

VOL/R, HPVC

SSIF AGC

Scart

HP

inpu

t sw

itch

outp

ut s

witc

h

DSP

L,R,C,Surr,Sw,AVL,BBE,VDS

Dolby Pro Logic,Beep, Control ..

AD

C

Noisegen

Vol/Bal:Aux1/2/3

SS

IF

LS

InL,R5 InL,R5

8:1

External2ND sound IF

FM

QS

SS

IF

Tune

r

Analogue domain :• 1st SIF = QSS down-mixing• AM demodulation• FM mono demodulation

• 2nd SSIF with separate AGC• Switch for external SSIF input• Analogue cross-bar switches• Volume controlled HP output

Digital domain : • Stereo sound demodulation• Output processing• Digital cross-bar switching • I2S In and outputs, FM stereo radio• DCXO Xtal oscillator trimming

I2C write address of SSD = B0H

AM

DC

XO

DAC2

I2S3I2S2

I2S1

I2C read address of SSD = B1H


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Evolution of Audio/Video standards:

• Modulation Schemes for Terrestrial TV Sound Carriers:

- FM (Frequency Modulation) : most common- AM (Amplitude Modulation) : mono & only in France (L,L1)- NICAM (DQPSK) : Digital transmission

Video luminanceSound carrier

Colour carrier(s) Second sound carrier:

FM or NICAM

Multiplex standards

frequency


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BTSC multiplex spectrum:

50

25155

1 2 3 4 5 6 6.5FM d

evia

tion

[kH

z]

L+R

L-Rdbx

compressed

SAP (FM)dbx

compressed Professionalchannel

f/fH

Pilo

t

EIAJ multiplex spectrum:25155

1 2 3 4

(L+R)/2 (L-R)/2 or “B”FM

f/fH

Pilot


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Downmixer

Deci.

Deci. NICAM dec.

SAP/EIAJ

MPX

FM/AM Ch 1

FM/AM Ch 2

FM ident

Noise det.

decimationdeemphasisdBx noise red.dematrixchannel select

DemDecEasyProgramming

DemDec partof Sound DSP

SSIF

Demodulators

Demodulator / Decoder:

• Auto L,R or dual A,B decoding, whatever standard detected or selected(or identical to “MONO” if no multi-channel available, indicated by flags: GST,GDU=0,0 )

• MONO from 1ST sound carrier (FM or AM)

• SAP (Second Audio Program) for BTSC, optional dbx decompression

• DCXO Xtal oscillator trimming = more accuracy (+ phase adaptation for NICAM)

ADC

AudExt ADC

DemDec HW

External L,Ror AM-mono

Decoded Stereo-Left or Dual-A (or mono)

Decoded Stereo-Right or Dual-B (or mono)

Mono from 1ST sound carrier

SAP from BTSC

DC

XO

Noi

se /

sile

nce

AudioControlBass MgT

Dolby Pro LogicVDS

Main Channel Processing

SW Processing

Centre Channel ProcessingSurround Chan. Processing

(L+R)/2

Dig

ital O

utpu

t Cro

ssba

r

EPICS7A Sound DSP + embedded firmware

Beeper

AUX1/I2S1 Channel

AUX3/DAC1 Channel I2S3AUX2/I2S2 Channel

Dig

ital I

nput

Cro

ssba

r

Audio Monitor

I2S2

I2S1

DAC1

DAC2

L/A

R/B

Mono

SAP

The DEMDEC decoding runs on a 32kHz basis. The sound DSP executes 108 MIPS. I2S input is only possible at 32kHz, in master-mode.Supported formats: Philips, Sony and Japanese LSB justified format.


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Supported Sound standards:

Carriers [MHz]Standard SystemSC1 SC2

SC1= mono

SC2 FM-deviation [kHz]nom/max/over

M/N Mono 4.5 - mono - 15/25/50M BTSC

+ SAP4.5

5 x fHMPX

FM- / - /50 pilot=15.7kHz- / - /15

M-Japan EIAJ 4.5 - MPX - 15/25/50 pilot=55,1kHzM-Korea A2+ 4.5 4.724 ½(L+R) ½(L-R) 15/25/50B/G A2 5.5 5.742 ½(L+R) R 27/50/80B/G Nicam 5.5 5.85 mono Nicam 27/50/80I Nicam 6.0 6.552 mono Nicam 27/50/80D/K A2

A2*A2

6.5 6.2586.7425.742

½(L+R) R 27/50/80

D/K Nicam 6.5 5.85 mono Nicam 27/50/80L/L1 Nicam 6.5 5.85 AM Nicam AM index: 54/100/- [%]FM radio Stereo 4.5 ..10.7 - MPX - 40/75/150 pilot=19kHz

• DBX noise reduction included, according BTSC system specification TM


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• DDEP = intelligent user interface to

DEMDEC = minimum SW interaction

• Auto signal detection, identification, de-matrixing, muting, routing, selection of de-emphasis, type & level adjust

• ASD = auto-standard detection, or SSS = static standard selection

• EXPERT mode = without automatism

• Optional over-modulation adaptation to overcome problems with largely over-modulated FM carrier (China, India...)

DDEP features:

DemDecEXPERT mode

StaticStandardSelection

AutoStandardDetection

OVerModulationADaPTation


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SSD control bits (1):BITS FUNCTION SETTING I / O MACRO FU REM

EPMODE1..0 Easy Programming Mode 00: ASD, auto detect 01: SSS, forced standards 11: Expert mode

I SSD SC

STDSEL4..0 STanDard SELection, Each bit enables detection of the sound carrier of a certain standard, Set at least one

xxxx1: 5.5MHz xxx1x: 6.5 xx1xx: 6.5 (France AM) x1xxx: 6.0 (UK,HongKong) 1xxxx: 4.5 (Kor, US, Jap)

I SSD SC B/G-A2+NICAM D/K-A2+NICAM L/L1-NICAM I – NICAM M-A2,BTSC,EIAJ

REST RESTart standard recognition 01: toggle I SSD SC E.g. after changing SAW+STDSEL

DDMUTE DemDecMUTE of decoder outputs 1: Soft Mute I SSD SC Cosine, 32x2ms

OVMADPT OVerModulationADaPTion 1: Enable I SSD SC

SAPDBX Second Audio Program DBX expansion 0: Use dbx for BTSC stereo 1: Use dbx for SAP

I SSD UC

FHPAL FH acc. PAL used for BTSC pilot tone 1: PAL fH for BTSC pilot I SSD SC

STDRES4..0 STandarD REcognition Status Standard & Stereo mode O SSD SC

SNDMOD Sound MODe 0000: Normal 0001, 0010: Hall, Matrix 0011: DPL (normal centre) 0100: DPL 3-stereo 0101: DPL phantom centre 0110, 0111: VDS 422, 423 1000: SRS TruSurround 1001: Noise sequencing

I SSD UC

GTV Platform:stereo: psnd_SetStandard, psnd_DetectStandard for EPMODE, STDSEL,

REST, STDRESTstereo: psnd_SetMute for DDMUTEstereo: psnd_SetEffect for SNDMODstereo: psnd_SetSAPDecompression for SAPDBXRest of bits is not implemented


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SSD control bits (2):BITS FUNCTION SETTING I / O MACRO FU REM MAINSS CENTERSS SURROUNDSS AUX1SS AUX2SS AUX3SS

MAIN Signal Source for LS Idem for Centre channel Idem for Surround channel Idem for Aux1 channels Idem Aux2 channels Idem Aux3 channels

000: L/R or A/B (or mono) 001: MONO 010: SAP 011: Ext via ADC 100: I2S 101: Noise Generator 110: Digital Silence

I SSD UC -If no stereo then mono -Mono first carrier -BTSC second audio -Ext or AM-mono -Master-mode only -For Dolby balance

MAINDM AUX1DM AUX2DM AUX3DM

MAIN Digital Matrix 000: AB 001: [A+B]/2 forced mono 010: AA 011: BB 100: BA 110: Auto AA, if Dual received 111: Auto BB, if Dual received

I SSD UC -Stereo -Mono from stereo -Dual language A -Dual language B -LR swapped -Auto-Matrix on -Auto-Matrix on

ASAFO1 ASAFO2 ASDAC1L ASDAC1R ASI2S1L ASI2S1R ASI2S2L ASI2S2R

Audio Select for DAC2L Idem for output DAC2R Idem DAC1 left output Idem right output Idem I2S output 1 left Idem right Idem I2S output 2 left Idem right

0000, 0001: Main L, R 0010: Subwoofer 0011: Center 0100: Surround 0101, 0110: Aux1 L, R 0111, 1000: Aux2 L, R 1001, 1010: Aux3 L, R 1011: Main Sum 1100: Digital Silence

I SSD UC

Connect any signal to any output

GTV Function: psnd_Connect


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Auto Standard Detection:1. Phase 1: measure carrier amplitudes:

(at least one) 4.5, 5.5, 6.0, 6.5MHz

2. Determine maximum amplitude

3. If maximum < threshold: FAILED

4. Decide mono standard: B/G, D/K, M, I, L

5. Phase 2: initiate search for multichannel standard(s)

6. Signal result in status bits STDRES4..0

Example: D/K search procedure

Channel1: FM, 6.5MHzmono output

Find largest?

Measure carrier amplitude,using ch. 2 AM demodulation

Channel 2: 6.258MHzFM, Europe IDENT on




Ident found? Ident found? NICAM found? Ident found?

Set standard“D/K A2 (1)”


Set standard“D/K NICAM”


timeout timeout timeout

yes yes yes yes

6.258 6.742 5.85 5.742

timeout

This audio detection algorithm is executed by firmware in the audio DSP. It can be configured by embedded (GTV) software to suit a certain application.

GTV Function: stereo: psnd_DetectStandard


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Channel switch with ASD:

Stereo: using DDEP with ASDASD carrier search

DDMUTE=1, wait 32ms

Follow SAW filter switching of thevideo-colour-search

M-SAW selected ?yes

NarrowSAW filter

STDSEL= 5.5/6.0/6.5MHz

Soft mute of DemDec outputs

= 4.5MHz

REST=0 →1 → 0 Toggle to restart ASD process

Read STDRES4..0

Found

DDMUTE=0, wait 32ms

yes

Adjust Back-End

De-mute DemDec outputs

Get resultStill searching ?

Possibly adapt AVL, volume-trim etc.

• Automatic selection of Mono/Stereo or AA/BB for Dual (set user preference)

DDMUTE=1 Keep sound muted


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Stereo Audio Back-End:

Dig

ital O

utpu

t Cro

ssba

r

I2S3

Dig

ital I

nput

Cro

ssba

r

Audio Monitor

I2S2

I2S1

DAC2

DAC1L/A

R/B

Mono

SAP

Ext L/A

Noise / Silence

Ext R/B

LevelAdjust

+MainSM

SWSM

CSM

SSM

AUX1SM

AUX2SM

AUX3SM

Mas

ter

Vol

ume

+Trim

DV

B o

r D

BB

Mai

nE

qual

CE

qual

Bas

s M

anag

emen

t

SDelay

Mai

nB

ass

Tre

Lou

dC

Bas

sT

re, L

oud

SB

ass

Tre

MainMsel

CMsel

SMsel

Main AV

LDPL

VD

S42

2/42

3or

Tru

Sur

roun

d

Pse

udo

Hal

l

Dem

Dec

Mat

rix

Vol

ume

+TrimAUX1/I2S1 Channel

AUX3/DAC1 Channel

AUX2/I2S2 Channel

CIN

SIN

C

S

L,R M/ST

L,R DPL

BB

E

(L+R)/2

Beeper

(L-R

)/2

(L+R

)/2

S-D

PL

C

Ext

Spa

tial S

tere

oor

Ext

. Pse

udo

Ste

reo

or 3

D s

ound

The Noise generator:- fulfills the DPL licensee requirements- produces weighted noise with >9dB/octave roll-off- has a center frequency between 500Hz and 1kHz- is selectable for all sources, in all combinations for L, R, Centre and Surround

A Noise Sequencer (under user control) allows easier alignment of sound parameter balance between the speakers.


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• Decay time constants: 20 ms, 2, 4, 8, 16 s

• Weighted-mode reduces influence of bass components (optional)

• Adjustable threshold UREF

Left In

Right In Right Out

Left Out

Level Detector(optional weighting) 1 / XAttack / Decay Filter

UREF

Stereo AVL: Auto Volume Leveling


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ExtendedPseudoStereo

ExtendedSpatialStereo

DolbyPro Logic

Virtual DolbySurround

Sound-Field features:

Mono

Stereo

DPLencoded

Source signal:


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• Retrieves the spatial information from any stereo signal

• Produces a larger sweet spot

• SRS approved

• “Centre” and “Space” control

SRS 3D Sound:

SRS TruSurround :• SRS TruSurround virtualizer (422/423), SRS approved

“422” = 4 channels to 2 speakers (virtual centre + surround speakers)“423” = 4 channels to 3 speakers (virtual surround speakers)

TM

TM


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• DPL licensee requirements fulfilled

• Stage includes Dolby 3 Stereo and Phantom (= no center speaker) mode

• Noise sequencer & Bass ManagemenT (BMT = bass redirection)

• VDS 422/423 according to Dolby specification, Dolby approved

Dolby Pro Logic, Virtual Dolby Surround :

Pseudo Hall / Matrix:• Pseudo Matrix: Centre: (L+R)/2

Surround: (L-R)/2, up to 30 ms delayed

• Pseudo Hall: Centre: (L+R)/2Surround: (L+R)/2, up to 30 ms delayed

TM TM


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Dolby Pro Logic & Bass Management:

Left

Right

Aut

o B

alan

ce

Ada

ptiv

e M

atrix

SurroundProcessing

L*

C*

R*

S*

-3dB

+

+

+

+

DPLPh3ST

DPLPh3STDPLPh3ST

DPLPh3ST

L

C

R

S

DPL Phantom 3-Stereo L L+C-3dB L+S-6dB C - C R R+C-3dB R+S-6dB S S -

Mode

• Virtualize speaker(s) for “Centre” or “Surround”

[dB] BMT1 BMT2 BMoff a1 -10 -100 -100 a2 -10 -100 -100 a3 -10 -4.5 -100 a4 a4DPL

-10 -100

-4.5 -100

-100 -100

Sw 0 1 1 b1 HP Flat Flat b2 HP Flat Flat b3 HP HP Flat b4 HP HP Flat

• BMT1 = single woofer system with improved filtering:small speakers for L, R, C, S plus extra SubWoofer

• BMT2 = normal center mode with bass splitter (DPL):large speakers for L, R; small for C, S (SW is optional)

• BMoff = wide center mode (DPL):large speakers for L, R, C; small speaker for S

+

+

a1

a3

a2

a4

lp

+

+

lp

b1

b3

b2

b4

L’

C’

R’

S’

SW’10

-10dB

The internal Low-Pass-filter for the SubWoofer can be switched flat, to allow the use of external SubWoofer filtering.

If DPL is active, then a4DPL is used.


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• The Stereo Expander makes a more wide sound field (“Incredible-Stereo”)

• The Mixer controls the intensity of the widening effect (alpha)

Stereo expander

Extended Spatial Stereo (ESS):

Left In

MixerRight In

Right Out

Left Out

Extended Pseudo Stereo (EPS):

Stereo expanderMonoRight Out

Left Out

De-correlator

• The De-correlator produces a pseudo stereo signal from a mono signal

• Control of effect intensity (“Incredible-Mono”)


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• Max. boost 18dB @20Hz, 4.5dB

@16kHz; range 30dB

• Adjustable non-attack-level

& non-attack -frequency

5-band graphic Equaliser, Loudness:

• 5 bands equalisers in L/R-Main

and Centre channels

• -12dB to +12dB in 1dB steps

-14

-12

-10

-8

-6

-4-2

+0

+2

+4+6

+8

+10

+12

20 10k50 100 200 500 1k 2k 5k Hz

dB100 300 1k 3k 8k


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Dynamic Virtual Bass (DVB):

Dynamic Bass Boost (DBB):

• Level-dependant Bass-Boost, needs subwoofer or large main speakers

• Impression of deep bass, by shifting the bass info to higher frequencies

• Used in small TV-Sets without subwoofer or full range speakers

Headroom

+12dB

0dB

60Hz

Left In LevelSensorRight In Right Out

Left Out

BoostControl

Left In

Right In

Right Out

Left OutGenerate

higherharmonics

AutoGain

Leve

l Sen

sor

Advice: Do not combineDVB, DBB, BBE

together

DynamicUltraBass - II

DynamicBassEnhancement


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• Dynamic delay compensation + program driven bass/treble augmentation

• Improves reproduction of transients

• Restores brilliance and clarity of original live sound

loudspeaker

BBEAud

io D

elay

frequency

Delay Compensation

frequency

loudspeaker

BBE

Am

plitu

de

Amplitude Compensation

BBE :TM


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Left In

Right In

Right Out

Left Out

Sub Woofercontrol

LowL+M+L

LowR+M+R

M+L

M+R

LowL+LowR=SW½SW+M+L

-½SW-M-R

(½SW)+M+L

(-½SW)+M+R

SW+2M+(L+R)

½SW++M+R

Eco Sub Woofer:

• Usual construction: one amplifier is inverting ⇒ heavy load for SW speaker

• New: “Eco Sub Woofer” = better power efficiency for SW-speaker (selectable via software)

Right Out

Left Out ½SW+M+L

-½SW+M+R

(½SW)+M+L

(-½SW)+M+R

SW+(L-R)

Left In

Right In

Sub Woofercontrol

LowL+M+L

LowR+M+R

M+L

M+R

LowL+LowR=SW

M = Mono contents = most of the audio energyL = Unique components in LEFT channelR = Unique components in RIGHT channelLowL = Low frequency contents of LEFT channelLowR = Low frequency contents of RIGHT channel SW = Assembled from LowL and LowR

Usually one of the loudspeaker amplifiers is inverting. The low Sub Woofer spectrum can not be reproduced by the (small) L & R speakers, so no filtering is needed for L & R. But in this construction, the Sub Woofer speaker has to deal with a heavy extra load (+2M+L+R).

Via software you can enable “Eco Sub Woofer” mode, that avoids this problem.Note: the 2 loudspeaker amplifiers must have the same polarity.


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• Level Adjust: range -15..+15dB (-84dB mute at “-16”), resolution 1dB

• Soft Mute/demute: cosine curve of 32 steps, rate = 2ms (takes 32 ms)

• Master Volume & Trim: – Trim = baseline of Volume setting (per channel)– Master Volume = offset, added to the major audio channels

Sum of Trim + Master Volume clipped to +24dB (max. gain)– Smooth Volume: 1/8dB steps, max. speed of 62,5dB/sec

• Bass & Treble: (independent of equaliser = easy control)– Range from -16dB up to +15dB– External resolution 1dB– Smooth: Internal resolution 1/32dB, max. rate of change 15.6dB/sec

Level-adjust, Volume/Trim, Tone:

µC

I2C-bus

Master Volume Trim

+

GainModule

Audiosamples

During power-off state the outputs “LS” and “HP” are muted.


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• Static Volume mode: (Bass, treble and loudness not affected)

– Master Volume + Trim limited to -30dB

• Static Control mode: (Set Loudness none-attack level ≤ 0dB)

– Master Volume + Trim limited to -1dB– Bass, treble or equalizer limited to +8dB

• Dynamic Volume mode: (Set Loudness none-attack level ≤ 0dB)

– Master Output signal limited to -3dB– Bass, treble not affected

• Dynamic Control mode: (Set Loudness none-attack level ≤ 0dB)

– Master Volume + Trim limited to +3dB– Bass & treble dependent on volume (see graph)

Clip management:

Bass & Treble limiting in Dynamic Control mode:

Bass/Trebleselected

Bass/Trebleactive

-16dB

-16dB

0dB +15dB

0dB

+15dB

+10dB

+5dB

-12dB Master Volume+Trim



+3dB Master Volume+Trim


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In / Out switching:

MicroMicro

RGBRGB

StereoStereo

ColourColour YUVYUV


VIF & SIFVIF & SIF

MonoMono

In/OutIn/Out


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SCART AV-switching (1):

Stat

R

VidL RIN

LIN

Vid

RGB

Fbl R / PR

G / Y

B / PBAV1

RG

B3

CV

BS

3

InL,

R2

RINLIN

VidC

Y

AV3

Y,C

4

InL,

R4

Out

L,R

1

IFV

O

Stat

R

VidL RIN

LIN

Vid

AV2

CV

BS

2

InL,

R3

Out

L,R

2

SV

O

C3

• 2x full SCART• 4x CVBS• 3x S-VHS• 2x DVD

• 1x full SCART• 1x SCART-in• 3x CVBS• 2x S-VHS• 1x DVD

Fbl3

RG

B3

LSL,RCV

BS

O

PIP

InL,

R5

RINLIN

VidC

Y

AV3

Y,C

4

InL,

R4

Stat

R

VidL

RINLIN

Vid

R/CGB

Fbl R/ C /PR

G/Vid/Y

B / PBAV2+4R

GB

2

CV

BS

2

InL,

R3

Out

L,R

2

SV

O

You

t

Ysy

ncIn

Sw

0

No

YU

V L

oop

No

YU

V L

oop

Fbl2

LSL,RCV

BS

O

PIP

InL,

R5

Stat

R

VidL RIN

LIN

Vid

RGB

Fbl R / PR

G / Y

B / PBAV1

RG

B3

CV

BS

3

InL,

R2

Out

L,R

1

IFV

O

C3

Fbl3

RG

B3

YU

Vin

UV

out

Ysy

ncIn

Loop

Fea

ture

You

t

A new feature is the capacitor at input YsyncIn. This allows DC re-clamping of the black-reference level, right before the sync-separator. This improves sync performance.

The DC-level on CVBS output pins allow direct coupling of a 75Ω transistor buffer/driver:

GTV Function: psnd_Connect()

+5V

1k

UOC- III

CVBSOUT

1k

1k

75 Ohm cable75Ω

75Ω


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Cinch AV-switching (2):

R

Vid

LRINLIN

VidC

Y

AV3

Y,C

4

InL,

R4

Out

L,R

1

SV

O

RINLIN

Vid

AV2

InL,

R3

CV

BS

2Monitor-OUT

HP

HP

L,R

2

• 3x CVBS• 2x S-VHS• 1x DVD• 1x MonitorOUT

InL,

R5

LSL,R

RINLIN

Vid

PBAV1

RG

B3

InL,

R2

PR

Y

Y,C

3

Fbl3

CV

BS

O

PIP

• 4x CVBS• 3x S-VHS• 2x DVD• 1x MonitorOUT

IFV

O

R

Vid

L

C /PR

Vid/Y

PBAV4

RG

BF

3

InL,

R5

RINLIN

VidC

Y

AV3

Y,C

4

InL,

R4

Out

L,R

1

SV

O

Fbl2

Monitor-OUT

RINLIN

HP

You

t

Ysy

ncIn

Sw

0

No

YU

V L

oop

No

YU

V L

oop

RG

B2

HP

L,R

2

RINLIN

Vid

PBAV1

RG

B3

InL,

R2

PR

Y

Y,C

3

Fbl3

LSL,R

RINLIN

Vid

AV2

InL,

R3

CV

BS

2

CV

BS

O

PIP

IFV

O

YU

Vin

UV

out

Ysy

ncIn

Loop

Fea

ture

You

t

GTV Function: psnd_Connect()


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Video switching CVBS/Y/C:INA INB INC IND Selected Video

CS1A CS1B CS1C CS1D

CV2 PIP output

Remark

0 0 0 0 x CVBS1 Mute 0 CVBS1 CVBS1 Internal from IF

0 0 0 1 1 CVBS2 CVBS2 “Internal” from pin CVBS2

0 0 1 0 0 CVBS2 CVBS2 Bit CV2 = 0 1 0 1 0 x Y2/C3 Y2+C3 No YCD in this position 0 0 1 1 x CVBS3 CVBS3 1 0 1 1 x Y3/C3 Y3+C3 0 1 0 0 x CVBS4 CVBS4 1 1 0 0 x Y4/C4 Y4+C4

Y + C added = CVBS

0 1 0 1 x CVBS5 CVBS5 1 1 0 1 x Y5/C5 Y5+C5

Only when YC=1

SVO1/0 SVO pin 48 function Remark

00 IF video output (CVBS1) SCART, after Sound trap & GD 01 Selected Video Output See bit INA..D

10 IF video input To Sound trap & Group Delay 11 Spare -

YCD Y/C Detection

0 CVBS signal at input

1 Y/C signal detected

• Y/C Detection (YCD) only done once: directly after source-switching

The YCD detector compares the chroma-amplitude on the selected Y and C. For this it needs the chroma bandpass circuit, therefore the YCD detection can not be done continuously.

GTV Function:IN: psys_SetSourceSwitchCV2: psys_SetCVBS2InputSignalSelectionYCD: psys_GetOutputYCDetector


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IE3/2,IN3,FIN,FINM,YUV2..0

Fast-Insertioncontrol

Insertion & loop-interface:

• External loop can be YUV or YPRPB (DVD) level (bit INTF)

CV

BS

& Y

/C S

witc

h

Digital Scaling &Double Window

CVBS2CVBS/Y3CVBS/Y4

C3C4

555851

5952

Sync

73 YSync IN75

U V

76 74 72

Y U V

71 70

Optional PIP orYUV-feature loop

YUV2..0,IE3/2

DVD-to-YUV

YUV-to-

DVD

DINT

INT

F

DA

CD

AC

DA

C

Y U V

RDS,TXT,CC

AD

C

AD

CA

DC

Y U V

VBICVBSSEL

CVBS/Y5 72

C5 70

CVBSOUT 64

CVBS1 Clamp

78 79 80

R3

/PR

G3

/ Y

B3

/ PB

Clamp

77

Fbl

3

IN3

INT

F

SYS

YUVinsert

Digitalinsert

Pea

king

,cor

ing

RGB3

RGB2

Col

our d

ecod

er

Com

b

RGB-to-

DVD

ClampClamp

DVDinsert

RGBinsert DVD-level-YPRPB

YIN2DVD/RGB2

Clamp

IntC

CLD

• PIP insertion possible over Double Window (after feature loop and digital interface)

PIPRGBinsert

PIPYUVinsert

• Connect YSyncIN to YOUT via 100nF, for optimal sync clamping

Scaling +PIP insert

CL

D

All input signals are “translated” into YUV or YPRPB (=DVD) and can be looped through an external interface. In this loop you can insert e.g. a picture improvement feature or PIP.

YOUT is always available, to be coupled to YSyncIN via 100nF, irrespective of the chosen input.

All input signals can be routed through the digital interface for half-screen-compression or panoramic-zoom.

For PIP insertion you can use bit FINM to insert AFTER the digital interface. Please note that PIP insertion always requires a Fast-blank insertion control, so IE2 or IE3 and pin Fbl2 or Fbl3 must be activated too (but must be inactive during vertical).

GTV Function:FINM: psys_SetFastInsertionModeINTF: psys_SetAmplitudePolarityYUV


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Video configuration YUV/RGB/DVD: Configuration YC YUV2..0 INTF

Function RGBF3 pins Function RGBF2 pins Remark

A 0 000 - RGBF2 input (IE3,2=0,1) IE3=1 disables RGBF2

0 Loop interface DVD B 0 001

1 Loop interface YUV C 0 010 - YUVF2 input (IE2=1) YUVF2 priority over RGBF3 D 0 011 -

RGBF3 input (IE3=1)

DVD2 input RGBF3 priority over DVD2 E 0 100 - DVD3 input (IE3=1) DVD2 input (IE3=0) IE3=1 disables DVD2 F 0 101 - DVD3 input (IE3=1) RGBF2 input (IE2=1) RGBF2 priority over DVD3

0 Loop interface DVD G 0 110

1 DVD3 input (IE3=1)

Loop interface YUV H 0 111 - DVD3 input (IE3=1) YUVF2 input YUVF2 priority over DVD3 I 1 000 - RGBF3 input (IE3=1) RGBF3 priority over Y/C J 1 111 - DVD3 input (IE3=1)

CVBS5 or Y5/C5 DVD3 priority over Y/C

• DVD = YPRPB = colour bar 100% saturation: Y= +1.0VPP, PR= +0.7VPP, PB= +0.7VPP

• YUV = colour bar 75% saturation: Y= +1.4VPP, U[B-Y]= -1.33VPP, V[R-Y]= -1.05VPP

• For insertion, always IE3/2 and pin Fbl3/2 must be activated (not for loop interface)

GTV Function:YC: psys_SetCVBSIE: pimg_SetRGBYUVBlankingEnableYUV: psys_SetRGBYUVINTF: psys_SetAmplitudePolarityYUV


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Switching priority YUV/RGB/DVD: IE3 IE2 FIN Fbl3 Fbl2 Displayed source Remark

0 0 x x x

0 1 0 x low 1 0 0 low x B

oth

disa

bled

1 1 0 low low

CVBS or YC mode Defined by bit INA..D

0 1 0 x high RGBF2, YUVF2 or DVD2 Switched on by Fbl2=high 0 1 1 x x RGB2, YUV2 or DVD2 Forced on

1 0 0 high x RGBF3 or DVD3 Switched on by Fbl3=high One

en

able

d

1 0 1 x x RGB3 or DVD3 Forced on

1 1 0 low high

1 1 0 high low 1 1 0 high high B

oth

enab

led

1 1 1 x x

Priority: YUV ⇒ RGB ⇒ DVD.

If input-2 and input-3 are of the same type, then input-3 gets priority over input-2

W hen both are RGB, condition IE3=1 disables RGB2 completely

• While FIN=1, pins Fbl2+Fbl3 are not in use but they can still

be read via IN3/IN2 ⇒ useful as digital inputs

• FINM=1 inserts fast-insertion after digital interface (PIP),

full-insertion remains before digital interface

Input Output

Fbl3 Fbl2 IN3 IN2

low low 0 0 low high 0 1

high low 1 0

high high 1 1

Bits IN3 and IN2 (while FIN=0) are sampled during the vertical interval (VBI). This allows software to detect the difference between fast-OSD-RGB-insertion(Fast-blanking overlay on just a few lines) and full-screen RGB insertion. Only during full screen insertion the Fbl3/2 line will be permanently high (so also during VBI).

GTV Function:FIN: psys_SetForcedInsertionFINM: psys_SetFastInsertionModeIE: pimg_SetRGBYUVBlankingEnableIN: psys_SetSourceSwitch


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Fast PIP insertion possibilities:

• PIP insertion AFTER feature loops: set FINM=1 & use Fast-blanking

1. Insertion can always be done into a YUV- or DVD-loop interface

2. PIP can best be inserted as YUVF2, or in series with RGBF3 (via own switch)

3. Dual full-SCART with 2x RGB can only enable one RGB at a time

Fast insertion of e.g. PIP Remark PIP as YUV into YUV- or DVD-loop OK PIP inserts itself in the loop via its own switch, no

Fbl required PIP at RGBF2 over RGB3 No RGB2/DVD2 is disabled during RGB3 PIP at RGBF2 over DVD3 OK PIP at YUV2 over RGB3 OK YUV has priority over RGB PIP as DVD over anything No PIP not possible as DVD PIP at RGBF3 over RGB2 No RGBF2 permanently disabled while RGB3 enabled PIP at RGBF3 over DVD2 OK RGB has priority over DVD PIP at RGBF3 over YUV2 OK RGB has priority over YUV (set FINM=1)


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PIP use-cases:

• PIP only of CVBS or Y/C sources

7374 72

Y U V

71 70

PIP insertRGBF or YUVF

Y

75

FBL

PIP notCompressed

73 YSync IN75

U V

76 74 72

Y U V

71 70

PIP in YUV-loopuses own switch

Y

Insertion

PIP alsoCompressed

64

CV

BS

PIP

• PIP in YUV-loop uses its own insertion switch

• Outside PIP-area, PIP-IC bypasses external RGBF input

72

G B R

71 70

PIP insertRGBF or YUVF+bypass RGBF

75

FBLNow PIP can show

RGB/YUV input+

RGBFBL


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Audio stereo switching:

• SCART: DAC1 = Front-End signal InL,R1 (from tuner)

Non-SCART: DAC1 = selected signal, unprocessed (SAS2..0)

• DAC2 available for monitor (outputs LS), when I2S DACs are added (LS1..6)

• I2S = future-proof extension interface, e.g. to an AC3-decoding DSP

SSIF

I2SOUT2

I2SIN/OUT3

I2SOUT1

FM

InL,R4

InL,R3InL,R2

SAS2..0

ADC

Dual 5 : 1

Dem Dec

DAC1

InL,R4

InL,R3InL,R2

HP2..0

Dual 8 : 1

SC2..0

VOL/R,HPVC

SSIF AGC

Scart

HP

DSP

Audio

DSPAD

C

Noise gen

SS

IF

LS

InL,R5 InL,R5

8:1

DAC2

External2ND sound IF

DAC

DAC

DAC

LS1LS2LS3LS4

LS5LS6

AC

3 D

SP

Optional

I2SIN for test purposes

AM

FM

QS

SS

IF

Tune

r

I2S3I2S2

I2S1

AMFMAM

SMLS

I2S outputs can be connected to an external DAC, e.g. UDA1334 DAC, to obtain more audio outputs. In that case the “LS” outputs can be serve as extra audio monitor outputs.

I2S output offers “future-proof” extension possibilities, e.g. when you want to upgrade a TV with an additional DSP for AC3 decoding.

In the current silicon the third I2S port has limited functionality (test purposes only).

When volume-controlled HeadPhones outputs are not needed, bit HPVC=0 can bypass the amplifier. This enhances the S/N performance when HPOUT is used as “fixed-level” output.

GTV Function:SAS register is used in psnd_Connect to establish signal paths.Bit HPVC has no implementation (initially set in LibCoMa)


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Stereo use-cases:

DAC1

InL,R2/3/4/5 Dual 8 : 1 VOL

Scart

HP

Aud

io D

SP

LS

8:1

DAC2DACUDA1334BT

CentreSurroundSub Woofer

SPDIFI2S3

I2S2I2S1

FMAM

LeftRight

Dem

Dec

Full DPL

Asia DPL

FE

DAC1

InL,R2/3/4/5 Dual 8 : 1 HPCV

Monitorbass+treble controlled

DS

P LS

8:1

DAC2

FMAM

LeftRight

Dem

Dec

CentreSurround

Virtual DPL Eur-Eco DPLInL,R2/3/4/5 Dual

8 : 1 HPCV

Scart or OFF

LS

8:1FMAM

LeftRight

OFF or CentreOFF or Surr

DAC1D

SP

DAC2Dem

Dec

InL,R2/3/4/5 Dual 8 : 1 VOL

Scart

HP

LS

8:1FMAM

LeftRight

FE

DAC1

DS

P

DAC2Dem

Dec

• Headphone independently switchable • Monitor output is sound controlled

• HP-out = only volume controlled • User-choice for either Scart-out or DPL

An

alo

gu

eD

igit

al

DACUDA1334BT

SRC

Full DPL:In European SCART chassis, the tuner signal (Front-End) must always remain present at the SCART output. This occupies DAC1. A full Dolby Pro-Logic implementation with 5 loudspeaker channels requires two external I2S DACs.

Virtual DPL:The sound DSP inside UOC- III “Hercules” can also virtualize DPL, requiring just two audio amplifiers.

European Eco DPL:This option allows the TV-user to decide between either SCART-Front-End-sound output or four independent channels for DPL. The Sub Woofer channel can be virtualized or connected between L&R amplifier outputs.

Asia DPL:Asian TV chassis normally have a “monitor” output that reproduces the same audio & video as displayed on the TV screen (so Front-End = inactive while external sources are selected). If you don’t implement independent HeadPhones control, then 4 channels are available for DPL reproduction.


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I2S-DAC application:

1ΩV

DD

A

VS

SA

VD

DD

VS

SD

100Ω

220k

100Ω

220k

OutL

OutR

VREF

BitClkWordSel

Data

Sfor1

Sfor0

Deem

PCS

Mute

SysClk

+3V3

UDA1334

1Ω

I2S_WS

I2S_D0

I2S_CLK

I/O pin

UOC- III “Hercules”

“Floating”Xtal 24.576MHz

DC

XO

:4

I2S_D1

I2S_D2

I2S_CLK = 256*fSBitClk = 64*fSI2S_WS = fS

• Very simple application

• I2S_Clk can be set 4 times faster to act as SysClk for noise shaping

UDA1334


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Audio I/O switching:

• 5 sources: four externals + one via Tuner (AM or FM)

HPO2 SO2

SAS2

HPO1 SO1

SAS1

HPO0 SO0

SAS0 AM

Headphone Output: Scart/Cinch Output: Selector Audio Input

REMARK

0 FM-mono intern From NB-PLL 0 0 0

1 AM-mono intern From AM demodulator 0 0 1 - Audio 2 input 0 1 0 - Audio 3 input 0 1 1 - Audio 4 input 1 0 0 - Audio 5 input 1 0 1 - DSP Fixed output DAC1 1 1 0 - DSP vol contr output DAC2 1 1 1 - Mute

Not available at audio INPUT

selector


HPVC H eadPhones Volume C ontrol active 0 : bypassed I Sound S C Better S/N SMLS Sound M ute LS outputs 1 : LS outputs muted I Sound S C Not HP outputs DSG D efine Sound G ain from input to output 0 : 0dB, 1 : +6dB I Sound S C +6dB needs 8V

GTV Function:psnd_Connectpsnd_SetMuteChannel


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FMI

AM

62, 63VOL

AudioOUTvolume-controlled

39 QSSOUT or SCARTOUTnon-controlled

ChromaRefOUT

Switch output2.1V+RefOUT33

+4.5V

E2D,QSS

Selected =ExtMONO

15KMute

SM0/1,FMI,AM

AMQSS

FM-De-Emphasis

From intern SIF

To mono NB-PLL

Ref to DVBIF down mixer

SSIF input

Mix Ref input

Mono AVLcapacitor

21

MonoAVL

East-West Amplifier

East-West drive 110º

AVLE

AVL

Options for pins 21,33,39,62,63:

CMB 2..0 Function of pin 33 I/O

000 Mono AVL capacitor (AVLE=0), SIF to NB-PLL and Stereo Decod.

I

001 2.1V + chroma subcarrier REFOUT O 010 SWO low output < 0.8V O 011 SWO high output = 4.5V O 100 Reference carrier input for

DVB down-mix (REFIN) I

101 SSIF to NB-PLL and Stereo Dec. I 111 SSIF input to mono NB-PLL,

intern SIF to Stereo Decoder I

QSS FMI AM E2D Function pin 39 Mode 0 - - 0 FM de-emphasis 0 - - 1 Ext. audio Out

Intercarrier

1 1 - 0 FM de-emphasis 1 1 - 1 Ext. audio Out

QSS-mono

1 0 0 - QSS output 0 1 1 - AM output

QSS mode

To Stereo Decod.

CMB2..0

SSIF

330..10kΩ

The function of these pins depend on the chosen application, e.g the capacitor for mono-AVL can be connected at pin 21 or pin 33.

CMB2..0=000:

In a mono-FM-configuration pin 33 can be used to connect the AVL capacitor.

CMB2..0=101 or 111:

By setting bit SSIF=1, pin 33 can become a Second-Sound-IF input. Useful for:- FM-radio- external sound band pass filter for 2nd of dual-carrier sound 4.724, 5.74MHz- extra selectivity (4.5, 5.5, 6, 6.5MHz) for extremely difficult signal circumstances

GTV Function:QSS: psnd_SetQSSAmplifierModeFMI: psnd_SetQSSAmplifierOutputSelectionAM: psnd_SetQssAmE2D: ptun_SetAudioSignalOnAUDEEMPinCMB: psys_SetCombFilterControl


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MonitorOut

Sound OutCVBS Out

SCART1CVBS2 Ext

CVBS1 Int

ExtSnd

SVOExt

Ext

Int

Select

15kFM

VOL

IntE2D

Europe

Sound Out

Ext Sound In

CVBS Out

CVBS InCVBS2 Ext

CVBS1 Int

DeEmph

ExtSnd

SVOExt

Ext

Int

Select

15kFM

VOL

Int

Input

E2D

Asia-Pacific

DeEmph

Ext Sound InCVBS In

SCART1-output is always Front-End

(tuner)

Monitor-output is viewed source

Source switching Europe ⇔ Asia:

GTV Function: psnd_Connect


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More functions with LESS pins:

• UART added for communication to add-on micro (DVB, DVD)

• Many pins can be “doubled” :– Sound Mute can be combined on Vertical-GUARD – LED can be multiplexed on local keyboard– Reset can be forced by short-circuiting “DecV1V8”– Mains-failure / PowerDown = connect to p27 EHT, read via bit XPR– Most I/O’s can be used as 3-level output,

combine e.g. write-protect with Standby,or 2 standby modes...

GTV Function:3 level output: rbsc_SetMLPortAnalogue value readout: rbsc_GetADC Switching from output to input an setting a value: rbsc_ConfigPort,

rbsc_SetPin


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EVG=1

Blanking ofRGBOUT pins

Vguard-input + I/O:

4.5V

3.3V

Vguard

47k

560 LED

NDFTDA8357

Verticalblankingperiod

• Double use of Vguard-input-pin (e.g. as LED driver or as Mute-output)

• Input: read bit NDF (=1 when guard-pulse fails), Vertical protection if bit EVG=1

• Open-drain Output : low when LED=1, floating during Vblank (1ms out of 20ms)

UOC III “Hercules”

13

10kMute

VGM1 VGM0 Mode of pin Vguard0 0 Vertical Guard (bit NDF)0 1 Vguard + LED output (0..3.3V)1 0 Switch output (0..5V)1 1 Input-only (result in bit NDF)

3.6VSample& Hold

VGM1,0

LED

GTV Function:NDF: psys_GetVerticalOutputEVG: psys_SetVerticalGuardModeLED: psys_SetModeLEDDriver


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Analogue Local Keyboard + LED:

• Keyboard scanning time-multiplexed with LED output(for Remote Control acknowledge & Error Signaling)

150 S11/7

180 S22/7

240 S33/7

330 S44/7

470 S55/7

820 S66/7

RL2

+3.3V

100k

RL11k2

S00/7

+3.3V

ADCIN

Config.

I/OOUT


P3.x/ADC

LED

Upper 0.75V of ADC range can not be used, due to +5V tolerant-constructionof I/O pads.

Reading back the ADC input costs just a few micro seconds. This is not noticeable in the light output of the LED.

The ADC input range VDD,MINIMAL- 0.75 Volt is lost, due to internal protections that make I/O pins 5V tolerant.

The ADC input has 8 bit resolution, so the resistor ladder network can be increased to handle more keys. In the application however, one should allow enough margin between the levels to handle noise from large currents flowing through ground tracks, cross talk etc.

GTV Function:rbsc_GetLocalKeyboardrbsc_SetLEDState


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Calculating Local Keyboard resistors:

• Upper 0.75V of ADC range can not be used :(due to +5V tolerant-construction of I/O pads)

0.75 * 100 / VDD,MIN = 75 / (3.3 * 90%) = 25,25%Highest usable level = 255 * 74.75% = 189D = BDH

• Divide this into the no. of keys you want,e.g. into 7 areas

• Position each switch in the middle of its area,S0 needs only ½ area (no tolerance below zero)

• Reserve ½ area noise margin above highest switch

• Choose e.g. R0 = 1.2kΩ (not too high, for noise immunity)

• Re-calculate levels with REAL resistors

• Re-calculate area-limits to be exactly in betweenchosen resistor divider levels ⇒ set in SW

S5

S4

S3

S2

S1

S0

S6

+3.3V

150

180

240

330

470

820

1K2

ADC25.2

5%

½

½

1

1

1

1

1

1

SW level

SW level R5

R4

R3

R2

R1

R6

R0VDDP

ES6.2D samples: upper dead-zone of1.3V plus lower dead zone of 200mV ??!!

In this example with 7 keys, standard range resistors can be used. The resistor tolerance should be less than 10%. We advice to use 5% types, allowing more noise margin in the application.

E.g. for switch S4 the resistor divider should give:

(R1+R2+R3+R4) / (R0+R1+R2+R3+R4) = KeyNumber / NumberOfKeys * AvailableRange = 4/7 * 74.75% = 0.43

Via a spreadsheet the resistor values and their ADC limiting values can be easily be calculated. So switch S4 is pressed when the software reads back an ADC value between 97D and 123D. The Hi-limit for S6 is ½ area above its center, leaving an extra noise margin under the Dead Zone ( = [74.75% * 255]-14 ).

GTV Function: LibCoMa Resource Basic Switches: RBSC_KEY1UPPERBORDER.. RBSC_KEY7UPPERBORDER

Absolute values Key Center

Sum R1..Rn Rn Practical

Sum R1..Rn Center Hi-limit =Dec =Hex

Dead zone [V] 0.75 0 0.0000 0.00 0.00 0 0 0.0000 0.0556 14 EVdd, nominal [V] 3.3 1 0.1068 143.46 143.46 150 150 0.1111 0.1634 42 29Minimal Vdd 90.00% 2 0.2136 325.87 182.41 180 330 0.2157 0.2689 69 44R0 [Ohm] 1200 3 0.3203 565.61 239.73 240 570 0.3220 0.3753 96 5FNumberOfKeys 7 4 0.4271 894.71 329.11 330 900 0.4286 0.4808 123 7A8 bit DAC 255 5 0.5339 1374.61 479.90 470 1370 0.5331 0.5895 150 96Relative values 6 0.6407 2139.76 765.15 820 2190 0.6460 0.6941 177 B0Dead zone [%] 25.25%AvailableRange 74.75%


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3-level outputs: drive more with less

• 3-levels by switching betweenOpen-Drain and Push-Pull

Open-Drain, float

Mid

Out

Config

3.3V

Push-Pull, high

Out

Config

3.3V

High

3.3V

Open-Drain, low

Low

Out

Config

3.3V

Hi

Mid

Lo

10k +3V

+8V

47k

47k

47k

1k1k

5

10k

47k

47k

3-level decoder + buffer:e.g. VST-3-band switch

Standby-VCR

10k+3V

47k

47k

10k

On/Off-TV

UOC III

I/O

Lo =OffMid=VCR stbyHi =On

• Example: 2 standby modi fora TV+VCR combi

Software can change the I/O pin configuration at any moment.

GTV Function:3 level output: rbsc_SetMLPortSwitching from output to input an setting a value: rbsc_ConfigPort,

rbsc_SetPin


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Power:

In/OutIn/Out

MicroMicro StereoStereoSync & Sync & GeometryGeometry

VIF & SIFVIF & SIF

MonoMono

RGBRGBColourColour YUVYUV

PowerPower


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Power supply inputs:

• Video-Signal-Processor (VSP) needs +3.3VSTBY and +5V• Scart audio output level of 2VRMS needs +8V, else 1.2VRMS at +5V• Digital part needs +1.8V ⇒ can be generated by IC (+external transistors)

• During SLEEP modes, +1.8V is generated inside the IC

• Set I2C-bus bit STB=0 to stop HOUT deflection drive by the VSPIf +5V is maintained, the VSP remains fully functional (for TV-VCR combi’s)

• Set µC SFR bit ROMBK.STDBY=1 to disable: VSP, OSD, RDS, TXT/CC-acquisition and Stereo sound Decoder (SSD)

• Set SFR bit PCON.IDL=1 to halt SW execution of the 80C51-µC, whilePWM, RCP, UART, I2C, INT, Timers/Counters, WatchDog stay active

Several Sleep modes:

When H+V deflection is not needed (e.g. VCR-mode or LCD-TV), all other functions in the VSP can be kept active, simply by maintaining +5V. If any of the +5V supply inputs fail (or too low), each has a supply-guard detector that will immediately stop the related functions in the VSP.

In µC-STDBY mode the 8051 core remains fully functional, but the VSP is putto sleep. Before going into µC-IDLE mode, the software should enter µC-STDBY mode first. This takes care that after wake-up from IDLE mode, many circuits stay off.

Another power mode called µC-POWERDOWN can be used instead of IDLE, but waking-up is then more difficult. In POWERDOWN mode only an external INTerrupt (or via the static SADAC) can wake-up towards STDBY mode.

GTV Function:fpmt_SetPowerStatepsys_SetTVProcessorStandby


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Power Modes:

• Startup Standby ⇒ Application mode can be done from 3.3V-only

• Mode Stop = Clock off ⇒ slower wake-up ⇒ check compatibility with Remote Control protocol (may miss first command, mode STOP needs repeating

full command codes like with RC-5)

Mode +5

V

need

ed

+8V

(+

5V)

+3.3

V

Sta

nd

by

Dec

Dig

2.

5VO

UT

+1.8

V

(ext

ern)

HOUT TV part

Micro part

Remark

Application mode

190mA 2mA 100mA 280mA STB=1 on

on On = All functionality available

VCR 190mA 2mA 100mA 280mA STB=0 tuner VCR mode = Front-end still active Deflection off

transition no - ??mA on

- STB=0 off

on

µC fully functional (set OSD=off) Standby 40mA limited µC-STDBY mode (Remote wake-up)

Idle 10mA IDLE µC-IDLE mode (using RCP)

Stop Sle

ep

no - ??mA

off

- STB=x

off

off coma Clock

stop µC-POWERDOWN mode Re-activate via INTerrupt or reset

In Standby & Idle the external 1.8V for the u-processor is switched off. Only a part of the digital core is kept alive, to detect wake-up events, by an internal 1.8V, derived from the 3.3V standby supply.

It is even allowed to generate the 1.8V in the line output stage, when switching to Standby & Idle, this 1.8V supply will automatically be 0. To get the lower power consumption, the digital Micro-core still has to be switched to IDLE mode (bit PCON.IDL).

In the transition to Standby mode, the micro must first disable the OSD.

Prior to entering IDLE or POWERDOWN always invoke µC-STDBY mode first (bit ROMBK.STDBY), to avoids high current peaks at wake-up.

During Idle mode the RCP (Remote Control pre-Processor) should be used to reduce false wake-up & obtain optimal power saving.

In mode Stop the internal clocks are halted. Re-starting takes more time. Therefor this mode is not suitable when a RC-protocol is used that doesn’t repeat the whole command code at every key-repetition (e.g. NEC: sends key-code only once, followed by fixed repeat-codes). If you missed the first command, you can not detect what it was


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Control of Standby Modes:

Application Mode Transition µC-Standby

µC-Idle mode

µC-PowerDown

SW set I2C-bit STB=0

SW set bit STB=1

SW set SFRROMBK.STDBY=1

SW set SFRROMBK.STDBY=0

SW set SFR PCON.IDL=1

SW set SFR PCON.PD=1HOUT = active+5V = needed

1.8V loop active

Soft-Mute audio,Disable amplifier

Any interrupt :Timer/RCP/Ext/UART/

I2C/WatchDog/…

Only External interrupt

SW set OSD off,SFR SADB.SSD_ON=0

HOUT = off+5V = not required

1.8V loop active

VSP disabled 1.8V loop off

OSD/TXT/CC off

HW resetsIDL/PD

Moving from “Application-Mode” to “µC-IDLE-mode” always goes via a short “Transition-state” and then to “µC-STANDBY-mode”.

Software must set µC-STANDBY prior to entering IDLE-mode, because every interrupt from e.g. Remote control (RCP) or timer (e.g. wake-up-timer) will bring the µC back to STANDBY-mode (and the VSP stays asleep).

For minimal TV-sleep-mode power we advice to use the RCP. This will reduce the number of false wake-ups significantly. As estimated average TV-sleep-mode power you can use: 90% µC-IDLE-current + 10% µC-STANDBY-current.

GTV Function: fpmt_SetPowerState


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??Temporary reset solution for ≤ ES7.2D samples: “System Consistency Check”.

See next slide.

V1V8Se

2.5V

+2.5V for VSP

1.8Vfeedback

DecDig (2.5V)

Detector<1.2V

+3.3VddA1 for I2C & Hdrive80C51 core& FlashProm

Reset

14

+5V+Vp1 for Geo

+Vp2 for IF&sw+Vp3 for RGB

+Vdd for Comb

45 +8V+Vp for ScartAudioOut

4k7

16478269

88

+3.3VddA1

IrefO

DDLE

5,7,9,90,91Vref’s

INT,Timers,RC-Preproc

1.8V25mA

+1.8V

= 3.3V logic= 1.8V logic

I/OPWMADCINT

SDASCL

Sle

ep m

ode

cont

rolle

r

QFP128, MCM

Which Vdd goes where:

• All µC-I/O lines use 3.3VddP (1.8V is used only internal, most I/O pins are 5V compatible)

• ALL 3.3V supply inputs must be connected to the same net (all 5V inputs also to one net)

• Self-controlled 1.8V loop, no external stabilisers needed, two nets (Domain1= 118 with 100+117+124+3, domain2= 96+93, pin 3 allowed to domain2. Pin 118 can supply domain1 only during standby)

Source=3mAMAXSink = 1mAMAX

I/O B

uffe

rs

47k

VddAnalogue

+1.8VddCore

Video ADCsAudio SDACs Audio ADCs

100, 117, 124

4

96

94

Audio SDACs (dig.) 3

93

max

(µC-Stdby,Idle,PowerDown)

RR

VddPeriphery µC

110

1.8VEXT ≥ 80%

+1.8V2

+3.3VSTANDBY

47k

+3.3VSTANDBY

140mA

140mA

DecV1V8 118

10µF 1k

114

+1.8V1

+3.3VSTANDBY is used for I2C, H-drive and to generate 2.5V DecDig. With simple transistors the 1.8V supply for the digital part can be made. Via pin 96 this is monitored (DDLE=1) to adjust the 2.5V DecDig, keeping the 1.8V within limits. When the DecDig voltage is OK, setting bit STB=1 can start the horizontal deflection (=LowVoltageStartUp: only 3.3V input required).

Note: the external 1.8V should not be available before 3.3VSTANDBY.

DDLE=0 makes 2.5V DecDig independent of the 1.8V feedback signal. Use this if you want to apply an external 1.8V instead of the self controlled loop.

When the digital core is switched to a SLEEP mode (µC-STDBY, IDLE or POWERDOWN), the 2.5V DecDig switches off. As the external generated 1.8V drops below 80%, an internal 1.8V supply (pin 118, derived from 3.3VSTANDBY) takes over and many circuits are disconnected. Pins 93+96 must de switched-off; all other 1.8V inputs are allowed to stay on: temporarily powered via pin 118 (1.8V supply transistors should NOT pull current OUT of pin 118).

The 1.8V for the 80C51 core is monitored by a reset circuit. When this decoupled voltage is less than 1.2V, a reset is generated.

Whenever pin DecDig drops < 2.0V, a POR is generated for the VSP and all I2C-bus registers must be re-written (including DDLE). Below 2.0V bit DDLE is ignored, to guarantee start-up of DecDig. At first-power-up the 2.5V DecDig always goes high, to assure proper start-up of the IC.


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Solving power failures ≤ ES7.2D samples:

• SW must perform regular “System-Consistency-Check”, to detect failure in power of clocking (use GTV routine that verifies R/W consistency of MMR’s)

• First try “soft-reset” else FULL-RESET:= switch-off DecDig (µC standby mode) and then pull 118 low

• 3V3STANDBY should be first of all power supplies

• With proposed "System Consistency Check" there is no specific order for start-up of power supplies. Still we advice to reserve a pin (114, push-pull-configured) plus 1 transistor for the "full reset"

??Necessary reset solution for samples

≤ ES7.2D

??The current ES5.2 samples of UOC-III (with Picasso-10) sometimes show a failure at start-up, dependent on how the various power-supplies are rising. Should you experience such problems, we can offer you a combined HW/SW solution to overcome this. In future samples this will be repaired. For the time being, we advice to use one I/O pin to be able to force a “full reset” by short-circuiting pin 118 to ground (150mA). Use e.g. pin 114 that is LOW during reset (= all I/O-pins except HW+SW-I2C pins). Keep 114 low unless you want to trigger the reset. As a result, pin 114 will again be made low by the reset.


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A

B

D

C

Short-circuits:

Protection strategy external transistors:

• DecDig can source max. 3mA or sink max. 1mATotal load on 1.8V is about 300mA (including sound DSP)

• Don NOT pull current out of 1.8V supply inputs• VDD1.8 > 2.1V shortens lifetime drastically. A built-in detector (bit SUPR=1)

signals this unwanted situation (e.g. show error message on OSD)

VDD 1.8V

DecDig 2.5V

E

+3.3

RP

RO

T

47k

4k7

2.1V

Short- cirtcuit

No protection Problem?

A No 1.8V No B VDD=3.3V

Yes

C VDD=3.3V

Yes

D T2 destroyed

Yes

E DecDig=0V No

T2T1

With protection Problem?

No 1.8V No VDD pulled up,

protected by zener No

VDD=2.1V, protected by zener

No

No 1.8V, T2 protected by RPROT

No

DecDig=0V No

The UOC- III “Hercules” avoids the need of (expensive) 1.8V stabilisers. Instead, it offers a 2.5V (3mA) output (pin DecDig) for an emitter-follower (PNP-boosted NPN), with analogue feedback via 1.8V input pin 96.

Note: It is not allowed to pull current out of the 1.8V inputs. Use emitter- or diode-type to supply these pins (or supply 1.8V out of 3.3VSTANDBY).

It is important to avoid dangerous situation by accidentally short circuiting of components or shorts in components due to end of lifetime. On this aspect “Hercules” has similar robustness as the TDA95xx UOC family.

GTV Function: psys_GetSupplyProtection


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BITS FUNCTION SETTING I / O MACRO FU REM EVG Enable Vertical Guard 1: enable protection I Pow/Prot SC Mute RGBOUT NDF No vertical DeFlection guard pulse 1: failure O Pow/Prot UC DFL Direct restart after Flash protection 0: soft restart

1: direct restart I Pow/Prot SC PHI2 pin

XDT X-ray DeTection 0: protection I Pow/Prot SC XPR X-ray PRotection 1: overvoltage O Pow/Prot SC EHTO pin

Power & protection related bits (1):

• Flash protection: (anti-glitch : condition must be active > 1µs)

– pulling pin p17 “PHI2” > 4.1V forces an immediate-stop– when pin is back to normal level:

• DFL=0: restart HOUT via softstart (= best safety for H deflection circuit)

• DFL=1: restart HOUT direct (= shortest HOUT disruption)

• X-ray protection: (anti-glitch : condition must be active > 1µs)

– pulling pin 32 “EHTO” > 3.9V sets XPR=1 & forces slow-stop of HOUT

– XDT=1 disables auto-switch-off, but error condition (XPR=1) can still be read

• Vertical Guard: when EVG=1, condition NDF=1 mutes RGBOUT

Status bit XPR is latched and cleared after an I2C-bus read action, unless the fault condition still exists. XPR is triggered when the EHT-compensation pin 32 is forced outside its normal operating range (1.2 .. 2.8V), above 3.9V. XPR=1 will cause a slow-stop of the horizontal line drive (HOUT, pin 67) plus discharge of the picture tube (OSO=1). This protection can be disabled by setting XDT=1.

Hint: Pin 32 can be used for switch-off via the mains switch, using an external detection circuit to monitor when the supply voltage drops.

Pulling phi-2 pin 17 above 4.1V will immediately stop HOUT. If pin 17 is left floating again, the line drive will automatically restart (Unless software reacts to protection bits like SUP before HOUT is restarted) : - with DFL=0 it will do a gentle soft-restart.- with DFL=1 it will immediately continue with normal HOUT periods. This gives

fastest recovery, but make sure that your line-deflection stage can handle it.

To prevent built-in protections from reacting on glitches, pins 17 or pin 32 mustbe kept above trigger voltage longer than 1 µs before the protection will act.

Status bit NDF is NOT latched. It is cleared after the fault condition is removed. In some chassis during source- or channel-change the vertical guard pulse is missing for some frames. Therefore we advice to check NDF=1 during at least > 200ms, before reacting to it in software (e.g. switch to standby).


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• Software must read POR until POR=0 (POR and XPR are cleared after reading)

• When POR=1 or XPR=1 : software MUST reset STB=0, BEFORE switching on again (STB=1)

• New: If Flash-prot did shut-down HOUT, SW can detect this via DFL4..0

• HOUT slow-start process takes at least 1175ms (DFL4..0)

BITS FUNCTION SETTING I / O MACRO FU REM POR Power On Reset 1: failure detected O Pow/Prot SC STB STandBy 0: standby of TV proc.

1: operational I Pow/Prot UC

DEFL DEFLection timer enable 1: read-out enabled I Pow/Prot SC DFL4..0 DeFLection timer read-out 5-bits status O Pow/Prot SC Slow start/stop


Status bit POR is cleared after an I2C-bus read action, unless the reset condition still exists.

POR is only related to the 3.3V part of the VSP and the reset input. It has nothing to do with the 5V part. When POR=1, all I2C register data needs to be rewritten: after POR=0 again.

Bits DFL4..0 represent the status of slow-start (-stop). With DEFL=1 the software can read this to monitor the line-start-up (-shut-down) process.

GTV Function:POR: psys_GetTVProcessorPORSTB: psys_SetTVProcessorStandbyDEFL: psys_SetReadOutDeflectionTimerControlDFL: psys_SetFlashProtectionEVG: psys_SetVerticalGuardModeNDF: psys_GetVerticalOutputDFL: psys_SetFlashProtectionXDT: psys_SetOvervoltageInputModeXPR: psys_GetXrayProtection


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BITS FUNCTION SETTING I / O MACRO FU REM SUP 5/8 Volt SUPply present 1 : OK O Pow/Prot SC SUPR 1.8 Volt SUPply Risen > 2.1V 1 : 1.8V too high O Pow/Prot SC Dangerously high


• Conditions that trigger SUP=0 will also slow-stop HOUT:– when VP1,2,3 or VDDCOMB drop below 4.0V – BGDEC drops below 2.1V

• ⇒ DSU : HOUT automatically restartswhen SUP=1 again

• ⇒ MSU / LSU : SW has to toggle STB:=1→0→1, before HOUT restarts+ execute “TV-Switch-On” (can not restart automatic because 5V derived from line deflection)

• An “1.8V” supply higher than 2.1V drastically shortens life-timeSoftware should check SUPR=1 and show there is a problem

NOTE: only works with proper designed application where nobody pulls the phi-2 pin too high during start-up, otherwise: switch on

via “TV-Switch-On”

Important : when the 5V falls below a certain level (4V), other protection bits can accidentally get triggered. If e.g. XPR=1, the HOUT will NOT automatically restart. Therefore all UOC- III “HERCULES” software should continuously check POR, XPR (or disable the protection functions).

Short spikes on the 5V supply can be handled by the HERCULES itself. If software reads SUP=0 for more than 40ms, we advice to switch to standby (STB=0).

GTV Platform:SUP: psys_GetTVProcessorPowerSupplySUPR: psys_GetSupplyProtection


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DFL Flash-protection: during start-up force to ‘1’, after start-up make choise

XDT

Xray Detection/Protection - if Protection: set switched to STB and XPR output bit is set to ‘1’, after reading and recovering, XPR output bit to ‘0’ To start-up toggle STB ->0->1 - if Detection: XPR output bit is set to ‘1’, after reading and recovering, XPR output bit to ‘0’

FBC Fixed beam current during switch-off RBL Force RGB Blanking Blanking level under control of CCC-loop RGBL Force RGB Blanking during start-up Fixed blanking level DDLE DecDig loop selection red disable REFOK defl enable readout deflection timer ssd soft start-up enable/disabled Useful for e.g. LCD-TV hsnf speed of I2C-bus

OUTPUT BITS important for PMT Bit name Bit function Remark POR Power on Reset XPR Xray prot NDF No vert. defl SUP Supplies OK SUPR 1.8V to high prot setoff read back when soft stop has finished dfl0..dfl4 read back of deflection timer

Important bits for PMT:

GTV Function:STB: psys_SetTVProcessorStandbySDC: psys_SetDutyCycleHorizontalDriveOSO: psys_SetVerticalScanAtSwitchOffVGM: psys_SetFunctionVguardSwioPinDFL: psys_SetFlashProtectionXDT: psys_SetOvervoltageInputModeFBC: psys_SetFixedBeamCurrentSwitchOffRBL: pimg_SetRGBBlankingRGBL: pimg_SetRGBOutputBlankingDDLE:RED: psys_SetREFOKBitDEFL: psys_SetReadOutDeflectionTimerControlSSD: psys_SetSlowStartUpModePOR: psys_GetTVProcessorPORXPR: psys_GetXrayProtectionNDF: psys_GetVerticalOutputSUP: psys_GetTVProcessorPowerSupplySUPR: psys_GetSupplyProtectionDFL: psys_SetFlashProtection


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On / Off flow:

“TV-Switch-On”

Main Loop: “Regular Check OSD, SSD”

“Power-On”?? Consistency Check +5V & 1.8VEXT available @ reset

Check for start-up problems

Serious problem?

< 3

Go into TV-standby or switch-on ?

TV- factory production Align DCXO, if more accuracy desired

Choose the method you like

Store cap-bank value in Eeprom

Method A Method B Method C

SW should recall this value every time

On or Off ? To TV-standby

Load optimal value from Eeprom

“TV-Sleep”

Retry max. 3x

Yes

No

“Safety-Shut-Down”

Off ?

On

Yes

No

“Load DCXO cap-bank”

?? Check SSD availability

AC-on



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Power Topologies:

• DSU= Direct Start-Up– Both +1.8VEXT & +5V are

coming Directly from main-SMPS

• LSU= Line-voltage Start-Up– Both +1.8VEXT & +5V are

coming from Line deflection LOT/FBT

• MSU= Mixed Start-Up– +1.8VEXT from main-SMPS– +5V from Line deflection LOT/FBT

UOC-III“Hercules” FBT

/LOTHOUT

MainssupplySMPS

3.3VSTB

5V, 1.8VEXT


/LOTHOUT

MainssupplySMPS

3.3VSTB

5V, 1.8VEXT


/LOTHOUT

MainssupplySMPS

3.3VSTB

5V1.8VEXT

?? 1.8V from Line not possible yet, use DSU instead

?? ES7.2D: 5V must be present during reset, use DSU instead


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Example: AC-on for DSU

• If 3.3VSTB has risen > 2.7V, the VSP-digital part is in control & forces HOUT=high• 2.5VDECDIG & 1.8VPERMANENT will come-up too (µC internal reset sequence begins > 1.2V) until

software starts running, then SW enables 5V & 1.8VSWITCHED

3.3VSTBMom

ent o

f AC

-on

2.5VDECDIG

1.8VPERMANENT Pin 118,117,100,124

1.8VSWITCHED Pin 3,93,96

5VSWITCHED

A: HOUT is forced high

B: POR level DecDig

C:

E:

D: detector levelµC reset startsDCXO forced

SUP=OK level4.0V

5.0V

2.7V

2.0V

1.4V1.2V

0V


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• Hout forced high (protection when 3V3<2.7V or DecDig<2.0V)

• DecDig rises > 2.0V = trip level for POR & STB(VSP-logic starts default: STB=0, sound muted)

– Picasso wait until 1V8INT rises above1.2V (pin 118), DCXO forced to 7FH

• N1B/C: µC-POR held until 1V8EXT > 1.4V (1V8EXT keeps 8051 reset, will change)

• µC begins internal reset (takes several ms, most I/O pins set LOW)

• SW Init I2C, “Load DCXO-cap-bank” (get optimal value from Eeprom or from FLASH)

• SW initialise WatchDog, RCP, I/O pins ….• IF TV-set has to stay asleep (e.g. read on/off status back from Eeprom)

THEN SW switch “TV-Sleep”ELSE- SW refresh configuration control of µC & SSD and SW Reset-OSD- SW make sure µC is NOT in SLEEP-mode (µC-STBY/IDLE/POWERDOWN)

- SW read VSP status until VSP-POR=0

• Now the SW can begin with “TV-Switch-On”

DSU / MSU: Power-On



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• Precondition: µC NOT in any sleep mode (µC-STANDBY/IDLE/POWERDOWN)

– SW check POR=0, “Reset-OSD”, Init SSD (keep sound muted)

– SW write all I2C registers, always keep STB=0 (RGBL=RBL=DFL=1, OPC=AKB=0)

• Optional: choose OSO,FBC,SDC,VGM, (reduce VSP version control register FFH)

• Optional: to use 1V8 loop: set DDLI=1 (else DigDec fixed at 2.5V)

– DSU: SW check VSP-SUP=OK (8/5V>4V, clock=OK, 3V3>2.7V, DecDig>2V, BGDec>2V)

MSU: No check on SUP (5V comes from line deflection LOT/FBT)

– Optional: SW (re-)enable desired protections XDT,EVG– SW activate supply for FBT/LOT line deflection stage (can also be done with DecDig)

– SW activate HOUT: STB=1– IF startup fails (too long > 5s) (SW check DFL4..0 )

THEN do a “Safety-Shut-Down” (and blink error LED)

ELSE (no need to check SUP ⇒ is already part of DFL4..0 during slow-start)

– IF VGUARD used (EVG=1 to enable VGUARD-protection)

THEN check that vertical reads back NDF=0 within 1000ms– Optional: SW (re-)enable desired protection DFL– Start up the CCC loop (black current + RGB gain stabilisation)

DSU/MSU: TV-Switch-On

During the slow-start-process we advice to set DFL=1. In applications with Flash-detection circuitry or Dynamic Phase-compensation connected to the Phi2-pin, the extra wires can sometimes lift the DC level on the pin too high (With DFL=0 this would cause a slow-restart, perhaps even multiple restarts). After Slow-Start is completed, SW can set DFL according set-makers choice.

The slow-start-process begins with setting STB=1. If DEFL=1 the SW can now monitor the start-up of HOUT. Normally this takes 1175ms unless any protection mechanism is activated. Should the start-up take much too long (>5s), then software can best do a safety shut-down (e.g. retry 3 times and then stay off). Set STB=0, switch-off and show the error (e.g. on an LED).

If a vertical guard pulse is connected, bit NDF (No DeFlection) can be checked to verify correct operation of the vertical deflection stage. Use this option always together with EVG=1 (Enable Vertical Guard), to mute the display and prevent damage to the picture tube. If software keeps on reading NDF=1 for more than 1000ms after SUP=1, apparently the vertical deflection is damaged. Set STB=0, switch-off and show the error (LED).

Bit NDF=1 can be caused by more conditions:- Vertical guard pulse: not present / low enough / high enough / wrong timing- Vertical ramp capacitor (150nF) short-circuited


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Regular Check (1):• Advised error handling: (read all VSP status bits in ONE action)

IF POR=1 (3V3, DecDig)

or SUPR=1 during > 5s (1.8V too high)

or NDF=1 during > 200ms (no vertical)

or SUP=0 during > 40ms (no +5/8V)

THEN “Safety-Shut-Down” :Set STB=0 (HOUT off via slow-stop, when possible)

Wait 1.2sset SFR ROMBK.STDBY=1 (µC=standby + VSP=sleep, DecDig=low)

Wait > 1s and try to restart (POR=0) (discharge, retry 3 times)

If the error persists,then switch off & remain in standby (blink error LED, signal WHY)

ELSEIF XPR=1 (Xray prot via EHT pin)

or DFL4..0 < 0FH (flash prot triggered)

THEN TV-Switch-On (fast)

Regular check:When the TV in running, the timing for error conditions is different from the “cold” start-up timing.

Some status bits are latched (POR, XPR) others are not. All status bits should be read within one I2C-bus message. This avoids that one routine clears a latched bit, that should have been read by another routine.

Safety Shut Down:After switching to standby we advice to insert some delay time, to discharge power supply capacitors. If e.g. during a flash-over or spark-test some circuit has gone into latch-up, the problem is often removed by powering it down.

The advised procedure gives a balanced trade-off between safety and ruggedness against mains interruptions (AC on/off/on/off…).

GTV Function:LibCoMa settings for the time-out of violationspsys_GetProtectionViolation


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Regular Check (2):• Error flags in TCG-µC are handled on interrupt basis (EDET)

– IC-temperature > 130º ⇒ Reduce power (blink error LED & switch off non-vital

functions, e.g. disable SSD??)– IC-temperature > 140º ⇒ Immediate switch off– 1.8VEXT or 3.3V too low ⇒ Do a “Reset-OSD”

N1B/C?? : clear 1V8 + 3V3 flags

• SW Reset-OSD consists of: – Mute sound, switch SSD=off– Switch-off DINT=0 – SW toggle bit SFR ROMBK.D6:= 0→1 (⇒ resets OSD & all except 8051 core)

– If problem persists ⇒ “Safety-Shut-Down”

Reset OSD:

Temperature flags in EDET:

When the IC gets very hot (>130º Celsius), the µC can receive an interrupt signal that allows the software to switch-off non-vital functions.

If this is not enough too cool down the IC and the temperature rises above 140ºCelsius, then SW should switch-off the TV immediately.

Reset OSD: does NOT reset the 8051 µC core

At each switch-on of 1.8VEXT and +5V, software can now reset its OSD part by writing SFR register ROMBK.D6 from “0” to “1” (other transitions have no effect). We advice to combine this reset with switching off the SSD and the digital video interface.

GTV Function:Interrupt definition in fpmt_dcn.c file


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DSU/MSU: TV-Sleep• Soft-mute audio• SW remove OSD (dynamic animation: close the curtains)

• SW set STB=0 (triggers HOUT slow stop)

• SW read DFL4..0 & wait until < 02H?? (Hdeflection ready with slow stop process)

• Disable supply for FBT/LOT• Temp. for N1C??: disable EDET• SW set µC SFR ROMBK.STANDBY=1 (DecDig falls low)

• SW disable WatchDog, set Keyboard_wake_up….• SW set µC-IDLE mode (Timers & RCP remain active)

– Micro will stand-still until an interrupt wakes the 8051– Upon RCP interrupt: temporary in STANDBY, then return to IDLE mode

• Upon wake-up: – re-enable WatchDog, Keyboard, SFR ROMBK.STANDBY=0– Temp. for N1C??: re-enable EDET & discard one false EDET-interrupt– TV-Switch-On



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DCXO timing & tuning (1):

• Trimming of integrated Xtal-clock-capacitors enhances total accuracy

• IC-production stores a nominal cap-bank center-value in FLASH= FLASH-value (using typical components, to annihilate IC production tolerances)

• Registers involved to control the cap-bank:

– µC-SFR register:• P3DCXOCTRL.D6..D0 (POR value = factory-FLASH-value )• P3DCXOCTRL.CAPMUX (1= from SSDNICAM , 0= from SFR)

– SSDNICAM register: (non-SSD versions: set CAPMUX=0)• DCXO_CTRL_REG.NICPLCENTER (POR value = 3FH,7bit = 3F8H,10bit)• DCXO_CTRL_REG.NICPLPLIM (Frequency-range limiting)• DCXO_CTRL_REG.NICPLSCALE (Phase adaption speed)

GTV Function:psys_SetCrystalAlignmentpsys_GetCrystalOptimumViaNicampsys_GetCrystalOptimumViaColour


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• Other µC Registers, used for tuning:

– µC-SFR register:• I2S.I2S_CLK1..CLK0 (I2S bit clock, 00 = 256 x FS)• I2S.EN_I2SCLK (1 = I2S bit clock out, 0 = GPIO)

• Remarks:• 256 x FS = 8.192 MHz = DCXO output frequency / 3• I2S output clock can be made visible on GPIO pin 103 (P0.3/I2SCLK)

• I2S output is only available in full stereo or AV stereo version


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• Other SSD Registers, used for NICAM tuning:

– SSDDEMDEC register:• DDEP_CONTROL_REG.DPMODE (DEMDEC easy programming mode)• DDEP_CONTROL_REG.STDSEL (Standard selection)• DDEP_CONTROL_REG.REST (Reset DEMDEC)

– SSDINFO register:• INF_NIC_STA_REG.VSP (Identification of NICAM sound)• INF_NIC_STA_REG.CO_LOCKED (NICAM frame and CO sync.)

– SSDDEV register:• INF_DEV_STA_REG.VDSP_C (NICAM decoder VDSP flag)


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• Other VSP Registers involved:

– COSMICSYNC1 register (0x3E) :• SYNCHRONISATION1.red (bit 6, REFOK bit disabled)

• During DCXO tuning, the internal 24.576Mhz reference VCO of the VSP could loose its lock to the DCXO. No-lock sets bit SUPOK=0 and HOUT will switch-off. This is prevented by setting bit red=1 during DCXO tuning


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Optimal value for DCXO cap-bank:

• A set-maker can find his own Application-OPTIMUM via 3 methods :(No alignment –only transfer of FLASH VALUE-- gives same accuracy as UOC-II)

1. Per IC you can read back it’s FLASH-value via P3DCXOCTRL.D6..D0, directlyafter µC-POR

2. For a specific IC+application, find it’s best ABSOLUTE-value:-A- NICAM test signal ⇒ read back from NICPLCENTER (CAPMUX=1)-B- SW controls cap-bank ⇒ measure frequency e.g. via I2S clock output-C- Colour test signal, determine middle of colour locking range

⇒ read back from P3DCXOCTRL.D6..D0 (CAPMUX=0)3. OFFSET-value = ABSOLUTE-value – FLASH-value

Store the OFFSET-value in Eeprom (Nvmemory) 4. Combine this OFFSET-value per IC with it’s own FLASH-value

• Remark: when each individual TV is aligned, you can also store theABSOLUTE-value of it’s IC in Eeprom


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-A- Find optimum: using NICAM (1)

• Apply NICAM signal (e.g. B/G NICAM) with good reception quality– Use a NICAM generator with ≤ 1 ppm frequency tolerance (=NICAM spec.)

• Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6)

• Load SSD with FLASH-value (read-out via SFR, directly after POR)

– Set DCXO_CTRL_REG.NICPLPLIM to 0x1FF (511=max)

– Set DCXO_CTRL_REG.NICPLSCALE to 0x0 (0=max range, scale 1.0)

– Set DCXO_CTRL_REG.NICPLCENTER to 0x0

• Set-up the DEMDEC in the SSD (via DDEP_CONTROL_REG)

– Set EPMODE (bits 1..0) to 0x01: Static Standard Selection mode– Set STDSEL (bits 6..2) to 0x05: B/G NICAM

• Re-start the DEMDEC to acquire NICAM (via DDEP_CONTROL_REG)– Set REST (bit 7) in DDEP_CONTROL_REG to ‘1’


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-A- Find optimum: using NICAM (2)

• Wait until NICAM is detected, using status bits:– INF_NIC_STA_REG. VDSP or CO_LOCKED or

INF_DEV_STA_REG. VDSP_C and the error-counter ERR_OUT has gone down to 0X0

• Wait 100..500ms extra to make sure PLL is fully settled• Read 7-bit ABSOLUTE-value from INF_NIC_ADD_REG.DCXOCAPS,

(unsigned 7-bit integer, stable when only one LSb toggling)

• Save in Eeprom• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)


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-B- Find optimum: using I2S

Measure absolute frequency via I2S clock output:• Enable pin 103 (P0.3/I2SCLK) as I2S bit clock output @ 256 x FS (=8.192MHz)

– Set I2S.I2S_CLK to “00”– Set I2S.EN_I2SCLK to ‘1’

• Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6)

• Start with FLASH-value (read-out via SFR, directly after POR)• Use SW to modify this in P3DCXOCTRL.D6..D0 until I2S clock reads-out correct

MHz• Store this 7-bit ABSOLUTE-value in Eeprom• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)


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-C- Find optimum: using colour-lock

Find the middle of the colour-locking range:• Start with FLASH-value• Select a very good CVBS signal e.g. with PAL colour• Set COSMICSYNC1 bit red=1 (reg 0x3E.bit 6)

• SW modify DCXO tuning until colour is found• Make sure Cosmic is locked to that colour• SW decrease DCXO tuning until colour is just lost ⇒ LOWLIMIT

• SW increase DCXO tuning until colour is just lost ⇒ HIGHLIMIT

• Optimal 7-bit value: (HIGHLIMIT + LOWLIMIT)/2 = ABSOLUTE-value• Save this in Eeprom• Set COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)


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Load DCXO cap-bank:

• N1B/C: During µC-POR & SLEEP modes, DCXO is HW-initialised to 7FH

• SW initialise cap-bank settings:Non-SSD versions: set CAPMUX=0 & don’t write DCXO_CTRL_REGSet COSMICSYNC1 bit red=1 (reg 0x3E.bit 6)

IF stored in EepromTHEN fetch & copy into SSDNICAM DCXO_CTRL_REG & in P3DCXOCTRL.D6..D0 ELSE SW fetch 7-bit FLASH-value from P3DCXOCTRL.D6..D0,

convert into 10-bit data & write to DCXO_CTRL_REG. NICPLCENTERSet COSMICSYNC1 bit red=0 (reg 0x3E.bit 6)

• N1B: Note: non-SSD version is not possible for N1B !!!

• N1C: cap-bank is controlled by SFR P3DCXOCTRL.CAPMUX, from – CAPMUX=1 : SSDNICAM DCXO_CTRL_REG register (during NICAM)

– CAPMUX=0 : SFR P3DCXOCTRL.D6..D0 (in non-SSD version mono/AVstereo)


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3.32.50

POR

I2C

STB

Hout

POR is reset to 0, at the first I2C status register-read after 3.3 Volt supply > 2.50 Volt

When POR=1, read till POR=0, write all I2C registers with STB=0. Then set STB=1

3

Sl.Start

1

Sl.Start

2

Sl.Start

4

Protection: +3.3V supply

1 When POR = 1, software must read till POR = 0. Then all I2Cregisters must be written with STB = 0Pending on the power supply:5 V from main supply: check SUP = 15 V from FBT: Low Voltage Start-up, no extra check neededThen write STB = 1

2 When the power drops shortly (spike )below 2.50 V, POR is set to 1and latched. H-out is immediately switched off.When the software detects POR = 1, the start-up procedure as in 1must be repeated

3 When the power drops below 2.50 for a longer time, Hout isimmediately stopped and the device is put in reset condition

4 Once the voltage rises above 2.50 V again, the start-up procedure asin 1 must be followed

The presence of the 3.3 Volt is basic for reliable working of the µprocessor part and the digital part (I2C registers and Hout drive circuit). Checking the 3.3 V regularly by reading POR and taking appropriate action when POR = 1 has absolute priority over all other matters. The µprocessor will not work when 3.3V is too low (< ~1.9V).

GTV Function: LibCoMa settings for the time-out of violationspsys_GetProtectionViolation


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+3V3 stays intact

54.0

STB

RGB

Hout

SUP

Pin 17PHI-2

Pin 32EHTO

XPR

4.1V

3.9V

Sl.StartSl.Start

1

Sl.Stop

2

Sl.Start

3

Sl.Start

4

Sl.Stop

Disch.

6

Automatic Automatic

Sl.Stop

Disch.

5

Reset to 0, first I2C read after pin 32 < 3.9 V

Protection: +5V from main supply (=DSU)

We assume the 3.3 Volt is OK. Note that the 4.0 level of the + 5 V supply has in reality a hysteresis of about 0.2 Volt (4.1 V SUP → 1, 3.9 V SUP → 0)

1 Check SUP = 1. Write STB = 1. Then Hout will begin via Slow Start.

2 When 5 V supply drops below 3.9 V, Hout will be stopped according the Slow Stop procedure. The RGB outputs are immediately blanked.

3 When the supply rises again above 4.1 V, Hout will automaticallystart again via Slow Start

4 The Flash protection is activated when the voltage at pin 17 is kept ≥ 4.1Vlonger than 1 µs. Hout is immediately stopped to protect the line transistorand RGB outputs are blanked. When pin 17 drops again < 6 Volts, Hout isautomatically started via Slow Start.

5 The Overvoltage protection is activated when the voltage at pin 32 iskept above 3.9 V longer than 1 µs. XPR is set to 1, Hout is switchedoff according the Slow Stop procedure, RGB outputs discharge theEHT and the IC is set in Stand-by. When XPR = 1, software mustread till XPR = 0, then write STB = 0 followed by STB = 1

6 Writing STB = 0, Hout Slow-Stops and RGB outputs discharge the EHT.

GTV Function:STB: psys_SetTVProcessorStandbySUP: psys_GetTVProcessorPowerSupplyXPR: psys_GetXrayProtection


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Handling differs from previous slide !!

54.0

STB

RGB

Hout

SUP

Pin 17PHI-2

Pin 32EHTO

XPR

LSU

4.1V

3.9V

LSU

1

Slow St.

2

LSU

3

Slow St. LSU

Disch.

4

Slow St.

Disch.

5

Reset to 0, first I2C readafter pin 32 < 3.9 V

Protection: +5V from FBT (=LSU/MSU)

• With LSU/MSU, SW action is needed to recover from dip / flash / Xray-protection

1 When the 3.3 V is ok and all I2C registers are written, STB can beset to 1. Hout performs a Low voltage Start-up via Slow StartThe 5 Volt from FBT will rise. At 4.1 V (0.2 V hysteresis.) all othervideo processor blocks are released (including RGB outputs)

2 When the 5 V drops below 3.9 V (e.g. due to overload), H-out willstop according the Slow Stop procedure and the RGB outputs areimmediately blanked. Because the Hout is stopped, the 5 V will notreturn any more. The µprocessor can check this by monitoring theSUP bit. A new Low Voltage Start-up must be initiated by writingSTB = 0 followed by STB = 1.

3 Activating the Flash protection stops immediately Hout and blanksthe RGB outputs. Also now the 5 V doesn’t return because Hout isstopped. A new Low Voltage Start-up must be initiated by togglingSTB (see 2)

4 Activating Overvoltage protection stops Hout via Slow Stop, RGBoutputs discharge the EHT and the IC is set in Stand-by. The µprocessor must check XPR and SUP and when XPR = 0 initiatea new Low Voltage Start-up by toggling STB.

5 Setting STB = 0 switches off Hout via Slow Stop and the RGBoutputs discharge the EHT.


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H/V sync & geometry:

In/OutIn/Out

MicroMicro StereoStereo

VIF & SIFVIF & SIF

MonoMono




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• Alignment free H-oscillator, 2 control loops

• Low Voltage Start-up facility (LVS)

• Intelligent Vertical count-down circuit

• Vertical driver optimized for DC output stages

• H & V geometry including Parallelogram and Bowcorrection for large screen picture tubes

• H & V Zoom function for 16:9 + (digital) Panorama

• Slow Start / Stop procedure

H,V-sync & Geo Processing:

The low voltage start-up (LVS) makes it possible to initialise the horizontal drive using only 3.3 V. It is possible to supply the +5 Volt from scan rectification of the FBT/LOT.

Parallelogram and Bow correction are available for applications with real flat picture tubes.

When vertical is zoomed out more than 105%, the extra over-scan is blanked to prevent picture tube damage.


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3 –

UO

C-I

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pres

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2-10

0

64µsSwitch On

0 to 12% in 57ms

55% 45%

28,8µs28,8µs28,8µs28,8µs

timeSwitch Off

43ms

1mA picture tube discharge, during 38ms

HDRIVE

12 to 73% in 73ms 73 to 100% in 1045ms

TO

N%

0 1175ms24µs 24µs 24µs

With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0

35,2µs

8µs

Slow start / quick stop:

25%

During slow start, the off-time of HOUT is kept fixed at 28.8 µs. The on-time increases from 0 to 35.2 µs (for 55:45 duty cycle). In this way, overstress of the line transistor is prevented and the EHT builds up gradually. The three speed-variations even enable the use of very large picture tubes with a “DAF” gun.

During switch-off, the Hout frequency is doubled immediately and the duty cycle is set to 25% fixed, during 43 ms. The RGB outputs are driven high to get a controlled discharge of the picture tube with 1 mA during 38 ms. This will decrease the EHT to about half the nominal value (= safety requirement). For this feature, the RGB amplifier must be able to return a 1mA “Iblack” measurement current (like TDA6108A).

When bit OSO is set the white spot/flash during switch off will be written in overscan and thus will not be visible on the screen. Careful application must guarantee that the vertical deflection stays operational until the end of the discharge period.

With bit SDC the duty cycle can be changed from 55:45 to 60:40 when STB=0.

GTV Function:STB: psys_SetTVProcessorStandbyOSO: psys_SetVerticalScanAtSwitchOffSDC: psys_SetDutyCycleHorizontalDrive


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VerticalGeometry

Line Phase “soft” lockphi-2 loop

Line oscillatorphi-1 loop

PHI1VCO

FXTAL

Calibrator

Timing:1600Noise

detector

FOA/B

STM

Coincidencedetector

SL

Hsyncseparator

FORF/S, DL,NCIN,OSVE

PHI2

SandCastleGenerator

HSH, HP,HB,SDC

67 Horizontaldrive

66

Slow Start& Stop

VerticalSawtooth

VOSD

HP2

FlashProt.

1718

FlybackIN /SandCastleOUT

Flash detection

HBL,WBF/R

Blanking

VerticalGeometry

East-WestGeometry

26 27

32 EHT/XrayProt

XPR

>3.9V

Vsyncseparator

22 Vertical drive

EW,PW,L/UCP,TC 21 EW drive

(AVL)

SSL

50%30%

FSL

Auto70/3570%

SN2..0

VID

SID

>4V

HOSD

YOUT

HCO

23

YSYNC

74

73

POC

DC

cla

mp

IVW/F,FSI

DFL

Safety

XDTXPR

Clk

3V3

5V Dig

BG

STB,SDC

VA,VSH,SC,VLIN,VX,VSC,SBL,VSD

Sync and Geometry:

SD2..0,CMSS

Sw

itch

VerticalDivider

SelectedVideo

SYM

HTXT

Datasyncsep.

CSO

Videosources

To TXT/CCdecoding

New: Better sync performance, due to clamp right before sync part.The horizontal oscillator (PHI-1) uses the X-tal reference frequency to calibrate it's free running frequency (roughly 25MHz). It has several time constants and gating modes, including a “very slow” mode (stable OSD) when SID does not identify valid CVBS.

By forcing phi-2 pin 17 above 4.0Volt, the HOUT is immediately stopped. Using an external detection circuit this can be used for flash protection. When the voltage drops < 4.0 volt, HOUT starts via the slow start procedure.

Pin 36 can be forced >3.9V to implement an over-voltage detector (status bit XPR). HOUT will be slow-stopped. Software has to toggle STB=0 and back to STB=1 before HOUT starts again (safety).

For non-EW versions, pin 21 connects the AVL capacitor (bit AVLE=1).The R and C at pins 26 and 27 must have good temperature stability

To enable TXT/CC decoding from YPrPb input, set bit HTXT=1. In all other cases the data comes via the CVBS-switch and HTXT should be set 0

GTV Function:SID: ptun_GetIdents, ptun_GetVideoIdentXPR: psys_GetXrayProtectionAVLE: psnd_SetAVLEnabledOnEastWestOutputPin


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67Horizontal drive

(open drain output)

66FlyBack In /Sandc. Out

Max. +5V

+ ++

+8V

24k

FBT/LOT

Flybackcapacitor

Capacitivedivider

Currentlimiter

Clipper

5.3V3V

2V2.7V

= Burst-Key= H-clamp= DC detect= Vertical

Sand-Castle

100..300µA

WrongH-timing = colour problems(loads Burst-Key)

SandCastle pulse:

• Switch-on protection (= 300mV below H-clamp level) takes care that HOUT never switches ON during an FBT-flyback

Active Pull downat start-up

5.3V3V

ϕ1ϕ2

Def

lect

ion

Tim

erDFL4..0

The PHI2-loop compensates for temperature effects of the switching of thedeflection transistor (high voltage and large currents).

The “SandCastle” pulse contains all synchronisation information:- the PHI-1 related chroma Burst-Key pulse- the PHI-2 feedback = H-flyback = Horizontal blanking pulse- the Vertical retrace = Vertical blanking pulse

We have to avoid destructive switch-on of the line deflection transistor during a flyback period. A built-in protection will NOT switch the Horizontal drive “on” (= pin 66 goes low) when the H-flyback input has a DC level above 2.7V.

When a capacitive divider is used to derive the Flyback information, an active pull-down will prevent H-flyback from accidentally floating too high.

Hint:If you see SandCastle being pulled low, apparently the IC tries to (re)start. During a slow-stop(protection), you can also see the pulling-down.

If you have colour detection problems, then check the timing of the H-flyback in the SandCastle pulse. If the Burst-Key pulse is distorted, then also the timing for the colour recognition may be affected.


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• Use OSD-mode or POC=1 only when video-sync-performance is irrelevant

(and SW must detect SL=1 to exit from OSD mode)

• If you use FOA,B=0,1 (Slow mode) ⇒ SW must select FOA,B=0,0 when IVW=0(otherwise catching may be slow)

Fast Search

STM

PHI1 VCO1600xFH

FXTALCalibrator

:1600

Noisedetector

Coincidence detector SL

Hsyncseparator

No Noise

01

11

SID VideoIdent

Sw

itchCVBSSW

Y/CVBSEXT

CVBSINT

No Noise

10

VCR

RF

RF, DVD

VCR only

Sync loss

No signal

PHI-1 loop:

00

1

1

SID,SL= 0,0

OSD-mode

1

0

17

Sw

itch

SD2..0

Auto

VID

FOA/B

SyncGating

Slow Full

CleverFast

Slow Full

Fast Full

Fast None

SLVery Slow

Very Slow

0

Phi1-mode

INA..D

POC

H+V sync

VDX,VDXEN,INA..D

VDX VDXEN Coupling VIF-AGC-gating to Sync x 0 Yes, while INA..D = tuner 0 1 Yes, Sync is coupled to VIF signal 1 1 Not coupled, no sync gating

VID Remark 0 PHI1 coupled to SID 1 PHI1 only controlled by FOA/B/POC

CMSS

IF-AGC

Slicer

Normal off air reception or cable:

FOA,B = 0,0 (Auto) for RF or VCR, possible on all program numbersFOA,B = 1,1 (Fast) is optimised for VCR, but not suitable for RFFOA,B = 0,1 (Slow) is best for RF-only or DVD, but not suitable for VCR

No RF signal conditionsThe “Very Slow” no-signal mode (controlled by SID,SL,VID=0,0,0) enhances the OSD stability (e.g. during search-tuning)

SoftWare overrule:For extreme conditions, SW can force a slow “OSD-only” mode via FOA,B = 1,0 (e.g. when SL=0). Switching back to normal mode must be done by SW under the condition: SL=1 or an integration of SID over a longer period.

POC=1 gives very stable OSD but also disables SL. It should only be used when video synchronisation is irrelative (e.g. welcome-screen).SID acts as PHI-1 helper when VID=0 and SD2,1,0=0,0,0 or selects the same source as INA..D.

IF-AGC-gating:When PHI-1 sync is synchronous to the tuner signal, active gating can improve the signal stability. If a tuner CVBS signal goes via a “SCART-loop-through” (= external input), set VDX,VDXEN=0,1 to active IF-AGC-gating.


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SID (1): as PHI-1 helper

Switches PHI-1 slower when there is no signalSID as PHI-helper

SD2..0=0,0,0 & CMSS=1

Allow some time to stabilise

Couple SID to the main video & sync separator

Gives better OSD stability during noise-only,prevents PHI-1 from staying FAST @ no sync

• When sync fails (SL=0) then PHI-1 will try to re-acquire in fast-mode

• With VID=0, SID can automatically select slow-mode (gives more steady OSD)

• SW can also force slow-mode: VID,FOA,FOB = 1,1,0 (but needs SW to return)

VID=0

Wait 10??ms

Then couple SID to PHI-1 time constant

Coupled circuits

SD2..0 CMSS Video input Remark 000 1 Selected by INA..D Main sync separator 001 0 CVBS1 (tuner, IF) 010 0 CVBS2 011 0 Y/CVBS3 100 0 Y/CVBS4 101 0 G2/Y/CVBS5 (pin 72) 110 0 G3/Y (pin 79) 111 0 Spare

Use separate, dedicated sync separator. Source selection for SID is done by SD2..0. (In these positions CMSS=don’t care)

With CMSS=1, the SID detection bit uses the main sync separator, which is always coupled to the displayed picture (as selected by INA..D).

When SID has to judge a signal from another, non-selected source, then bit CMSS=0 makes SID use another, independent sync separator circuit.

GTV Function:CMSS: psys_SetVideoIdentSyncSelectionFO: psys_SetPhiOneLoopTimeConstantVID: psys_SetVideoIdentificationActsOnFO: psys_SetPhiOneLoopTimeConstantSID: ptun_GetIdents, ptun_GetVideoIdentSL: ptun_GetSyncIdentVID: psys_SetVideoIdentificationActsOnPOC: psys_SetSynchronisationEnableSD: psys_SetVideoIdentificationSourceIN: psys_SetSourceSwitchVDX: psys_GetModeIFSyncInterfaceVDXEN: psys_SetEnableVDX


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SID (2): for multi-purpose

Most of the time SID helps PHI-1

Check:Auto de/mute SCART1 out

Once per second SID is used for other tasks

• Software extends functionality of SID circuit by multiplexing tasks

1x per second

Switch SID as PHI-1 helperStable OSD

Check:Auto source switching

Loop forever

Sample presence of sync on all sourcesIntegrate the result over several samples

When there is no sync on the Tuner signal,then mute the FE-A/V outputs on SCART1

yes

During AV modes:Control recalibration of IF

Implement this as ONE process,to avoid unnecessary switching

Every time when the source selection for SID is modified, or when it’s sync separator (CMSS) is changing, please always allow some 10ms stabilisation time before reading back SID.


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SID (3): automatic source switchingCheck presence of sync, e.g. once every 2 secondsSample all sources

VID=1

If sync was already failing, then set PHI-1 slow during the sampling of SID

SL=0 ?no

FOA,B= 0,1 slow OSD mode

Temporarily break coupling between SID & PHI-1

CMSS=0, SD2..0 > 0,0,0 Test all available sources (SD2..0 ≠ 0,0,0)

no

Re-couple SID to PHI-1

Is sync available on that source ?

All tested ?

• No need for sense-contacts & signal detectors, fully under SW control

• For RGB(F) sources, check also IN2,IN3

yes

Next SD2..0Read SID=1 ?

Wait 10??ms Detection time of SID circuit + switch-over time

CMSS=1, SD2..0=000

VID=0Wait 10 ??ms

Coupled circuits

Let it stabilise to avoid glitch

Restore FOA,B Put PHI-1 back to your own preference

Test all & do the switching after some integration

Temporary: for SD2..0=001 (CVBS1)use LOCK instead of SID

SID to Front-End + CMSS=0 temporary gives false sync indication

??E

S7.2D

During TV

-standby S

IDcan not yet

be used for wake-up

If you want to “borrow” the SID bit for detecting sync on other input signals (non-selected), then you will have to stop using SID as PHI-1 helper.

SW can quickly poll all available sources and then restore SID as PHI-1 helper.

Advice: Integrate the read-outs of SID for each external source over several samples, e.g. continuously “1” during 1 second. This avoids too nervous switch-over when e.g. a plug is connected or a VCR starts to play.

While you are polling other external sources, you can either:- force PHI-1 always slow during this polling period (= simple)- check the IF-lock bit IFPL & switch PHI-1 slow if it fails (= need SW)- only force PHI-1 slow when SL=0 before you started polling (=advised),

and accept some OSD instability during a few ms.


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SID (4): IF gating & recalibration

VDX VDXEN Coupling V IF -AGC-gating to Sync x 0 Yes, while INA..D = tuner 0 1 Yes, Sync is coupled to VIF signal

• European SCART1 plug permanently outputs tuner signal, to be used for loop-through” decoders/de-scramblers

• Make it a USER’s choice to select for AV1:

SCART-AV1 choice Bits Remark [1] Tuner output + External input,

correlation unknown VDX,VDXEN=x,0 Active IF gating only when Tuner is

selected [2] No Tuner output, only

External input VDX,VDXEN=x,0 and VSW=1 during Ext. input

No tuner output during External input (like Asia-Pacific: no cross-talk)

[3] Decoder ON = Tuner signal looped-through

VDX,VDXEN=0,1

Active IF gating even when AV1 input selected gives better tuner performance

• IF-gating makes LOCK more reliable• With [1] during external AV input the IF-PLL can loose lock too early at high modulation,

result = re-calibration of IF-PLL with visible distortion• SW can improve this, during AV input:

– Disable auto-recalibration via IFLF=1, couple SID to tuner (SD2..0=0,0,1 CMSS=0) – When SID also detects no tuner signal, then temporarily set IFLF=0 (= recalibrate)

Tun

er

IF

De-

Scr

ambl

er

SCART1

AV1

CVBS-Status

FE

When the De-Scrambler detects a signal that it can decode, it will activate the “CVBS-Status” line. Now SW should react by switching to AV1 external input.

Front-End mode:While the tuner signal is selected (INA..D=0,0,0,0) the IF-gating is keyed by the sync circuitry, so SID is then freely available to do other functions. If the IF gets out-of-lock AND there is no sync, then the IF-PLL will be recalibrated (IFLF=0).

In AV modes: (not Decoder-On)Now sync coupling is not possible (not synchronous to tuner signal), so then the SID circuit can be used to decide about recalibration. While IFLF=1 it will not recalibrate.

Remark:In TV/VCR combi’s the Front-End can be kept active during TV-standby (STB=1) by maintaining the +5V power supplies. In this special case the SIDdetector is forced to Front-End (SD2..0=irrelevant, overruled by hardware), but SW needs to set CMSS=0 (= use dedicated sync separator).

The SID detector can only work while +5V is available.

GTV Function:IN: psys_SetSourceSwitchVDX: psys_GetModeIFSyncInterfaceVDXEN: psys_SetEnableVDX IFLF: psys_SetCalibrationIFPLLDemodulator


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SID (5): SCART1 front-end muteSCART1 = always tuner audio & video outputAuto mute SCART1 out

If front-end is viewed: better use SL,otherwise: use SID independent

SID=1 ?yes

Background process

INA..D=0,0,0,0 ?yes

no

Mute SCART1 outputs

SL=1 ?no

yes

CMSS= 0

Couple SID to front-endSD2,1,0= 0,0,1

Use other, dedicated sync separatorWait 10?? ms Allow time to stabilise

Demute SCART1 outputs

no

Loop Mute/Demute as a background process

• Use SID →temporay: LOCK to mute tuner output signal on SCART1 if no sync

• When SD2..0=0,0,1 and IFLF=0 then SID=0 will recalibrate the IF

IFLF= 0 Allow IF-recalibration if no sync

Mute audio and video

Restore IFLF IFLF=1 prevents IF from recalibrating

Tem

pora

ry: u

seL

OC

Kin

stea

d (s

ee n

ext s

lide)

SL is a more reliable video signal indicator, but always coupled to PHI-1 (= selected/viewed video source). While watching a source OTHER than front-end, you can use SID because this has its own independent source selection (SD2..0) and sync separator (CMSS=0).

Video mute:Do NOT mute the Front-End via VSW=1, as this will shut-down the whole IF section and tuner-AGC. Consequently SID will never detect sync anymore.

-Front-End video output “IFVO” (pin 43,44) can be muted via IFO2..0.- Selected video output “SVO” can be muted via SVO1..0=1,0 (??=1,1).- CVBS-PIP video output can be muted via CS1A..D=0,0,0,0.

GTV Function:IN: psys_SetSourceSwitchSL: ptun_GetSyncIdentSD: psys_SetVideoIdentificationSourceCMSS: psys_SetVideoIdentSyncSelectionIFLF: psys_SetCalibrationIFPLLDemodulatorSID: ptun_GetIdents, ptun_GetVideoIdent


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LOCK detection:

• SID has a tiny problem while CMSS=0 (dedicated sync slicer) but only when:– A tuner signal without sync is received (Front-End no signal), gives high noise amplitude – AND an other source is viewed

• Unwanted effect: SID keeps telling there is sync, while there’s only noise• Temporary solution: use LOCK instead, but only in this case (FE while AV selected)

• Careful: also LOCK has its attention points:– When FE is viewed, LOCK is vertically gated = more reliable (black during VSYNC) = OK – When AV is viewed (Back-End synchronised to other source) & VIF input signals are

modulated > 85% (white picture), then LOCK toggles between lock/no-lock, while there’s still signal

• Solution: read LOCK several times and integrate via SW– E.g read 4 times with > 20ms interval; then integrate: ≥1 out of 4 = OK

Temporary problem,will be solved by trimming the dedicated sync slicer

(CMSS=0) in future silicon.(Normal sync slicer = OK)

GTV Function:CMSS: psys_SetVideoIdentSyncSelectionSID: ptun_GetIdents, ptun_GetVideoIdent


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PHILIPS

TEXT• HOSD connected to PHI-1 (HP2=0):

(coupled to the incoming signal)

PHILIPS

TEXTPHILIPS

TEXT

PHILIPS

TEXT

• HOSD connected to PHI-2 (HP2=1):(coupled to the display)

Stable OSD with noise & VCR trick modes

PHI-2 corrections (HP, HB, HSH) also active on OSD

PHI-2 corrections (HP, HB, HSH) not active on OSD

Slightly less stable OSD with noise & VCR trick modes

Horizontal reference OSD:

Three horizontal geometry corrections are made in the PHI-2 loop:

• Horizontal Parallelogram HP

• Horizontal Bow HB

• Horizontal Shift HSH

When using the parallelogram and bow correction the horizontal reference of the OSD must be connected to the PHI-1 to obtain the same geometry correction for incoming signal and OSD (HP2 = 0).

When these corrections are not needed, the setmaker is free in his choice

Note when the horizontal reference is taken from the PHI-2, (HP2 = 0) the horizontal position of the OSD is not changed when shifting the video with HSH.

GTV Function:HP2: psys_SetSyncForTextOSDHB: pimg_SetHorizontalBow (BOW)HSH: pimg_SetHorizontalShift (HS)


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35%70%

100%

Top Sync

Weak, noisy signal Strong signal Large signal

• Slicing level depends on noise detector(Fixed 175mV under Top Sync for very large sync pulse amplitude)

• FSL=1 forces 60% (use for non-standard signals with distorted black level)

• Similar bit for Horizontal: SSL (SSL=1: 30%, SSL=0: 50%)

175mV

>350mV

70%60%

100%

Top Sync

Vertical Sync slicing:

The vertical synchronization automatically adapts its sync-slicing level to the signal conditions. For optimal performance, it slices:- at 60% for weak signals (> 24db, measured by the noise detector ).- at 35% for strong signals (or forced 60% when FSL=1).

With negative modulation, the sync pulses have the largest amplitude of the IF signal. When there is noise, it is best to slice near the top of the pulse, at 60%.

For strong signals (no noise) we slice at 35%. This improves behavior with signals that have compressed sync, only during vertical interval.

In areas where this is not needed, the sync performance can be made more immune to disturbances by fixing the level to 60% via bit FSL=1 (e.g. coded signals with variable black level during vertical or some cheap DVD players).

When the sync amplitude becomes extremely large (> 350mV), the slicing is done at a fixed level of 175mV below top sync (end of proportional AGC range)

The horizontal sync separator slices at 50% or 30%(direction top sync), depending on the SSL bit.

GTV Function:FSL: psys_SetVerticalSyncSlicingLevelSSL: psys_SetSlicingLevelSyncSeparator


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Effect of position change vertical sync pulse

No verticalcatching

No verticalcatching

• Divider system + DC vertical amplifier gives:- Fast settling (speed-up with NCIN=1 : keeps vertical forced into Acquisition Mode)

- Minimal visibility of (short) sync interruption

• Automatic Comb-filter = OFF in “Acquisition Mode”

AcquisitionMode

Narrow Window522..528 lines622..628 lines

Norm Window525 ± 1 line625 ± 1 line

15 frames 15 frames

3 frames 3 frames

FSI=1

IVWF=1

IVW=0

FSI=0

NCIN=1

NCIN=1

Direct Sync Direct sync in windowelse sync at 528/628 Exact counter sync

Effect of missing vertical sync pulse

Vertical rolling Small vertical jump None

6 frames

Vertical Divider:

7 framesIVW=1 IVW=1

NCIN=1

In “Norm” window, the counter inserts after exactly 525/625 lines a vertical retrace pulse and checks whether there is a pulse from the vertical sync slicer. A missing pulse (temporary disturbance) will not be visible because it inserts a vertical retrace pulse, at the correct position.

After 3 missing pulses of the vertical sync slicer it will go to “Narrow” window. A missing pulse will cause insertion of a vertical retrace pulse after 528/628 lines. Here a slight jump of three lines can be visible.

After 3 more missing pulses the system goes into fast “Acquisition” mode using directly the output of the vertical sync separator to generate the vertical retrace pulse.

This divider system assures fast settling and at the same time high immunity against intermitted disturbances (spike noise).

Setting bit NCIN=1 will speed-up vertical catching even more,e.g. when switching channels:

- Change channel or video input- Force NCIN=1- When SL becomes 1, force NCIN=0 (after phi-1 is locked).

Note that as long as NCIN=1, bit IVW will not indicate “vertical-in-lock”.

Before the 50/60Hz indication bit FSI is really valid, bit IVW=1 should be checked to make sure the vertical synchronization is really locked. The result is: 50Hz, 60Hz or not-locked.


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BITS FUNCTION SETTING I / O MACRO FU REM FORF/ FORS

FORced Field frequency 00: auto 60Hz, 01: forced 60Hz, 10: keep last, 11: auto 50Hz

I Sync SC

NCIN Force No CoINcedence for vertical divider

0: normal, 1: force search window

I Sync SC For faster vertical catching

SSL Sync Slicing Level 0: 50% 1: 30% direction top sync

I Sync TK

FOA..B Forced phi-1 time constant 00: Auto 01: Very slow mode 10: fast/slow+gating 11: fast

I Sync SC

POC Phi-One Control sync mode 1: loop switched off I Sync SC VID Video IDent mode 0: SID controls phi1 loop

1: no influence I Sync SC Improves OSD

stability FSL Forced vertical SLicing Level 0: auto, 1: fixed 60% I Sync TK OVSE Enable Vertical OverScan

(RGB measurment lines) 1: enabled I Sync SC

HTXT Href for TeleteXT from own dedicated TXT sync slicer

0: dedicated sync slicer 1: from main sync circuit

I Sync SC 0= normal, 1= TXT/CC via YPRPB

MVK (anti) MacroVision Keying 1: active I Sync SC Active only during NORM mode

Sync related bits (1):

For enhanced stability of On Screen Display e.g. during search-tuning, the phi-1 loop can automatically be switched slow by SID (=Signal-Ident = simple 16kHz detector). Set bit VID=1 to enable this.

With POC=1, the phi-1 is set to free-run mode (X-tal locked). In this mode bit SL can not be used to detect line-sync-lock.

GTV Function:NCIN: ptun_SetVerticalDividerModeSL: ptun_GetSyncIdentIVW: ptun_GetStandardVideo FOR: psys_SetForcedFieldFrequencySSL: psys_SetSlicingLevelSyncSeparatorFO: psys_SetPhiOneLoopTimeConstantPOC: psys_SetSynchronisationEnableVID: psys_SetVideoIdentificationActsOnFSL: psys_SetVerticalSyncSlicingLevelOVSE:HTXT: psys_SetCsoSourceForTxtMVK: psys_SetMacroVisionKeyingEnabled


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SL Sync in Lock 1: phi1-loop locked O Sync SC IVW In Vertical divider Window during

15 consecutive sync pulses 0: no standard 1: 525/625 lines

O Sync SC

IVWF IVW Fast during 7 pulses 1: valid V-sync O Sync SC Faster than IVW

FSI Field Synchronisation Indication 0: 50Hz 1: 60 Hz

O Sync SC

HP2 H-Phase ref. of OSD to phi-2 0: to phi-1 I Sync SC SDC Set Duty Cycle of H-out 0: 55:45

1: 60:40 I Sync SC Change activated

only while STB=0 SN2..0 Signal-to-Noise ratio readout

of selected source 000: < 18 dB 001..110: 18 .. 43 dB 111: > 43 dB

O Sync SC

BITS FUNCTION STEPS RANGE MACRO FU REMHB Horizontal Bow 63 -1.. +1 us Sync ALHP Horizontal Parallelogram 63 -0.75.. +0.75 us Sync ALHSH Horizontal SHift 63 -2.. +2 us Sync ALWBF W ide Blanking Front 15 3.5 .. 5.9 us Sync SCWBR W ide Blanking Rear 15 7.8 .. 10.2 us Sync SC

Sync related bits (2):

For the “real-flat” picture tubes the IC offers controls for Horizontal-Bow and -Parallelogram (HB and HP). These controls are internally made as dynamic offsets between phi-1 and phi-2 loops.

Normally the On Screen Display is synchronized to the phi-2 loop (= most direct coupling for a fixed position on the screen), but when HB and HP are used, bit HP2=0 should be used to synchronize the OSD to the phi-1 loop. Otherwise the OSD will appear curved, while the video display is straight (bow & parallelogram compensated).


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BITS FUNCTION SETTING I / O MACRO FU REMDL De-interLace 1: de-interlace I Geo SCHCO Horizontal COmpensation EHT

tracking mode1: off, only on vertical0: both EW & vertical

I Geo SU

OSO Overscan Switch Off 1: switch off in vertical overscan

I Geo SU

SBL Service BLanking 1: active I Geo ALVSD Vertical Scan Disable (set to mid

position on screen for VG2 blackcurrent alignment, see HBC, WBC)

1: no vertical deflection I Geo AL

VGM1..0 Vertical Guard Mode 00: vertical guard01: vg & LED output10: switch output11: input, via NDF bit

I Geo SC

LED LED switch output 0: LED off, switch high1: LED on, switch low

I Geo SC

AVG Adjustment VG2 voltage 0: normal operation1: enable measurement

I Geo AL

FBC Fixed BeamCurrent switchoff 0: Blanked RGB outputs1: Fixed beam current

I Geo SC

EVB Extended Vertical Blanking 1: active I Geo SC

Geometry related bits (1):

To minimise visibility, the discharge of the picture tube during slow stop can be done in vertical overscan by setting bit OSO=1.

To help Vg2 alignment, the vertical deflection can be disabled via VSD=1 (one horizontal line on the screen). With AVG=1 the beam current can be read out via HBC and WBC, to align the “VG2-voltage (see section “RGB processing”). This even makes automatic alignment of VG2 (“screen”) possible.


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BITS FUNCTION STEPS RANGE MACRO FU REM EW EW W idth 63 700-0 uA Geo AL PW EW Parabola/W idth 63 0-440 uA Geo AL middle -

top/bottom SC S-Correction 63 -10 .. 25 % Geo AL TC EW Trapezium Correction 63 100 uA Geo AL top-bottom UCP EW Upper Corner Parabola 63 -55 .. 55 % Geo AL LCP EW Lower Corner Parabola 63 -55 .. 55 % Geo AL VA Vertical Amplitude 63 80 .. 120 % Geo AL VS Vertical S lope 63 -20..+20 % Geo AL VSH Vertical SH ift 63 -5.. +5 % Geo AL VX Vertical eXpand (zoom) 63 75..138 % Geo UC VSC Vertical Scroll 63 shift -18..19 % Geo AL VL0..1 Vertical Linearity 00

01 10

Full screen Lower vert lin Upper vert lin

Geo AL

VLIN Vertical Linearity 63 85 .. 117 % Geo AL VL0/1=00

Geometry related bits (2):

Component tolerances and DC offsets in the vertical circuit are compensated by the alignments: Vertical Slope (VS), SHift (VSH) and Scroll (VSC).

Mechanical offset in a picture tube is only compensated when a DC-coupledvertical amplifier is used, like TDA8357/59.


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SubTitleSubTitle

SubTitle

SubTitleSubTitle SubTitle

Horizontal Expand

+ Vertical Zoom

Vertical Compress

+ Vertical Slope :Move up bottom,top remains

SubTitle SubTitleSubTitle

SubTitleSubTitleSubTitle

SubTitle

4:3 tube,picture 16:9full width

16:9 tube,picture 4:3side bars

16:9 tube,picture 16:9sub title inblack bar

Vertical Expand Vertical Slope : lift sub title

SubTitle

+ Vertical Scroll

Geometry Zoom:

• + Digital zoom 3:4 ⇔ 16:9 and panorama mode (some types)

On a 4:3 picture tube the vertical zoom function can be used to compress a “full-screen” 16:9 picture back to normal aspect ratio.

On a 16:9 picture tube, a 4:3 picture can be displayed with black, vertical side bars. To make the picture “fill” the screen again, we can use H + V expand. If sub titles needs to be lifted, the Vertical Slope (VS) or Scroll (VSC) can be used. VS will keep the top of the screen constant, but modify the aspect ratio.VSC will move the whole picture and keep aspect ratio constant.

On a 16:9 tube, a 16:9 picture in “letter-box” format is normally expanded to fill the screen. In some area’s the black bars are used to transmit sub titles or on-line news flashes. In that case the Vertical Slope can be used to lift the lower black bar back on the screen.

Some versions of TDA110xx have digital zoom:- linear compression = 4:3 on 16:9 tube with black side-bars, or- panorama = non-linear stretched left & right edges

GTV Function:VS: pimg_SetVerticalSlope (VSL)VSC: pimg_SetVerticalScroll


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Width adjustment

Position of horizontal blanking adjusted separately

LEFT: Wide-Blanking Front (bits WBF)RIGHT: Wide-Blanking Rear (bits WBR)

4:3 picture on 16:9 CRT

WBF WBR

Outside visible picture, in overscan

Wide blanking:

On /off = bit HBL (Horizontal Blanking)

Wider range = bit WBI (6.24µs shift to center, use for digital 4:3 compression on 16:9 CRT)

When a 4:3 picture is displayed on a 16:9 tube, the East/West modulation can be used to compress the picture to normal aspect ratio. But the edges of the video, that are normally in the overscan, will then become visible. This can be adjusted with Wide Blanking front and rear.

In case the CVBS timing is not symmetrical, both Front and Rear edge blanking can be adapted individually.

GTV Function:WBF: pimg_SetWideBlankingStartWBR: pimg_SetWideBlankingEndHBL: pimg_GetWiderHorizontalBlankingWBI: psys_SetTimingWideBlanking


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Colour decoding:

In/OutIn/Out


YUVYUV


VIF & SIFVIF & SIF

MonoMono

RGBRGBColourColour


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Colour Decoder:

• PAL+NTSC or PAL+SECAM+NTSCFull Multi system, including Latin America

• Automatic-detecting colour search system, or software-forced system

• Integrated Base-band delay lines

• Automatic COMB filter for PAL-M/N/BG and NTSC-M– Enabled by CFA=0, permanently off when CFA=1– Automatically switches off when:

• No proper colour-system detected• No vertical in-lock (IVWF=0, or while NCIN=0)

?? ≤ ES7.2D: Automatic Comb switching=OK, but manual toggling CFAcan show visible vertical jump ⇒ hide this by switching during VBI interval.Will be solved in UOCIII-N2


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Y/CVBS

0..320ns

YINT

Burst detector

Chroma detector

ACL

ACC

Filter tracking

VCO

IDS

HUENTSC

DirectDigitalSynthesiser

0o 90o

IDN

IDP

B-Y

1H

1H

15

UINT

VINT

FXTAL

BPS

AutoSystemManager

IDN/P/S

FCO,CM2..0,PSNS,CHSE1..0

CD2..0

+/-

SECAMCloche

CB

R-Y

DTR

CLO

4H/2H

PAL /NTSC

Auto-CombFilter

CFA0

C

Y/C mode

Y/C, B&W or comb

YD3..0

Y

C

RefO Σ∆

DigitalFilter

H/2H/2

H/2

1bit

Colour Decoder Circuit:

Cbps

SBO1..0

COMB YCD

The CVBS signal is split into:- luminance path “Y” where all chroma components are trapped- chroma path “C”, via a band pass filter (“Cloche” for SECAM)

The Direct-Digital-Synthesiser locks to the incoming colour carrier, during the chroma burst. All trap and band pass frequencies are set relative to the DDS.

Colour is detected by combining information of the 3 multipliers:- Presence of a chroma-burst will set IDN (Ident Ntsc)- A +/- 90° phase alternation each line (H/2) sets IDP (Ident Pal)- A SECAM-demodulated level alternation each line H/2 sets IDS(Ident Secam)

For NTSC signals, the U+V baseband delay line can be bypassed or can be used as simple kind of comb filter. When the real comb filter is ON and NTSC is decoded, please set BPS=1 (=bypass) for optimal effect.

The base-band delay between Y and U&V (e.g. caused by different group-delay in SAW filter) is aligned by the luminance-delay bits YD3..0.

The automatic comb-filter is disabled when:- there is no stable vertical in-lock condition (IVW=0) - there is no suitable colour system detected (CD2..0=0 or Secam/NTSC443)- software disables it via CFA0=1 (preferred during search-tuning & Auto-Store)


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Nominalburstlevel

Nominalcarrierlevel

Too largecolourcarrier

Too smallcolourcarrier

Chroma signal

Burst

Colour Decoder: ACC

A video signal (CVBS) is fed through a chroma band pass filter, to separate the burst and colour carrier from the Black & White part.

The Automatic Colour Control circuit measures the chroma amplitude during the burst-key pulse (generated by synchronization part). It then tries to make this amplitude equal to the nominal value.

Since chroma amplitude and burst amplitude have a fixed relationship in the video standards, the colour carrier will be stabilized to its nominal value too.

If an attenuation or amplification of the colour frequency (e.g. 4.43 MHz) has occurred in the transmission of the TV signal, the ACC will automatically compensate this. The original colour saturation level is reconstructed.


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Nominalburstlevel

Nominalcarrierlevel

Chroma signal

Burst

Nominal burst,but wrong ratio

chroma-to-burst

Maximalcarrierlevel

• Too high chroma carrier level = over saturation• ACL=1 reduces during scan, burst unaffected

Colour Decoder: ACL

When the ratio between burst amplitude and chroma level is wrong, severe over-saturation can occur.

The Automatic Colour Limiter will reduce undesired over saturation, caused by too high chroma/burst-ratio. It reduces the too high chroma carrier level to a maximum allowed level.

The ACL adapts the chroma gain only during scan, so that the burst amplitude remains unaffected (maintain good chroma sensitivity).

Note:

Please disable the ACL circuit during SECAM reception (FM-modulated chroma) by setting I2C-bus bit ACL=0. In most other cases the ACL can best be left “on” (ACL=1).

GTV Function:ACL: pimg_SetAutomaticColourLimiting


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Chroma band-pass characteristic

SAW filter roll-off

+

=

Setting bit CB=1 gives 10% shift:

More symmetrical spectrum

CCPC

Ideal chroma spectrumBand-pass-filtered chroma spectrumA-symmetrical chroma spectrum

Chroma Roll-Off, bits CB or CLO:

When a SAW filter has too much roll-off for high chroma frequencies, this can be compensated by setting tool-kit bit CB=1 or CLO=1 for SECAM. This shifts only the chroma bandpass (not the calibration).

Especially the FM-modulated SECAM colour system profits from CLO.Under weak-signal-conditions, the SECAM PLL demodulator can sometimes loose its lock to the chroma carrier. Then it will jump to “where the maximum energy is”. Result = colour streaks (typical red- & blue-ish “flameche”) after a bright vertical line on a noisy CVBS picture. With a more symmetrical spectrum, the chroma PLL will reduce visibility of the SECAM flameche.

The AM-modulated PAL and NTSC chroma systems are less affected by SAW filter roll-off, but under specific field conditions the “tool-kit” bit CB can help to improve weak-signal ident-performance

Use CB=1 or CLO=1 only if necessary because it does affect the chroma spectrum.

GTV Function:CLO: psys_SetCentreFrequencyClocheFilterCB: pimg_SetChromaBpCentreFrequency


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BITS FUNCTION SETTING I / O MACRO FU REM ACL Automatic Colour L imiting 1 : on I ColDec TK PSNS Pal Sensitivity at Noisy S ignals 0 : lower sensitivity I ColDec TK For VCR (forced) & PAL-only

Please combine with SN1,0 BPS ByPaSs base band delay line 1 : bypassed I ColDec SC For NTSC if Combfilter= ON DTR Double chroma TRap 0 : single, 1 : double I Filt/Sw SC Suppress more, less

bandwidth CB Centre of chroma Bandpass 1 : 10% shifted I Filt/Sw SC CLO CLOche centre frequency 1 : shifted I Filt/Sw SC SECAM “Bell” filter

CHSE1..0 Ch roma ident Sensitivity for PAL and NTSC

00 : -34dB 01 : -37dB 10 : -41dB

I Filt/Sw SC

SBO1..0 SECAM B -Y O ffset 00 : +4.0 01 : +1.0 10 : -1.0 11 : -4.0kHz

I Filt/Sw AL Compensate tolerance, 01 or 10 to be used as “neutral”

CMB2..0 Multi-purpose CoMB pin function

001 : 2.1V+subcarrier I ColDec SC See I/O switching

CFA Comb F ilter Action 0 : 4H-PAL/2H-NTSC 1 : off

I Filt/Sw SC

FCO Forced Colour On 1 : no colour killing I ColDec TK COMB COMB filter active 0 : Not active O ColDec SC YCD Y/C Detector, higher chroma

burst on ”C” than on “Y/CVBS” 0 : CVBS detected 1 : Y/C signal detected

O ColDec SC Works only once, directly after a source change

Colour Decoder related bits:

Pin 33 (RefIn/Out…) can have different functions, which can be selected by the bits CMB2..0.

With FCO=1 the colour killing function can be disabled (only when one single colour system is forced). This enables colour under non- standard condition, e.g. trick play in TV-VCR combinations.

A forced suppression of colour can be done by setting SATuration=0.E.g. while software tries to determine the colour standard by switching SAW filters.


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CM3/2 /1/0

Colour Mode selected

Auto Freq. Software sel.

0000 PAL/NTSC/SECAM Auto Fa 0001 PAL/SECAM Auto Fa 0010 PAL Forced Fa PAL-BG/I/DK 0011 NTSC Forced Fa NTSC-443 0100 SECAM Forced SECAM 0101 PAL/NTSC Auto Fb 0110 PAL Forced Fb PAL-N 0111 NTSC Forced Fb 1000 PAL/NTSC/SECAM Full Auto Fa,b,c,d Auto 1001 PAL/NTSC Auto Fc 1010 PAL Forced Fc PAL-M 1011 NTSC Forced Fc 1100 PAL/NTSC Full Auto Fb,c,d Tri-norma 1101 PAL/NTSC Auto Fd 1110 PAL Forced Fd 1111 NTSC Forced Fd NTSC-M

Colour Mode bits:

• For correct RGB-matrix during DVD/YUV input, SW should define:- when FSI=1 (60Hz) : CM3..0=1,1,1,1 & MAT=0- when FSI=0 (50Hz) : MAT=1

CD3/2/1/0

Colour Detection

Freq. MHz

0000 No system 0001 NTSC-443 Fa 0010 PAL-BG/I/DK Fa

4.433619

0011 “NTSC?” Fb 0100 PAL-N Fb

3.582056

0101 “NTSC?” Fc 0110 PAL-M Fc

3.575611

0111 NTSC-M Fd 1000 “PAL?” Fd

3.579545

1010 SECAM

Each colour system can be forced using the CM bits. For flexibility also three automatic modes are implemented:

-1000 = Full (all systems at all chroma frequencies)- 0000 = PAL/NTSC/SECAM 4.43 MHz only (Europe)- 1100 = NTSC M, PAL M, PAL N (Tri-norma, LATAM)

The CD info is derived from the information of the three different demodulators, plus the locked frequency of the digitally controlled chroma oscillator. Normally there is no coupling to the vertical frequency, so even “non-standard” (VCR) signals like e.g. “PAL-443 at 60Hz with DK-sound” can be recognised. Except “SECAM-60Hz” can not be decoded in AUTO-mode.

Remark: PAL at frequency Fd (NTSC-M) is not possible when CM2..0=1000. We have blocked this position to improve robustness against false locking. Also NTSC ident is blocked for PAL-M/N frequencies.


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Subcarrier MHz 50Hz FSI=0

60Hz FSI=1

False 50 FSI=0

False 60 FSI=1

Fa 4.433619 PAL-443 NTSC-443 PAL-60 NTSC-50 ? -

Fb 3.582056 PAL-N ? NTSC ? NTSC ? Fc 3.575611 ? PAL-M NTSC ? NTSC ? Fd 3.579545 - NTSC-M PAL ? PAL ?

SECAM SECAM (ME)SECAM-60 - -

Handling non-standards:

• Distorted signals may be mis-identified ( transcoding VCR, noisy RF… )

• Combine CD3..0 with FSI, IVW and decide by software• Changing CM3..0 is (internal) vertically synchronised

(always wait until next Vertical Blanking Interval (= VBI-interrupt EBUSY), before it is effective)

• Auto-modes: each frequency-change takes 2xVBI time,before a colour system can be detected

• Advised order for 3.5MHz standards: PAL-N→PAL-M→NTSC-M (Fb,c,d)

By using an intelligent software-forced colour-search procedure, a reliable colour detection can be achieved even under difficult circumstances. The algorithm can then be optimised, by intelligent combination of:- Vertical deflection (50Hz, 60Hz or not locked)- Sound decoding (M, BG, I or DK)- Selected SAW filter (M or BGIDK)

GTV Function:fmst_SetColour / Sound / Systemfmst_GetColour / Sound / Systemfmst_GetDetectedColour / Sound / Systemfmst_IsColourNTSC / PAL / SECAMfmst_IsColour / Sound / SystemDetectionBusySL: ptun_GetSyncIdentPSNS:CM: pimg_SetColourDecodingDirectFSI: psys_GetFieldFrequency


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-10

-200

3 –

UO

C-I

II“H

ercu

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pres

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tion

2-12

8

Off-air M/BG switching:

Wait 2xVBI

4.5 MHz narrow VIF+SIF filtersSelect M-SAWSet CM=(PAL-N),TriNorma Reset: CM=PAL-N, wait 1xVBI

then set CM=TriNorma

Standard OK ?

All 3 tested ?no

2 x 20ms per chroma frequencyyes

FSI=0 ?

60HzPAL-M, PAL-N or NTSC-M

Test FSI before switching SAWSelect BG-SAW

Set CM=Auto at freq. FaLow sensitivity, wait 2xVBI

Select BG-SAWSet CM=Auto at freq. Fa

Wait 2xVBI

Standard OK ? yes PAL-443, SECAM-50 or NTSC-50Not found, try again

High sensitivity, wait 1xVBI

Standard OK ? PAL-60 or NTSC-443 or SECAM-60

yes

Not found, try again

Loop

3x

• If not found, retry a few times

NTSC detected yes NTSC-443

Allow PAL-60 ?

PSNS=1, wait 1xVBI

PAL detected ?

no

yes PAL-60

“China”-option

yes = 50Hz

A full-multi-standard TV receiver has switchable SAW filters. Software shouldset the colour-detection mode CM3..0, dependent on the selected SAW filter.

Pre-conditions: SL=1 (video present), PSNS=0 (no preference for PAL).

We advice to test the small bandwidth “TriNorma” systems first, in the order Fb→Fc → Fd. To make sure the IC starts in the correct order, please setCM3..0=0110 (PAL-N). Wait for the next Vertical Blanking Interval (VBI or “Busy-interrupt”), since the CM bits are only clocked-through during VBI. Then set CM3..0=1100 (TriNorma) and allow 2 VBI periods: one for clocking-through the CM bits plus one for the IC to detect a colour system. If this did not yield a detection, then determine the vertical frequency from bit FSI.

For 50Hz, set CM3..0=00xx to only test at frequency Fa (PAL-443, SECAM-50, NTSC-50). Wait only once 2xVBI, because the frequency Fa remains constant. PAL can be given higher priority via PSNS=1, since NTSC-50 is non-standard.Remark: Use PSNS=1 ONLY after channel switching & the signal is stable.

For 60Hz, test PAL-60 only when you really want it, since this often causes false identification with NTSC-443 (e.g. played-back from noisy tape). SECAM-60 is deliberately tested after PAL & NTSC since this rarely occurs.

Not found means you can retry a few times, but not indefinitely. Black&White transmissions without chroma-burst still exist. Therefore we advice to stop colour-search after a few seconds. Select M- or BG-SAW, dependent on the audio carrier. If that is not present, then take the M-SAW.


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YUV features & processing:

In/OutIn/Out

MicroMicro StereoStereoPowerPower Sync & Sync & GeometryGeometry

VIF & SIFVIF & SIF

MonoMono



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• Full YUV-loop interface (alternatives: DVD,CVBS,RGB or Y/C)

• Internal OSD insertion (not Saturation or Contrast controlled)

• Double window implementation

• Linear / non linear scaling for 16:9 sets

• Tint (~hue) on UV signals (including DVD)

• Peaking, Coring, Black \ Blue \ White-stretch, Transfer-Ratio and Scavem (also on TXT)

YUV processing:


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FXTAL

Cal

ibra

tor

CON

Mat

rix

R

G

B

+

Chroma Oscillator

Fa=4.433619 MHzFb=3.582056 MHzFc=3.575611 MHzFd=3.579545 MHz

TPAL

TNTSC

TSECAM

NTSC

CD2..0

SECAM

PAL

CM2..0

Y

U

V

SAT

BKS,BSD,AAS,TFRYD

MUS,MATPK,COR

YPRPB

CMB0/1

+4.5V

Alternativefunction

Comb

CV

BS

& Y

/C S

witc

h

HUENTSC

WS

TINT,TUV

Sca

ling

& D

oubl

e W

indo

w

IE2,IE3

DSK

CVBS2CVBS/Y3CVBS/Y4CVBS/Y5

C3C4

51545872555970C5 B

lues

tret

ch

Sync

SYS

Scavemprocessing

Scavem TXT Delay

Delay65 Svm

33

RINT

GINT

BINT

Signal routing:

Pea

king

,cor

ing

DINT

Tin

t

Dyn

. Ski

n to

ne

Sw

itch

Sw

itch

73

YSync IN

Halftone

RGBOSD

MMR: 87F7H

Ins

BLS

IN2

70727175 Fbl2

B/PbG/Vid/YR/C/Pr

78 R / Pr

Fbl3

798077

B / PbG/Y

IN3

YUV2..0, YC, INTF, FIN, FINM, IE3/2

INTF

DVD-to-YUV

74

Y U V

75 76

YUV-to-DVD

RGB-to-DVDInverse

PAL-Matrix

UV

offs

etOUV, OFB,BLOG,BLOR

HCT

• During DVD/YUV input colour detection is impossible; SW must select the correct RGB-matrix (NTSC-matrix when FSI=1 (60Hz) : CM3..0=1,1,1,1 & MAT=0 or PAL-matrix when FSI=0 (50Hz) : MAT=1)

= located in digital die

Colour decoding of PAL/SECAM/NTSC needs some processing time, that has to be compensated in the luminance path (fixed time). Further delay between Luma and Chroma is compensated by YD=Y-delay alignment.

OSD amplitude is set independently of Contrast or Saturation by Memory Mapped Register 87F7H in the µProcessor part and by bit HCT. Half-tone insertion (box with reduced contrast of main picture) is possible.

External RGB+F input (SCART) is converted to YUV, allowing Saturation control. Since RGB-to-YUV uses an inverse-PAL matrix, also YUV-to-RGB should be forced to PAL matrix (MAT=1), to get correct colours.- “YUV” mode is compatible with add-on feature IC’s,- “YPBPR“ mode allows direct connection of a DVD player.

The AC-coupling to YSYNCIN via an external capacitor allows better clamping and enhances the sync performance. It also eliminates horizontal-picture-shift when switching between video sources.

For full-screen-inserted RGBF input (without Sync-on-green), the sync normally comes via a CVBS input. Set SYS=1 only for this mode.


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BITS FUNCTION STEPS RANGE MACRO FU REM

PEAK5..0 PEAK ing 63 -20 .. 75 % Filt/Sw UC Neutral = 0DH

0 .. 415 ns Fsc = 4.43MHz YD3..0 Y (Luminance) Delay 15

0 .. 520 ns Filt/Sw SC

Fsc = 3.58MHz


RPA1..0 Ratio Pre/Aftershoot of peaking in direction white

00: 1/1, 01: 1.5/1 10: 2

I Filt/Sw SC

RPO1..0 Ratio Pre/Overshoot of peaking in direction black

00: 1/1, 01: 1/1.3 10: 1/1.7, 11: 1/0.7

I Filt/Sw SC

COR1..0 CORing, active below this video level

00: off, 01: 20 IRE 10: 40 IRE, 11: 100 IRE

I Filt/Sw SC

CRA0 CoRing A?? on SVM 0: 8%, 1: 15% I Filt/Sw SC

Peaking & coring:

PF1,0 Peaking Freq Delay Used for REM

00 2.7 MHz 190 ns NTSC-M/N, PAL-M/N 3.6 MHz Chroma

01 3.1 MHz 160 ns Alternative for 00 Set makers choice

10 3.5 MHz 143 ns PAL-BG, SECAM, NTSC-443 4.4 MHz Chroma

11 4.0 MHz 125 ns External RGB/DVD No Chroma encoding

GTV Function:YD: pimg_SetLuminanceDelayTimeHCT: psys_SetHighContrastOSDSYS: psys_SetYUVSynchronisationInputModeFSI: psys_GetFieldFrequencyCM: pimg_SetColourDecodingDirectMAT: pimg_SetColourMatrixAdaption


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SV

M o

utpu

t

10 50 IRE 100

• No VM for small signals (VM-coring area, defined by bit CRA0)

• High VM-gain for grey signals up to 50IRE; less gain for larger signals

• Selectable delay between VMOUT and RGBOUT (max. Video: -210ns, OSD: -300ns)

• VM gain adapted to H-position on the screen (temp. simplified parabola, no SPR2/1/0)

(edges of screen need more VM than centre)

• SVMA=1 : more low-frequency gain (6dB extra at 1MHz)

Yin

Scan-velocity modulation (VM):

2Vpp max.

ScaVeMprocessing

Delay

Delay

65

SVM2..0

YINT

OSD

SFR:SCAVTXT SMD1 SVMA,SPR2..0

SMD0 CRA0

VMOUTGain

left right

Position-dependent gain adapt

VMA1/0

Hor.position

Scan Velocity Modulation improves the horizontal spot quality of a picture tube, by temporary changing the scan speed of the electron beam. Near left&right edges we need more SVM than in the center, especially for real flat CRT tubes

GTV Function:CRA0: pimg_SetCoringOnScavemSVMA: psys_SetScavemOutputSignal


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• I2C bit BSD sets black stretch depth to -10 or -20 IRE (above 50 IRE no stretch)

• Black Stretch switched off when bit BKS=0

Black Stretch (1):

Yin

You

t

10 50 IRE20

0

10

50

20B

SD

=0

BS

D=1

-20

-10

Stretch

BKS=0

GTV Function:BSD: pimg_SetBlackStretchDepthBKS: pimg_SetBlackStretchMode


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active area

Black stretch off

Required 10%active area to switch-off Black-Stretch

Black Stretch (2):Measurement Window

• 1: Determine dynamic black-stretch-reference level (in window)

• 2: In window, measure sum of area’s where video is below that reference

• 3: If more than 10% area (relative to full screen) is below the reference, then switch black stretcher off (or 20% when AAS=1)

Test method : black pluge on a grey background

=

AAS

=0

AAS

=110%

90%

For best effect of the black-stretcher, the TV application has to be carefully optimised (Beam Current Limiting, stability of the CCC loop, no line sag).

The easiest way to check the black stretcher, is with a gray background (below 50 IRE, otherwise no stretching at all). Then apply a black section, a bit less than 10% of the viewing area. If you increase the section above 10%, the black stretcher will switch off smoothly (no discontinuities).

So when there is enough black in the video, stretching stops.

GTV Function:AAS: pimg_SetBlackStretchArea


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Yin

You

t

max. 18%White Stretch

• GAM=0: White-Stretching dependent on average detector (= APL) Bits WS1/0 determine:- the Average Picture Level (APL) where the white stretching begins- maximum achievable stretch (at 50 IRE)

• GAM=1: fixed non-linear luminance transfer (gamma)

Bits WS1/0 select one of 4 characteristics

White Stretch / Gamma:

8% 100%

100%

17

Whi

te S

tretc

h G

ain

incr

ease

10%

APL

WS1,0

=1,1

12%

18%

25 28 40

WS1,0

=1,0

10

WS1,0

=0,1

50% 50

GTV Function:GAM: pimg_SetGammaControl


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• Transfer Ratio = dynamic brightness reduction, changing linearly with the Average Picture Level (APL)

• No video-dependent shift when bit TFR = 0

• Eco-Histogram = combined Black&White-Stretch plus Transfer-Ratio

Transfer Ratio:

20

2

10%

800

Brig

htne

ss

4

APL

⇓

TFR=0

TFR=1

Unwantedwhite compressionat high picture level

Less white compression,(some loss of dark details)

TFR

=1

Visible on a CRT:

100 IRE

Red

uce

TFR=0

A “histogram” function tries to maximise using all available shades of gray within the available contrast-space. By combining the features of UOCIII you can implement a similar behaviour:

-Black-Stretch makes more contrast-space on the lower end:If the darkest part was not black yet, it will pull this towards black

-TFR = auto-brightness:If the CRT produces much light output, the beam-current limitingwill compress the brightest details. TFR=1 makes more contrastspace for bright details, by reducing the brightness a little

-White-Stretch (gamma):This will enhance details in the mid-gray values, but only if theaverage picture is not too bright

GTV Function:TFR: psys_SetLuminanceDCTransferRatio


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• Blue discolouration at high intensity = brighter impression (at same energy)

• No effect on lower-intensity parts (e.g. skin tones)

• Blue Stretch switched off when bit BLS=0

• NRR=1 : no RED reduction during Blue Stretch (taste dependent)

Blue Stretch:

R,G

,B g

ain

200

20

100

80 IREYin

Blue-Stretch gives a “brighter-than-bright” impression by making a blue discolouration for the brightest picture details. More light-output is not possible because of Beam-Current limiting. So Blue-Stretch enhances the light-impression without needing more energy.

GTV Function:BLS: pimg_SetBlueStretchNRR: psys_SetNoRedReduction


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RGB back-end processing:

In/OutIn/Out


ColourColour YUVYUV


VIF & SIFVIF & SIF

MonoMono

RGBRGB

The Cut-Off control circuit with “Continuous Cathode Calibration” stabilizes the picture tube alignment during age-ing of the TV set.

Not only a White Point adjustment, but also a Black level offset adjustment is now provided. This enables independent colour temperature setting for Low-and High- light. With this new feature even (cheap) picture tubes with non-standard gamma characteristics can be used.White Point registers: WPR, WPG & WPB for Red, Green & Blue.Black Level Offset registers: BLOG & BLOR = offsets on Green and Red

(Blue instead of Red if OFB=1).

The contrast of the OSD can be set via the RGBOSD control in a µProcessor MMR register. The Contrast setting has no effect on the OSD, butBeamCurrent limiter and PeakWhite limiter do (see next slide).


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Digital black-current loop: Why?

• One-point offset compensation is sampled-analogue(should react fast & precise to EHT / VG2 variations)

• Gain-control needs stable application: digital implementation allows intelligent integration via software (wait till warm, skip exceptions)

• Long-term drift compensated, a little each time(SW can read back loop-parameters & store them as start values for next switch-on)

• Hide visibility of gain adaptation (e.g. SW adapts gain during channel-change)

• Any Start-up behavior can be made via software (pre-compensation)


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10µA

150µA

1.2mA

130V 60VVCATHODE

ICATHODE

CCC-loop:

• DC cut-off- & gain-control make a CRT-tube behave “ideal”

The R,G and B characteristics of a picture tube have a gamma shape.

The DC offset (black, Cut-Off) is compensated, using measurement pulses (10µA because it is not possible to measure with zero current). This control loop has to react fast, because the Cut-Off depends on VG2, which is dependent on EHT-voltage, which can be influenced by BeamCurrent.

A digital gain-loop annihilates differences, using a second calibration point (150..280µA).


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220µ

A

87

86

85

RBL Blanking

DAC

BRI

CCC MeasurementPulse Generator

10µA

84

LeakageCompensator

WBC,HBC

Low LightOffset RGB

IblackPeak

White

Reduce CON & BRI

Sample & Hold

BOUT

GOUT

ROUT

BINT

GINT

RINT

83

BCL=AverageBeam-CurrentLimiterInfo

AKB,EGL,AVG

OSO,FBC

1mA Beamcurrent

Discharge

RGB output control:

VG2Window

RGBL0.8V

Preset GainLoad

3x Counter

PGR/G/B

LPG

GLOK,RG/GG/BG

Drive levelCL3..0White PointWPR/G/B

Σ

<-5µA=up>5=down

• EGL=0 holds gain loop

• LPG=1 allows pre-setting (& holds loop too)

Beam Current LimiterPeak White Limiter

CBS,PWL,SOC

DACs

detector

PTW

SLG1,019

0

280

150

BLOR,BLOG,OFB

OUV

UV-offset

A fast Peak White Limiter (PWL) and a slow Beam Current Limiter (BCL) can reduce contrast and brightness to avoid over-drive of the picture tube(prevent: geo-distortion, local doming, de-focusing).

The Continuous Cathode Calibration loop (CCC, AKB= Auto Kine Bias) consists of a DC-offset correction (black current) and a gain correction loop. For good performance, the RGB amplifiers must be able to handle positive and negative leakage currents. This is included in all Philips Semiconductors RGB amplifiers with a current measurement output (e.g. TDA6107A/08A). The gain control loop annihilates gain differences between R,G and B channels (due to age-ing, component tolerances etc.)

Before adapting the RGB drive, the IC will measure and compensate the leakage currents (normally 2..10µA). The IC can handle +/- 75µA.

The black current input is also used to set 1 mA discharge current during controlled shut-down of HOUT (if bit OSO=1), and to measure the beam current during Vg2 alignment (VSD=1).During blanking (RBL=1) the outputs are driven 1.1V below black level.

GTV Function:EGL: pimg_SetEnableGainLoopCCCLPG: pimg_SetRGBGainPresetLoadOSO: psys_SetVerticalScanAtSwitchOffVSD: psys_SetVerticalScanDisableRBL: pimg_SetRGBBlanking


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Using the PTW bit:

PTW = Picture Tube Warm detector

• During start-up: disable the gain loop, EGL=0 (For stable PTW-readout, the RED preset gain should be set approximately 3 steps higher than was previously read back in a warm set)

• Load preset gain into the counters by toggling LPG=0→1• Set EGL=1 (enables measuring lines, counters are blocked while LPG=1)

• Keep reading until PTW=1 : now the picture tube is warm, i.e. the RED gain-measuring line causes a current larger than the current selected(SLG1..0 :150, 190, 220 or 280µA)

• Set EGL back to 0 (makes PTW indication invalid)

• After loading desired preset gains, toggle LPG=1→0

Before the cathodes of the CRT-picture tube are warm enough, it is not possible to display any picture/OSD. The heating-up takes several seconds and determines most of the “TV-cold-start-time”.

Using the PTW bit, your software can read back exactly when the CRT can start to display = automatic adaptation of start-up time.

GTV Function:PTW: psys_GetIndicationPictureTubeWarmEGL: pimg_SetEnableGainLoopCCCLPG: pimg_SetRGBGainPresetLoad


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Start up CCC loop:

Give-up if it takes too long, >10s

Continuously stable during 400ms

Sample BCF ~ once per frame

Keep RBL=1 for black switch-on

Wait until Picture Tube Warm

Offset ∆ during startup (∆ =~3, on red)

Check for failures: SUP, NDF …

Black-Current-loop stable ?

Keep LPG = 1 !!

Time-out<10s?

Start: Time-out

Init: BCF_OK_Cntr=0

Wait 20ms (= 1x VBI)

BCF=0?

Increment: BCF_OK_Cntr+1

BCF_OK_Cntr=20?

=10s

Set: RBL=0

Init: STB,RGBL,RBL=1;AKB,EGL=0

no

Set: RGBL=0 , EGL=1

Set: gain preset PGx=last value + ∆Clock-in presets, toggle: LPG=0→1

Switch-on: STB=1 & wait 1.5s

Set: gain current SLG to last value

Set: gain preset PGx=last valueClock-in presets, toggle: LPG=1→0

no

PTW=1? no

Switch back to stored optimal value

Set: EGL=0 Freeze the gain loop = best stability

While the black-current-stabilisation “CCC”-loop is not yet stable, the “black” level at the RGB drive outputs is undefined. Temporarily these outputs can be forced to a fixed level via RGBL=1. But before the CCC-loop can start, SW must set RGBL=0.

It is not mandatory to postpone OSD display until BCF=1, but severe OSD discoloration may occur. Suggestion: use “rainbow” OSD colours for start-up, this also helps to speed-up the stabilisation of the CCC loop.

For CCC-loop-start-up, we advice to check for a continuous period of 400ms where BCF=1, before releasing the blanking (RBL=0). But if for any reason this would take more than 10s, simply let go and un-blank the screen.

Note: To enable the mechanism for PTW, the gain-loop must be active (EGL=1) but the CCC-loop counters must be kept frozen (LPG=1). The check for PTW+BCF uses only the RED channel, so SW only needs to add the ∆ in the RED preset PGR.

GTV Function: fpmt_SetPowerStateBCF: psys_GetBlackCurrentConditionPTW: psys_GetIndicationPictureTubeWarmEGL: pimg_SetEnableGainLoopCCCPGR: pimg_SetPresetGainRed


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SW aided gain control (1):• Measure loop gain ⇒ integrate over long period ⇒ adapt gain• Don’t measure while CRT-tube is cold, wait e.g. 15 minutes

– During warm-up: use values from Eeprom (previously stored PGR/G/B)

• Measuring can be done: (read back RG, GG, BG)

– Continuously, with immediate adaptation (automatic) = visible– Incidentally (during channel-switch or enter standby); adapt gain later = invisible

• Adapt gain only a little bit per correction: age-ing is slow• Exceptions: sometimes larger adaptation needed:

– During TV-production ⇒ “Factory-mode” (align WP after settling of Gain)– After TV-production ⇒ “Virgin-mode” (e.g. first 10 times switch-on)– After Servicing (calibrate) ⇒ re-enable “Virgin-mode” (replacing IC or CRT)

• Use intelligent SW-integrator:– Average the measured errors– Adapt gain only when same +/- error is detected multiple times

Normally the GAIN hardly changes in a TV, only a little bit due age-ing of components. An Automatic loop sometimes over-reacts on glitches, that is why we now make it possible to integrate over a longer period. SoftWare now has full control how fast/slow corrections are done.

In Factory mode you can leave the CCC-loop ON during a burn-in period. If the CCC-loop has reached its stable end-value (GLOK=1) within about 1 second, the TV chassis is OK, else it could be redirected to a repair stage.

Hint:If something was damaged in the TV set, also the SW-integration may end-up at max. or min. values of PGR/G/B. This could be used as a trigger to enter “Protection-mode” → blink an error LED and switch power off.

GTV Function:GLOK: pimg_GetIndicationCCCGainLoopPGR: pimg_SetPresetGainRedPGG: pimg_SetPresetGainGreenPGB: pimg_SetPresetGainBlue


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Gain-SW (2): Measure & integrate

Blank screen & enable CCC loop

Read out the CCC loop counters

In Virgin-mode you may want to correct large errors earlier or not

One INC/DEC per 2 fields (40ms)

Set: RBL=0

Init: RBL=1; EGL=1

Read back RG,GG,BGAllow 320ms for CCC loop

Set: gain preset PGx=last valueClock-in presets, toggle: LPG= 0→1→0

Switch back to stored optimal valueSet: EGL=0

Store PGx in Eeprom

Freeze the gain loop again

Virgin-mode? yes

Many samples taken?

Consistent error over many samples ?

no

Persistent error?no

Don’t do this during 15min warm-up period

Integrate over a long time span

no Other correctionstrategyPGR,G,B:=+/- 1 step

TV still too cold?

SW controlled Gain loop

Do not measure/adapt the gain settings while the TV is cold (e.g. 15 minutes).

The three CCC-gain-loop counters do one INC/DEC per 40ms, so if you start at 50% of 128 (7bits) it can take 64x40ms=2.56s to reach min/max PGx value. We advice to limit the sample-time < 350ms, otherwise channel-switching becomes too slow.

During some “invisible” periods, the Software can measure the correctness of the gain settings. We advice to do this:

- during (black) channel switch-over- when switching the TV into standby

We temporarily enable the gain loop; after taking an “RGB-sample” we will go back to the previous gain setting. Integrate the “samples” over a longer period, to cancel out spikes/noise etc.


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White point color temperature adjustment

(WPR, WPG, WPB)

BLORBLOG

VCATHODE

ICATHODE

WPRWPG

WPB

Low-light color temperature adjustment:

BLOG on Green, BLOR on Red (or on Blue when OFB=1)

Color temperature adjustment:

GTV Function:WPR: pimg_SetWhitePointRedWPG: pimg_SetWhitePointGreenWPB: pimg_SetWhitePointBlueBLOG: pimg_SetBlackLevelOffsetGreenBLOR: pimg_SetBlackLevelOffsetRedOFB:

psys_SetBlackLevelOffsetBlue


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Bit OSVE=1: measuring lines are kept in the vertical over-scan

16:9 picture on 4:3 CRT

Vertical compression

OSVE=0

OSVE=1

CCC measurement lines:

CCC-measurement lines become visible on the screen

Note: check compatibility with your vertical deflection amplifier !

It is possible to keep the CCC-measurement lines always in the overscan, even while the picture is vertically compressed by underscan.

Before using bit OSVE, please verify that the vertical amplifier is capable of handling the “jump”.

TDA8357/59 can, provided that:- a zener diode is present between output pin 4 “OUTB” and ground- sufficient supply decoupling is present.

GTV Function:OVSE: dsys_SetBlackCurrentMeasuringLinesInOverscan


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Adjustment procedure:

• First Program desired White Limiting level (PWL)

• Then select Soft Clipper level : 0%, 5% or 10% above PWL

White limiting level (PWL bits)Soft Clipping level (SOC bits)

< 2µs 2 µs

Spike shorter than 2 µs : Only Soft Clipping active

Peak longer than 2 µs : White Limiter also becomes active

CVBS/Y

White limiter & Soft clipper:

The White-Limiter is a feed-forward system. A 2µs delay avoids reaction on sub-titles. When PWL gets triggered (=video above selected PWL level), it draws 4mA from the 4.7µF capacitor at the BCL pin. This will reduce contrast (& brightness) until the over-drive condition is removed. After this, it will take again 2µs before PWL reacts to the next over-drive.

The soft clipper is intended to clip high frequency peaks if the video signal. Its attack level can be selected 0, 5 or 10% above the selected PWL level, via bits SOC1,0.

By careful application it is possible to do more on feed-forward (PWL, SOC) and less on Beam-Current feed-back. This improves stability of the TV picture and gives a brighter picture before “local-doming” occurs.

GTV Function:PWL: psys_SetPeakWhiteLimitingControlSOC: psys_SetSoftClippingLevel


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BeamCurrent

Info

EXTERNAL

RGBINTERNAL

BCL pin

2. Slow Beam current limiter:also drains current from cap.

2

1. Fast White limiter:drains current from capacitor

Decrease capacitor voltage:- CONTRAST reduction- BRIGHTNESS reduction

DAC

CON

DAC

BRI

< <

RGBINTERNALSoft Clipper

SOC

1 White leveldetector

PWL

2µs

Beam Current Limiting:


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BITS FUNCTION SETTING I / O MACRO FU REM AKB Auto Kine Biasing

= black current stabilisation loop 0: enable CCC loop, 1: disable CCC loop

I RGB SU

BCF Black Current loop Failure 1: loop is not stabilised O RGB SC PTW Picture Tube Warm 1: cathode > 150..280µA O RGB SC See SGL BKS BlacK Stretch mode 1: on I RGB UC EVG Enable Vertical Guard 1: protection enabled I RGB SU HBC Helper below/above Black Current

window (See also WBC and AVG) 0: below window 1: above window

O RGB AL

WBC Window Black Current 1: Iblack is within window (12..20uA)

O RGB AL

IE3/2 Insertion Enable fast blanking input 1: enabled I RGB SC IN3/2 Reflect level on the fast blanking

INput pin of RGB 3 or 2 1: active O RGB SC Sampled during

vertical retrace MAT PAL/NTSC MATrix 0: auto

1: forced PAL matrix I RGB SC NTSC can be

forced via CM3..0=1,1,1,1

MUS NTSC Matrix USA 0 : Japanese NTSC 1 : USA NTSC matrix

I RGB SC “0” often preferred also for USA

CLD CLamp Delay 1: 400ns compensation I RGB SC When YUV-loop feature needs this

LLB Low Level Beamcurrent 1: enable 0.5mA pull-down on BCL pin

I RGB SC

HCT High Contrast selection for OSD/TXT 1: 3dB more I RGB SC

RGB related bits (1) :

The CCC-loop can be switched off for LCD applications by setting AKB=1.

The beam current during Vg2 alignment can be monitored using HBC and WBC (under / above window, in window).


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BITS FUNCTION SETTING I / O MACRO FU REM XPR X-ray PRotection 1: failure detected O RGB SC

AVG Alignment VG2 1: enabled I RGB SC Output via WBC and HBC

BLS BLue Stretch 1: enabled I RGB SC

NRR No Red Reduction during Blue Stretch 1: no reduction I RGB SC

DSK Dynamic Skin tone compensation 1: enabled I RGB SC DSA Dynamic Skin tone Angle 0:117º, 1:123º I RGB SC

RBL RGB BLanking 1: outputs blanked I RGB SC

RGBL Force RGB outputs Low, prevents RGB drive at start-up & black switch off.

1: RGB outputs blanked I RGB SC Use only during start/shut-down

BLBG BLank Blue & Green 1: blank B&G channel I RGB SC For Factory adjustments SYS SYnc Switch (when RGBinput is selected) 1: use CVBS for Sync

0: Sync on Green I RGB SC Full-inserted RGB has sync on

accompanying CVBS signal WS1..0 White Stretch 00: off

01: 10%, APL=17% 10: 12%, APL=25% 11: 18%, APL=28%

I RGB SC Average Picture Level = where white stretching-gain starts to reduces again

SOC1..0 SOft Clipping level 00: PWL level 01: 5% above PWL 10: 10% above PWL 11: soft clipping off

I RGB SC

YUV1..0 YUV/RGB input selection I RGB SU

OUV Offset UV or Red & Green 1: UV colour offset 0: RG(B) low-light offset

I RGB SC


YUV input levels are compatible with :

- all Philips Semiconductors IC’s with YUV interface (YUV1,0=1,0)

- YPRPB levels coming from DVD players (YUV1,0=1,1)

The RGB outputs can be blanked using RBL. Also black switch-off is possible (when the picture tube is discharged, using a bleeder).

When the CCC loop has not yet stabilised, e.g. during switch-on, the RGB outputs can temporarily be forced to a fixed DC level via RGBL=1.


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BITS FUNCTION STEPS RANGE MACRO FU REM BLOR /G Black Level Off-set Red / Green 63 -100..+100 mV RGB AL

BRIGHT BRIghtness 63 -0.4..+0.4 V RGB UC

CON CONtrast 63 -14..+6dB RGB UC

TINT TINT , works on any input 63 -30..+30 ° RGB UC Hue works only on CVBS/YC

SAT SATuration 63 0 .. 300 % RGB UC

WPR /G /B White Point Red / Green / Blue 63 0.. +6 dB RGB AL

PGR/G /B Preset Gain Red / Green / Blue 63 45VPP..180VPP RGB SU CRT drive at nominal contrast

CL3..0 Cathode drive Level 15 0.. +6 dB RGB SU Nominal CRT drive

PWL Peak White Limiting Level 15 RGB SU


BITS FUNCTION SETTING I / O

MACRO FU REM

OFB BLOR OFfset active on Blue or Red channel

0: on Red I RGB SC Depends on alignment method

OUV Offset UV or Red & Green 1: UV colour offset 0: RG(B) low-light offset

I RGB SC Depends on alignment method BLOR/G range –50..+50mV

EGL Enable Gain Loop in CCC system

1: loop active I RGB SC

SLG Select Loop current Gain 00: 220uA 01: 150uA 10: 280uA 11: 190uA

I RGB SC

GTV Function:HBC: dsys_GetBlackCurrentLevelWBC: psys_GetBlackCurrentWindowBLOR: pimg_SetBlackLevelOffsetRedBLOG: pimg_SetBlackLevelOffsetGreenAVG: psys_SetVG2AdjustmentModeVSD: psys_SetVerticalScanDisableAKB: psys_SetBlackCurrentStabilisationWPB: pimg_SetWhitePointBlueWPG: pimg_SetWhitePointGreenWPR: pimg_SetWhitePointRedCL: psys_SetCathodeDriveLevel


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540 690 VG2 [Volt]

160

130

VC

ATH

OD

E[V

olt]

VG2 preparation (1): find BRIAVG

1. Connect Voltmeter on BLUE cathode, set VSD=1, BLOR/G=20HEX(Take Blue first, because Red & Green can be adapted via BLOR/G)

2. Adjust BRIVSD (Brightness-DAC) until voltage = specified cathode cut-offAdjust BLOR/G so that all 3 cathodes have same voltage

3. Increase VG2 until a faint line just becomes visible = VG2IDEAL

4. Set AVG=1, VSD=0, AKB=0 (CCC loop on), apply a black video signal,maintain VG2IDEAL position

5. Adjust BRIAVG until HBC,WBC=1,1 (in window ~ 15µA)

6. Average this for a number of TV sets = BRIAVG(Using Brightness-DAC for DC offset, levels out system tolerances)

Choose high Cut-off = allow more range to increase drive while VG2 is lowered due to Beam Current load

860

Use IC as voltage generator AND for current- measuring

The brightness DAC can select the proper DC cathode-cut-off voltage for your picture tube (=BRIVSD while VSD=1). Via this DC you can find the optimal position for the VG2 potentiometer.

Maintaining this VG2 we now adapt BRIAVG (AVG=1) to find the “15µA-IBEAM” point via I2C-read-back bits HBC,WBC. For a given combination of tube & amplifiers & FBT/LOT, this BRIAVG value should be determined ONCE.

Now the VG2 alignment can be automated, using HBC,WBC=1,1 (=15µA) as a reference.

The Cut-Off voltage is a function of VG2. Under working conditions, the Beam Current load will lower EHT & VG2 voltage. The CCC loop must increase the drive voltage to compensate for this. We advice to choose a high Cut-off voltage, allowing more room for the CCC loop to compensate.

- DC-range for the CCC-loopRGBOUT = 1.65V +/- 0.85V

86V 190VVOUT,CATHODE

2.3V

1VVIN

= V

RG

B,O

UT

1.65V

Gain = 80x

Spec TDA6108A:190VOUT at 1VIN

138V

3V


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1. Define drive level, set CL-bits accordingly (CRT specification)

2. Set BLOR,BLOG=20HEX (no black-level offset)

3. Set AVG=1, AKB=0, Brightness=BRIAVG (= value found during in preparation)

(No video signal necessary, but avoid excessive beam current)

4. Align VG2 until WBC,HBC=1,1 (±6V accuracy on cathodes)

5. Set AVG=0, nominal Brightness (back to normal values)

6. Align WPR/G/B (WP always after VG2 alignment)

VG2 alignment (2): AVG method

PHILIPS

HBC,WBC=1,0

Measurement window

CCC active

“Black” DC leveldeterminedby BRIAVGand VG2

Keep OSD position below measurement bar

HBC=1Decrease VG2

WBC=1VG2 is OK

20µA

HBC=0Increase VG2

12µA

Make sure that the CCC loop is enabled: AKB=0.

While AVG=1, a black bar of 15 lines is visible (lines 67 - 81), during which the current into the black current pin is monitored

For precise alignment, it is best to have the same conditions as were used to determine BRIAVG (black video). This assures that VG2 is not lowered due to large Beam Current.The CCC loop will try to adjust, so transition effects may be visible. SW can show the alignment status on the OSD or on LEDs.

After VG2 alignment, set AVG=0 and Brightness to nominal position. Then align the white-point via the WPR,G,B registers.


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In fact the same as during the preparation: but no OSD possible !

1. Define drive level, set CL-bits accordingly (CRT specification)

2. Set BLOR,BLOG=20HEX (no black-level offset)

3. Set VSD=1, AKB=1 (loop OFF), Brightness=BRIVSD (= value from preparation)

(No video signal visible, V-deflection is switched off)

4. Align VG2 until a faint line just becomes visible

5. Set VSD=0, nominal Brightness (back to normal values)

6. Align WPR/G/B (after VG2 alignment)

VG2 alignment (3): VSD method

V-deflection-off concentrates all video-lines onto ONE line.Then lower VG2 until cathodes just start to emit light = correct Cut-Off


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LCD-mode (1):

UOC III “Hercules” can be used as front-end for LCD-TV:

• No Phi2 loop necessary (pull-down resistor on pin 16 = zero jitter contribution)

• Bit ??CSY will be renamed “LCD” in UOCIII-N2LCD=1 : composite H+V-pulse on pin FBISO (sandcastle for CRT)

– CRT-failsafe switch-over: only during Standby (while STB=0 !)

• Separate H & V-pulses can be made from:– SandCastle-pulse, via simple slicing circuit– Pins HOUT and VSCAP

Pin HOUT does not change function since it would be disastrous for CRT-deflection, if it ever modified the timing accidentally.

For safety also pin FBISO can only change function during standby. So toggling bit CSY only has effect while STB=0.

The “composite H+V” output on pin FBISO uses the PHI-1 as horizontal reference pulse (sync-acquisition PLL). During sync-loss or noisy video signal, this reference may take fast phase jumps. If an LCD scaler has problems with this, SW can set FOA/FOB=1,0 bits to damp the PHI-1 loop (= very slow).

GTV Function:CSY: psys_SetConditionFlybackInputPinSTB: psys_SetTVProcessorStandby


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LCD-mode (2):

• Slow-start (not necessary for LCD) can be disabled via DSS=1 (reg49, D7),this shortens HOUT start-up to 100ms (use AKB=1=off)

• SW can detect exactly when picture can be displayed:DFL4..0=01011, fast start-up is highly appreciated

• CCC-loop off (AKB=1) gives no sync-residue on RGBOUT

– Blanking-functions remains partially intact (vertical, HBL,WBF,WBR, see Notes Page below)

• If fill-in of blanking-level is required, then use AKB=0 and apply a dummy-circuit on pin BLKIN

When the black-current CCC-loop is switched off (AKB=1), the black level is determined inside the IC (fixed 1.65V). At nominal BRIghtness, the blankinglevel is 0.3V below this black. You can adapt this difference by increasing BRI, since the horizontal blanking level is NOT influenced by BRI.

Note:

With AKB=1, some black level offset may appear between R,G and BOUT, that can be slightly temperature-dependent. The artificial blanking functions are still active, but they will act differently from normal CRT operation (loop on):- the video is no longer suppressed- the brightness DC-adding is suppressed (= normal during blanking)- the signal is not pulled below black anymore

You can use BRIghtness to make the video “black” equal to the blanking level (blanking level does NOT change with brightness control).

With AKB=0 (loop on), the black level is determined by the application (pin 84: BlkIn) so internal offsets & temperature effects are eliminated. With a dummy circuit any black level can then be made and all artificial blanking functions will behave normal.

GTV Function:DSS: psys_SetSlowStartUpMode (SSD)AKB: psys_SetBlackCurrentStabilisationDFL: psys_SetFlashProtection


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LCD with TDA9178:

• TDA9178 needs SandCastle pulse for its H & V measurement windows(Falling-edge of blanking pulse must be after edge of Burst Key)

4k7

10k

+5V

1n2 680p

39k

R1 C1

R2

C2 HSYNC

74HCT04

HOUT

SandCastle

VSYNC

4k7

4k710k

200µA

TDA9178

NPN

• Example circuit to generate H, V, SandCastle

HOUT

Delay=R1*C1

Duration=R2*C2HSYNC

SandCastle

Burst Key Vertical

H-flyback pulse asin CRT-application

YOUT

Y,U,VIN

TD

A91

78

SandCastle

VSYNC

H shaper

+8V

10kHOUT

V slicerHSYNC

I2C

YsyncIN

47k

V

H

10k

10k

U,VOUT

res

Circuit = not needed for N2: generating H,V,SandC will be

integrated

Dependent on the applied LCD-scaler IC you can derive positive or negative H & V pulses.

Horizontal:Time-constant R1C1 delays the rising slope of HOUT and positions the artificial “HFLYBACK” or HSYNC pulse over the Burst-Key pulse in the SandCastle signal.The pulse duration of HSYNC is determined by R2C2.

Vertical:The vertical pulse is derived from the SandCastle (=directly coupled to the vertical counter mechanism), by slicing it at 0.8V TTL-level. The NPN transistor suppresses the H-pulses right before the slicer, but when a Vertical pulse already started, the NPN will be disabled until the end of the vertical interval (emitter of NPN lifted-up so that it can not conduct collector-current).In case the slopes of your SandCastle are too slow, you may experience HSYNCresidue in your VSYNC output ⇒ Consider adding ~ 47pF(res.).

Note:The Y,U,V inputs of UOCIII have input clamps that are active during the Burst-Key period. The TDA9178 should not modify the “black” level while input clamping is busy, therefore the falling slope of HSYNC (added into SandCastle) must be after the Burst-Key period has finished.


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Micro controller:

In/OutIn/Out

StereoStereo

VIF & SIFVIF & SIF

MonoMono



MicroMicro

File: Herc_3.ppt = Micro part, v1.6 30-09-2003 by E.Arnold


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Aux RAM4KBytes

Main RAM256 Bytes

80c51CPU

6-cycle

ProgramROM 128K

Timers+Counters

12.288 MHzDCXOOscillator

WatchDog

24.576MHzXtal

:2

To Analogue part

H,V

R,G,BOSD

FblOSD

SCAVTXT

ContrastReduction

Remote Cntrl ProcRDS

RBDS

PowerOn

Reset

Supplyguards

Character ROM12 x 9/1012 x 1312 x 1616 x 18

Matrix FLA

SH

PK26ROM 4K

FLA

SH

ProgramROM 128K

Display RAM10K (10pages)

Timing

DisplayGenerator

50/60Hz

Memory InterfaceRAM

Dou

ble

Win

dow

& P

anor

ama

YU

V-P

roce

ssin

g

In (Flash)SystemProgramming

2MHz Hs-I2C

Text/Control/Graphics µ-Controller:

SFR extensions

TPWM ADC

UART

D/A

I2C

SSD TV

I/O

Data Capture

DataDecoderCVBS

CompositeSyncInput

TimingCC

SFR

TXT

The Standard 80c51 core is extended with:

- ROM bank switching

- Watch-dog timer (generates reset when not re-loaded in time)

- Improved oscillator with amplitude stabilization

- Internal extension bus, address via Special Function Registers SFR

- Dedicated I/O ports, PWM (digital to analog), ADC (analog to digital)

- Data slicer for World System Teletext (WST), Closed Captioning (CC),Wide Screen Signaling, Video Programming System (VPS), Program Delivery Control (PDC), Video Programming via TXT (VPT) etc.

- Character generator for Teletext (row x column=25x40) and for CC/OSD (14 rowsx48columns, and for OSD up to 16 rows)

Abbreviations:

PK26 = packet 26, a TXT extension to transmit more than 127 characters

UART = Universal Asynchronous Receiver Transmitter

RDS = Radio Data System

Fbl = Fast-blank insertion of characters over video (also called InSw or VDS)


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Jump sheet micro topics:

• RAM, Flash-ROM, ISP-programming

• Power Saving Modes

• I/O, ADC, PWM, I2C, UART

• Interrupts, Timer/Counter, Watchdog

• RCP (Remote Control Pre-processor)

• Data Capture, TXT, CC, RDS, RBDS

• Display, Double-Window


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• Intel 80c51 compatible instruction set

• 6 states per Machine-Cycle with 12.288MHz ref (Xtal=24.576) gives 488ns per Machine-Cycle

• 1 to 4 Machines-Cycles per instruction

• Wake-up: Reset, Interrupt, SAD-Analogue Level

• Address Spaces: 8-Bit ‘MOV’ and 16-Bit ‘MOVX’

• UART (asynchronous serial transceiver)

80c51 Micro Core:

The most frequently used instructions require only 1 byte ROM and 488ns execution time (at 24.576MHz Xtal = 12.288 MHz internal clock).

The 8-bit MOV instruction is more code efficient, but has limited working range. The 16-bit MOVX instruction can access the full 64K RAM space within one instruction.


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TCG Power saving modes:

Function Standby Idle PowerDown Clocked circuits (Xtal always on) active active off 80c51 CPU core active off off Remote Control Pre-processor active active off Interrupts Edge-trigger Edge-trigger Level-trigger Timers / Counters active active off Watch Dog Timer active Disable by SW Disable by SW

UART, PWM’s active active off S-ADC DC compare active active active OSD & data aquisition off off off RAM contents maintained maintained Some are lost

Exit from power saving mode via:

SW resets bit STANDBY in SFR ROMBK

Interrupt clears bit IDL in SFR

PCON

Interrupt clears bit PD in SFR

PCON

Optimal power efficiency for the TV’s standby mode is achieved if software puts the micro first into STANDBY and then in IDLE / POWER-DOWN.(bit STANDBY in SFR ROMBK and IDL,WLE in SFR PCON)The watchdog timer should be disabled, before entering a sleep mode (reset bit WLE in SFR PCON).

STANDBY mode is used to handle wake-up interrupts from remote control, local keyboard SAD or timers. If no action is required, then go back to IDLE / POWERDOWN mode, else switch the TV “on” in STANDBY mode, followed by NORMAL mode.

POWERDOWN can only be used if no timer-driven background processing is needed. Since the internal clocks are stopped, it will take several milliseconds to come out of POWERDOWN. E.g. the first RC-command could be missed, but that can be solved by selecting a proper RC protocol (like RC5 : repeats each command completely, every 121ms).

IDLE mode is normally used during TV standby, since it offers immediatewake-up of the core. We advice to use the Remote Control pre-Processor to reduce the number of (false) wake-up events.



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• 12 Vectored Interrupts, 2 priority levels(a level one can interrupt a level two interrupt)

80c51 Interrupts:

- EX0- ET0- EX1- ET1- EDET- ECC- ES2- EBUSY- ET2PR- EUART- ERDS- EX2

INTerrupt 0Timer 0INTerrupt 1Timer 1DETectorCC data availableI2C transmit/receiveV-blanking period BUSY (config H/V via MMR 87FFH)

16-bit Timer 2 with 8-bit PRescalerUART transmit/receiveRD(B)S data availableINTerrupt 2

03H0BH13H1BH23H2BH33H3BH43H4BH53H5BH

SAFETY interrupt:

- Chip Temperature too high> 130ºC or > 140ºC (SFR FBH)

- 1.8V or 3.3VSTANDBY too low (SFR A1H)

- Remote Control Processor- INT0, falling-edge trigger- INT0, level sensitive

• 1V8EXT too high can be read via VSP bit SUPR

Software can give each interrupt source its own priority level. Processes that require very accurate timing can be given higher priority.

The Software Analogue to Digital converter (SAD) can be configured to trigger INT1, to bring the core out of Power Saving mode. This is useful to implement an analogue scanned local keyboard with wake-up.The Closed Captioning data acquisition is partly done in software. The acquisition of (faster) Teletext data is done by hardware.

The I2C-bus hardware is designed for a “multi-master” environment. With software it is possible to implement I2C-bus master- and even slave-modes.Via the Display Busy interrupt it is possible to synchronize e.g. display updates to the vertical scan of the picture tube, avoiding transition effects.Timer2 is a 16-bit timer with 8-bit prescaler and auto-reload. With its very long time-span (8.192s) it is ideal for software clocks.

Safety interrupt EDET signals conditions that can harm the silicon. Status can be read via bits: 1V8GUARD, 3V3GUARD, TEMP130 & TEMP140. Interrupt is cleared by writing bits to zero (=different from other interrupts).

A voltage of > 2.1V at the 1.8V inputs drastically shortens lifetime. This error condition can be read from the VSP via I2C-bus bit SUPR.


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Timer/Counters:

• Timer0 & 1 are configurable as Timers or Event Counters(16-bit counter or 8 bit with automatic reload)

• Timer mode: fXTAL= 24.576MHz

– Count rate = machine cycle = [2 x 6] / fXTAL = 0.4883µs

• Event Counter mode:– Count rate = 2 * machine cycle = 0.976µs

• Timer2 (16 bit) with (8 bit) Pre-scaler (has automatic reload) :– Interval = [TP2H * 256 + TP2L] * [TP2PR +1] * 0.4883us

• Timers remain active during STANDBY & IDLE mode

SFR registers, related to Timer 0 and 1 are:TCON 88HTMOD 89H mode selection, gatingTL0 8AH value (R/W) of Timer 0 low byteTH0 8BH idem, high byteTL1 8CH idem, low byte of Timer 1TH1 8DH idem, high byte

Timer 2 has more controls:TP2CL 9CH current value of timer, low byteTP2CH 9DH idem, high byteTP2L 91H auto-reload value, low byteTP2H 92H idem, high byteTP2PR 93H 8-bit pre-scaler valueTP2CRL 94H status register


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• Reset the micro-controller after reasonable time-outWatchDog interval = [256-WDT]*216*488.3ns (= 32ms .. 8.2s)

• Activate by setting bit WLE in Power Control SFR : PCON

• Safe disable by loading the value 55H in WatchDog Key SFR WDTKEY

• In some modes too early wake-up must be prevented.Advice: disable the Watchdog during

– IDLE or POWERDOWN mode– ISP (otherwise: risk of incomplete programmed samples)

Watchdog Timer:


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• 256 Bytes Main SRAM (80c51 ‘MOV’ Instruction)

• 4 KBytes Auxiliary SRAM (80c51 ‘MOVX’ Instruction)

• 10 KBytes of Display SRAM (Using SFR TXT14,15)

• SRAM for 64 Dynamic Redefinable Chars (animation, morphing)

• 16x12-Bit CLUT Memory (mapped as registers)

Embedded RAM Memories:


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• Different addressing method for upper 128 Bytesaccesses RAM or SFR

7FH

Lower 128 Byte RAMDirect & Indirect

addressing

00H

FFH

128B RAMonly Indirect

addressing

80H

128B SFRonly Direct addressing

00..07H Register-Bank008..0FH Register-Bank110..17H Register-Bank218..1FH Register-Bank3

Bit-addressablespace

20..2FH

RAM30..7FHR7R6R5R4R3R2R1R0

Special Function Registers= extension method for 80c51

Register-Bankselect bits in PSW

R-Bank

Internal RAM: “Idata”

The RAM between 30H and FFH is not allocated for any special area or functions . The Program Status Word is accessible as an SFR PSW , located at address D0H.

Examples of addressing modes are:

Mnemonic Instruction Instruction bytes

Oscillator periods

Indirect : XRL A,@Ri XOR indirect RAM to Accu 1 6 MOV direct,@Ri Move indirect RAM to direct byte 2 12 MOV @Ri,#data Move immediate data to indirect RAM 2 6 Direct : MOV direct,A Move Accu to direct byte 2 6 ANL direct,#data AND immediate data to direct byte 3 12 MOV direct,direct Move direct byte to direct byte 3 12


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Auxiliary RAM: “Xdata”

Address Area Size FFFFH 9100H - ..64K

90FFH 8800H DRC’s 2.25K

87FFH 87E0H Display Control 32B

871FH 8700H CLUT 0.25K

84FFH 8000H CC Data 1.25K

74FFH 7000H RD(B)S Data 1.25K

6FFFH

2000H

Display RAM TXT/CC/RDS/RDBS

20K

1FFFH 0000H Auxilary RAM 4/8K

• On-board “external” RAM, called Auxiliary Xdata is accessed via 8051-instruction “MOVX”

• Physical RAM shared for Teletext, Closed Caption & RDS/RBDS

– Capture : store in RAM– Display : read & convert to RGB

• Auxiliary RAM (except Display RAM) is– Not initialised at Power-On-Reset– Maintained in Power Saving modes

All Xdata – except the Display-RAM – can be used to maintain data during standby-mode of the TV (even when a short reset occurs). Please note that this Xdata is NOT cleared, so software must do that after reset.


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Display RAM:

• At PowerOnReset automatically initialised to 20H (= “space” char.)

• Contents lost during Power Saving modes (SW use page-clearing)

• Same physical RAM are is used for :RDS/RBDS when register TXT27.RDS_ON=1or for CC when TXT21.CC=1, else for Teletext

• Teletext page area = 10K


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Display RAM Page Clearing:

• Auto-clear at POR ⇒ TXT13.PAGE CLEARING=1 signals:“busy clearing”

• SW can clear a section ⇒ set TXT9.CLEAR MEMORY=1,pointed by TXT15.BLOCK<3:0>, TXT15.MICRO_BANK<3:0> ,then set TXT13.PAGE CLEARING=1 and HW does the clearing

• Data Capture will clear a page when:- a NEW page header is acquired- the erase bit C4 is set

While the hardware is busy clearing a RAM-page, it should not be accessed. SW should wait until hardware resets bit “PageClearing-busy”.


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• 128 ( / 256) Kbytes Program ROMplus 4KByte of Packet X-26 ROM (Flash module 1)( + Test ROM + redundancy )

• 14K x 16 bits Character Pixel ROM (Flash module 2)

plus 2K look-up tables( + redundancy )

• Programmable ROM:- industrially via Parallel programming (14 pins needed)

- via serial ISP (In-System-Programming) (High-speed I2C-bus)

Embedded Flash-ROM:

Flash module 1 holds:- Program ROM = 6 large sectors of 128 pages of 256 bytes- Packet 26 ROM = 1 small sector of 16 pages of 256 bytes- Test ROM = 1 small sector

Flash module 2 holds:- Character ROM = 1 large sector- Lookup tables for efficient storage of character sets

For Parallel programming a page is accessed as 128 words of 16-bit. For ISP programming via I2C-bus as 256 words of 8-bit (= easier because I2C-bus is byte-oriented).

The number of character fonts that can be stored in Character ROM, depends on the Font sizes used by the software.

The 14K x 16 bit character Pixel ROM allows :- in 12x10 matrix (or 12x9) storage of ??? character fonts- in 12x16 matrix (or 12x13) storage of ??? characters.

With DRCS the number of characters can be further extended, limited only by the available program ROM.

Fore-ground and back-ground can both be selected independently from two palettes of 8 colours out of 4096 possible colours (4K).

Check ROM size: 4 base sets and/or 4 twisted sets.

No. of fonts??


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• Extension above 64KB byROM-bank switching (via SFR,supported by Keil C51 compiler)

7FFFH

Common 32KB

0000H

FFFFH

Upper 32KB

8000H

Sta

ndar

d 80

c51

= 64

KB

64K

Bank 0

32K

96K

Bank 1

64K

128K

Bank 2

96K

160K

Bank 3

128K

192K

Bank 4

160K

ROMBK2/1/0

Program-ROM bank switching:

ROMBK<2:0> 0 to 32K 32K to 64K 000 Common Bank0 001 Common Bank1 010 Common Bank2 011 Common Bank3 res. 100 Common Bank4 res. 101 Reserved Reserved 110 Reserved Reserved 111 Reserved Reserved

The ROM bank switching is supported by several commercial compilers. A future extension beyond 128 or 192K is possible. The SFR ROMBK is located at address FBH.


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I2C-bus:

• The HardWare I2C-bus (Master/Slave-Transmitter/Receiver) runs at– Normal/Fast mode @ 12kHz .. 384kHz– High speed mode @ 128kHz .. 2.084MHz

• I2C can be disconnected from outside-world. Internally it connects:– TextControlGraphics µ-processor– TV processor– Digital Sound processor– ISP (In-circuit Serial Programming) of FLASH memory blocks

I2Cinterface HW-I2C

SCL

SDA10E

10E

470E

470E

+3.3V

Other I2C slaves

PC

Eeprom

3k3

3k3

470E470E

WISP,WIC32

TV

cha

ssis

FLASHISP

TV

proc

esso

r

SSD

80c5

1

The duty cycle of the I2C-bus SCL clock output can be selected according “STANDARD” of “FAST” mode by bit F/S in SFR FSBIR.

The maximum clock speed is set:- in F/S mode via SFR FSBIR<4:0>- in Hs mode via SFR HSBIR<4:0>

GTV Function: ri2c_SetRuntimeSpeed


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– Factory alignment data can be copied from HW to SW-bus, via a “software-bridge” (= µC acts as I2C-slave on HW-bus and as I2C-Master on SW-bus)

– µC-HW can be given any I2C Slave-address (but only ONE)

• For max. safety of alignment-data,put Eeprom on a “split-bus”, usingsoftware I2C (on any pair of free I/O pins)

– Keep this safety-bus very short

Split I2C-bus:

I2Cinterface HW-I2C

SCL

SDA10E

10E

470E

470E

+3.3V

Other I2C slaves

PC

Eeprom

3k3

3k3

3k3

3k3

SW-I2C

• Do not connect HW-I2C-bus permanently to other I/O pins: (like SW-I2C)

– No extra safety anymore (then better connect all to only HW-I2C-bus)

– Reset-polarity of most I/O pins (=low) may block HW-I2C communication(exception: special pins ??98 & 99 are high during reset)

TV

cha

ssis

FLASHISP

TV

proc

esso

r

SSD

80c5

1

The I2C-bus lines SDA & SCL will normally be quite long in a TV chassis.Series resistors must be added to protect the connected IC’s against energy pick-up, during flash-over of the picture tube or static discharges.

A split-bus with very short connection between µC and Eeprom minimizes the chance that alignment data is destroyed by high-energy spikes.

GTV Function:LibCoMa switch RI2C_SPLIT_BUSri2c_2ndBusAddresses


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• Initialize internal µP registers

• Disconnect external I2C-bus pins

• Initialize TVP + SSD (via HW-I2C-bus peripheral)

• Connect external I2C-bus pins

• Enable Remote Control Processor (RCP)

• Initialize other I2C-bus slave devices

I2C start-up procedure:

The first action after RESET should always be the definition of I/O pins like Power-On/Off, Volume and Mute.

The micro processor communicates with the TV processor part via a standard I2C-bus protocol (Slave WRITE address 8AH). To eliminate the risk that other I2C-bus devices can disturb the communication to the TV processor part, we advice to disconnect the external I2C-bus pins during each of these transmissions.

As start-up code we advice to use the BOOT code, supplied by Philips Semiconductors. This will take care of all necessary initializations.

Disconnect external I2C pins by setting TXT21.bit1=0 (SFR B5H).


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In System Programming:

• Why ISP ?– Allow very late (re-) programming during TV-production– Easy software upgrade, e.g. after-sales-service – For true EMC tests, trial-runs etc.

• Why ISP via I2C-bus ?– ZERO additional costs in TV chassis– Easy interface to a Personal Computer,

programming SW called “WISP”

• Several I2C-bus speed-modes:– Normal (< 100kHz, rugged communication protocol)

– Fast (< 400kHz, careful with capacitive bus-load)

– High-speed (up to 2 MHz, adapted I2C-protocol)

Reload value HSBIR<4:0>

Mod_Clock 12.288MHz

Div

0 Not allowed 3 1 2.048MHz 6 2 1.365MHz 9 3 1.024MHz 12 4 819kHz 15 5 688kHz 18 6 585kHz 21 : : :

31 128kHz 96

ISP programming:

During production of a TV chassis, the whole Flash-ROM can be used for TV-Factory-SW. When the final destination is known, ISP can re-program the ROM with the End-Customer-SW. This allows maximum flexibility.

Although ISP-programming takes < 10 seconds, the process can be speed-up by programming the non-variable part (Char, Pk26) before the IC is soldered-in (e.g. as part of a quality-check). Later during TV production the remaining blocks can be programmed via ISP.

Other programming methods:

In our Philips IC-Factory we can use other fast programming techniques. These methods can not be used in the end-application (need access to many pins & special pulse-sequences + levels).

Exi

stin

g si

licon

+ S

W:

limite

d to

1.2

MH

z??


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Hs-I2Cinterface

Max.2.048MHz

I2C SCL

SDA10E

10E

470E470E3k

3

3k3

+3.3VOtherslaves

10E

10E

+3.3V

220E

220E

HsLowIN,MAX = 0.8VHighIN,MIN = 2.0V

LowOUT,MAX = 0.4VHighOUT,MIN = VddE - 0.4V

WISP-SW & I2C programmer:

• Philips-ISP-software “WISP” drives several PC-to-I2C-bus interfaces:

– “Single-Master” or “TraCII”, via Centronics parallel port (Normal / Fast mode)

– “TraCII-XL”, via rugged USB-port (Normal / FAST / High-speed mode)

USB

Programmer TV chassis

PC FLASH

80c5

1

ISP

Pic

asso

/H

ercu

les

WISP

• Attention points for Hs-I2C mode: (MAX speed = 2.048MHz)

– Minimize capacitive bus-load & cross-talk in chassis layout

– Avoid collision with non-Hs-slaves: use high series resistor & Programmer’s impedance-switch to overrule non-Hs-compliant devices

ISP can be done at any I2C-bus speed (Normal / Fast / Hs-mode).

High-speed-mode ISP programming:

The series resistors to non-Hs-I2C-mode-compliant slave devices can be chosen higher, just enough to receive I2C data from the bus-master.

During Hs-mode the Programmer-interface can set extra low driving impedance (switch), so that even when a slave tries to pull-down SDA/SCL, it can not disturb the Hs-communication.


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In System Programming:

Open Flash-lock

Power-On-Reset

ISP programming

Release I2C-busShut down all functions

Write Flash

Make sure I2C is not blockedDisable what you can, for minimalheat dissipation

Hard-reset to resume normal mode

Write pages of 256 bytes

Read CRC checksum

Erase Flash Erase one or more sectors at a time

Verify Flasherror

OK

Use “WISP” Philips provided SW tool

• ISP can not read-back the ROM, just a CRC-checksum (“MISR”)

Always check the internal I2C-bus is coupled & not blocked, prior to opening the Flash-lock. While the flash-lock is open, the 8051 core is forced to execute “NOP” instructions (= SW effectively standing still)

“MISR” = Multiple Input Selection Register, a sort of checksum calculation


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I2C-addresses:

• TV-Processor = 10001010B=8AH (=during I2C-Write; 8BH during Read)

or alternative = 10001110B=8EH (if pin SVM not used & pulled high)

• Micro ControllerRESERVED = 01100110B=66H (67H during I2C-Read)

– Reserved in Philips’ I2C address allocation– Free programmable by SW in SFR S1CON. – Hardware can only be given ONE slave address– Used by “Work-Bench” I2C-bus software

• StereoSoundDecoder = 10110000B=B0H (B1H during I2C-Read)

(alternative not yet implemented:10110010B=B2H (configured via micro controller)

• Flash-ISPENABLED = 01010010B=52H (53H during I2C-Read)


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• Universal AsynchronousReceiver / Transmitter controlled by SFR’s: PCON, S0CON, S0BUF

Full duplex UART:

UART Mode Characteristic Baud rate =

0 Serial 8-bit (LSB first) in or out via RxD, TxD outputs the shift clock

1/6 of µC clock (12.288MHz)

1 10-bit transmitted by TxD or received by RxD: start-bit=0, 8 data-bits (LSB first), stop-bit=1 Timer1 overflow rate

2 11-bit transmitted by TxD or received by RxD: start-bit=0, 8 data-bits (LSB first), a 9th data-bit, stop-bit=1

1/32 or 1/64 of µC clock

3 Same as Mode-2 Timer1 overflow rate

• Mode 2+3 suitable for multi-processor communications:9th data-bit can generate an interrupt

80c51CPU

TPWM ADC

UART

D/A

I2C

SSD TV

I/O

ROM

RAM

Timers+Counters

SFR extensions

TXD

RX

D


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• RC-Processor = hardware to reduce the number ofwake-up’s for the 80C51 core (from sleep mode)

• RCP = intelligent hardware filter to eliminate false bits,Software handles the RC protocol

• Most RC protocols use “pulse-distance” modulation with a fixed “mark-to-space” ratio for “1” and “0”

• Most protocols have a special start-bit timing:- RC-5 use bi-phase modulation, no real start-bit- RC-6 is 2x faster than RC-5, with start-bit

Remote Control Processor (RCP):

UOC-III has special low-power circuitry to achieve a low-power sleep-mode. To limit unnecessary wake-up’s on false infra-red RC-pulses, the RCP acts as a hardware filter.

All infra-red RC-pulses are blocked until the first GOOD pulse (bit) is measured.

Bit-decoding is done by software and the filters are programmable over a wide range. Therefore this RCP is compliant with all known commercial infra-red RC-protocols.

GTV Function:rbsc_GetRemoteKey LibCoMa settings for RC5 and NEC protocol. Also any other High/Low time modulated protocol can be configured using LibCoMa(RBSC_REMOTECONTROL_RCP_XXX)


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Sta

rtbi

t=1

Not

-enl

arge

dbit=

1/0

Tog

gleb

it=1/

0

S4

S3

S2

S1

S0

5 S

yste

mad

dres

sbi

ts

C4

C3

C2

C1

C0

6 C

ontro

lco

de bits

C5

1 0 0 0 01 1 0 1 1 0 01 11

14 periods of 2tp =14x2x889µs = 24.89ms,

Command repetition =64x2tp= 113.78ms

Min

imal

Dat

a-cl

ean

3tp

= 1.

5 x

bitti

me

= LOW period timer A

= HIGH period timer B

Interrupt

Example:command 53DECin system 0

Japan code (at INT pin) :Start-bit

4tp8tp 3tptp

0 1

tp tp

0 0 1 1 0 0 1 0 0

RC5 bi-phase (at INT pin) :


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Startpoint = RC-input pinINT goes low

Phase 1:IF INT goes high again before Cntr has reached ALTHEN the LOW period is too short => exitELSE count µC clocks in Cntr until it reaches AL, then reset Cntr

Phase 2:IF INT does NOT go high before Cntr reaches AH THEN the LOW period is too long => exitELSE copy Cntr value into result register RA and reset Cntr

Phase 3:IF INT goes low again before Cntr has reached BLTHEN the HIGH period is too short => exitELSE count µC clocks in Cntr until it reaches BL, then reset Cntr

Phase 4:IF INT does NOT go low before Cntr reaches BH THEN the HIGH period is too long => exitELSE copy Cntr value into result register RB and reset Cntr

generate an interrupt to wake the microif micro can react within AL, then interrupt-latency = zero

LowPeriod

AL

AH

RA

SW programs limiting values:AL = minimal LOW time 75%AH = maximal LOW time minus AL 125%BL = minimal HIGH time 75%BH = maximal HIGH time minus BL 125%

End results in output registers:RA = LOW time minus ALRB = HIGH time minus BL

HighPeriod

BL

BH

RB

INTA B

AL= 0.75 x tSHORTEST AH= 1.25 x tLONGEST - AL

RCP-Method (counter & comparator) :


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24.576MHz

CDIV = ClockDIViderDRCP= Disable RC Proc.NFP = Not First PulseNGP = No Good Pulse

Spi

ke fi

lter PosEdge

NegEdge

Counter Cntr

state

Comparator <

Write-only

Read-only

Int0

Pre-condition: SW sets NGP:=0; NFP:=0

CASE State OF1: IF (PosEdge AND Cntr<AL)

THEN State:=5 Low pulse too shortELSE IF PosEdge

THEN Cntr:=0; State:=22: IF NOT(Cntr<AH)

THEN State:=5 Low pulse too longELSE IF PosEdge

THEN RA:=Cntr; Cntr:=0; State:=33: IF (NegEdge AND Cntr<BL)

THEN State:=5 High pulse too shortELSE IF NegEdge

THEN Cntr:=0; State:=44: IF NOT(Cntr<BH)

THEN RB:=Cntr; State:=5 High pulse too longELSE IF NegEdge

THEN RB:=Cntr; NFP:=1; State:=65: IF (NFP=1)

THEN NGP:=1; Error after first pulseState:=6

6: Cntr:=0; State:=1 IF (NFP=1) stay idle @ error during FIRST pulseTHEN Trigger INT0

ENDCASE

1

2

3

4

Logi

c

NFP,NGP,DRCP

Read/write

• NO interrupt latency ⇐ Comparator canbe changed WHILE counting (modify timing for next bit, after measuring previous)

• Suitable to measure 1.5 bit “Data-Clean” time after a string (added: “RB:=Cntr”, State 4)

1 (CDIV+1)

AL

CDIV

AH

BLBH

RARB

DA

T

Mux

SF

R

RCP-Implementation:

12.288MHz:2

DRCP

CDIV

Int0

pin

Edg

e/Le

vel

TCON

EX0

Timer /Counter0

ET0

To check that a complete RC message was received, SW should demand a “Data-Clean” time of at least 1.5x the longest bit-time. This prevents false decoding of RC-=protocols that have similar timing, but more bits per message.

Remark:For correct synchronicity of data transfer, some registers settings become effective only after two registers are written. E.g. register RCP1 is clocked-through only after RCP2 is written (see datasheet).Interrupt 0 must be enabled, edge-triggered (SFR TCON); DRCP=0, EA=1.

Warning: Never set RCP-interrupt-0 as low-level-sensitive. If any process sets EA=0 while the low-level trigger towards Int0 has passed, the RCP interrupts will be missed. ⇒ Especially if SW has missed an interrupt that leaves NGP=1 then the RCP waits until SW re-initialises: NFP,NGP=0,0.


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• World System Teletext- 625 / 525 WST, level 1.5 teletext, VPS, WSS625- 0 and 10 page devices available- Processing in hardware

• Closed Caption- Support complete enhanced character set- Supports eXtended Data Services (XDS)- Supports Violence Chip transmissions- Processing in software

Data capture:

The Video-recorder Programming System (VPS) and Wide Screen Signaling (WSS) bits (different data rates) can be captured by the Teletext data capture hardware. WSS is used for aspect-ratio switching of the displayed picture (16:9, letterbox). When WSS is not decoded, you can assume 4:3 aspect ratio (or some other user preference).

Closed Captioning data is transmitted at a much lower data rate than teletext (only 2 bytes in line 21 at 525 or 25 at 625 line transmissions). CC data processing is simply done in software during the Vertical Blanking Interval (VBI).

Automatic Channel Installation (ACI) data is transmitted on special teletext pages, not accessible by the TV user. They contain machine-readable data, with station names and transmitter frequencies.

When ACI is transmitted on a network, installation of a new TV receiver becomes easy. Software first starts searching for an channel with ACI information (usually on a low RF frequency). Once found, it simply stores all channel frequencies plus station names in EEPROM.This could be done in just a few seconds.


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• OSD-Clock = Line locked PLL (coupled to Hsync PHI-1/-2)

• Two modes: CC or Teletext (using TXT21)

- MMRs (Memory Mapped Registers) for CC control & status- SFRs (Special Function Registers) for TXT control & status

• 2-page display (two panels side-by-side: e.g: TXT/TXT or TXT/CC)

Double Window mode (50% compressed video + a TXT/CC panel)

• Scan Velocity Modulation (separate for video and for TXT/CC)

• Contrast reduction of defined areas (both TXT & CC mode)

Display Features (1):

The OSD is internally inserted in the RGB path of the video processor.It automatically tracks to the brightness setting of the main picture, but it is not affected by saturation or contrast control. For optimal readability, the OSD contrast can be given an offset.

In general the OSD will use the CC-type of display, with its extra features. The TXT type of display is maintained for easier display of Teletext pages. Display mode TXT and CC can not be used simultaneous within ONE page(but is possible in 2-page mode).

Part of the CC data acquisition is done interrupt-driven, in software. For code efficiency most CC control registers are “memory-mapped”. Since TXT data acquisition is done by hardware, the TXT control is implemented through “Special Function Registers”.


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• Teletext mode: 40 Columns x 25 RowsOSD / CC: up to 48 Columns x 16 Rows

• Character Matrix (Pixels x Lines) :12 x 9/10, 12x13, 12x16 and 16x16/18Smoothing for double-height/width characters

•• FringingFringing (shadow) in both TXT and CC Display Modes

• Italics, Under-line, Over-line and Scrollingavailable in CC Display Mode


The number of TV scan lines per display row can be set to 10,13,16 or 18 and is independent of the character size being used.

In 525 line display mode (60Hz) the value of 10 is automatically changed into 9 lines per row.

According CC standard EIA608B max. 80% of visible screen may be used for CC. At 60Hz with 525 lines this is: [525/2 - 23] * 0.8 = 192 lines. Using 12x13 character fonts this allows max. 14 lines of CC.


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• 8 Foreground plus 8 Background Colours,selectable from a palette of 4096

• Serial attributes: Set At or After, occupy a space

• Parallel attributes: Set At, no space introduced

• 64 DRCs (Dynamically Re-definable Characters)

• Overlap 2 DRCs to form a 4 - colour Character(32 on the screen at any one time)


DRCs are particularly useful to display dynamic effects, like shape-shifting icons.

Normally a character can have only a foreground and a background colour. If more than these two colours are needed in a special character, two DRCs can be overlapped to have four colours within one character. This is only possible for 12x13, 12x16, 16x16 or 16x18 characters.


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16

12

Compose a 24 x 16 character from two12 x 16 characters

12

• Features like fringing are compatible

10

12

Compose a 24 x 20 character from four12 x 10 characters

12

10

Joined Characters:

With joined characters it is possible to display detailed symbolic languages, like e.g. Kanji characters.


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Double height / width:

• CC Mode Display example

Normal height & width

Double width

Double height

Double height &double width

Settings for this CC example:

1. Set SFRsTXT1 := 0x20; ⇒ TXT Acq. off, avoid write accesses to blocks 0 + 1TXT21 := 0x51; ⇒ Display lines per char = 13 / Set char. matrix =

12x13 / Configure display to CC mode TXT18 := 0x83; ⇒ National Option Table = 8 / Set Basic Char Set = 3TXT19 := 0x83; ⇒ Enable Twist char. set / Twist Char Set = 3

2. Set OSD register (MMRs)DISCON (X:0x87F0) = 0x03; ⇒ Set screen colour (0: value address of

CLUT) / Mixed video modeTEXTPV (X:0x87F1) = 0x20; ⇒ Set V/H sync polarity / Vertical offsetFRINGC (X:0x87F3) = 0x0F; ⇒ Set fringe colour (0: value address of

CLUT) / Set fringe (N/E/S/W)TEXTPH (X:0x87F2) = 0x0B; ⇒ Set Fine H-offset / Set Text area startTAE (X:0x87F4) = 0x31; ⇒ Display width 36 char (0Bh + 36d)RGBBR (X:0x87F7) = 0x08; ⇒ Set RGB Brightness=8 (medium)OSDSTATUS(X:0x87F8) = 0x00; ⇒ No scroll area visibleHDELAY (X:0x87FC) = 0x02; ⇒ H-sync. DelayOSDCONF (X:0x87FF) = 0x28; ⇒ Config CC & fast blank adjusted

3. Set Colour Look Up Table (CLUT)4. Set CC Display Map: start positions of each line & display data area


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Feature TXT CC Boxes serial serial Horizontal size 1x / 2x / 4x serial 1x / 2x serial Vertical size 1x / 2x serial, 4x global 1x / 2x serial Smoothing double-size yes yes Flash / Scroll / Cursor serial / no / yes serial / yes / yes Italic / Underline / Overline - / - / - • / • / • serial Foreground colours 8 serial 8 serial + 8 parallel Background colours 8 serial 16 serial Soft colours (CLUT) 16 from 4096 16 from 4096 Screen colours 16 global 16 global Fringe, colours N + S + E + W, 16 global N + S + E + W, 16 serial Contrast reduction local yes yes DRCS 64 global 64 global Character matrix HxV 12x 9/10/13/16 12x 9/10/13/16/18,

16x16/18 Rows x Columns 25 x 40 16 x 48 Displayable characters 1000 624 4-colour characters 32 32

Features of TXT and CC:

All display features, summarized in one table.


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What is TeleteXT:

• TXT is a digital addition to analogue TV signals, that contains textual & graphical information

Skip section about TXT


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Data Capture 625WST:

• 625 line sync, 64.00µs line period, 6.9375MHz data bit rate

• Auto-detect & forced acquisition modes on lines 6..22 (VBI), or full field

• 45 bytes/line, 40 bytes of which are stored in rows 0..23 of page memory

• Capable of acquiring packets X/0, X/1-24, X/26/X, X/27/0, 8/30/X

Data Capture 525WST:• 525 line sync, 63.56µs line period, 5.7272MHz data bit rate

• Auto-detect & forced acquisition modes on lines 7..17 (VBI), or full field

• 37 bytes/line, 32 bytes of which are stored in rows 0-23 of page memory

• Capable of acquiring packets X/0/0, X/0/1-24, X/T/1-24, X/0/26/X, X/T/26/X, X/0/27/0 4/0/30/X and 4/T/30/X.


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Data Capture PAL-N:

• 625 line sync, 64.00µs line period, 5.7272MHz data bit rate

• As 525WST, except no auto-detect mode

Data Capture VPS:• Auto-detect of VPS data (bit rate 5MHz, data rate 2.5MHz) on field 0, line 16

(625 line sync, 64µs period)

• 28 data bits (bi-phase decoded) stored as 7x5-bit words (4 data bits plus bi-phase error flag) in row 25 of page memory


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Data Capture WSS:

• Acquisition of WSS data (bit rate 5MHz, data rate 5/6MHz =833kHz)on field 0, line 16 (625 line sync, 64µs period)

• 14 data bits (bi-phase decoded) stored with bi-phase error flags inthree registers: wss1<4:0>, wss2<4:0>, wss3<7:0>

Data Capture US-CC:• Acquisition of US-CC data (bit rate 32/63.56 µs=503kHz) on a single line from

lines 1..32 (525 line sync, 63.56µs period), in either or both fields (default line 21)

• Stored as transmitted (i.e. odd parity encoded) in two registers,ccdata1<7:0> and ccdata2<7:0>


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TXT levels:

• Level 1 Teletext = textual + graphical information– Alpha-mosaic characters– Spacing attributes– Fixed colour palette– 25 Rows x 40 Columns

• Level 1.5– Extended character range

• Level 2.5 (hardly transmitted → not in Hercules)

– Extended language range– Non-spacing attributes – Increased colour palette with re-definable colours– Enhanced graphics, e.g. DRCs + side panels

P100 Title text and other info 14:05:00This is row 1

This is a demonstration page

This is row 23Next Page Prev Page Other Page Index


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TXT transmission (1):

• During the Vertical Blanking Interval (VBI), off-screen– VBI = the first few (~25) lines of the transmitted TV picture, which are not

displayed on the screen (on lines 6..22 or 318..335)

• “Full Field” not supported (instead of picture, professional use only)

VBI

Visible TV picture

Field fly-back(retrace)


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• One packet (45 bytes = 360 bits) per TV line, each containing:the magazine & row of the display, the data and ‘preamble’

• Packets are gathered together to form a page of Teletext

• Odd-parity encoding for displayable information

• Hamming 8:4 encoding for Important control or address info


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P100 Title text and other info 14:05:00This is row 1

Packets 0..24 are displayable andtransmitted as 7-bit ASCII values

This is row 23Next Page Prev Page Other Page Index

Page header (Packet 0)

Page body (Packets 1..23)

Page navigation (Packet 24)

X/25 rarely transmitted, not decodedX/26 / 0..15 special charactersX/27 / 0..15 Fastext linksX/28 / 0..15 not decoded

Page related Extension Packetsfor Level 1.5 (“Ghost-Rows”)


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TXT Page Header Packet 0:

• First 5 bytes = ‘preamble’ (used by TXT decoding hardware)

Bytes 2 1 2 8 32

Contents Run -In Framing

Code Mag & Pkt No.

Page No., Subcode & Control bits Displayable Data

Display Preamble Teletext 100 Jul 30 13:05/22

• Columns 0..7 contain 8 bytes of attributes (not directly displayed):- Magazine 0..7 (Displayed as 1..8)- Page 0..0xFF (Normally 0..99 BCD, but also HEX machine readable)

- Subcode 0..0x3F7F (Usually only BCD values 0..0x79 used)

- Page attributes: Subtitle / NewsFlash / Erase- / Update-Page / / Interrupted-Sequence / Serial- / Parallel-Transmission // Inhibit-Display / Language-Control / Suppress Header

• Columns 8..31 contain 24 bytes of header information (broadcaster, page number, date etc.)

• Columns 32..39 normally contain the time (HH:MM:SS in 8 bytes)


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TXT Body Packets 1..23:

• Packet number 1..23 corresponds to display row 1..23

• 40 bytes displayable text / graphics (some may be invisible control characters)

• Missing packets are displayed as blanks

• Text transmitted as ASCII values

• Serial (spacing) attributes: Foreground / background colour / Boxing / Text size (Double height/width/size) / Flashing / Conceal / Text- / Block-graphics

Bytes 5 40

Contents Preamble Displayable Data


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TXT Navigation Packet 24:

• Transmission = optional; only displayed with Fastext decoding,giving visual feedback on the function of the colour keys

• 40 bytes displayable text / graphics (some may be invisible control characters)

• Without Fastext, row 24 can be used for alternative page navigation (e.g. “Favourite Pages” mode)

Bytes 5 40

Contents Preamble Displayable Data


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TXT extension Packets:

• These packets are not directly displayed - but might have an effect on the display or help navigating around a database of pages

• For Level 1.5: - Packet X/26 (Accented characters)

- Packet X/27 (Fastext links)

- Packet 8/30 (Program name)

• Other packets may be included in the transmission to support more complex Teletext standards like Level 2.5 (not included in Hercules)

• Downwards compatibility, e.g. :Older decoders that can not decode packet 26 information, will display the normal body packet information: e.g. ‘a’ instead of ‘ã’


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TXT Packet 26:

• A Packet 26 can overwrite a position with a special character. E.g. symbols or characters with diacritical marks (á, ç, ê, ï, ø …),selected from character codes > 7FH (non-ASCII)

Bytes 5 1 39

Contents Preamble Designation Code (8:4 Hamming)

13 “Triplets” of Data (24:18 Hamming encoded)

• Triplets: - Address field (6 bits): 0..39=Column, 40..63=Row

- Mode field (5 bits): effect depends on row/column address- Data field (7 bits)

Examples: Row address group & Mode 00100B : “Set Active Position”Column address group & Mode 01111B :“Character from the G2 set”

• Max.16 Packet 26’s per display page (=208 triplets), using the “designation code” (= data byte used as Packet 26 address extender)


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TXT Packet 27:

• Defines the page that the Fastext colour keys should access:– Links 0..3 correspond to RedRed, GreenGreen, YellowYellow and CyanCyan– Link 4 is the ‘pre-capture’ link (“start-page” or “Magenta”, usually ignored)

– Link 5 is used for the Index (White) key

• Link Control byte can disable some or all of the links

• Transmitted using 8:4 Hamming encoding

Bytes 5 1 6 x 6 1 2

Contents Preamble DC Links 0..5 Link Control

Cyclic Redundancy

Check

Link N

1 1 1 1 1 1 Page

Units Page Tens S1 S2 +

M1 S3 S4 + M2&M3


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TXT Packet 8/30:

• Special packet, not connected to a specific page - only Magazine 8• Displayable Data = string to identify broadcaster or programme

Bytes 5 1 19 20

Contents Preamble DC Service Data Displayable Data

• Transmitted in 2 formats:– Format 1: (DC=0 or 1), Service Data includes:

• Initial display page number• Programme identification• Universal Time information• Broadcasting network identification

– Format 2: (DC=2 or 3), Service Data includes:• Initial display page number• Programme identification• PDC Information (Programme Delivery Control)


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Elements of a MagazineElements of a Magazine

MIP• Magazine Inventory Page• Page MFD• Identifies page function

and number of sub-pages


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Elements of the ServiceElements of the Service


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Packet Transmission:

• Teletext packets are transmitted in the order:– Packet 0 Header– Packet 27 Fastext links– Packet 28 Not decoded– Packet 26 Overwrite special characters– Packets 1..24 Body of a page

• Packets 1..24 may be transmitted in any order and multiple times per page (a method most often used for subtitle pages)

• Page is opened: when a header for a particular page arrivesPage is closed: only when another header packet arrives

(in parallel mode: when page-header in same Magazine arrives)


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Serial / Parallel Transmissions:• Serial Page Transmission: in a loop of page 100..899

– Individual page transmission time = short, but long cycle time

• Parallel Page Transmission: Per magazine, loop page 0..99– Individual page transmission time = long, but apparent short cycle time

Display rolling Headers:• While searching a page, show all appropriate incoming Headers

– Serial Transmission:• All pages except those with attribute “interrupted sequence”

(used by pages that are transmitted frequently & thereforeout-of-sequence so that they are quickly accessible)

– Parallel Transmission:• All pages in the same magazine as the one being searched for except

those with attribute “interrupted sequence”


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Teletext Time:

• Last 8 bytes of header packet 0, normally used to transmit the current time. Format HH:MM:SS where:

– Hours (12 or 24 hours clock):Minutes:Seconds– The separator “:” can be any character– Time field occasionally used to display rolling messages

• Serial transmissions:– Can be obtained from any page header

• Parallel transmissions:– Only from page headers in same magazine as current display page.

Time may vary between magazines, as different magazines may be provided by different sources (National / Local)


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Page Numbering:

• BCD page numbers (0..9) normally used for display pages• Hexadecimal pages reserved for transmitting special data

– Some transmissions use hexadecimal pages for interactive quizzes.These are accessed using the Fastext colour key links

• A “page” can consist of more than one display page = “subcodes”

Page Subcodes:• All pages have a subcode 0..3F7FH (no subcode uses value 0)

• BCD subcode numbers are used for displayable sub-pages• Subcodes 0..79H can be stored individually by page gathering

applications such as Multi Page Teletext• Subcodes > 79H will overwrite subcode 0 (according WST Teletext standard)


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TOP Transmission:• Table Of Pages= alternative to Fastext (Germany, Austria, Australia …)

• Broadcaster gathers related pages into:– Blocks: could be a subjects such as News or Sport– Groups: could be Local News, National News and Financial News

or Football, Tennis and Golf

• Block + group pages have names, transmitted on Additional Information Table pages (AITs, whose HEX page numbers are in BTT info)

• Block + group info transmitted in Basic Top Table (BTT, page 1F0H)

– BTT is used to pre-capture certain pages, for fast navigation – Navigation in a TOP transmission is done by TXT application SW

Row 24 should show: next / previous page, next block, next group

• To improve TOP navigation, broadcasters can transmit a “Hitlist”in the BTT, to be compiled & displayed by TXT application SW

E.g: List of today’s most interesting pages → internet style “What’s new”


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What is Closed Captioning:

• CC is a digital addition to analogue TV signals, that contains textual information, relevant to the TV signal

Skip section about CC


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Line 21 Services:

• Transmitted like TXT (much lower data rate) , only 2 bytes per field (odd parity):

– Line 21 for 525 line transmissions = Closed Captions

– Line 25 for 625 line transmissions = Video Captions

• Multiple streams for different languages:– CC1..CC4 = 4 streams of Closed Captions for the hearing impaired

– T1..T4 = 4 streams of Textual info

– XDS = 1 stream of transmission related info (( eXtended Data Services includes “Content Advisory info”, often called “Vchip”)

• CC displayed on any row 1..15 ( Paint On / Pop On / Roll up by 2, 3 or 4 rows )

Text displayed by scrolling through a window on rows 1..15

XDS info (no fixed layout ⇒ application SW) displayed in any order, anywhere


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Line 21 Transmission Method:

• Character Codes : ASCII 20H..7FH , Control Codes : ASCII 01H..1FH

• Data-stream is transmitted in bursts, each starting with a control code that defines the stream:

– XDS : 01H .. 09H

– CC1 / CC3 / T1 / T3 : 10H .. 17H

– CC2 / CC4 / T2 / T4 : 18H .. 1FH

• Odd / even field identifies streams that use same control codes:

– Field-0: CC1 / CC2 / T1 / T2

– Field-1: CC3 / CC4 / T3 / T4 / XDS


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Line 21 Control Codes:

• Control Codes consist of a pair of bytes :

– First byte defines the stream type

– Second byte defines a specific type of control action

• Control codes are normally transmitted twice in succession to ensure

correct data reception (only one copy of the data is acted on)


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Line 21 XDS-Control Codes:Code Byte 1: XDS Stream Type Code Byte 2: XDS control action

01H

Data relating to current TV programme

03H

Data relating to future TV programme

01H 02H 03H 04H 05H 06H 07H 09H

10H ..17H

Programme - ID number - Length - Name - Type - Rating - Audio info - Caption info - Aspect ratio - Description

05H Channel information 01H 02H 03H

Network – Name - Call letters - Tape delay

07H Miscellaneous information

01H 02H 03H 04H 40H

Time of day Capture ID Data Location Local Time Zone Channel Number

09H Public service information 01H 02H

Weather Code Weather Message


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Line 21 CC-Control Codes (1):

• 4 types of CC control codes:

– Special Character code: Inserts special or accented characters

– Mid Row codes: Changes attributes (e.g: Foreground colour, Italics, Underline)

– Miscellaneous Control codes: Changes Display styles

– Preamble Address codes: Character Position, Foreground colour, Italics, Underline

• First control byte determines CC1/CC3 and CC2/CC4:

– In field-0: CC1 or CC2

– In field-1: CC3 or CC4


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CC1 CC3

CC2 CC4 Byte 1: CC Stream Type Code Byte 2: CC control action

11H 19H Special Character Codes: allows display of non-ASCII characters

E.g: ® , ™ , â

11H 19H Mid Row Codes: set/change foreground colour, underline or italics

20H / 21H 22H / 23H 24H / 25H 26H / 27H 28H / 29H 2AH / 2BH 2CH / 2DH 2EH / 2FH

- White / Underline - Green / Underline - Blue / Underline - Cyan / Underline - Red / Underline - Yellow / Underline - Magenta / Underline Italics / Underline

17H 1FH Miscellaneous Position: add tab offsets to data position ( 1 tab = 4 spaces )

21H 22H 23H

Tab offset 1 column Tab offset 2 columns Tab offset 3 columns

Field-0Field-1


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CC1 CC3


14H 1CH Miscellaneous Data Selection / Data Style :

20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH

Resume Caption Loading (Pop On) BackSpace AOF reserved AON reserved Delete till End of Row Roll Up captions 2 rows Roll Up captions 3 rows Roll Up captions 4 rows Flash ON Resume Direct Caption (Pain On) Text Restart (Clear Memory) Resume Text Display Erase Displayed Memory Carriage Return (New Line) Erase Non-displayed Memory End Of Captions (Flip memories)


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Line 21 CC-Control Codes (4):CC1 CC3


11H 12H Preamble Address: Row1 / 2 12H 1AH Preamble Address: Row3 / 4 15H 1DH Preamble Address: Row5 / 6 16H 1EH Preamble Address: Row7 / 8 17H 1FH Preamble Address: Row9 / 10 10H 18H Preamble Address: Row11 13H 1BH Preamble Address: Row12/13 14H 1CH Preamble Address: Row14/15

4xH / 6xH x = 0 / 1 x = 2 / 3 x = 4 / 5 x = 6 / 7 x = 8 / 9 x = A / B x = C / D x = E / F 5zH / 7zH z = 0 / 1 z = 2 / 3 z = 4 / 5 z = 6 / 7 z = 8 / 9 z = A / B z = C / D z = E / F

Colour for line Y / Y+1 White / White underlined Green / + underlined Blue / + underlined Cyan / + underlined Red / + underlined Yellow / + underlined Magenta / + underlined White, Italic / + underlined White, Attribute line Y / Y+1 Indent 0 / Indent 0 underlined Indent 4 / + underlined Indent 8 / + underlined Indent 12 / + underlined Indent 16 / + underlined Indent 20 / + underlined Indent 24 / + underlined Indent 28 / + underlined


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Line 21 GTV-CC Library SW:

• Decodes all 8 Closed-Caption and Text channels

• Supports eXtended Data Services (XDS)

– Delivers packets of information to the application

• Supports “Content Advisory” (e.g: violence control, US & Canadian “Vchip”)

• GTV-CC Library SW allows:

– one line of the display to be used for OSD (CC1..4 or T1..4 modes)

– some display attributes to be fixed

– character fringing to be used instead of background colour


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RDS / RBDS:

• European Radio Data System, USA Radio Broadcast Data System– MPX signal, carried in FM radio channels 87.5 .. 108MHz– Raw stream bit-rate = 1187.5Hz

• Signal from QSS sound part or SSIF input :– Analogue FM mono demodulation into MPX signal– AD-Conversion via shared Y-ADC (into 10-bit parallel data @ 304kHz)

– Carrier extraction & down-mixing (from 57kHz into base-band)

– Bi-Phase-Shift-Keying demodulation & clock recovery– RDS / RBDS block detection– Error detection & correction– Fast block synchronization & “flywheel”– RDS/RDBS data & status info available in SFR registers– Interrupt to synchronise RDS-processing SW with new RDS data

GTV Function:prds_EnableRDSDecodingprds_GetMS, prds_GetMSStatusprds_GetPI, prds_GetPIStatusprds_GetPS, prds_GetPSStatusprds_GetPTY, prds_GetPTYStatusprds_GetPTYN, prds_GetPTYNStatusprds_GetRT, prds_GetRTStatusprds_GetTP, prds_GetTPStatusprds_GetTA, prds_GetTAStatusprds_GetHours, prds_GetMinutes, prds_GetTimeStatusprds_GetDay, prds_GetMonth, prds_GetYear, prds_GetDateStatus


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Scaling, Panorama & DW:

• Double-Window &Scaling never usedsimultaneously

Line memory 1

Line memory 2ADC Pixel

manipulationDAC

outin

HsyncPLL

out(Non-) linear scaling 36MHz

Double Window 54MHz

27MHz

4:3 transmission asdisplayed on a 16:9 tube

Linear scaling + black edgesrestore 4:3 aspect ratio

Non-Linear panorama scalingrestores ~4:3 aspect ratioand fills the 16:9 screen

Double Window compression

1/31/6 1/6

1.5x 1.33x 1.17x

The video ADC writes into a line-memory (sample frequency = 27MHz), while the display reads back from another line-memory (alternating).

The scaling mode is set in SFR Video_process DW_PA:

Note:

When line-compression is not needed, we advice to switch-off the digital interface (DINT=0).

DW_PA<1:0> DINT Mode Remark 00 0 Normal Full width unprocessed 01 1 Double Window

compression Compressed video on left hand side

10 1 Linear scaling 4:3 on 16:9 tube 11 1 Non-linear scaling 4:3 on 16:9 tube


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Double Window & 2-Page:

PHILIPS

Normal TV + OSD Full TXT 2–Page TXT

Left & Right usesame font (12x10)

Double Window(video + TXT)

OSD / CCPHILIPS PHILIPS

P100 CNN TUE 12 OCT 14:22:15-------------------------------------------------

TELETEXT

-FULL-TXT (NO VIDEO)-MIX (TRANSPARENT BACK)-BOXED

P100

TXT-----------------------

Panel A

P101

TXT-----------------------

Panel B

PHILIPS

OSDPHILIPS

No OSD Overlay

NO OVERLAY

TXT-----------------------

P101

TXT-----------------------

Panel BOSD / CC

-----------------------

Panel AOSD

Double Window: Function enabled by SFR : DW_PA<1:0> of Video_process reg. = ‘01’Show Video / TXT, Video / CC, compressed video

Two Page: Function enabled by via MMR (87FF): Two_Page Configuration register.Show TXT / TXT on 2 panels side-by-side

?? Twin pageCC-CC

not possible ?


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Push-Pull(output only)

Out

Config

3.3V

Output

Open-Drain

I/O

Out

Config

5V

In

Quasi-bi-directional

I/O

Out

Pulse

3.3V 3.3V

In

High Impedance(input only)

InputIn

• Changing configuration can be done by software, any time

+5V tolerant +5V tolerant

• All port-pins are individually configured & controlled

80c51 TCG µ-controller Ports:

PxCFGA<y> = 0PxCFGB<y> = 1




For television applications, the “open-drain” and “high-impedance” configurations are preferred (minimal radiation).

The 4 different modes of operation for the pins of Port 0,1,2,3 are selected by SFRs P0CFGA/B, P1CFGA/B, P2CFGA/B, P3CFGA/B.

“Push-pull” should only be used with adequate EMI-stoppers.

“Quasi-bi-directional” is used during (fast) IC-factory testing. Here the active pull-up is on during one clock cycle (81.3ns), to obtain fast rising edges.

The “Open-Drain” output configuration is 5V tolerant, so if the U.O.C. has to interface with 5V logic, this is the configuration that should be used.

The “High-Impedance” configuration can also be used during standby mode, to reduce current consumption. “High-Impedance” is also 5V tolerant, but it has no output possibility.

GTV Function:rbsc_ConfigPort, rbsc_ConfigPinrbsc_SetPinrbsc_SetMLPin


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• Some instructions operate on the port-- latches : ANL, ORL, JB, CLR, SET, ...- pins : MOV, XCH, ...

• Be careful with “Read-Modify-Write” instructions (ANL,ORL…) NOT to overwrite a port accidentally

(see Notes Pages below …)

80c51 Port Operations:

The following I/O port operations read the port latches (not on port pins)

ANL logical AND, e.g: ANL P1,AORL logical OR, e.g: ORL P2,AXRL logical EXOR, e.g: XRL P3,AJBC jump if bit=1 & clear, e.g: JBC P1.1,labelJB/JNB jump if bit=1/bit=0, e.g: JB P2.0,labelCPL invert bit, e.g: CPL P3.3INC/DEC inc/decrement port, e.g: INC P1DJNZ decr. & jump if not zero e.g: DJNZ P1,labelMOV Px.y,C move carry to bitCLR Px.y clear bitSET Px.y set bit

Some are “Read-Modify-Write” instructions (ANL,ORL…), that read the port-latches, do their operation & write the new byte back to the latches. This avoids possible mis-interpretation of the voltage level at the pin.

Following instructions operate directly on the port pins:

XCH exchange port with accu e.g: XCH A,P3MOV input from a port, e.g: MOV A,P1

output to a port, e.g: MOV P1,FFH


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PORT 0

102

Tim

er 0

GENERAL I/O

123 115 12011198 9997 107 108 109

P1.0 P1.1P0.5 P1.3

PORT 1

P1.6 P1.7

14BIT

PWM

5x6 BIT

PWM

4x8 BIT

ADC

Intern

I2C

I2C

SCL SDA

• All I/O pins can sink 4mA (at 0.4V)

112

P2.0

PORT 2

P2.1 .. P2.5 P3.0 .. P3.3

PORT 3

I2S

I/O

106

P0.0 .. P0.4

Tim

er 1

INT

0

INT

1

126

P1.2

INT

2

UA

RT

P1.4 P1.5

128 127

I/O ports:

The I2C-bus peripheral is also used for communication between the micro processor core, stereo sound decoder and the video processor part (efficient in silicon area, low radiation). For multiple (split) I2C-busses, simply use 2 I/O pins to implement SW-driven I2C (e.g. for safety of EEPROM with alignment settings).

Port P2.0 can be switched as 14-bit PWM for Voltage Synthesis Tuning (SFR register TDACH.bit7=1 enables TPWM on port 2.0). All other pins on Port 2 can be switched as 6-bit PWM.

The SW-ADC can select one out of four Port3.x pins via SFR register SAD

GTV Function:rbsc_SetTDACrbsc_ConfigPort, rbsc_ConfigPinrbsc_SetPinrbsc_SetMLPinrbsc_GetADC


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• 4-Input,SuccessiveApproximationDAC +

-8 bitstatic

SADAC

VHI

Int1

ADC0ADC1ADC2

ADC3

• Result of comparison available when ST bit resets (ST was set by SW to start the comparison; bit is reset by hardware)

• 5V tolerant Inputs (Causes range 3.3V-0.75V to be lost)

Resolution = 3.3V / 256 = 13mV

Software A/D converter:

‘0’ for input voltage ≤ DAC

Channel select by SFR: SADCH<1:0>

SFR: SADB<7:0>

DC compare mode

The software ADC uses an analogue comparator plus a DAC to set areference level. This gives better temperature stability than direct A-to-D conversion. Via successive approximation the software can determine the analogue input voltage (using SFRs SAD and SADB). After writing these registers, SW starts the comparison by setting the ST bit. A few instruction cycles later the SADAC has executed the comparison and resets ST.

The output of the comparator can be coupled to Interrupt 1. This is useful e.g. to generate a wake-up signal when a local keyboard switch is pressed.

GTV Function: rbsc_GetADC


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• Even works during POWERDOWN mode (in DC_COMPare mode)

1. Disable INT1 using the IE SFR.2. Set INT1 to LEVEL SENSITIVE using the TCON SFR.3. Set DAC to desired threshold level via SAD/SADB SFRs.4. Select input pin P3.0,1,2,3,4 via CH1,0 in SAD SFR.5. Enter DC Compare mode via DC_COMP bit in SADB SFR.6. Enable INT1 using the IE SFR.7. Enter Power-Down/Idle/Standby. (sleep until wake-up trigger)8. Upon wake-up, restore SAD to conventional operating

mode by disabling the DC_COMP bit.

SAD wake-up interrupt:

The DC-wake-up threshold level should correspond e.g. with a certain local-keyboard switch in a resistor-divider network at 3.3VSTANDBY.

GTV Function:LibCoMa setting: RBSC_KEYBOARDWAKEUPTHRESHOLDrbsc_LocalKeyboard


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• Five 6-bit Pulse Width Modulation Outputs

• Individual Enable Bits

• Controlled via SFRs PWM0,1,2,3,4

• Period of 10.42µs, Resolution of 0.16µs

D5..0

10.42µs

6 bit PWM-DACs:

PWMx AnalogueVoltage

+3V3 or +5V

10K

10k

The 6-bit Digital-to-Analogue converters use simple duty-cycle modulation. At value 00HEX the pin is continuously low; at value 3FHEX (=63DEC) the pin is high with one 0.164µs pulse to ground.

GTV Function:rbsc_SetPWM0, rbsc_SetPWM1, rbsc_SetPWM2, rbsc_SetPWM3,rbsc_SetPWM4, rbsc_SetPWM5, rbsc_SetPWM6


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• Period of 20.83µs, individual enable bit

• 7 MS-bits for BASIC period, fast settling

• 7 LS-bits for 14-bit accuracy, required for VST

TD 13..7

128 periods

TD 6..0

14 bit Tuning DAC for VST:

The seven most significant bits TD <13:7> determine the basic HIGH period between 0 and 20.83µs, with a resolution of 0.164 µs.

This allows fast settling of tuning voltage jumps, e.g. when changing channels.

The seven least significant bits TD <6:0> can extend 1 up to 128 of the basic periods by 0.164µs.

Example:if TD<6:0> = 01H then 1 in 128 periods will be extended by 0.164µsif TD<6:0> = 03H then 3 in 128 periods will be extended.

GTV Function: rbsc_SetTDAC


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Emulator Systems:• “MX51-B(H)” + “Glue” + “UOC-III” emulator adaptor

• ISP to (re)program characters-sets into emulator

• Two bond-out emulator chips : Picasso (=µC) & Cosmic (=TVP)

– For emulator purposes, we don’t want to swap IC’s– Emulator uses MAX. version of Picasso & Cosmic bond-outs– These can be configured to act as lower specified versions

(via I2C & SFR registers)

Emulator boxHITEX

MX51-BH-23

Em

ul.

Ad

apto

rP

R73

06x

“Glue”PHERC-A1

• Buy your tools at our business partners:– Emulator+Glue+adaptor+socket: WWW.HITEX.DE

– High-speed I2C interface: WWW.TELOS.DE

– C-compiler, linker & debugger: WWW.KEIL.COM

Picasso

Cosmic

The Hitex-MX51 emulator box emulates Program ROM. The 80c51 core executes its own program plus the monitor SW of the debugger system (while halted).

Character sets should be Flash-programmed into the micro processor part of Hercules, e.g. via ISP.


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Demo board

Display

Video Generator

CVBS, Y/C, YPrPb, RGBPAL,SECAM,NTSC,

TXT,CC WSS

RF Generator

BG/I/DK/L/L1/M/NA2,NICAM,MPX,FM

QFP128Picasso

tun

er

Emulator boxHITEX

MX51-BH-23

I2C

I2C

I2C-businterface

Typical evaluation set-up:

WISP

QFP128Cosmic

Em

ul.

Ad

apto

rP

R73

06x“Glue”

PHERC-A1

QFP128flexfoils

WIC32

Per

son

alC

om

pu

ter • Tools for Engineering purpose only:

– WIC32, WISP, GTV-examples

• Distribution through partners:– Emulation, I2C, Compiler, support

The emulator-adaptor panel holds two generic bond-out IC’s. Together these can be configured to emulate all Hercules versions.

All direct components are on the panel, only the less critical signals are connected via a flexfoil-cable to the QFP128 contra-socket (target).

The emulator-adaptor panel can run without a target connected (+3.3V, +5V, +8V supplies needed).

Via the Hs-I2C programmer, the character ROM and some configuration data must be programmed into the Picasso bond-out.


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3-79

Which Vdd goes where ?

• All µC-I/O lines use 3.3V (1.8V only internal)

VddP, most are even 5V compatible

V1V8SeClkoP+N

IrefO

P_TmSelSifInP+N

SndInL,RP+N

VrefAd

Csi,H,VdispISda,Scl2Out+In

Y,U,Vout+InYuvRef

CorB,ScavTxtR,G,B,Vds

Snd1,2outL+R

MC

M in

terf

ace

EA

RDWR

IntD

Port2

AD0..7

A8..17

ALE

PSEN

Port1Port0

2.5V

+2.5V ref

Dec

Dig

<1.2V dipdetector

+3.3VSTBY

+3.3VddA I2C+Hdrive

80C51 core&

FlashProm

118

14

+5V

+Vp1 for Geo

+Vp2 for IF&sw

+Vp3 for RGB

+Vdd for Comb

+5V+3.3VddP µC-Periphery

+1.8VddCore

45 +8V+Vp8 for Scart

16

47

82

69

88

+3.3VddA

117

124,99,73

110

+1.8V to AudioDsp

DecV1V8

CosmicPicasso

+1.8V 3xAdc 89,21

+3.3V Audio 67,74,22

23,25,27,70 VrefPOSLa

tch

Em

ulat

ion

RA

M /

RO

M D0..7

A0..17

Port sense

lines

BndSel

ReDrawn by E. Arnold, 22-01-2002

+3.3VSTBY

= 3.3V logic= 1.8V logic

+3.3Vfrom

target

IF,Audiovideo

Geo-metry

10k

3V3+3.3V from target

+3.3Vstb+5V

Reset

TARGET

GLUE-board

Philips Emulator-ADAPTOR board PR7306x

EM

UL

AT

OR

-bo

x H

itex-

MX

51C

om

pu

ter

+3.3

VS

TA

ND

BY

conn

ecto

r

(MCM: 5,7,9,90)

(MCM: 22,94)

(124,100,93)

(MCM: -)Emitter

followers1.8V

Reset


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Special Bond-out signals :For emulation purpose:PSEN = ProgramStoreEnable = read-strobe to external program memoryALE = AddressLatchEnable = latches lower address byteEA = ExternalAccess = execute from external memory, when EA=lowAD0..7 = Address A0..7, multiplexed with data D0..7A8..18 = Address A8..18 (A8 formerly called “BONDSEL”)RD, WR = Read, Write signals for external data memoryINTD = Interrupt Disable = used for Xdata monitoring by some emulator systemsFor easier/faster factory testing: (not for emulator purpose)STANDALONE = Allows PICASSO to operate without a COSMIC connectedVPEX_CHAR = +11V for character FLASH PROMVNEX_CHAR = -5.0V for character FLASHISA_VIREF_CHAR = Output sense amplifier (ISA) & 3.3V supply for character FLASHACU_CHAR = Address count-up for character FLASHDCM_CHAR = Duty-cycle measurement for character FLASHDCM_PROG = Duty-cycle measurement for program & PK26 FLASHACU_PROG = Address count-up for program & PK26 FLASHISA_VIREF_PROG = Output sense amplifier (ISA) & 3.3V supply for program & PK26 FLASHVPEX_PROG = +11V for program & PK26 FLASHVNEX_PROG = -5.0V for program & PK26 FLASHOVP = Overrule protectionSupply lines:VddA = +3.3V standby supply, always present. Used to make 1.8V intern during sleep modes.VddC = +1.8V, used by 8051 core outside sleep modes (limits internal dissipation)VddP = +3.3V standby, supplies all I/O, MCM-interface & BondOut pins

On the emulator, it is preferred to use the Picasso Xtal Clock for all, because the “DCXO” has internal, tunable Capacitors (= low PPM with simple Xtal).Especially during NICAM decoding, this clock is carefully phase-adapted to the incoming NICAM signal.


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Platform

Application

User Interface

Res

ou

rce

Sound Fn

Drivers

Hardware

TuningVideo

Functionlayer

CC TXT 100page

ACI

EPG

Software: Layer Model

Philips Semiconductors a “GTV” software platform, characterised by:- Faster development time by using tested modules- Easier multi-site development- Constant quality and stability

By offering modules, the set maker only has to spend effort in creating his own User Interface. This reduces software development dramatically.“GTV” software is organised in 6 well ordered layers, that only interface to adjacent ones. Each layer:

- has a guideline for its type of functionality- has an API (Application Programming Interface), providing the basic

functions that can be called from the layer above- Allows calling functions only in downward direction so that lower layers

are independent of the upper layersInformation to be passed upwards is handled by software events, as described in the execution architecture.

The hardware can be different in various TV-set implementations. Therefore it is shielded by a driver-layer (like Bios ROM in Personal Computers).The platform-layer allows easy plug-in of different functional modules. The application-layer determines the functionality of the TV and finally the User Interface gives it a certain “face” to the end user.For example: “Electronic Program Guide” is an application that uses the basic TXT functions and the 10 page teletext library.


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Reso

urce

Function

Platform

Device drivers

Hardware

Generic drivers

Application

Reso

urce

Function

Platform

Device drivers

Application

• Register access• Monitor hardware changes• Implements functionality

Generic drivers

• Map generic driver API to device specific API• Contains the run-time device configuration

• Provides generic functionality• First abstraction of the hardware• API hardware independent• Implementation hardware dependant• Access of device drivers via generic driver

• Add functionality on top of platform API• Data Management• Change Management

• Includes the main loop• Map user commands to TV control function• Handles display

• General purpose functions for GTV• Mandatory basic resources• I²C, Eeprom, timers

GTV layers:

Device-drivers provide access to the registers (=control parameters) of hardware devices. They monitor changes in the state of the hardware and trigger software events.

Generic-drivers manage access to a set of similar device drivers. They reflects their functionality, without adding any. The generic driver has knowledge of the current configuration and is therefore able to divide the driver calls over the proper device drivers.

The Platform provides generic TV control functionality,required to build a TV. It does this by coordinating and integrating the generic drivers. The platform API is independent of the hardware (present / absent in the exact TV hardware chosen. Since the platform provides generic functions usable in all TV’s, any TV specific software must be located in higher layers.

The Function-layer contains functions that vary from one TV to another but rely on the generic functionality provided by the platform. They may be implemented in a general way that spans a family of TVs. The function layer adds “software-value” (SW-only features) to functions provided by the platform. It is the only layer that can be bypassed.

The Application-layer contains the GTV application. It maps user-commands on TV-functions, and handles OSD for the user interface.

The Resource-layer holds parts, required throughout the entire software system (or would confuse the layered diagram) like: I²C, timers, etc.


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Application around the IC:

File: Herc_4.ppt = Application, v1.1, 30-09-2003 by E.Arnold

In/OutIn/Out

StereoStereo

VIF & SIFVIF & SIF

MonoMono



MicroMicro

The diagrams in this presentation are intended to explain the functional behavior of a TV receiver with UOCIII “Hercules” concept.

© Philips Electronics N.V. 2003

All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The presented information does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Author:

Philips Semiconductors - Business Line Mainstream Tv SolutionsE.C.P. Arnold

TV System Design - Eindhoven,The Netherlands


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“Avoids costly redesigns”

Design Process:

• Before start: gather all information in design team, add own expertise

• Choose: design method, quality assurance, planning, EMC, board size, layout rules, component use etc.

• Clear ALL items in start-up phase, everybody involved should be aware of the chosen design method

• Define ground structure for whole TV set

• Make first model and evaluate

The Guard Ring approach:

What is very important about this approach, is that everybody should understand WHY we need a Guard Ring.

First define (check) a ground structure for the whole TV set (including tube, speakers, connectors, mains filter etc.). Pay special attention to the signal transfer structure AND the return-currents for each signal.

Around IC’s, Guard Rings are recommended. Sometimes shielding isrequired, that may be part of a Guard Ring.

Finally adapt the chosen structure for optimal application.


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The Guard Ring approach

• Do not change design philosophy (and loose all effort spent so far)

• Use Guard Ring approach, a proven method for TDA8362/62A,TDA8375,TDA8844 and UOC-I/II

• Follow guidelines for UOCIII “Hercules”, and it is possibleto design FIRST-TIME-RIGHT

• Guard Ring enables simple-but-effective optimization– It’s inside is “isolated” from the environment– A MUST for Single-layer PCB technology, model also applicable for

Multi-layer with reference ground plane

Design Philosophy:

On a multi-layer PCB, where one layer is used as reference ground plane, the Guard Ring philosophy is the same although the implementation is different. You should also try to isolate an IC from its environment, but now by using the ground layer as a reference. Keep other currents away from the reference ground under the IC & its direct components.


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Single Connection

Guard Ring

Disturbing Ground Current: ID

1/2 ID

1/2 ID

ID

IC

1. Single connection (low inductance) isolates IC from rest of layout2. Ring shields capacitive coupling3. Low pass filters to Ring, NO other tracks in guard area4. Easier EMC experiments: marginal influence on the rest5. Guard ring as large, hollow star ground for other circuits6. Last rescue: shielding box (connected at many points to the Guard Ring)

Basic Guard Ring function:

With an ideal Guard Ring, a disturbing ground current can not flow under the IC, only through the Ring.

The Guard Ring makes it possible to put the IC on its own, “clean” island. With this construction your engineers can do trouble shooting in an effective way: solve something WITHOUT introducing two new problems !

EMC regulations already cover up to 150MHz, 900MHz, 1.8GHz, 1.9GHz and may be specified up to 2 GHz. We expect that this will force the consumer industry to use more expensive PCB technology and perhaps more often a metal shield.

In areas where EMC qualifications are not mandatory by law, we still advice to use the guard ring approach to obtain a good performance.


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Disturbing Current: ID

A

B

C

ZSERIES = IC pin to guard ring impedance

ZLOCAL = IC pin to local ground

impedance

∆ID

∆ID

ID

7. Keep ZSERIES Ohmic (A, B, C) for predictable HF behavior8. Stray capacitance over resistors = 0.5 .. 1 pF,

Parallel wires = 1pF/cm, Series Inductance = 10nH/cm9. Ring length NOT equal to λ of expected radiation

Many pins = many connections:

In a more realistic application, an IC will have many connections to the “outside world”. Now a disturbing current ∆ID CAN flow through the IC & components, distributing the unwanted disturbance everywhere.

In this example, impedance A looks like a first-order low-pass filter.B will behave as a capacitive load. Impedance C can be anything.

For a predictable High Frequency behavior, it is best to try to keep the series impedance's Ohmic. This is less simple than it looks, because all components have parasitic properties.

If you expect strong fields with a certain frequency, the length of any loop in the PCB should NOT be equal to that wavelength (antenna).


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10. ∆ID: voltage over ZGUARD: local currents ∆ID through IC11. ZSERIES must be made as high as possible12. Ring = 3 to 5mm wide for low Ohmic part of ZGUARD

Disturbing Current: IDID

ZSERIES

ZGUARD

∆ID∆ID

∆ID

∆ID ∆ID

Non-ideal Ring:

The impedance of the Guard Ring itself can not be zero. Disturbance voltages over the Guard Ring can cause unwanted currents ∆ID through signal tracks; even local mesh currents. THIS is the main reason why EMC problems are so hard to tackle.

The total impedance of ALL parallel ZSERIES impedance's together should be maximized. If you forget one, the total effect is spoiled.

The Guard ring should be treated as a component. It should be allowed to occupy some PCB board space. In general half a centimeter wide copper serves well as a low impedance up to 2 GHz.

Never put jumper wires in the Ring. A jumper wire for sure is an inductance.


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• Minimize connections between circuits

• Connect the rings firmly to ground

• Put RF-blocking in every connection (choke, LPF or high impedance)

• Long wires = more filters

Applicable to thewhole chassis !

Every circuit its own Guard Ring:

The Guard Ring applies also on a macro scale, for large PCB design.

Circuits should not influence each other, so we isolate each one within its own, individual Guard Ring.

Less connections = less chance of unwanted disturbance.

Every long track is a potential antenna for RF disturbance, including supply and ground tracks !!

Chokes are effective to suppress RF energy in a certain band, whereas Low-Pass-Filters can be designed for frequency roll-off.


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8Do’s and don’ts with


Important rules, step by step

The two most important rules are:

• Put a ground plane under the IC, directly connecting ALL ground pins.

• Create a >3mm wide Guard Ring around the IC + direct components.

The following slides describe the UOC-III in QPF128 package, mounted on Single-layer PCB material.


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Ground references:

1

18

12

28

40

125

121

101

95

92

89

81

68

68

VIF

SIF

Xtal• Low impedancebetween ground pins= ground plane

• Leave Xtal floating, use no external capacitors

• Single-sided PCB:extend ground-planeand connect via multiple tracks

“ground-plane” under IC,

locally extended outside pinning

• Keep Digital & Analogue currentsaway from each other, decouple locally

Guard Ring

Digital ground-plane

Analogue-plane

?? UntillES7.2D:

add 2x 6p8

1. All time bases are calibrated to the Xtal (max. 30ppm).The oscillator design has tunable capacitors inside to improve accuracy of the clock (no external capacitors). This improves system performance of: NICAM decoding, Colour catching, sync locking, OSD, Teletext, C.C. decoding etc.

2. The space under the IC should be filled with a ground plane. If you need to cross this with a signal, it is best to put a jumper in the signal wire. Avoid using jumpers or zero Ohm SMD’s in a ground connection. These have higher inductance than a thick copper track.

3. Connect all ground pins to the copper plane under the IC.

4. Components that need ground reference, should all be connected to the ground-plane, or to local extensions of it. These extensions should be kept free from other currents, to allow really “clean” grounding.


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Grounding & supply:

• Parallel ground wires = less inductance = better reference

• Extra coil in digital VDDCore ⇒ effective on-chip decoupling

+VDDP

+VDDC

+VDDA+VDD ZA

ZC

ZP

CP

CC

CACA,LF

LC,EXT

Ground connections:

The voltage reference inside the IC is connected via several parallel bonding wires. The resulting inductance is low enough to avoid ground-bounce by AC-currents (all I/O pins would start radiating).

Supply, VDDPeripheral and VDDAnalogue:

Analogue circuitry needs good, external decoupling, both HF and LF.

Supply, VDDCore:

Digital circuitry produces wide-band noise. On-chip decoupling helps to short-circuit this inside the IC. Don’t put an external capacitor CC direct at pin VDDC, because this will route more of the digital noise outside the IC. Better increase the series inductance with LC,EXT because:

LC,EXT limits extern AC currents, ALSO through ground connection !!(= less ground-bounce by switching of core circuitry)

(Voltage model:larger L in supply = less voltage over small L in ground)

The supply-bounce will of course increase, but pure digital circuitry is quite immune for that (practice value: LC,EXT = 2.2 µH to 15µH).

Conclusion: an external coil can make on-chip decoupling more effective.


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IF-PLLloop filter

• Pin 41 is sensitive for disturbances. Any modulation can be visible on the screen

40 PL

LIF

• First 390Ω at pin 41, then 100nF to ground

IF-PLL loop filter decoupling:

A modulation of the IF-PLL loop-filter voltage, will automatically cause a frequency modulation. Via the SAW filter’s Nyquist slope, a PM-to-AM (Phase Modulation to Amplitude Modulation) conversion takes place. This results in a visible modulation of the CVBS output.

Between the resistor and the capacitor, we have a good monitoring point of the IF-PLL loop filter voltage. That’s why the capacitor is connected to ground and not the resistor. Use only a high Ohmic probe, otherwise you may influence the IF-PLL too much.


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• Pin 28 is ground for SAW filter pin 3 (to internal IF circuitry)

• The lF-PLL loop filter is connected as short as possible, with a separate track to ground pin 40

• Pin 18 and 40 must have a short connection (via ground plane)

24

25

IF inputs IF AGC

LPF

VCO

V/I

0o

90o

40

41

IF-PLLLoop Filter28

18 Integrated IF-AGCtime constantsMain Ground

IF Ground

IF-PLL loop filter:

SAW

The Application Manual gives details which ground pins are used as reference for certain circuits. In all cases it is best to connect ALL ground pins to a ground plane under the IC.


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• Bandgap = reference for many functions Decouple pin 20 both HF & LF

• BOTH capacitors to same groundnear pin 18

18

12

20 = Bandgap19 = SECPLL

Band gap & SECAM-PLL decoupling:

• Take care that NO digital currentscan flow via pin 18 (will disturb Bandgap grounding)

• Improper decoupling ⇒- horizontal jitter - disturbed vertical deflection - etc.

• SECAM-PLL needs 220nF decoupling to neighbour pin 18, use low-leakage type

Band-Gap pin 19 needs 2.2 uF low-frequency decoupling plus 10 nF high-frequency decoupling. If these two capacitors are connected to different grounds, all voltage differences will be injected into the Band-Gap reference voltage.

The SECAM PLL decoupling capacitor should be a “low leakage” type. Otherwise black-level offsets on the U and V signals can occur, depending on temperature, humidity etc.

Static offset can be visible, mostly in B-Y. This can now be compensated via bits SB01..0. (Secam B-Y Offset adjustment)


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• Internal digital supply pin 14 should be decoupled to pin 12via minimal 220nF

18

12

14 = DecDig

Digital decoupling:

• DecDig = 2.5V can be used to control a 1.8V supply⇒ add series resistor to keep

decoupling local⇒ add 2.2uF for loop stability

The DecDig pin 14 decouples an internal voltage of 2.5V. This voltage can be used to make a self-controlled 1.8V supply. Via software it is possible to enable a feedback from three 1.8V supply inputs towards the DecDig 2.5V output.

During standby mode of the video processor, the DecDig pin is pulled low (< 0.4V at max 1mA sink current).


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One connection of IC-ground to Guard Ring:

1

18

12

2840

125

121

101

95

92

89

81

68

Local reference

ground

68

Guard Ring

• Guard-Ringaround highimpedantzone

• Single pointgroundingmust haveLOW inductance

Low inductance

ONEconnection

Double Layer PCB:

All critical components can best be mounted under QFP package and grounded to the ground-plane.

Single Layer PCB:

The grounding of direct components can NOT be made to the ground-plane. For proper grounding of critical components like phi-1/2, bandgap etc., a separate ground structure is necessary. This should be connected to the ground plane under the IC, via as many connections as possible. For single-layer layout this will certainly cost some board space.

Guard Ring:

The IC-ground should be grounded via ONE point only, near the tuner and IF path. When ALL currents are kept local, there will be hardly any current through the connection towards the Guard Ring. Still it is important to give this connection the lowest possible inductance, to avoid problems with flashes (surges, discharge tests etc.).


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CRT-panel ground to Guard ring:

1

18

12

2840

125

121

101

95

92

89

81

68

68

BGRIbl

• Iblack returnneeds clean path

12µA Iblack-return

• Guard-Ringmust havelow impedance

69

• Comb filterVDDCOMB only to pin 68, no shared currents

The RGB cable that goes to the CRT panel (picture tube) is always long and will act as antenna for disturbances. The three RGB outputs can be equipped with filters, but the ground connection can NOT. Therefore it is best to lead this to the Guard Ring.

Make sure the Guard Ring is low Ohmic, otherwise ground currents can be super-imposed on the small measurement currents (12uA) of the black current stabilization loop (CCC). This can show as loop instability.

The Comb-Filter supply input pin 69 must be decoupled to ground pin 68. Since this is quite noisy, we advice to route pin 68 only to the ground-plane.


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Phi1 & Phi2 loop grounding:

18

12

28

17 = Phi116 = Phi2ϕ 2

ϕ 1

• Clean groundingat pin 18

• Dominant for sync performance VIF

SIF

The two phase loops are very sensitive, to get a good sync performance. This also means that the phi-1 and phi-2 components need a good, clean ground.


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Vertical reference components:

18

12

28

ϕ 2ϕ 1

• Clean groundingat pin 18

27 = Iref26 = VsCap

VIF

SIF

• Keep vertical referencecomponents very close to the IC

The vertical ramp capacitor and the current reference resistor demand a clean, separate grounding to pin 18. Disturbance on these reference components can easily be visible as “line pairing” on the screen. The human eye is very sensitive to this kind of effects (up to -60dB).


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Vertical driver decoupling:

• Vertical drive = long lines⇒ add series resistors

18

12

28

ϕ 2ϕ 1

22 = VdrB23 = VdrA

VIF

SIF

V-Amplifier

V-deflection• Disturbance, picked up

by deflection cable runsthrough V-amplifier, into pins 22+23

• Neutralize parasitic coupling to VIF by decoupling Vdrive A/Bpin 22+23 at pin 18and use series resistors

The connecting wires to the vertical deflection coils are long. They can easily pick up disturbances, so the outputs of the vertical amplifier should be equipped with filter chokes plus capacitors.

The large output transistors have large capacitive coupling to the amplifier’s substrate. So HF disturbance can “walk-through” the vertical amplifier, into the vertical drive lines. These are located next to the SAW filter inputs, so pins 22 & 23 need to be decoupled near the IC.

At the position where the vertical drive lines cross the Guard Ring, it is best to put 1k Ohm series resistors. If the drive lines are long, it may be better to add a second filter stage. Keep the tracks between series resistors and pins 22,23 short to minimise parasitic coupled “body” to the VIF lines.


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SAW filters and IF leads:

• SAW filter substrate (pin 3) via clean groundingat pin 28

• Leave pin 28 floating(= internally connected to GND pin 40)

18

12

28

ϕ 2ϕ 1

VIF

SIF

“Method 1”

The tuner output is normally 75 Ohm. After the SAW filter the impedance is higher (2 kOhm), so it is logical to put the SAW filter as close as possible to the One-Chip.

To avoid differential pick-up, it is best to route the IF leads completely symmetrical. Even for an a-symmetrical tuner output, the wiring should be kept symmetrical. The ground wire should be grounded near the signal source, so at the tuner.

The SAW filter substrate pin 3 should be grounded to the One-Chip pin 28, via a clean, separate path.

The tuner should be connected to the IC main ground pin 18. Try to minimize the total loop surface of IF lines and ground connections.

In a-symmetrical application, SAW filter pin 2 must be grounded(for optimal trap performance, according manufacturer).


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Switch able SAW filters and IF leads:

• Compromise:single-point groundingSymmetrical around IF path

18

12

28

ϕ 2ϕ 1

VIF

SIF

“Method 2”

switch

• Keep IF-area as smallas possible

• You can connect pin 28 tothe IC ground plane, butONLY after EMC-validation was proven OK

Try to keep the total loop surface of IF lines and ground connections minimal. A large “body” will pick-up more disturbance than a small one.

Method 2:

Switch able SAW filters are usually driven form an a-symmetrical tuner. SAW pin 2 has to be switched to either pin 1 or pin 3. This means we can NOT use the SAW filter as separator (see “Method 1”) between Guard-Ring and IF ground pin 28.

The alternative is to route the ground all around the IF-area.

The vertical reference components can now be connected differently, but try to keep the SAW filter substrate (pin 3) free from modulation. Use as many parallel ground connections as possible.

Grounding of pin 28:

First verify that no unwanted currents can flow through pin 18. If this is OK, then it is safe to connect pin 28 to the ground plane.


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SAW filter grounding, SECAM-L1:

Tuner

PC CCPC-CC

33.9

38.3

40.4

SC

29.5

PC CCPC-CC

IF:

VideoSAW:

Injecteddisturbance

RF:

Low

Z

IF GndIF Gnd

Each pin of a SAW has somesubstrate capacitance. Thisbypasses the filter-curve unlesssubstrate is grounded very well

4.43

PCCC

55.7

Injecteddisturbance

f28 40

Sym-metricalIF inputs

No sharedcurrents

In Europe an EMC test (EN55020, Conducted-Current Immunity 26.. 30MHz) needs special attention: when a SECAM-L1 transmitter is tuned and the injected disturbing frequency is at: FIF - chroma.

The SAW filter suppression at 29.5 MHz is about 35dB. The video part demodulates this unwanted lower side-band to base-band, were disturbs the Colour Carrier demodulation. This will be visible, so the SAW filter application is very important (you can’t filter away this disturbance anymore).

Keep layout and track impedances symmetrical (even with a-symmetrical tuner). Any a-symmetry makes the signal less immune to common-mode disturbance.

The SAW filter pins inevitably have parasitic capacitance to the SAW-substrate. This capacitive path bypasses the SAW. Therefore the substrate should have a low-impedance ground connection, preferably near the IF inputs (SAW IN = 75 Ohm, SAWOUT = 2 kOhm). The track must not share currents that generate (over the track impedance) a disturbance voltage between SAW-ground and IF-circuitry-ground.

We advice to connect the IC-ground to the tuner, close to the IF leads.


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IF path:

+

+

28

40

24

25

“Method 1”

+

+ “Method 2”

Tuner

75 2k

Z23Z13 Z43 Z53

2

1 4

5SAW

3

1 ground connection: make use of Common-Mode rejection

2 ground tracks, symmetrical ground around IF circuitry

UOCIII

Method 1:

We advice to connect the main ground pin 18 to the tuner. Keep this ground a bit close to the IF leads to minimize the loop area for magnetic coupling. Method 1 clearly shows that currents, injected at the tuner metal housing will NOT flow through the SAW filter grounding. When the IF tracks are symmetrical, we can now use the Common-Mode rejection of the SAW filter to “isolate” the tuner from the IC.

Method 2:

It is difficult obtain perfect symmetry. When the SAW filter performance is critical, the tuner output amplifier should have the same ground reference as the IF input amplifier. BUT: by connecting the ground via the SAW filter, ALLother IC currents will ALSO flow through this path. To avoid IF disturbance, it is best to route TWO ground tracks, next to the IF lines. Both ground tracks must be connected:

- near the tuner,- under the SAW filter, via its pin 3- near the IC and to pins 28 and 18

Magnetic pick-up can be minimized by twisting the IF lines half ways, (SMD jumper) between SAW filter and IF inputs (2kΩ) this can be very effective.


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Asymmetrical tuners:

+

+

28

40

24

25

Switch

A

B

For switchable SAW filters, surrounding ground is a MUST

+

+

28

40

24

25

Tuner

Hercules

75 2k

Z23Z13 Z43 Z53

2

1 4

5SAW

3

Single ended “asymmetrical” tuners should be connected to the SAW filter via a symmetrical pair of IF tracks, routed close together.For optimal filtering, SAW pin 1 should be IF-input and pin 2 ground.

For applications with a switchable SAW filter, a grounding near the IF path is even more important. Usually an a-symmetrical tuner is used, to minimize the switching components.

The switch is in the IF signal path: it either short-circuits filter “A” or “B”.It is obvious that the return-ground from SAW to tuner has to be routed close to the IF track.

Just like in “Method-2” on the previous slide, it is best to embed IF, SAW and the complete switching circuitry between ground tracks.

Remarks:

- If the (capacitive) load of SAW plus switch is high (>12pF), anamplifier/buffer is necessary in the IF signal.

- The command line of the switch should have a blocking impedancefor IF (& HF) frequencies, near the SAW filter. A transistor is NOT ablocking impedance so a base resistor (47k) should be added.


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SAW filter switch @ 5V:

• Minimal parasitic capacitances on tuner IF output = less components

• Enough reverse voltage to havelow capacitance of switch diode

BSwitch 5

41

2

3

TunerIF1

IF2 high

Tuner

A

+5V

VR

>3V

R1

A

low

Tuner+5V

I F >

3mA

R2

L1

B

Band switchdiode BA782

• Enough forward current to makeswitch diode conducting

• Use coil L1 (makes SAW & switch “Ohmic”)

to couple DC-switching (= less capacitance to IF lines)

E.g VIF: K7257M orSIF: K9653D

Tuner+5V

R2

L1

R1

R3

Digitalswitch

L2

C1

C2

R4

The Tuner IF output stage can usually drive up to 20pF capacitive load. With two switch able filters (VIF+SIF SAW) plus wiring you can easily exceed this capability. Therefore a coil L1 to ground is added, that will annihilate the capacitive load and give a more “Ohmic” impedance.

Coil L1 now allow us to put DC-switching voltages on the IF-line withoutadding capacitive load to it (parasitic capacitances of components).Coil L1 is permanently AC-grounded via capacitor C1.

Note:Although the switching transistor could be directly driven from an I/O port, we add a second transistor + high Ohmic base resistor. This avoids EMC injection into the SAW filter grounding.

Make sure that the +5V has a series choke plus proper decoupling (C2) to the IF ground. The series choke has to block EMC injection via the supply.


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QFP-128 package on Single Layer:

• In first layout: provision to splitground-planes into digital and analogue part

⇒ Solve cross-talk issues in chassis

⇒ Re-connect after evaluation

• Connect 28 toground-planeafter validation

1

18

12

2840

125

121

101

95

92

89

81

68

68

BGRIbl

VIF

SIF

Xtal

PL

LIF

Guard Ring

Single PointGrounding

“ground-plane” under and

outside pinning

Guard-Ring aroundhigh-impedant zone

It is best to start a new layout with the ground plane and the Guard Ring. During the layout phase, e.g. series resistors can be used to jump over the Guard Ring. In this way the copper area, spent for better grounding can be “hidden” under the components. Thus minimizing the extra PCB area for the Guard Ring approach


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SMD package on Bi-Layer:

• Always put a ground-plane under the IC, even on 2-layer PCB• Connect ALL ground pins to this Local Ground-plane• Route return-currents first to their GND pin and then to ground

= keep both signals AND return currents separated

Gro

un

d

Lay

er

Lo

cal G

rou

nd

-p

lan

e

Parasitic capacitor,parallel over R

R

R

Ground strip under series resistor reducesparasitic parallel capacitance

Line-up the series resistors, to minimise the parasiticcapacitive coupling to long lines

Even with double layer material a ground plane under the IC is still necessary. This assures that all ground pins share the same reference-potential. No currents should ever flow into one ground-pin, through the IC and then out via another ground-pin.During flashes (=high dI/dt) this might pull certain parts of the silicon below zero and cause malfunction.

On a bi-layer we recommend to make the two IF connections between SAW filter and IC above each other. By carefully implementing a “twist” halfways, the EMC performance can be increased considerably. Especially in the range around the IF frequency (e.g. for BG: 33.4 .. 44.4MHz).


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Layer4 = Signal

5 V PowerPlane

Layer3 = GND

4 layer: Ground & Power structure

3.3V Power Plane

Layer2 = “GND”Keep layer3 as un-interruptedground layer / shield

Layer2 is mainly usedas ground layer, butlocally as power plane

Every IC has it’s localGround plane directly underthe IC-body

1.8V1 Power PlaneLayer1 = Signal

LocalIC

Ground

LocalIC

Ground

Component side 1.8V2

• Connect ALL IC-ground pins to the Local Ground-plane on Layer-1• Route return-currents first to their GND pin and then to Layer-2


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4 layer: decoupling capacitors3.3V Bulk decoupling capacitorclose to IC

Signal1

Gnd2

Gnd3

Signal4 5V Power Plane under IC

3.3V Power Plane under IC

5V 3V3FerriteBead

FerriteBead

Local Ground Plane under IC

5V Bulk decoupling capacitorclose to IC QFP128


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ü1- All ground pins direct to ground plane under IC

ü2- VDDA+P well decoupled, VDDC via extra choke (no C on pin)

ü3- Narrow Guard Ring around IC + direct components

ü4- Blocking impedance in every line across Guard Ring

ü5- Single-point grounding near IF (or symmetrical around IF tracks)

Five absolute MUSTs:

Above anything else, a good ground connection with low-impedance is needed. Feeding “strange” currents through the ground inside the IC may lead to unpredictable results (all references are made to ground).

Pure digital circuitry like a micro-core - with On-Chip decoupling - can handle quite some supply bounce. Use this property to limit radiation:put a coil in the core supply BEFORE decoupling it. Reserve a small capacitor directly on the pin, but do not mount this unless the supply bounce is too high. For C18 process the max Vdd-peak = 2.4V.

The Guard Ring + blocking impedance's are the hardware equivalent of a “fire-wall” in computer networks.

The IF part is the most delicate one. Therefore we give it the best possible ground reference.


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Summary of grounding:

• VIF,SIF SAW short ground track to pin 28. Short & symmetrical tracks to pin 29,30 & 24,25• Xtal as close as possible via symmetrical, short tracks• All 100nF/220nF decoupling capacitors very close to belonging ground and supply pin

– pin 3,4,5,14,15,20,38,45,47,69,82,90,91,93,94,100,117,118,124• Loop filter components close : Secam pin19; IF pin 41; Phi1,2 pin 16,17• In principle, try to route decoupling capacitor to ground pin:

– pin 3,4 to pin 2– pin 12 to pin 88– pin 89 to pin 90– pin 91,93,94 to pin 92– pin 100 to pin 101– pin 110 to pin 121– pin 124 to pin 125– pin 82 to pin 81– pin 69 to pin 68– pin 14 to pin 12– pin 15,16,17,19,20 and pin 22,23 and pin 26,27 to pin 18

• Keep digital currents away from DECBG decoupling pin 20 to pin 18


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Reference Receiver “USB”

An application example:

• A complete TV system, more than just a demo-board

• Made by Philips Semiconductors to:- Eliminate potential problems before customers get ICs- Evaluate IC, Hard- and Soft-ware- Have a realistic reference TV- Small-Signal “Plug-In” allows quick comparison between

various IC concepts (e.g. UOCII versus UOCIII Hercules)

The UocSuperBig TV receiver has its small-signal part on a Plug-in module, that contains just the IC and its surrounding components. This enables evaluation of several IC-concepts in the same environment.

Test results are significant for customer implementations, because the USB layout is as “realistic” as possible. The Plug-in module hardly affects system performance, especially not when the connectors are skipped and the Plug-in is directly soldered onto the USB chassis.

The USB-receiver can be used as a “system-level” reference design.


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Mechanical floor plan of a receiver:

• Large components & heat sinks determine floor planD

rive

r

LOT / FBT

GreenChipTM

Eas

t-W

est

Tra

nsi

sto

r

Au

dio

RectifiedMains

CapacitorSMPS

Mains

Tuner

Vertical

TD

A8357

Filt

er

LineTransistor

SAW

If you start building a receiver, you always start with the large components.

1. The Line Fly-Back Transformer is usually at the PCB edge becauseof focus & VG2 alignment and mechanical stability (e.g. drop-test)

2. Scart plugs need to be accessed from the rear side

3. The tuner should be far away from the FBT, to avoid self-locking(receiving own H-deflection).

4. The SAW filter is shortly connected between tuner and VIF/SIF inputs

The rest of the PCB is for Vertical, Audio and Power Supply.


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Ground floor plan of a receiver:

Dri

ver

LOT / FBT

GreenChipTM

Eas

t-W

est

Tra

nsi

sto

r

Au

dio

RectifiedMains

CapacitorSMPS

Mains

Tuner

Filt

er

LineTransistor

• Keep Guard-Ring area SMALL !

CRTSupply

CRT

High Impedancestructure

Low Impedancestructure

Vertical

TD

A8357

ICSAW

Small area onPower Ground

This ground pattern is in accordance with the Guard Ring philosophy.

The ground strip at the rear side is used to short-circuit radiation, picked up between antenna cable and mains power cord (safety caps).

For HF disturbances, the mains filter and the SMPS transformer are easily bypassed. To avoid unwanted coupling to the UOC, the central “back-bone” in the ground pattern can be used as a barrier. Suppression filters at the secondary side of the SMPS can be grounded to this structure.


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Minimise Audio-Video crosstalk:

• Separate ground currents (IC-ground from AV-inputs) including shield grounds• Advice for first layout: (minimise risk)

reserve 68pF from each (audio &) video input to IC-ground (close to IC)

– Reduces risk of cross-talk (HF-pick-up, video-to-video, video-to-audio etc.)

– After test phase evaluation some capacitors may be deleted

DC-clampcircuit

100p Sparc gap

LineImpedanceTermination75

E

100E

Coupling capacitorholds DC-clamp voltage

100E

These components suppressenergy from discharges

Inside ICcircuits areDC-coupled

DC-clamp currentinto < 300Ω

68p

100n

Example: video input with DC-clamp


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Flash precautions:

• Capacitivecoupling via cables

IC

R2

D1

R1

C1

R3+Vs

FB

T/L

OT

R5 C3

R4

D2

C2

Anti-crackling layerAnode

RG

B

CRTSupply

Aquadag

spar

k ga

ps

D.U.

V

H

Vertical Deflection

Horizontal Deflection

EHT

VideoAmp.

Cat

hode

s

Foc

us

Grid

-2

Grid

-1

Fila

men

t

+8V

A good ground floor plan is essential for a TV set to survive Picture-Tube flashes. But also wiring and component-choice play a role.

Picture Tube: (hard-flash or soft-flash type)The PT has a capacitance (1..3nF, 30kV) between aquadag and anode. A flash discharges this capacitance to the electrodes in the gun. A hard flash PT can reach peaks up to 500A, a soft flash type has a resistive layer that limits to 90A,~300 Ω.

Video CRT amplifier: (limiter resistors R1,R2 & protection diodes D1)spark-gaps limit the max flash voltage and can be integrated in the picture-tube socket or on the PCB. A super soft flash will not open spark-gaps and can last quite long. When such a flash is dumped (via D1) into a supply capacitor (C1), this must be able to absorb almost all energy out of the PT.

EHT, deflection:The (vertical) deflection coils are capacitively coupled to the PT (even more with anti-crackling layer). A flash can short-circuit the line-output stage, while unexpected large currents can flow out of C2 (~½nF).

Guard Ring and cables:Any “body” is capacitively coupled to the flash, so select the position of connectors and cables very carefully. Keep currents away from the IC.


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Simple 3-level decoder:

• Less lines needed for switch functions

• 3-levels by switching between Open-Drain and Push-Pull

• SW can change I/O configuration per pin, at any moment

Out

Config

3.3V

Sw

3.3V

3V

0.5V

Mid

High

Low

1

-

+

-

+

0V1.5V3.3V

Low + Open DrainHigh + Open DrainHigh + Push Pull

SoftwareLevel

47k

47k

Open collector output buffers

High

Mid

Low

3-leveldecoder

47k

10k

47k

47k

1k

1.5k

+3V

+8V

47k

Mid

High

Low

Mid

High

Low

Mid

High

Low

Mid

High

Low

Mid

High

Low

Mid

High

Low

Open-Drain,

float

Mid

Out

Config

3.3V

Push-Pull, high

Out

Config

3.3V

High

3.3V

Open-Drain, low

Low

Out

Config

3.3V


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Cheap 3-Band switch for VST tuner:

• Only one transistor for +5 Volt tuner band switching

Px.xPx.x

Hercules+8V

HiMidLo

VST tunerI

III

IV5V compatible, 4mA

sink 4k7

47k

3k3

3k3

3k3

4k7

4k7

4k7

The band-switch inputs of a VST tuner usually have internal pull down resistors of 4.7kOhm. With 5V tuner types, a band-switch is activated when the input pin is above 4.5V. This specification can not be met by a micro controller that is running at 3.3V. But since the digital UOC outputs are 5V tolerant, we can add pull-up resistors of 3.3kOhm to +8V. Together with the 4.7kOhm pull-down this gives a “high” level of 5V.


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UV

1316

/ 133

6

IF1IF2

SW

4.43 38.9

PCCC

3.58

IF 45

1

2

3

1k8

4k7

+8

1k8

10k

10k

Inter-Carrier Sound

K72xx

VIF1VIF2

4.43 38.9

PCCC

3.58

45

1

2

5.5 .. 6.5SC

45

4.5

SIF1SIF2

1

2

K96xx

K3953M / 53D

VIF1VIF2

4.4338.9

PCCC

45

1

2

34k7

+8V

1k8

10k

10k

K9656?D

5.5 .. 6.5SC

45

3

L1 : 40.4

SIF1SIF2

1

2

33.9

L1

1k8

45

1

2

X6966M

36.15

3

8MHz

38.9 = K7252M Euro38.0 = K72xxM China45.75= K72xxM USA

SC

38.9 = K7257M+K9653D Euro38.0 = K7262M+K9655D China

3

3

Quasi-Split Sound Hybrid Analogue + DVB

Switchable SAW filters:

SAW filter types:

X72xxX = Video & Inter-carrier SAW, simplified switching(5 pins: switch= pin 2 to pin 1 or pin 2 to GND pin 3)

X96xxX = Audio SAW, simplified switching(compared to X94xxX / X95xxX)

X35xxX = Combined QSS sound & video in 5 pin package

XxxxxD = SIP5D low-profile package (high density packaging)

Type numbering e.g.: G 19 84 MTV standard:G = B/G B = Australia J = IK = D/K or BG..DKL = L + L1M = M/N USAN = M Japan

Family

Number

Package:M = SIP5KD= SIP5DK = DIP10KL = DIP18D


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Global Traveler:

• NTSC-M-N,PAL-M-N-BG-I-DK,SECAM-BG-DK

• Mono or stereo

• Very compact design

I2C-2

CVBSMON

Flyback

H-drive

BeamCurr

+8V

V-drive

Guard

+12V +36V

RGB

IBLACK

Stby

+3.3V +115V

I2C

Keyb

AudioOUT

Peri

Audio Amplifiers

TDA6108A3x RGB Amplifier (80)

TDA8359DC Vertical Amplifier

BU2508DFHorizontal Deflection

& EHT

TEA1507GreenChip SMPS

PCF851162Kb EEPROM

EA99009

24.576MHz

RGB/YPRPB

Y/CVBS

C

IRPCA8521

RC-5 Transmitter

De-Gauss

EHT

H

V

LS

16:9110o

Audio

Audio TDA120xx“Hercules”“Hercules”

VIFSecond Sound IFFM demodulatorSource Switching

Sound ControlSync ProcessingGeometry Control

PAL/SECAM/NTSCRGB ProcessingMicro controller32 .. 192K ROM

1 .. 2K RAMTeletext

Closed CaptioningOn Screen Display

RDS/RDBSStereo processing

I2C AGC VIF

UV1316PLL Tuner

SAWFilters

M/M

LS


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DC-coupled Vertical Deflection :

• Vertical Shift easily set via DC offset

B

DA

C

E

4.5V

VOUTA

VOUTB

VFEEDBACK

VGUARD

VP = +13V

VFLYB = +36V6

3

9

7

4

1

2

5

TDA8357/59

RMEAS

LDEFL

+ RDAMP

CompRCOMP

ZCOMP

Comp

IDRIVEA

IDRIVEB

iCOIL

< 560

< 560

2k2

2k2

2k7

InA

InB

GndRCON

iCOM - ½iVERT

iCOM + ½iVERT

600650700

400

100150200

VA

I DR

IVEA

,B (µ

A)

3FH00H 1FH

8

10k

VGUARD1n

TDA10xxx

100E

1n

1n

The improved vertical amplifiers TDA8357 & TDA8359 (2 & 3A) have:

• Higher LVD-MOS IC process voltage 68V (was 60V for bipolar 8351)

• Better SOAR because DMOS has no secondary breakdown

• Lower dissipation and lower scan voltage (e.g. +13V , was +16V)

• Improved reliability: homogenous heat distribution across the device

• Reduced dissipation at end of flyback (add zenerdiode + resistor)

The required input biasing plus the conversion from current into voltage is done via two fixed resistors RCON of 2.2kΩ. The gain of the vertical amplifier can be selected by RMEAS.

• Max. peak current (while VA = 3FH) out of IDRIVEA or B is :ICOM+¼ IVERT,MAX = 400 + 300 = 700µA

• Input voltage at pins 1 and 2 should remain below 1.6 Volt :700µA x 2.2kΩ = 1.54 Volt

• Nominal (VA=1FH) differential voltage between InA,B or over RMEAS is:950µA x 2.2kΩ = 2.1 Volt

• RCOMP must be calculated (see data sheet), voltage of ZCOMP=VP.

• IDRIVE pins max. output voltage = 2.5V ⇒ series resistors < 560E


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Horizontal Deflection:

• Low voltage start-up from 3.3V

Hor. Driver

IC

+VB

Pulse shaper

HorizontalDrivePulses

ϕ2-loopH-flyback

LH

CBCS

Linearitycorrection

CF

CDIV

+VB

LP

FBT

+5V, +8V, +13V, +36V

TDR

RDR LLEAK

+8V

EHT, VFOCUS , VG2

Beam Current, EHT tracking

TD + D1

+3.3V

Scan-rectifiedsecondaryvoltages

• 5V (IC), 13V & 36V (Vertical Deflection) scan-rectified

How to set-up the horizontal deflection stage ?

• Determine necessary (scan) current through LP and LH (data sheets)

• Find amplification factor of T1 at this current (e.g. BU2508DF at IC=2A gives 6x current amplification)

• Calculate the base current for T1 ( [2A / 6] + [0.7V / 47Ω] = 330 + 15 = 345mA)

• Divide it by the voltage ratio of the driver transformer (e.g. “10:1” with 345mA gives 35mA)

• Collector current of TDR will roughly be double this current (2 x 35 = 70mA)

• Make sure TDR gets enough base current to drive thiscollector current

• Adapt RDR with a given supply voltage so that TD gets its calculatedbase drive current


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Beam Current limiting:

47nRinging

6k8

220k

1k8

2n2

33u

83BCL

HerculesFBT / LOT

EHT

+8V

32EHT

IBEAM

10kOnly ONE long line

13 VGUARD

TDA83598

Guard

27k

82k

+5V

100k

1n

100

10k

• All EHT & beam current via pull-up• Anti-ringing filter close to FBT (large currents)• EHT compensation fast, average BCL is slow

• VGUARD ↑ 3.60V and ↓ 3.45V

47kOvervoltage

detector

• High-impedance = EMI-blocking in long connection line

A line FlyBack Transformer (LOT or FBT) produces severe “beta” ringing, up to several MHz. This unwanted (large) current must be short-circuited close to the FBT.

The transistor-integrator for BCL gives a “fast-attack” and “slow-decay” for too high beam current. Further it enables sharing ONE (long) line over the PCB with the EHT compensation input.

The vertical guard pulse should be connected to the VGUARD input. Make sure that the (long) VGUARD line is sufficiently “blocked” The vertical pulse should go >3.60V and return <3.45V before video-line 17.

Make sure the > 4µ7 capacitor is directly connected at the BCL pin (no resistor in between), otherwise the Peak-White-Limiter can start oscillating (typical rhythm of 2 µs periods, see Peak-White-Limiter function).


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1.7

2.8

0.8

1.7

2.8

0.8

1.7

2.8

0.8

BCL below 2.8V :

Start CONTRAST reduction

BCL below 1.7V (CBS=0)or below 2.4V (CBS=1) :

Start BRIGHTNESS reduction

BCL below 0.8V :

Blank RGB outputs

BCL voltage:

• Reducing CON & BRI limits max. beam current (e.g. 1.5mA)

When the Beam Current increases, the voltage on pin BCL decreases. As the BCL voltage drops below 2.8V V, first the CONTRAST will be reduced (no loss of visible video).

If this is not enough to limit the Beam Current, the BCL voltage can drop further. Below 2.4 V (bit CBS=1) or 1.7V (CBS=0), also the BRIGHTNESS will be reduced. This can push the low-intensity part of the video below black-level.

Below 0.8 V the RGB outputs are forced to blanking level (= slightly below “black” level).


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+33V

R1

R2

Improved resolution for VST:

0 Tuning [Volt] 30

850

400

Freq

uenc

y

[MH

z]

0 Tuning [Volt] 30

35

3.5

Ste

epne

ss

[MH

z/V

olt]

X =

0 Duty Cycle [%] 100

30

0

Vtu

ne [V

olt]

Non-linearPWM Integrator


28

7

Ste

epne

ss

[MH

z/V

]


850

400

Freq

uenc

y

[MH

z]

The characteristic of a tuner is dominated by a varicap (= capacitance of a reverse biased diode). If we increase the tuning voltage linearly, the tuned frequency changes by an “S” shaped curve. In e.g. the UHF band the tuning steepness will vary between 35 and 3.5MHz/Volt when tuning from low to high frequency. The tuning resolution varies by a factor 10.

For accurate VST tuning, a linear translation from “duty-cycle” to frequency would be ideal. In other words: the same “kHz/step” irrespective of high or low position in the band.

We achieve this by using a “non-linear” integrator for the 14-bit tuning PWM DAC. By selecting different charge and discharge time constant, we can modify the translation from duty-cycle to voltage. When we multiply this with the tuner steepness characteristic, the maximum steepness reduces (28MHz/V) and the minimum increases (7MHz/V). Important is, that the steepness variation reduces from 10 to a factor 4.

End result:- more linear translation from duty-cycle to frequency- more constant tuning resolution (better than 50kHz/step)- no need to compensate tuning curve in software


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Search-tuning with IF-PLL:

• IF-PLL can only “see” what comes through the SAW

PC SC50 .. 850MHz

FRF+FIF

AGC

HFOsc

FRF

FIF

FIF

PCSC

SAW

AGC out

SC

Tuner

IF in

U.O.C

IFOsc

AGC

• Tuning up makes AGC react first on PC

An off-air antenna signal FRF is mixed in the tuner with a local oscillator (FRF+FIF) to a fixed Intermediate Frequency FIF. The value of FIF depends on the market area (local laws, EMC relaxations) :- Japan = 58.75MHz - America & other NTSC countries = 45.75MHz- China = 38.0MHz- All others = 38.9MHz

The IF signal is filtered by a Surface-Acoustic-Wave filter, that passes only the desired channel bandwidth around FIF (selectivity). The filter should always be close to the U.O.C., because the SAW is the only frequency-selective component in the whole IF path.

In the U.O.C. the IF signal is first “gain-controlled” (IF-AGC), then mixed with an IF oscillator to “base-band” video. The audio carrier is removed in a sound trap. The amplitude of the resulting CVBS signal is used to close the loop for the tuner AGC (and IF-AGC). This gives a constant CVBS signal at variable antenna levels (FRF).

Search-tuning can best be done in upward direction, so that the AGC loops can settle on the Picture Carrier (see next slide).


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Search-tuning with IF-PLL:

• For weak transmitters the catching range is only 1 MHz- Conclusion: coarse tuning step size < 1 MHz (advice: 800kHz)

• Stepping high to low gives AGC jump + locking on SC

• Stepping low to high gives earliest locking on PC

Catching range= 2 MHz (+/- 1MHz)

The free-running frequency of the IF-PLL oscillator is calibrated exactly to the chosen IF frequency (using Xtal reference). The catching range of the IF-PLL is 2MHz, symmetrical around FIF (without taking SAW filter characteristic into account).

When searching for a weak transmitter signal, the SAW filter attenuation above FIF will limit the catching range to about 1MHz. The software search-tuning algorithm should take care that tuning “steps” are always smaller than this worst-case 1MHz.

Search tuning can best be done from low to high RF frequency. For search-tuning-down, the IF-PLL will lock on the Sound Carrier. Just before the Picture Carrier enters the SAW filter, it falls in the “neighbour” sound channel trap of the SAW filter (-60dB). This will cause large jumps in the AGC. Software should allow extra delay time to let this stabilize, before evaluating Sync Lock and AFC information.


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Search-tuning speed:

• Using IF-Ident (SID), LOCK, Sync-Lock (ϕ1=SL) & AFC:(850-50)MHz / 0.8MHz x 30ms = 30s (no signals, no AGC jumps)

plus ~ 30 stations x 0.8s = 24s

• Avoid “large-signal” jump behaviour, keep it smooth

• Tuner AGC 10x slower than IF AGC (unless i-AGC can be used)

18dBµV..100dBµV8µV..100mV

nom.60dBµV=1mV

Osc IF

64dBIF AGC

40dB Tuner AGCCVBS1VP-P

-18dB IF spec:150mVMAX,RMS

Tuner spec:110dBµVMAX

350mVRMS=1VP-P

iAGC

+52dB takes 2ms-52dB takes 50ms

LOCK takes<20ms

<2MHz jump takes 2ms>3MHz takes about 30msLarge jump takes ..60ms

Tuner spec: osc.lock < 150ms

Small jump takes <20msLarge jump takes ..300ms

Tuner spec: 50ms .. 2s

Fast “Auto-Store” is always a compromise between catching-performance and search-tuning speed. The most important item is a reliable first “stop”criterium.

- When weak-signals are not important, the activation of tuner AGC take-over (bit AGC) provides an early signal. During search the TakeOver Point could be adapted. Speed idea: 800 / 1.5 x 22ms = 12s.

- When a tuner with I-AGC (internal) is applied, the AGC take-over of UOCcan be used to measure the signal amplitude (wobble T.O.P, read AGC).

- Once the tuner AGC is triggered, SW can speed-up the tune-in processby stepping quickly through the first ~ 3MHz, followed by AFC check.

- In areas with many transmitters, SW can use tricks to tune faster througha range of transmitters: after finding the first, step to the next with a 5 or6MHz jump. Normally adjacent transmitters have equal amplitude, soAGC remains constant.

- “Pure” search-tuning that catches ALL transmitters will take 50..100s.


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Reliable tuning algorithm (NEG):

1. Step-up 800kHz, followed by 30ms delay until: (SID=1).AND.(LOCK=1).AND.(SL=1) (AUTO-STORE: use STM=1)

2. If found then step-up 62.5kHz + 30ms delay and check SL againSL=1 should not fail for longer than 300kHz

3. Read-out AFC (2-complement notation) and jump exact to centerCheck IVWF=1 (needs >7 frames) else skip unwanted signal

4. Store in Eeprom, upon first recall: determine standard,Auto-following, re-store in Eeprom (TV & tuner are warm)

SL.AND.LOCK.AND.SID

AFC

1 1 1 2 2 2 3

4

For AUTO-STORE we advice to use STM=1 & as a first “stop” criterium:

(SID=1).AND.(LOCK=1).AND.(SL=1)

For MANUAL-SEARCH it is better to use STM=0 and:

(SID=1).OR.(LOCK=1).OR.(SL=1)

Normally an AUTO-STORE finds all stations. Only when this fails, the user occasionally has to find a problem-station via MANUAL-SEARCH. In this case it is better to stop on a false lock than to skip a (weak) signal.

During the second phase of the tuning process, sometimes a shortinterruption of the signal can occur. This is inherent to the series-chain of PLL’s in the system, together with AGC behavior and a SAW filter.

When a transmitter is found with STABLE SL=1 and AFC-read-out, it can immediately be stored in Eeprom, but we advice to add a check for IVWF=1 before you do, to skip unwanted false-locks.

On a cold-installed TV, you should store a transmitter together with a flag signaling that fine-positioning still needs to be done. When the user recalls the station for the first time, it is likely that the TV has warmed-up enough. Then SW can do fine-positioning and store the exact position in Eeprom.


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Tuning algorithm for SECAM-L:

1. Set CM3..0=0,1,0,0 (=SECAM)Step-up 800kHz, followed by 60ms delay until: (SID=1).AND.(LOCK=1).AND.(SL=1) (AUTO-STORE: use STM=1)

2. If found then step-up 62.5kHz + 60ms delay and check SL againSL=1 should not fail for longer than 300kHz

3. Read-out AFC (2-complement notation) and jump exact to centerCheck IVWF=1 (needs >7 frames) else skip unwanted signalCheck CD3..0=1,0,1,0 (=SECAM) else skip false lock

4. Store in Eeprom, upon first recall: determine standard,Auto-following, re-store in Eeprom (TV & tuner are warm)

SL.AND.LOCK.AND.SIDAFC

1 1 1 2 2 2 3

4

During a SECAM-L search, the system can sometimes give false lock on Negative-modulated transmitters. Sensitivity for this is reduced by STM=1 plus an additional check for SECAM colour ident.

Make sure that before checking IVWF=1, the synchronisation has had at least 7 frames times stable signal (e.g. 160ms).

After IVWF=1 you can immediately demand that chroma should have detected SECAM too (takes about 40ms).


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Limit this to max 350ms

Program switching:

• Long post-mute avoids sound glitches while “zapping”• < 350msMAX is experienced as “immediately”• Keep IF-calibration off; only enable (IFLF=0) during channel-change

Sound Mute

SLHorizontal-sync

AutomaticFollowing

RBL (or via OSD)

1 2 3 4 5

Video Blanking

Fast Verticalcatching

> 40ms pre-mute

NCIN

IVW/FVertical-sync

500ms post-mute

Mute audio, fetch new Eeprom data

Changetuning

Station found, Startsound & colour acq.

Picturestable

Long post-Muteavoids glitcheswhile “zapping”

IFLFIF PLL calibrationSwitch-On IF-calibration only

during channel-change

Audio pre-mute (soft) should be effective 40ms (~25Hz) before changing the tuning. This avoid plops during program or source switching.

Video blanking (RBL=1) is postponed to the latest possible moment, to keep the visible transition short. <300ms is experienced as “immediate response” where as >350ms gives a “sticky” feeling of the remote control. If it takes >350ms to lock on the new station, we advice to remove the picture blanking (RBL=0). RBL-blanking is internally synchronised to the vertical-retrace. As alternative SW can use a black OSD screen to blank the video. This has the advantage that possible OSD will not blink.

As soon as SL=1 is found, the speed-up for vertical catching must be disabled (NCIN=0), otherwise bits IVW and IVWF will not work.

Automatic following (AFC) should begin immediately after SL=1, to cancel temperature effects in the tuning system.

Switch-On IF calibration (IFLH=0) after video blanking. Release it (IFLH=1) after SL=1 and before un-blanking the video.

Fast settling of the AVL (auto-volume-leveling) after changing channel or source, is achieved by setting AVLM=1 during the audio Mute period.


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Lowest Power during TV-standby:

• Determine best output level for each I/O pin (advice to design for “low”)

• Carefully determine SW delays between switching power circuits (take-over-time, avoid glitches …)

• Always maintain 3.3VSTBY (needed for I/O pins & necessary for infrared receiver)

+

minimal current when LOW

Output-A

+minimal current when HIGH

Output-B


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Make your SW reset-proof:

• Keep backup-copy in Eeprom of:– Last tuned program number– All analogue settings– On/off status of the TV

• Refresh the backup only when:– Something has changed in the current status– Remote control and local keyboard were “silent” for > 20 seconds

• Don’t overwrite Eeprom bytes that have not changed• Expected life-time for Eeprom with 105 erase/write cycles:

– Average 10 refresh-overwrites per hour– Average 3 hours per day = (105 / (10*3)) / 356 = 9.13 years

• After RESET, software reloads the backup-copy from Eeprom and the TV continues as it was before


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55UOCIII “Hercules”The ultimate TV design:

Powering attractive TV products !

Philips Semiconductors - BL Mainstream Tv Solutions

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