H E T E R OG ENE OU S I N T E G R A T I ON

R O A D M A P

W L P T W G

H I R W O R K S H O P A T E C T CM A Y 2 8 , 2 0 1 9 John Hunt

ASE US IncCo-Chair

Rozalia BeicaDowDuPont

ChairSenior Director, Engineering,

Marketing &Technical PromotionASE (US) Inc

Global Director Strategic Marketing Electronics & Imaging

Specialty Products Division of DowDuPont

Presentation Outline

2

WLP Technical Working Group

Our Focus Area

WLP Market Drivers

Industry Trends & Challenges

Future work & Acknowledgements

Sze Pei Lim

WLP TWG Team

3

Chairs:Rozalia Beica John Hunt

Team Members:R&D Institute

Alvin Lee

Hiroyuki Shida

Mat. & Equip. Suppliers

Tanja Braun

OSAT IDM Fabless & OEM

Key Chung

Suresh Ramalingam

Market Research

Jerome Azemar

Steffen Kroehnert

Patrick Thompson

New Members are

Welcome!

Tom Buschor

Monita Pau

Takeshi WakabayashiHarry Shimamoto

David Butler

Li Li

Mike Delaus

Focus of WLP TWG

4

Leadframes

QFN,QFP

w/o IC substrates

Fan-in Fan-out

IC substrates-based

BGA(organic substrate)

W/B BGAFlip Chip CSP/BGA 3DIC 2.5D SiP

Embedded die(in substrate)

PCB substrate

Increased functionality, I/Os, integration complexity

Single die

Multiple Dies

Integration:2D 3D HIR

Embedded die

SiP

Embedded die

(in substrate)

Dies & Passives

Fan Out Packaging Technology was developed to expand this packaging capability beyond the limits of the die from Low to High Density formats

While Fan Out has been processed in wafer format, nearly all suppliers are working to develop rectangular panel versions

Wafer and Panel Level Packaging

5

WLP – Wafer Level Package: Includes all packages that are processed as packages while still in wafer form, prior to singulation

Wafer Level Chip Scale Package - WLCSP

Since WLCSP by definition is “Chip Scale”, there are a limited number of variations that lend themselves to Heterogeneous Integration (HI)

Wafer Level Fan-out Packaging - WLFOP

⇒ the WLP TWG will include Fan Out packages that are manufactured on both “Round” and “Rectangular” wafers

Market Drivers for WLP

6

I/O Density Smaller pitches Smaller dies Higher density of

I/Os

Integration IPD SiP 3D

Thermal Performance

Electrical Performance Shorter interconnects Lower parasitics Higher package speed Higher frequencies

Form-Factor No laminate substrate required Smaller thickness Smaller footprint

Lower packaging cost Lower test cost

Cost

Lower power consumption Lower thermal resistance

Market Drivers & Enabling Technologies

7

Main Markets • Mobile (90% market)

Market Drivers & Capabilities• Small footprint • Better electrical performance• Lower cost package:• Thinner package • Lower thermal resistance

Enabling Technologies• Wafer Processing• Bumping• Thin Film RDL

Main Markets • Mobile (90% market) (LD & MD)• Networking (HD)

Market Drivers & Capabilities• Small footprint • Better electrical performance • Lower cost package: • Thinner package • Lower thermal resistance• Larger Package Size• Improved Reliability performance• PoP Package capability• SiP Package capability

Enabling Technologies

Fan InWLP

Fan Out WLP

• Wafer Processing• Bumping• Thin Film RDL

• Wafer Molding• Low Temp cure RDL Polymer• Panel Processing

Heterogeneous Integration using WLCSPWLCSP

Basic WLCSP

WLCSP w/TSVsPoP

WLCSP w/TSVsMulti-Component

2D – Die to Die face to face stacking• Secondary die mounts on pads between solder balls on face of die• Can be active die or MEMS, or IPD die

3D – TSV through WLCSP – Die face to Die backside stacking• Uses TSVs to allow secondary die to be mounted on backside of primary die

Fan out allows partitioning of functionality

Digital, Analog, Components, MEMS, and IPDs

Fan Out SiPMulti Sourced Die

Die 140nmFab1

Die 228nmFab2

Die 314nmFab3

+MEMS, XTALs,

Filters, etc

XTAL

MEMS +Passives

Source:

Heterogeneous Integration using Fan-out

10

2D Packaging 3D Packaging

Hybrid Fan-out

Fan-Out Applications

Devices that can be found in FOWLP packages today

Devices that could be found in the future in FOWLP

Devices that will likely remain not move to FOWLP

Samsung Galaxy S7 (2016) Qualcomm Audio Codec

WCD9335 – eWLB package (Nanium/STATS ChipPAC)

Bosch MRR1Plus Radar (2015) Infineon RASIC™ (77GHz RADAR System

IC Chipset) – eWLB Package

BK Ultrasound Sonic Window (2015)Multichip Module – eWLB Package (Nanium)

Continental ARS400 Radar (2015) NXP MR2001 (77GHz multichannel RADAR)

– RCP Package

NXP SCM-iMX6Q (2017, APE, PMIC and Flash memory – Fan-Out PoP (NEPES)

Apple iPhone 7 (2016)A10 APE – InFO package (TSMC)

Apple iPhone 8 and X (2017)A11 APE – InFO package (TSMC)

Mobile (Smartphone) Beyond Smartphone

Automotive

Medical

IoT

Source: Adapted after Yole Developpement

Fan-out Evolution & Growth

12

Integration: Chip first / face down Chip first / face up Chip last / face down

Infrastructure:Wafer

Panel

Data source: Yole Developpement

Fan In/ Fan Out Packaging Convergence

13

Wafer Bumping

WLCSP

Flip Chip Assembly

Wafer Level MEMS

Fan Out

Fan Out 3D

2.5D Interposer

Conformal Shielding

Fan Out Multidie

Coreless Substrate

Antenna in Package

WLPHeterogeneous

Integration

Key Challenges

14

Common challenges for WLP Increasing package size above 8 mm x 8 mm (reliability concerns)

Thin package profile using very thin silicon die (wafer handling becomes increasingly difficult at lower thicknesses)

Heterogeneous integration of different materials (CTE mismatch; dielectrics, conductors and semiconductor devices, interfacial adhesion, stress/warpage, etc.)

Cost Reduction

Fan-Out Die shift during/after Molding Controlling levels of Warpage at each process stage Fine Line and Via capability for High Density Fan Out

package requirements Processes to allow inclusion of low cost passive

components Development Processes compatible with Panel Production Development of Equipment & Materials suitable for panel

processing

Fan-in Increasing I/O count beyond 200 within small

form factor Increased complexities with dies at more

advanced nodes CPI reliability concerns

• Singulation of advanced node die increases potential for latent edge defects, and handling damage post tape & reel

Contributing WLP TWG Members: David Butler – SPTS (UK) Douglas Yu – TSMC (TW) Hiroyuki Shida – Shin-etsu (Japan) Jerome Azemar – Yole Developpement (France) Monita Pau – DowDuPont (US) Takeshi Wakabayashi – HTL (Japan) Tanja Braun – IZM Fraunhofer (Germany) Tom Buschor – Nuvotronics (US) Mike DeLaus – Analog Devices (US) Rozalia Beica – Dow DuPont (US)

Future Work

15

In progress to finalize the WLP Chapter

Markets and Applications Market drivers / benefits of WLP/PLP Industry activities overview• Major challenges• Discussions of key technical issues• Summary and final remarks• Definition of terms• Table• Acknowledgements

Acknowledgements

Interested in joining the WLP team? - Please send email to rozalia.beica@dupont.com

Next Iteration of Chapter will expand on, and update all topics as applicable