heterogeneous noc router -...
TRANSCRIPT
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Heterogeneous NoC Router
Final Presentation
06.03.2012
Moti Mor
Tomer Gal
Instructor: Yaniv Ben Itzhak
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Background – Bus On Chip
• Busses are commonly used on SoC as the main
communication protocol
• Slow transfer rates
• High power consumption
• Only 2 units communicate simultaneously
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Conventional Bus on Chip
C C C C C C C
C = Client
BUS
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Background – Homogeneous NoC
• The SoC units communicate through a
network of routers
• Each router is assigned for a single unit
• Supports many simultaneously connections
• Cons:
– Loaded router may still have bottle-necks
– Resources are not assigned to the highly loaded
areas
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Background – XY mesh NoC
C C C
C C C
C C C
R R R
R R R
R R R
C = Client
R = Router
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Project Definition & Goals
• Learning the NoC basics and particularly the
Heterogeneous NoC router
• Design the architecture and implementation of:
– A single Heterogeneous Router
– A network of Heterogeneous Routers
• Measurements of the Heterogeneous NoC
– Latency
– Throughput
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Project Development Stages
• NoC & Het NoC concept learning
• Architecture and Logic Design
• HDL Implementation
– Building a NoC & Source/Sink (With VHDL
Implementation)
• Functional Simulation
– Measurements
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1 VC
1 VC
1 VC 1 VC
3 VCs
3 VCs 3 VCs
3 VCs
1 VC
1 VC
1 VC3VCs
1 VC
1 VC
1 VC 3VCs
(a) Base-line: Uniform
capacity and number of
VCs approach.
(b) Non-uniform link
capacities approach
].12) [Redundant VCs(
(c) Non-uniform number of
Redundant VC approach (
].15, 13) [capacity
: Our approach(d)
Non-uniform link capacities
and number of VCs.
Possible Solutions
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Architectural Design of the selected Solution
• Parametric controlled XY-Based
Heterogeneous NoC routers
• Attributes controlled by the parameter:
– Number of virtual channels per port
– Port bandwidth
– Buffer size (Capacity robustness)
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Router VC AllocatorR O P CG
R O P CG
R O P CG
R O P CG
R O P CG
Packet
Decoder
In - ports
Out- ports
Switch
Allocator
Switch
Traversing
H
Decodes the flit and stores in the desired buffer
Determines the requested output port
Determines the virtual channel in the next router
Allocates a route from the input port to the output
port
Sends the flit across the allocated route
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Special Problems:Problem 1
• Packet representation in HDL:
– HDL language is based on signals and physical
components - difficult to represent an abstract
structure like a ‘Packet’
– Makes data tracking in simulation more difficult
– No robustness - Protocol changes, packet size,
fields, bandwidth
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Special Problems:
Problem 1
Solution:
• The use of ‘Records’ (Data structures)
– Implementing the in/out ports as ‘record’ type
– Enables protocol robustness in packet size, fields,
bandwidth
– Enables packet & flit tracking throughout the
simulation
– Enables simple adding/removing debug fields
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Packet
Head Flit
Destination
X Y
Flit ID VCDebug
Fields
Source IDPacket
S/NNo. Of
Flits
Body Flit 1..N
Data Flit ID VCDebug
Fields
Source IDPacket
S/NNo. Of
Flits
Tail Flit
Data Flit ID VCDebug
Fields
Source IDPacket
S/NNo. Of
Flits
Solution Implementation
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Switch allocation tasks:
• Allocate all inputs to all outputs
• Prevent conflicts
• fairness
Special Problems:Problem 2
2 dimensional ripple carry arbiter
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Problems:
• Feedback is not synthesizable!
Special Problems:Problem 2
2 dimensional ripple carry arbiter
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Solution:
• Diagonal wave-front
• round-robin priority rotation
scheme – prevents feedback
Special Problems:Problem 2
Diagonal propagation arbiter
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Project Summary
• NoC concept learned:
– Computer network basics
– Router basics
– Homogeneous NoC
– Article reading about Q.NoC
• Design of Heterogeneous NoC Router Architecture
• HDL implementation
– Client implementation (source and sink)