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  • 0740-7475/03/$17.00 2003 IEEE Copublished by the IEEE CS and the IEEE CASS SeptemberOctober 2003 17

    IC MANUFACTURING TEST is changing, with anincreased emphasis on at-speed testing to maintain testquality for larger, more complex chips and new fabrica-tion processes. Growing gate counts and increasing tim-ing defects with small fabrication technologies forceimprovements in test quality to maintain the quality levelof chips delivered to customers after testing. Improvingthe stuck-at test coverage alone still might leave too manytiming-based defects undetected to reach quality goals.Therefore, at-speed testing is often necessary.

    Scan-based ATPG solutions for at-speed testing ensurehigh test coverage and reasonable development effort.This article explores applying at-speed scan testing. Weintroduce new strategies to optimize ATPG to apply spe-cific clock sequences that are valid with the circuit oper-ation. We also use these strategies to have ATPG generatetests that use internal clocking logic. Furthermore, wecombine the same technique with programmable phase-locked loop (PLL) features to support applying high-fre-quency, at-speed tests from internal PLLs. As a result, wecan base the application of precise clocks for at-speedtests on on-chip clock generator circuitry instead of testers.

    Motivation for at-speed scan testingIC fabrication processes produce a given number of

    defective ICs. Many companies have gotten by with sta-

    tic stuck-at scan testing and a limitedamount of functional test patterns for at-speed testing to uncover these defectiveICs. They often supplement these testswith IDDQ tests, which detect many typesof defects, including some timing-relatedones.1 In the past, these tests effectivelyscreened out enough of the limited num-ber of timing-related defects. However,at the smaller geometry sizes of todays

    ICs, the number of timing-related defects is growing,2 aproblem exacerbated by the reduced effectiveness offunctional and IDDQ testing. Functional testing is lesseffective, because the difficulty and time to generatethese tests grows exponentially with increasing gatecounts. The electrical properties of 0.13-micron andsmaller technologies have caused many companies torely less on IDDQ tests, because a defective devices cur-rent will be difficult to distinguish from the normal qui-escent current. Some have abandoned IDDQ testsaltogether for these small-geometry devices.

    The main force behind the need for at-speed testing isthe defect characteristics of 0.13-micron and smaller tech-nologies that are causing more timing-related defects.3 Forexample, one study on a microprocessor design showedthat if scan-based at-speed tests were removed from thetest program, the escape rate went up nearly 3%.4 This wason a chip with a 0.18-micron feature size.

    We can use functional tests to provide at-speed tests,but the functional test development problem is explod-ing exponentially with chip growth. For a different micro-processor design, the development effort to create thefunctional test set took three person-years to complete.5

    Furthermore, these tests consumed a large percentageof the tester memory, and the test time to run them wassignificant. Because the effort to create effective at-speed

    High-Frequency, At-SpeedScan TestingXijiang Lin, Ron Press, Janusz Rajski, Paul Reuter,Thomas Rinderknecht, Bruce Swanson, and Nagesh TamarapalliMentor Graphics

    Editors note:At-speed scan testing has demonstrated many successes in industry. Onekey feature is its ability to use on-chip clock for accurate timing in theapplication of test vectors in a tester. The authors describe new strategieswhere at-speed scan tests can be applied with internal PLLs. They presenttechniques for optimizing ATPG across multiple clock domains and proposemethodologies to combine both stuck-at-fault and delay-test vectors into aneffective test suite.

    Li-C. Wang, University of California, Santa Barbara

  • functional-test patterns is daunting, more companies aremoving to at-speed scan-based testing.

    Logic BIST can perform at-speed test but is usuallycombined with ATPG to get high enough coverage. Thevalue of logic BIST is that it provides test capabilities,such as secure products or in-system testing, when testeraccess is impossible. Logic BIST uses an on-chip pseudo-random pattern generator (PRPG) to generate pseudo-random data that loads into the scan chains. A secondmultiple-input shift register (MISR) computes a signaturebased on the data that is shifted out of the scan chains.

    There is reasonable speculation that supplementinga high-quality test suite in production with logic BISTmight detect some additional unmodeled defects. At-speed logic BIST is possible using internal PLLs to pro-duce many pseudorandom at-speed tests. However,employing this test strategy requires additional deter-ministic at-speed tests to ensure higher test quality. Thistest strategy also requires adhering to strict design rulechecking and using on-chip hardware to increase testa-bility and avoid capturing unknown values. Some spec-ulate that logic BIST will improve defect coveragebecause it will detect faults many times. However,although it does provide multiple detections, they occuronly at the fault sites that are random-pattern testable.Also, although logic BIST may be useful for transitionfault testing, the low probability of sensitizing criticalpaths with pseudorandom vectors makes logic BISTunsuitable for path delay testing.

    Scan-based tests and ATPG provide a good generalsolution for at-speed testing. This approach is gainingindustry acceptance and is a standard production testrequirement at many companies. However, scan-based,at-speed ATPG grows the pattern set size significantly.This is because it is more complicated to activate andpropagate at-speed faults than stuck-at faults. Becauseof this complexity, compressing multiple at-speed faultsper pattern is less efficient than for stuck-at faults.Fortunately, embedded compression techniques cansupport at-speed scan-based testing without sacrificingquality. When using any kind of embedded compres-sion solution, however, engineers must take care not tointerfere with the functional design, because core logicchanges can significantly affect overall cost.

    Moving high-frequency clocking fromthe tester to the chip

    In the past, most devices were driven directly from anexternally generated clock signal. However, the clockfrequencies that high-performance ICs require cannot

    be easily applied from an external interface. Manydesigns use an on-chip PLL to generate high-speed inter-nal clocks from a far slower external reference signal.The problem of importing high-speed clock signals intothe device is also an issue during at-speed device test-ing. It is difficult and costly to mimic high-frequency(PLL) clocks from a tester interface. Studies have shownthat both high-speed functional and at-speed scan testsare necessary to achieve the highest test coverage pos-sible.4 To control costs, more testing will move from cost-ly functional test to at-speed scan test. Some companieshave already led the way to new at-speed scan testing byusing on-chip PLLs.6 Although this is a new idea, it is gain-ing acceptance and use in industry designs. These tech-niques are useful for any type of scan design, such asmux-DFF or level-sensitive scan design (LSSD).

    Because a delay tests purpose is to verify that the cir-cuitry can operate at a specified clock speed, it makessense to use the actual on-chip clocks, if possible. Younot only get more accurate clocks (and tests), but youalso do not need any high-speed clocks from the tester.This lets you use less-sophisticated, and hence cheap-er, testers. In this scenario, the tester provides the slow-er test shift clocks and control signals, and theprogrammable on-chip clock circuitry provides the at-speed launch and capture clocks.

    To handle these fast on-chip clocks, we haveenhanced ATPG tools to deal with any combination ofclock sequences that on-chip logic might generate.6 TheATPG user must simply define the internal clockingevents and sequences as well as the correspondingexternal signals or clocks that initiate these internal sig-nals. That way the clock control logic and PLL, or otherclock-generating circuitry, can be treated like a blackbox for ATPG purposes, and the pattern generationprocess is simpler.

    At-speed test methodologyThe two prominent fault models for at-speed scan

    testing are the path-delay and transition fault models.Path delay patterns check the combined delay througha predefined list of gates. It is unrealistic to expect to testevery circuit path, because the number of paths increas-es exponentially with circuit size. Therefore, it is com-mon practice to select a limited number of paths usinga static timing-analysis tool that determines the most crit-ical paths in the circuit. Most paths begin and terminatewith sequential elements (scan cells), with a few pathshaving primary inputs (PIs) for start points or primaryoutputs (POs) for endpoints.

    Speed Test and Speed Binning for DSM Designs

    18 IEEE Design & Test of Computers

  • The transition fault model represents a gross delayat every gate terminal. We test transition faults in muchthe same way as path delay faults, but the pattern gen-eration tools select the paths. Transition fault tests tar-get each gate terminal for a slow-to-rise or slow-to-falldelay fault. Engineers use transition test patterns to findmanufacturing defects because such patterns check fordelays at every gate terminal. Engineers use path delaypatterns more for speed binning.

    At-speed scan testing for both path-delay and transi-tion faults requires patterns that launch a transition froma scan cell or PI and then capture the transition at a scancell or PO. The key to perfor


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