High-Frequency, At-Speed Scan ?· high test coverage and reasonable development effort. This article explores applying at-speed scan testing. We ... combined with ATPG to get high enough coverage. The

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  • 0740-7475/03/$17.00 2003 IEEE Copublished by the IEEE CS and the IEEE CASS SeptemberOctober 2003 17

    IC MANUFACTURING TEST is changing, with anincreased emphasis on at-speed testing to maintain testquality for larger, more complex chips and new fabrica-tion processes. Growing gate counts and increasing tim-ing defects with small fabrication technologies forceimprovements in test quality to maintain the quality levelof chips delivered to customers after testing. Improvingthe stuck-at test coverage alone still might leave too manytiming-based defects undetected to reach quality goals.Therefore, at-speed testing is often necessary.

    Scan-based ATPG solutions for at-speed testing ensurehigh test coverage and reasonable development effort.This article explores applying at-speed scan testing. Weintroduce new strategies to optimize ATPG to apply spe-cific clock sequences that are valid with the circuit oper-ation. We also use these strategies to have ATPG generatetests that use internal clocking logic. Furthermore, wecombine the same technique with programmable phase-locked loop (PLL) features to support applying high-fre-quency, at-speed tests from internal PLLs. As a result, wecan base the application of precise clocks for at-speedtests on on-chip clock generator circuitry instead of testers.

    Motivation for at-speed scan testingIC fabrication processes produce a given number of

    defective ICs. Many companies have gotten by with sta-

    tic stuck-at scan testing and a limitedamount of functional test patterns for at-speed testing to uncover these defectiveICs. They often supplement these testswith IDDQ tests, which detect many typesof defects, including some timing-relatedones.1 In the past, these tests effectivelyscreened out enough of the limited num-ber of timing-related defects. However,at the smaller geometry sizes of todays

    ICs, the number of timing-related defects is growing,2 aproblem exacerbated by the reduced effectiveness offunctional and IDDQ testing. Functional testing is lesseffective, because the difficulty and time to generatethese tests grows exponentially with increasing gatecounts. The electrical properties of 0.13-micron andsmaller technologies have caused many companies torely less on IDDQ tests, because a defective devices cur-rent will be difficult to distinguish from the normal qui-escent current. Some have abandoned IDDQ testsaltogether for these small-geometry devices.

    The main force behind the need for at-speed testing isthe defect characteristics of 0.13-micron and smaller tech-nologies that are causing more timing-related defects.3 Forexample, one study on a microprocessor design showedthat if scan-based at-speed tests were removed from thetest program, the escape rate went up nearly 3%.4 This wason a chip with a 0.18-micron feature size.

    We can use functional tests to provide at-speed tests,but the functional test development problem is explod-ing exponentially with chip growth. For a different micro-processor design, the development effort to create thefunctional test set took three person-years to complete.5

    Furthermore, these tests consumed a large percentageof the tester memory, and the test time to run them wassignificant. Because the effort to create effective at-speed

    High-Frequency, At-SpeedScan TestingXijiang Lin, Ron Press, Janusz Rajski, Paul Reuter,Thomas Rinderknecht, Bruce Swanson, and Nagesh TamarapalliMentor Graphics

    Editors note:At-speed scan testing has demonstrated many successes in industry. Onekey feature is its ability to use on-chip clock for accurate timing in theapplication of test vectors in a tester. The authors describe new strategieswhere at-speed scan tests can be applied with internal PLLs. They presenttechniques for optimizing ATPG across multiple clock domains and proposemethodologies to combine both stuck-at-fault and delay-test vectors into aneffective test suite.

    Li-C. Wang, University of California, Santa Barbara

  • functional-test patterns is daunting, more companies aremoving to at-speed scan-based testing.

    Logic BIST can perform at-speed test but is usuallycombined with ATPG to get high enough coverage. Thevalue of logic BIST is that it provides test capabilities,such as secure products or in-system testing, when testeraccess is impossible. Logic BIST uses an on-chip pseudo-random pattern generator (PRPG) to generate pseudo-random data that loads into the scan chains. A secondmultiple-input shift register (MISR) computes a signaturebased on the data that is shifted out of the scan chains.

    There is reasonable speculation that supplementinga high-quality test suite in production with logic BISTmight detect some additional unmodeled defects. At-speed logic BIST is possible using internal PLLs to pro-duce many pseudorandom at-speed tests. However,employing this test strategy requires additional deter-ministic at-speed tests to ensure higher test quality. Thistest strategy also requires adhering to strict design rulechecking and using on-chip hardware to increase testa-bility and avoid capturing unknown values. Some spec-ulate that logic BIST will improve defect coveragebecause it will detect faults many times. However,although it does provide multiple detections, they occuronly at the fault sites that are random-pattern testable.Also, although logic BIST may be useful for transitionfault testing, the low probability of sensitizing criticalpaths with pseudorandom vectors makes logic BISTunsuitable for path delay testing.

    Scan-based tests and ATPG provide a good generalsolution for at-speed testing. This approach is gainingindustry acceptance and is a standard production testrequirement at many companies. However, scan-based,at-speed ATPG grows the pattern set size significantly.This is because it is more complicated to activate andpropagate at-speed faults than stuck-at faults. Becauseof this complexity, compressing multiple at-speed faultsper pattern is less efficient than for stuck-at faults.Fortunately, embedded compression techniques cansupport at-speed scan-based testing without sacrificingquality. When using any kind of embedded compres-sion solution, however, engineers must take care not tointerfere with the functional design, because core logicchanges can significantly affect overall cost.

    Moving high-frequency clocking fromthe tester to the chip

    In the past, most devices were driven directly from anexternally generated clock signal. However, the clockfrequencies that high-performance ICs require cannot

    be easily applied from an external interface. Manydesigns use an on-chip PLL to generate high-speed inter-nal clocks from a far slower external reference signal.The problem of importing high-speed clock signals intothe device is also an issue during at-speed device test-ing. It is difficult and costly to mimic high-frequency(PLL) clocks from a tester interface. Studies have shownthat both high-speed functional and at-speed scan testsare necessary to achieve the highest test coverage pos-sible.4 To control costs, more testing will move from cost-ly functional test to at-speed scan test. Some companieshave already led the way to new at-speed scan testing byusing on-chip PLLs.6 Although this is a new idea, it is gain-ing acceptance and use in industry designs. These tech-niques are useful for any type of scan design, such asmux-DFF or level-sensitive scan design (LSSD).

    Because a delay tests purpose is to verify that the cir-cuitry can operate at a specified clock speed, it makessense to use the actual on-chip clocks, if possible. Younot only get more accurate clocks (and tests), but youalso do not need any high-speed clocks from the tester.This lets you use less-sophisticated, and hence cheap-er, testers. In this scenario, the tester provides the slow-er test shift clocks and control signals, and theprogrammable on-chip clock circuitry provides the at-speed launch and capture clocks.

    To handle these fast on-chip clocks, we haveenhanced ATPG tools to deal with any combination ofclock sequences that on-chip logic might generate.6 TheATPG user must simply define the internal clockingevents and sequences as well as the correspondingexternal signals or clocks that initiate these internal sig-nals. That way the clock control logic and PLL, or otherclock-generating circuitry, can be treated like a blackbox for ATPG purposes, and the pattern generationprocess is simpler.

    At-speed test methodologyThe two prominent fault models for at-speed scan

    testing are the path-delay and transition fault models.Path delay patterns check the combined delay througha predefined list of gates. It is unrealistic to expect to testevery circuit path, because the number of paths increas-es exponentially with circuit size. Therefore, it is com-mon practice to select a limited number of paths usinga static timing-analysis tool that determines the most crit-ical paths in the circuit. Most paths begin and terminatewith sequential elements (scan cells), with a few pathshaving primary inputs (PIs) for start points or primaryoutputs (POs) for endpoints.

    Speed Test and Speed Binning for DSM Designs

    18 IEEE Design & Test of Computers

  • The transition fault model represents a gross delayat every gate terminal. We test transition faults in muchthe same way as path delay faults, but the pattern gen-eration tools select the paths. Transition fault tests tar-get each gate terminal for a slow-to-rise or slow-to-falldelay fault. Engineers use transition test patterns to findmanufacturing defects because such patterns check fordelays at every gate terminal. Engineers use path delaypatterns more for speed binning.

    At-speed scan testing for both path-delay and transi-tion faults requires patterns that launch a transition froma scan cell or PI and then capture the transition at a scancell or PO. The key to performing at-speed testing is togenerate a pair of clock pulses for the launch and cap-ture events. This can be complicated because moderndesigns can contain several clocks operating at differentfrequencies.

    One method of applying the launch and capture eventsis to use the last shift before capture (functional mode) asthe launch eventthat is, the launch-off-shift approach.Figure 1 shows an example waveform for a launch-off-shiftpattern for a mux-DFF type design; you can apply a simi-lar approach to an LSSD. The scan-enable (SE) signal ishigh during test mode (shift) and low when in functionalmode. The figure also shows the launch clock skewed sothat its late in its cycle, and the capture clock is skewed sothat its early in its cycle. This skewing creates a higherlaunch-to-capture clock frequency than the standard shiftclock frequency. (Saxena et al.7 list more launch and cap-ture waveforms used by launch-off-shift approaches.) Themain advantage of this approach is simple test pattern gen-eration. The main disadvantage (for mux-DFF designs) isthat we must treat the SE signal as timing critical. Whenusing a launch-off-shift approach, pipelining an SE withinthe circuit can simplify that SEs timing and design.However, the nonfunctional logic related to operating SEat a high frequency can contribute to yield loss.

    An alternate approach called broadside patternsuses a pair of at-speed clock pulses in functional mode.Figure 2 shows an example waveform for a broadsidepattern. Each clock waveform is crafted to test only asubset of all possible edge relationships between thesame and different clock domains. The first pulse initi-ates (launches) the transition at the targeted terminal,and the second pulse captures the response at a scancell. This method also allows using the late and earlyskewing of the launch and capture clocks within theircycles. The main advantage of this broadside approachis that the timing of the SE transition is no longer criti-cal, because the launch and capture clock pulses occur

    in functional mode. Adding extra dead cycles after thelast shift can give the SE additional time to settle.

    Logic BIST and ATPG test can generate launch-off-shift and broadside patterns. Logic BIST includes clock-control hardware to provide at-speed clocks from a PLL.The clocks sequence is usually constructed in a BISTapproach such that the clocks that control a higheramount of logic will be pulsed more often during thepseudorandom patterns. When using deterministic testpattern generation, an ATPG tool can perform the analy-sis to select the desired clock sequence on a per-patternbasis to detect the specific target faults. ATPG can useprogrammable PLLs for at-speed clock generation if thePLL outputs are programmable. Both logic BIST andATPG generally shift at lower frequencies than thefastest at-speed capture frequencies to avoid powerproblems during shift. In addition, a fast shift frequen-cy would force high-speed design requirements for thescan chain. It is the timing from launch to capture that isimportant for accurate at-speed testing.

    Controlling complex clock-generatorcircuits

    To properly use high-frequency clocks that are gen-erated on chip, engineers must address several issues.

    19SeptemberOctober 2003

    Laun

    ch

    Cap

    ture

    Shift Shift Lastshift

    Capture Shift

    Clock

    Scanenable

    (SE)

    Figure 1. Launch-off-shift pattern timing.

    Laun

    ch

    Cap

    ture

    Shift Shift Deadcycle

    Shift

    Clock

    SE

    Figure 2. Broadside-pattern timing.

  • Sequences of multiple on-chip (internal) clock pulsesare necessary to create the launch and capture eventsneeded for at-speed scan patterns. Engineers can createthem using various combinations of off-chip (external)clocks and control signals. To generate an appropriateinternal clock sequence, it is inefficient to have an ATPGengine work back through complex clock generators todetermine the necessary external clock pulses and con-trol signals for every pattern. Furthermore, you cannotlet the ATPG engine choose the internal clock sequenceswithout regard for the clock-generation logic, becausethe ATPG engine might use internal clock sequencesthat cannot be created on chip.

    To solve these issues, we have implemented an inno-vative ATPG approach that lets you specify legal clocksequences to the tool using one or more named-captureprocedures. These named-capture procedures describea sequence of events grouped in test cycles. Includedin each procedure is the way the internal clock

    sequence can be issued along with the correspondingsequence of external clocks or events (condition state-ments) required to generate it. Using these procedures,you can specify all legal clock sequences needed to testthe at-speed faults to the tool. The ATPG engine can per-form pattern generation while only considering theinternal clocks, their legal sequences, and the internalconditions that must be set up to produce the clocksequence. The final scan patterns are saved using theexternal clock sequences by automatically mappingeach internal clock sequence to its corresponding exter-nal clock/control sequence. Using internal and exter-nal clock sequences (plus control signals) is efficientfor behaviorally modeling the clock-generation...

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