High-Level Constructors and Estimators

Majid Sarrafzadeh and Jason CongMajid Sarrafzadeh and Jason Cong

Computer Science DepartmentComputer Science Department

UCLAUCLA

{majid,cong}@cs.ucla.edu{majid,cong}@cs.ucla.edu

An Overview of PACT

•Architectural Primitives•Cells

Application in C

PACT cc

PACT sim

PACT EstimatePACT Synth

Commodity System

ApplicationSpecific System

Overview of PACT

Power Aware Compilers1. Optimization framework2. Library function characterizations3. High-level transformations4. Low-level transformations

Power Aware CAD1. Behavioral power estimation2. Behavioral low-power synthesis3. Logic level power estimation4. Logic level low-power synthesis

Power-Aware Applications1. Enable new missions2. Enable new capabilities

Power Aware Architectures1. Develop power aware methodologies 4. Software/hardware techniques2. Apply methods to specific structures 5. Profiling techniques3. Hardware only techniques

 

Power Aware CAD Behavioral level high-level power estimationBehavioral level high-level power estimation

Estimate power consumption at RTL VHDL level using switching tablesEstimate power consumption at RTL VHDL level using switching tables

Behavioral level low-power synthesisBehavioral level low-power synthesis Use high-level power estimation to drive CDFG operation scheduling and Use high-level power estimation to drive CDFG operation scheduling and

resource allocation for low-powerresource allocation for low-power

Logic/layout level accurate power estimationLogic/layout level accurate power estimation Develop stochastic techniques for combinational and sequential circuitsDevelop stochastic techniques for combinational and sequential circuits

Logic/layout level low-power synthesisLogic/layout level low-power synthesis Use power estimators to perform low-power logic synthesis such as gate sizing, Use power estimators to perform low-power logic synthesis such as gate sizing,

clock gatingclock gating

Power Aware CAD

RTL VHDL Input

ParserBuilds CDFG

Behavioral powerestimator

Behavioral synthesis(Schedule, Allocate,

floorplan)

Logic power estimate(deterministic, prob.

stochastic)

Logic synthesis(global factoringlocal resizing)

Netlist of gates withpower controlPower models

Resourcelibrary

Resourcecharacterize

Compiler

Architecture

High Level Power Estimation: Motivation

The breed of new systems is going to be ultra complex with rich The breed of new systems is going to be ultra complex with rich computational functionality and networking capabilities. computational functionality and networking capabilities.

These devices will be mobile and low power will be a major These devices will be mobile and low power will be a major concern in their design process.concern in their design process.

Efficient power estimation technique will enable faster time to Efficient power estimation technique will enable faster time to market.market.

Power Estimation: Requirements Quick estimation methodology to enable efficient Quick estimation methodology to enable efficient

design space explorationdesign space exploration The estimation methodology should be sufficiently The estimation methodology should be sufficiently

“early on” to enable large improvements“early on” to enable large improvements It should strike the correct balance between It should strike the correct balance between

simplicity in abstraction and accuracy of predictionsimplicity in abstraction and accuracy of prediction It should not go through the whole flow of Logic It should not go through the whole flow of Logic

Synthesis and Physical Design to do the estimationSynthesis and Physical Design to do the estimation

Our Approach

Study of the Effects of Individual optimization steps Study of the Effects of Individual optimization steps in the design process on the overall accuracy of in the design process on the overall accuracy of power prediction. power prediction.

This would enable us come up with confidence This would enable us come up with confidence numbers associated with each prediction. These numbers associated with each prediction. These confidence numbers could be used by optimization confidence numbers could be used by optimization steps to drive architectural explorationsteps to drive architectural exploration

Points

FACT: Certain designs are more predictable than FACT: Certain designs are more predictable than others, example simple DFG kind of computations others, example simple DFG kind of computations can have higher predictability than designs with can have higher predictability than designs with loops and conditional statementsloops and conditional statementsQuestion:Question: WHY? WHY?

To answer this we will study the effects of various To answer this we will study the effects of various computations of accuracy. computations of accuracy.

Some Preliminary Results

+

C2C1C0 C3

FIR Filter

Scheduling and Binding Solution-I

+

+

+

* *

*

*

Binding Of Operations

Clock-1

Clock-2

Clock-3

Clock-4

Two Adders, Two Multipliers

Scheduling and Binding Solution-II

+

+

+

* *

*

*

Binding Of Operations

Clock-1

Clock-2

Clock-3

Clock-4

Two Adders, Two Multipliers

ComparisonFor Solution IFor Solution I

Combinational Gate Area: 815Combinational Gate Area: 815Flip Flop Area: 631Flip Flop Area: 631Power: 3.20 uwPower: 3.20 uw

For Solution IIFor Solution IICombinational Gate Area: 823Combinational Gate Area: 823Flip Flop Area: 687Flip Flop Area: 687Power: 3.20 uwPower: 3.20 uw

Solution X (changing resources): all over the mapSolution X (changing resources): all over the map

Framework Of Expriments

Synopsys BC, DC and Power CompilerSynopsys BC, DC and Power Compiler

The Power values were obtained by doing an RTL The Power values were obtained by doing an RTL simulation of the design and extracting the switching simulation of the design and extracting the switching activity. This activity was annotated to the gate level activity. This activity was annotated to the gate level netlist and power values were extracted at gate levelnetlist and power values were extracted at gate level

Basic Analysis of Results If the number of clock cycles and number of If the number of clock cycles and number of

resources do not change, If the test vectors are resources do not change, If the test vectors are randomly distributed, then there is not a significant randomly distributed, then there is not a significant variation in the power value of various bindings for variation in the power value of various bindings for DFG kind of applications. Hence estimation at this DFG kind of applications. Hence estimation at this step should have a high value of step should have a high value of predictabilitypredictability. .

This claim has to be validated by a lot of This claim has to be validated by a lot of experimentation with much larger benchmarksexperimentation with much larger benchmarks

Needs for Efficient Interconnect Estimation Models EfficiencyEfficiency AbstractionAbstraction to hide detailed design information to hide detailed design information

granularity of wire segmentationgranularity of wire segmentation number of wire widths, buffer sizes, ...number of wire widths, buffer sizes, ...

Explicit relationExplicit relation to enable optimal design decision at to enable optimal design decision at high levelshigh levels

Ease of interactionEase of interaction with logic/high level synthesis tools with logic/high level synthesis tools

Develop a set of Develop a set of interconnect performance estimation interconnect performance estimation modelsmodels ( (IPEMIPEM), under different optimization alternatives:), under different optimization alternatives: Optimal Wire Sizing Optimal Wire Sizing (OWS)(OWS) Simultaneous Driver and Wire Sizing Simultaneous Driver and Wire Sizing (SDWS)(SDWS) Simultaneous Buffer Insertion and Wire Sizing Simultaneous Buffer Insertion and Wire Sizing (BIWS)(BIWS) Simultaneous Buffer Insertion/Sizing and Wire Sizing Simultaneous Buffer Insertion/Sizing and Wire Sizing

(BISWS)(BISWS)

Interconnect Performance Estimation Modeling [Cong-Pan, ASPDAC’99, TAU’99, DAC’99]

Area Estimation for OWS

0

0.5

1

1.5

2

0 4000 8000 12000 16000 20000

length(um)

Model TRIO

Some Applications of IPEM Layout-driven physical and RTL level floorplanningLayout-driven physical and RTL level floorplanning

Predict accuratePredict accurate interconnect delay and routing interconnect delay and routing resource resource without really going into layout details;without really going into layout details;

Use accurate interconnect delay/area to guide Use accurate interconnect delay/area to guide floorplanning/placementfloorplanning/placement

Interconnect Architecture PlanningInterconnect Architecture Planning E.g. Wire width planningE.g. Wire width planning

Floorplanning + interconnect planningFloorplanning + interconnect planning E.g. Buffer block planningE.g. Buffer block planning

Available from Available from http://cadlab.cs.ucla.edu/~conghttp://cadlab.cs.ucla.edu/~cong

Conclusions Prediction can be done only on some specific problemsPrediction can be done only on some specific problems

Classify problems/steps that are predictableClassify problems/steps that are predictable To get good estimation, we may have to construct/commitTo get good estimation, we may have to construct/commit

More so, as more degrees of freedom (clock gating, More so, as more degrees of freedom (clock gating, sleep more, architectural “tricks”, …)sleep more, architectural “tricks”, …)

How to effectively combine predictors and constructors?How to effectively combine predictors and constructors?{majid, cong}@cs.ucla.edu{majid, cong}@cs.ucla.edu