high speed serial data link analysis - ansys uk/staticassets/high... · high speed serial data link...

© 2010 ANSYS, Inc. All rights reserved. 1 ANSYS, Inc. Proprietary© 2010 ANSYS, Inc. All rights reserved. 1 ANSYS, Inc. Proprietary

High Speed Serial

Data Link Analysis

© 2010 ANSYS, Inc. All rights reserved. 2 ANSYS, Inc. Proprietary

Agenda

• High-Speed Signal Data Path

• Simulation Requirements

• Ansoft HSSD Analysis Solution

• 3 Steps to Analysis HSSD Performance

– Step 1: Build the channel

– Step 2: Check Frequency Domain Performance

– Step 3: Check Time Domain Performance

• Demonstration


High-speed serial system design

• Evaluate the performance of the link between a

transmitter and a receiver


High-Speed Signal Path

• High-Speed Signal Path

• Discontinuities will distort signal quality and reduce

overall bandwidth of the system

Tx +

-

+

-

Rcvpath +

-

+

-


Simulation

Requirements


Simulation Requirements

• Components must be modeled using full-wave S-parameters

– S-parameters provide the best representation of the electrical

characteristics of very high-speed interconnects.



• Simulator must provide reliability and capacity for multi-gigabit

channel modeling

– Including S-parameters in transient simulations

– Maintaining passivity and causality

– Address multiple channel paths

– Combine transistor-level models of transceivers, pre-emphasis circuits

and equalizers with extracted full-wave parasitics.

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20__UnitInterval

1.00E-015

1.00E-014

1.00E-013

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

AE

YE

PR

OB

E(r

equired)

Ansoft LLC Nexxim1BER Bathtub ANSOFT

Curve Info

fcutoff='300MHz'

fcutoff='325MHz'

fcutoff='350MHz'

fcutoff='375MHz'

fcutoff='400MHz'



• GHz designs must include frequency- and-time domain

simulations to correctly predict system performance

– High-performance electronic designs often include operating

specifications in the time domain and in the frequency domain.


Ansoft HSSD

Analysis Solution


IC/Package/Board Simulation

HFSSTM

, SIwaveTM

, DesignerSITM

and Nexxim®

Tools overview

• HFSSTM

: general purpose full-wave 3D extraction

• SIwaveTM

: full-wave extraction of merged Package and Board model

• DesignerSITM

: schematic level design integration and management, transient simulation using S-Parameters with simulation accuracy, capacity, and speed with consistency across frequency- and time-domains.


HFSS

• Models arbitrary 3D geometries

– Connector Models

– IC Packages

– Vias


Why is HFSS the Accepted Industry

Standard for Accuracy?

• The mesh is automatically created and adapted for accuracy.

Create Initial

Mesh

Solve fields using the

Finite Element Method

Max(|DS|)<goal?Calculate local

Solution error

Generate

New Mesh

Calculate broad band

s-parameters (if desired)

no

yes


SIwave

• What is SIwave?

– Hybrid 2.5D full wave EM field solver

– Models layered structures

– Analyses performed

• Signal Integrity

• Power Integrity

• Electromagnetic

Compatibility/Interference


2D Extractor

• 2D field solver within it– 2D Extractor™

• A Must have for transmission line modeling (key requirement for pre-layout SI design)

– Creates Tabular W-elements

– Industry Golden Standard

• Parameterize with ease

• Analysis suite

– Parametrics

– Optimization

– Sensitivity

– Statistical

– TuningDifferent ‘thickness’


• Etching Factor

• Zo diff varies from 93.28 – 98.54 Ohms

W (mil) Z dif f (Ohm)

3.75 98.54

4.00 98.32

4.25 98.11

4.50 97.93

4.75 97.66

5.00 97.45

5.25 97.21

5.50 96.85

5.75 96.57

6.00 96.21

6.25 95.82

6.50 95.42

6.75 94.93

7.00 94.46

7.25 93.91

7.50 93.28

2D Extractor Manufacturer Tolerances


Ansoft Designer

Design Management Framework

• Fully Integrated Design Environment

– Schematic & Layout

– Time and frequency domain circuit simulator

– Component Libraries and Design Kits

• True Co-Simulation thanks to Dynamic Links with HFSS, SIwave, Q3D, 2D Extractor

• Import data from a variety of sources

– Spice netlists, S-parameters, W-elements

– Analytical Models (RLC, Tline, diode …)

– IBIS Models

• Powerfull Post-processing including signal integrity metrics, such as SSN, SSO, TDR, BER and eye diagrams

• QuickEyeTM and VerifEyeTM

– Fast convolution and statistical eye analysis of transient solutions

• IBIS- AMI (Algorithmic Modeling Interface)


Pre-Layout Channel

1 2 3 4 5 6 7

0 = SMP Connectors (HFSS)1 = Driver-Side Via Stub (Full Stackup HFSS Model)2 = Switch PCB Model (W-Elements from Q3D/2D)3 = Connector Model (HFSS)4 = Mid-plane PCB Model (W-Elements from Q3D/2D)5 = Connector Model (HFSS)6 = Blade PCB Model (W-Elements from Q3D/2D)7 = Receiver-Side Via Stub (Full Stackup HFSS Model)

0 0

0 00 00 0 0 0 0 00 00 0

0

0

0

0

Port1 Port2

Port3 Port4

HFSS

Switch

smp_p

smp_n

sw_p

sw_n

ref

1

2

W1237

1

2

W1238

1

2

W1239

HFSS

VHDM

+

- -

+

ref

HFSS

VHDM

+

- -

+

ref

switch

ref

switch

ref

blade

ref

blade

ref

HFSS

Mid-Plane

conn_p

conn_n

mid_p

mid_n

ref

HFSS

Mid-Plane

conn_p

conn_n

mid_p

mid_n

ref

HFSS

Blade

blade_p

blade_n

smp_p

smp_n

ref

Switch

HFSSsw_p

sw_n

conn_p

conn_n

ref

Blade

HFSSconn_p

conn_n

blade_p

blade_n

ref

HFSS

HFSS HFSS HFSS HFSS HFSS HFSS

2D Model 2D Model2D Model

HFSS

5.5” 18.25” 2.5”

HFSS HFSS


Post Layout Simulation

1 = Switch PCB Model (SIwave)2 = Connector Model (HFSS)3 = Mid-plane PCB Model (SIwave)4 = Connector Model (HFSS)5 = Blade PCB Model (SIwave)

54321

0 0 0 0 0

0

0

0

0

Port1 Port2

Port3 Port4

Mid-Plane

sw+

sw- blade-

blade+

ref

Blade

conn+

conn- smp-

smp+

ref

SWITCH

smp+

smp- conn-

conn+

ref

HFSS

C

ref

HFSS

C

ref

switch

ref

switch

ref

blade

ref

blade

ref

0 0SIwave SIwave SIwaveHFSS HFSS

HFSS HFSS


3 Steps to Analysis

HSSD Performance


Step 1:

Build the channel


Component

• Analytical Model

– Transmissiom Line

• Single/Differantial

– W-elements

• Imported Model

– Dynamic link

• HFSS, Siwave, 2D Exttractor,

Q3D

– Nport Model

• S parameter, NMF

– C Model

– Matlab Model

• Imported Netlist

– Spice, Spectre, HSPICE

1

2

P=1mmW1=1mmS1=1mmW2=1mmsub=Substrate

1

2

W5


Simple Channel Example

0 0 0 0

1

2

p1_N

p2_P

p3_N

p4_P

p1_N

p2_P

p3_N

p4_P1

2

ID=8

ID=

950

R1

0

HFSS Model

W element from netlist

S parameter


Step 2:

Check Frequency

Domain Performance


0.00 2.00 4.00 6.00 8.00 10.00F [GHz]

-45.00

-35.00

-25.00

-15.00

-5.00

0.00

Y1

Ansoft LLC S_ParameterTerminal ANSOFT

Curve Info

dB(S(Port1,Port1))

dB(S(Port1,Port2))

Frequency Domain: S, Y, Z parameter

• Differential

• Terminal

0 0

Port1 Port2

Port3

Port4

1

2

1

2

p1_N

p2_P

p3_N

p4_P

p1_N

p2_P

p3_N

p4_P

0.00 2.00 4.00 6.00 8.00 10.00F [GHz]

-70.00

-60.00

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

Y1

Ansoft LLC S_ParameterDiferential ANSOFT

Curve Info

dB(S(Diff1,Diff1))

dB(S(Diff1,Diff2))

dB(S(Diff1,Comm1))


Designer - S-parameter Analyzer

• Matrix color-coded visualization

• Large data set handling

• Multiple formats and data types• S, Y, Z matrices

• db, mag, phase…

• Statistical values – Average, min,

max, std deviation…

• Port post-processing options

• Renormalize

• Re-order

• De-embed (if Gamma defined).

• Passivity check option

• Multiple S-parameters support

• Statistical information


Check State-Space

0.00 2.00 4.00 6.00 8.00 10.00F [GHz]

-45.00

-40.00

-35.00

-30.00

-25.00

-20.00

-15.00

-10.00

-5.00

0.00

Y1

Ansoft LLC S_ParameterXY Plot 1 ANSOFT

Curve Info

S11 dB S parametersFreqDomain

S12 dB S parametersFreqDomain

S11 dB State SpaceStateSpace

S12 dB State SpaceStateSpace

• Verify State-Space Macro Model over S parameter

• Option to create state-space in Frequency domain analysis

• Manage fitting accuracy

• Compare using plot or Network Analyzer

• Causality Check


Step 3:

Check Time Domain

Performance


Time Domain Study

• Signal Integrity and Timing Studies

– Standard transient waveform and serial

data/clock analysis

• Investigate basic time-domain metrics

– Voltage max and min values

– Overshoot, rise time High-Speed System

Design and Analysis

– System performance metrics including

• Eye statistics

• Inter-symbol interference (ISI)

• Bit-error rate (BER)

– Data recovery

– Entire high-speed interconnect

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20

__UnitInterval

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

AE

YE

PR

OB

E(o

ut)

Ansoft Corporation PostLayoutStatVerifEye_Bathtub_jjb

0.0000

MX1: 0.2621

MX2: 0.7678

Curve Info

AEYEPROBE(out)

VerifEyeAnalysis

0.00 2.00 4.00 6.00 8.00 10.00Time [ns]

-0.50

0.00

0.50

1.00

1.50

Y1

[V

]

Ansoft LLC DifferentialDelay ANSOFT

Curve Info

V(In_Line_P)-V(In_Line_N)spacing='0.6mm'

V(Out_Line_P)-V(Out_Line_N)spacing='0.6mm'


Which Analysis?

• Transient

– When non LTI Circuit

• VerifEye

– Statistical BER investigation

• QuickEye

– Fast Convolution

• IBIS AMI

– Fast Convolution with compiled model


Designer - Transient Analysis

44 port S-parameter model

148,000 MOSFETs

1.7 Million Capacitors

500,000 Resistors

• Full SPICE accuracy variable timestep transient

• Full support for active and passive circuitry

• Solutions for frequency domain models

• State-space

• Convolution

• Passivity and Causality checking/enforcement

• Multiple numeric algorithms

• Trapezoidal

• Gear

• NDF2

• Multiple DC convergence options

• Beta/device continuation

• Device continuation

• Pseudo-transient

• Modified beta/device

• Alpha, beta, & device


Designer - VerifEye Analysis

• Statistical based analysis

• Setup includes

• Risetime, jitter, equalization and

bitrate

• Support for multiple probes at

different locations in channel

• 8b/10b Encoding

• Parametric variation solutions

• VerifEye outputs

• Bit error rate (BER) contour

and bathtub plots

• Post Analysis Jitter and Noise

• Gaussian and Uniform

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20__UnitInterval

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

1.00E+001

AE

YE

PR

OB

E(r

equired)

Ansoft Corporation StatisticalXY Plot 1

Curve Info

AEYEPROBE(required)VE_jitter_sweep__Amplitude='0.3258549673' jitter='2ps'





Designer - QuickEye Analysis

• Convolution based bit analysis

• Setup includes

– Risetime, jitter, equalization

custom bitrates and patterns

• Support for multiple probes at

different locations in channel

• Parameters can be swept

• Peak Distortion Analysis

• 8b/10b Encoding

• QuickEye outputs

– Pulse response, contour plots, VT

curves and eye diagrams

• Eye diagrams include

– Histograms, eye masks, mask

violations, characteristics


Designer-IBIS AMI

• IBIS AMI (IBIS Algorithmic Modeling Interface)

– New standard provides encryption alternative

– Analysis support, similar to QuickEye

• Impulse Response based

– Parameterized Model support

• Compiled Drivers and Receiver Models


Focus on QE


Determine worst case bit pattern - QE

• Peak Distortion Analysis (PDA)

• Based on deviations in the step response

• Results can be used to provide the bit pattern for

QuickEye eye sources

PRBS11 Peak Distortion Analysis


Evaluate Impact of TX Jitter - QE

• TX Jitter

– Jitter amplification is present

• TX DCD

• TX RJ – Gaussian

• TX UJ

• TX PJ


Evaluate Impact of RX Jitter & Noise - QE

• Receiver Jitter/Noise

– Modeled with PDF distribution

• RX Gaussian RJ

• RX UJ

• RX Noise

– Gaussian

– Uniform

• Two options:

– Receiver jitter for time deviations in the clock

– Receiver noise for voltage deviations (e.g. power

supply noise)


Threshold Detection - VE

• Minimum Latch Overdrive

– Separate high/low decisions for BER

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20__UnitInterval

1.00E-015

1.00E-014

1.00E-013

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

Y1

Ansoft Corporation channel_statisticalXY Plot 2

Curve Info

AEYEPROBE(probe_out)VerifEye__Amplitude='0.0002303681338V'

AEYEPROBE(probe_out)1Imported__Amplitude='0.0002303681338V'


Crosstalk Analysis - QE and VE

• Cross-talk Analyses

– Independent voltages,

resistances, FFE, DFE,

data rates, phase

relationships, bit

patterns, and mixing of

SE and Differential

channels

– Allows mixing of

different bus

architectures

• PCIe, SATA, SAS, DDR,

ClKs,…User has control of

initial transient step

response to ensure

settling has occured


Insert Equalization - QE

• Feed Forward Equalizer

– N taps (pre and post-cursor)

• Automatic tap weight

determination

• User specified (completely

parameterizable) tap weights

• Decision Feedback Equalizer

– N taps

• Automatic tap weight

determination

• User specified (completely

parameterizable) tap weights


QE Demo


Validation:

HDMI Channel


Validation:HDMI Channel

• This case highlights the benefits of the

modular platform.

• TMDS (transition minimized differential

signaling) is the serial-link spec used

to transmit the data – SPEEDS.

• A HDMI Type-A Test Adapter (provided

by Efficere*) is used to interface HDMI

assemblies to measurement

equipment.

*Efficere Technologies - http://www.efficere.com/


HDMI Channel Setup

Instrumentation

test adapter

HDMI Assembly

(connectors + cable)

test adapter

2.5m and 10m


HDMI Adapter Details

HDMI

Receptacle

cable to Sampling Scope

and TDR head

PCB Traces

GPPO

connector

Blue cable

SMA

HDMI Connector

and Cable


HDMI Adapter Design - HFSS

HFSS used to design and model the GPPO

connector launch – virtual prototyping leads

to industry-leading performance for adapter.

Transmission line (W-element)

models were output

from the HFSS waveport data.

So … three models with

one simulation!

PCB microstrip

coax


TDR Measurement Detail: Adapter

DC1 receptacle

SMA

blue

coax

GPPO

PCB

mstripHDMI cable …

These other traces were created by

disconnecting the adapter at different

locations. They are helpful in constructing

models and identifying exact locations

HDMI connector


Hybrid Simulation-Measurement

Procedure

Design

Build and

MeasureModel

Simulate


HDMI Channel Validation

Measured

Simulated

SMA

blue

cable

GPPO

pcb

mstrip

HDMI

connector


TDR-based, VNA, and Ansoft

Results

THRU

2.5m cable

-15dB

-15dB


Thank You

high speed serial data link analysis - ansys uk/staticassets/high... · high speed serial data link...

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