high-speed serial interface

High-speed Serial Interface

Lect. 9 – Noises

2013-1High-Speed Circuits and Systems Lab., Yonsei University1

Block diagram


Serializer Sampler

ClockRecovery

Deserializer

PLL

Channel

Tx Rx

• Where are we today?

RxEqualizer

TxDriver

Sampling in Rx• Interface applications usually employ binary-

level signaling– Rx samples input signal with single threshold.


ChannelDATA

Sampler

Tx Rx

SamplingPoint

Threshold

InputSignal

Noise in time domain• Noises in high-speed interface can be easily

observed in time-domain– Noise waveform is added on the signal waveform


SamplingPoint

How noise affects sampling?• Noise at sampling point can cause wrong

sampling


SamplingPoint

How noise affects sampling?• Noise can disturb the disturb sampling point

– Noise can distorts clock generation both in Tx and Rx.– If sampling point goes outside of data period, sampling results in

wrong data.– Timing noise reduces sampling margin.


SamplingPoint

TxCLK

How noise affects sampling?• AM-to-PM noise conversion

– Amplitude noise at signal transition reduces timing margin.– Shorter the transition time, less the noise conversion


Threshold

Bit period

Timing margin

Jitter• Definition

– “Jitter is the undesired deviation from true periodicity of an assumed periodic signal in electronics and telecommunications, often in relation to a reference clock source.” –by wikipedia

– Jitter is noise observation in time domain.• Amplitude noise can be also observed as jitter

– Jitter reduces timing margin of sampling


Bit-error rate (BER)• Most important performance metric.

– BER shows end-to-end system performance.– Timing margin is evaluated from BER performance.

• BER is calculated as follows;

=


Bit-error rate (BER)


BER: Probability that the noise will exceed a given value

Bit-error rate (BER)• For Gaussian noises,

Probability that the noise will exceed a given value:


Bath-tub


http://prphotos.tm.agilent.com/2009/19oct-em09165/

Eye-diagram BER contour

Bath-tubfor

Timing

Bath-tubfor

Amplitude

Timing margin for BER<10-6 and 10-12

Where are noises from?• Device noise

• Channel noise

• Power supply

• Coupling


Device noise• Noise sources in MOSFETs

– Thermal noise in the channel– 1/f noise– Noise in the resistive poly gate– Noise due to the distributed substrate resistance– Shot noise associated with the leakage current of the drain

source reverse diodes* Reference: “ http://www.nikhef.nl/~jds/vlsi/noise/sansen.pdf ”

• Noise sources in other devices– resistor / capacitor / diode


Device noise• Device noise in amplifiers

– Device noise of Tx output and Rx input buffer stage generate random noise.

– This kind of noise is not significant in electrical-channel-based interface since the signal amplitude is usually large enough.

• Device noise in clock generators– Device noise of Tx clock generator and Rx clock recovery circuit

generate random noise.– This noise is significant and will be covered in next lectures.


Device noise• Duty-cycle distortion

– Originally metric of clock generation.– This kind of noise is deterministic and static.– Duty-cycle distortion gives asymmetric timing margin for high

and low signal.– Defined as follows;

= " "2013-1High-Speed Circuits and Systems Lab., Yonsei University16

Threshold

ClockSignal

Period of “High”

Bit period


– Single-ended signaling: threshold variation• Single-ended signaling requires threshold which is usually

generated in Rx side.• If threshold is not exactly mid-level, duty cycle is distorted.


Threshold > 0.5

InputSignal


Bit period

Duty cycle = 50%

Duty cycle < 50%


– Differential signaling: differential offset• Differential amplifier has differential

offset which is caused by mismatch of input transistor pair.

• Cross-point of differential signals is changed, thus, duty-cycle is distorted.


InputSignal +

InputSignal -


Bit period

Duty cycle < 50%

OUT-

IN+

OUT+

Ibias

Zload Zload

gm gm IN-

Channel noise• Random noise

– Electrical channel• Thermal noise in electrical channel generate random noise.• This kind of noise is not significant compared to channel ISI since

the signal amplitude is usually large enough.


Channel noise• Inter-symbol interference

– ISI is covered in previous lectures.– Reduces both amplitude and timing margin.– Dominant noise source in BW-limited channel.


Power supply noise• Performance degrades by power supply noise

– Lowered power supply voltage results in BW limitation.• Transition time is enlarged. AM-to-PM noise conversion ↑

– Decision threshold• Threshold voltage of CMOS logic is defined by P/N ratio and supply

voltage.

– Bias condition• Bias condition (gm or rout) is changed as supply voltage changes


Power supply noise• IR drop in power-supply rail

– Power supply rail is resistive channel• Large current drawing results in significant voltage drop.• Resistance is reduced by large-width of supply rail.• Power supply branching topology is also important.• The width and topology of power-supply rail should not be the main

limiting factor in PCB or IC design.


Device#1

Device#2

Device#3

VDD

I1 I2 I3VDD1 VDD2 VDD3

Power supply noise• Self-generated supply noise

– Power supply rail is also inductive channel• BW of current flowing is limited.• Capacitances are located near devices.

– Instantaneous current drawing results in peak on the supply.


OUTIN

VDD

VSS

IN

VSS

VDD

OUT

SupplySource

SupplySource

Power supply noise• Induced supply noise

– Supply noise from the external noise source• Power management IC cannot reject noise perfectly.

– Supply noise from adjacent device• Supply noise is generated from device sharing power supply rail


InterfaceChip

DC-DCConverter

Digital Signal Processing

Chip

220V AC

Power supply noise• How to minimize the effect of power supply

noise?– 1. supply filtering

• Supply noise can be filtered by external components.• Trade-off in supply filtering and the number of external components


InterfaceChip

DC-DCConverter

Digital Signal Processing

Chip

220V AC

Bead BeadCAP CAP

LC-typeSupply filter

(Ferrite bead, Ferrite choke)

Power supply noise• How to avoid the effect of power supply noise?

– 2. on-chip supply regulator• Supply regulator can be integrated on the IC.• Internal VDD is reduced.• Very large capacitors should be integrated.


VDD

Devices

VSS

Internal VDD

Vref

Power supply noise• How to avoid the effect of power supply noise?

– 3. circuit topology using differential signaling• Single-ended signaling suffers from threshold variation by supply

noise.• Threshold of differential signaling is defined as crossing point.

• Differential signaling requires much larger power consumption and chip area. trade-off


Threshold

InputSignal

InputSignal +

InputSignal -

Single-ended signaling Differential signaling

Coupling noise• Crosstalk between lanes

– Neighboring channels have both capacitive and inductive coupling


ZsZo

ZoZo

Mutual Capacitance, Cm Mutual Inductance, Lm

ZsZo

ZoZo

Cm

Lm

near

far

near

fardtdILV mLm

dtdVCI mCm

Coupling noise– Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT)


ZsZo

ZoZo

ZsZo

ZoZo

ICmLm

near

far

near

far

ILm

LmCmfarLmCmnear IIIIII

Coupling noise– Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT)


Driven Line

Un-driven Line“victim”

DriverZs

Zo

ZoZo

Near End

Far End

Coupling noise


TD

2TD

~Tr

~Tr

far end crosstalk

Near end crosstalk

Zo

V

Time = 2TD

ZoNear end Terminated at T=2TD

V

Time = 0

Zo

Near end crosstalk pulse at T=0 (Inear)

Far end crosstalk pulse at T=0 (Ifar)

Zo

ZoV

Time= 1/2 TD

ZoV

Time= TD

Zo Far end terminated at T=TD

Coupling noise• How to minimize inter-lane crosstalk?

– Enlarge space between channel• Most effective but trade-off with PCB artwork.

– Adjust transition timing of each lane• Split transition timing of adjacent lanes.

– ex) ½ UI delayed timing for even-numbered lanes.» Fluctuation appears at center of data period

– Compensate coupling at Tx side• Tx knows output data patterns of all lanes.


Coupling noise• Inter-chip crosstalk

– Similar coupling problem appears on the IC level.


N coupled lines: (a) capacitive coupling only, (b) inductive coupling only, and (c) capacitive and inductive coupling.Victoria Vishnyakov, “Multi-aggressor capacitive and inductive coupling noise modeling and mitigation” Microelectronics journal, 2012

Coupling noise• How to minimize inter-chip crosstalk?

– Separate sensitive signals

– Shield signal lines• Employing grounded-shielding line • Layout effort / area issues

– Use different metal layers for adjacent lanes• Usually minimum spacing within the same metal layer is much smaller

than the separation between metal layers

– Perpendicular routing for vertical metal layers (Manhattan routing)

– Limit maximum parallel routing distance


Coupling noise• How to minimize inter-chip crosstalk?

– Maximize signal transition time

– For differential signals, periodically twist routing

– Separate sensitive signals


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