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High-speed Serial Interface

Lect. 12 – Charge-pump PLL (VCO)

2013-1High-Speed Circuits and Systems Lab., Yonsei University1

CPPLL• CPPLL consists of

– Phase frequency detector (PFD)– Charge pump– Loop filter– Voltage-controlled oscillator– Divider


LoopFilter

VoltageControlledOscillator

MainDivider

ϕout

ϕref PD +Charge pump

LoopFilter

VCO• Ring-type VCO

– Circular connection of inverter chain



– Two conditions for oscillation (Barkhausen’s oscillation criteria)• Gain = 1 at oscillation frequency ω0

• Total phase shift around the loop is 2n at oscillation frequency ω0



– Single-ended VCO cell


IN OUT

Currentcontrolled

IN OUT

Resistorcontrolled

IN OUT

Supplycontrolled

(usingSupply regulator)

Cloadcontrolled


– Differential VCO

– Ring-type VCO is compact and widely used for generating clock signals in many digital systems

– Its phase noise performance is not very good – It is difficult to produce very high-frequency signals


Currentcontrolled

Rloadcontrolled

VCO• LC-type VCO

– Ideal LC tank


L C Z(w)

2

1( ) ||1j LZ j L

j C LC

1when ω , Z ω goes toLC

VCO• LC-type VCO

– Real LC-tank


LC Z(w)

2

1( ) ||1

j L RZ j L Rj C j RC LC

R

never goes toZ

VCO• LC-type VCO

– Oscillation with additional element


21j RC LCGm

j L R

LC Y(w)

R

Gm

1( )Y Z Gm

2

00 when

1 0RC LGm

Y ωRGm ω LC

21j RC LGm RGm LCj L R

1andRC RGmGm ωL LC

Negative Registance (or gain)

VCO• LC-type VCO

– How to realize negative resistance?


R

V+

I

Negative Gm

V+

I

VCO• LC-type VCO

– Negative resistance by cross-couple MOS pair.


V+ V-

Gm ~ -gm/2

VCO• LC-type VCO

– Frequency tuning? • Inductor: Passive component of metal.• Capacitor can be realized with MOS varactor


VCO• LC-type VCO

– Various topologies are possible


Ultra-Low-Voltage (ULV) PLL(Design Example)

High Speed Circuits & Systems Laboratory

Joungwook Moon

2013. 05. 07

Why Ultra Low Voltage?

• Demands for Low-power consumption– Increasing hand-hold devices

(Need longer battary life)– Limiting system power budget

(Max. power limitation)

• Decreasing VDD is one of the effective way–

(CMOS dynamic power consumption)

212

P CV F

Can Supply Voltage Be Decreased?

2010 2012 2014 2016 2018 2020 2022 2024 20260.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75S

uppl

y V

olta

ge (V

)

Year

• ITRS 2012, Supply Voltage is declining

What about Vth ?

• Vth cannot be scaled-down easily– Significant increase of the subthreshold leakage current

2009 ITRS Vth & Leakage current information

Design Target & Consideration

• Design Target- 0.4 V ULV PLL- Max. 100 uW power consumption- 350 MHz CLK freq.

• Design Consideration- Overcome Voltage headroom @ CP & VCO

(Multi-stacked circuits are prohibited )- Maximize output frequency- Meet the power budget

(maximize power efficiency)

ULV PLL Architecture

• CPPLL with Active Loop filter archtecture

Charge Pump

Mismatch-free 4-stacked CP @ EL 2000 Proposed CP

• Conventional multi-stacked CP cannot work with ULV supply

- Overcome Voltage headroom & current mismatch

Active Loop Filter (1)

2 1

2 1

1( ) sR CVoutF sVin sR C

c

• OP-amp noise and linearity can impact PLL performance

• OP-amp open loop gain limits the low-freq. gain

1-pole 1-zero low-pass filter

Active Loop Filter (2)

2 1 2

2 1 1 2/A P P

A P P A

C C CR R C C

1 2

1 2 /A A

A P

R kRC C k

RP1

CP1

CP2

• Determine the active-loop filter coefficients

Voltage Controlled Oscillator

• Ring-based VCO - To maximize VCO speed 2-stacked VCO - Different Frequency Control Method

Voltage Controlled Oscillator

• VCO Gain & Linearity- Gate control : small control range, non-linear large KVCO

0.0 0.1 0.2 0.3 0.4

0

100M

200M

300M

400M

500M

600M

Freq

uenc

y (H

z)

VCTRL (V)

FF TT SS

0

FF TT SS

KVCO

- Body control : large control range, linear small KVCO

Ref_0.1v

4bit UP/DN Counter

VoltageDAC

CLK divider X64

REF

Ref_0.3v

Automatic Frequency Calibration

• Small KVCO- Adv. : Insensitive to noise- Disadv. : limited available freq. range- Need to expand and search target freq.

regardless of PVT variation AFC

from CP

to VCO

Frequency Divider

• FD always support more freq. than VCO- ETSPC (Enhanced True Single Phase Clock)

(Fastest freq. speed, large power dissipation)

- TSPC (True Single Phase Clock)(Slower freq. speed, relatevely small power dissipation)

clk_divclk_div

TSPCETSPC

Test Equipment

Clock Generator

Ref. CLK

ULV PLL Test Board

Spectrum Analyzer OscilloscopePower Supply

Measurement Result

• Power consumption : 102 uW • Power efficiency : 0.291 mW/GHz

• Phase noise : -85.5 dBc/Hz @ 1 MHz• RMS jitter : 50.28 ps (0.017 UI)

• 350 MHz center frequency @ 0.4 V supply• Ref. spur reduction : -35.56 dBc -50.6 dBc

Ref. Paper Volt Freq. Power Consumption Remarks

1[VLSIC_2007] A 0.5-V 1.9-GHz Low-power phase-locked loop in 0.18-um

CMOS0.5V 1.9GHz 4.5mW Forward body bias

2[ESSCIRC_2009] Designing ultra-low

voltage PLL using a bulk-driven technoque

0.5V 610MHz 1.25mWBulk-driven @ VCO, Forward body bias

@ divider

3[TCAS I_2011] A 0.5-V 0.4-2.24-GHz Inductorless Phase-locked loop in a

system on chip0.5V 0.4~

2.24GHz 2mW

Gate switches@ CP

Low-voltagesegmented current

mirror @ VCO

4[CICC_2011] [JSSC_2012]

A 0.5V, 440-uW Frequency Synthesizer for Implantable Medical Devices

0.5V 400 ~ 433MHz 440uW

Dynamic threshold-voltage & switch-coupled @ CP,dual resistor-

varactor tuning @ VCO

Recently published ULV PLL

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