HomeworkAssignment#1SolutionsEE477Spring2017ProfessorParker

Note:+impliesOR,.impliesAND,~impliesNOT

Question1:

a) (4%)Usetransmissiongatestodesigna3-inputORgate

Note:Thereareothersolutionsaswellwhichusethesamenumberoftransistors.

b) (11%)Nowusetransmissiongatestoconstructthefollowingfunction:F=(A+B+C).(D+E)

ThemarooncircleisA+B+C.Thisisfedtothetopun-circledtransmissiongatewithpositivecontrolinput=

D+E(yellowcircle)andnegativecontrolinput=~(D+E)=~D.~E(greencircle).The2un-circledtransmissiongatesforma2-inputANDtorealizeOut=(A+B+C).(D+E)

Question2:a) (11%)UsetransmissiongatestodesignamultiplexerwithselectsignalsS0,S1,inputsA,B,C,D,and

outputOut.

Youcanarrangethesignalsinanywayyouwant.Oneimplementationisasfollows:

S1 S0 Out0 0 A

0 1 B

1 0 C

1 1 D

b) (4%)NowsupposeinputAisalwayslogic0andBisalwayslogic1.Canyoumakethecircuit

simpler?

OnlyanNMOSisrequiredtotransmita1andonlyaPMOStotransmita0.Sowecaneliminateacouple

oftransistors:

Question3:Considerthefunction:X=A.B.C.D+E.F.G.Ha) (4%)Drawitslogicgatediagramusingnegativegatesonly(NAND,NOR,INV)

b) (8%)Drawthestickdiagramofeachuniquegateyouhaveusedabove(i.e.ifyouhaveused2gatesofthesametype,justdrawthestickdiagramonce)

4-inputNAND 2-inputNAND

c) (5%)DrawacompoundgatetransistorleveldiagramofX

Question4:a) (4%)Supposeyouhaveadesignconstraintthatyourgatescanhaveamaximumof2inputs.Redraw

thelogicgatediagramofXusingnegativegatesonly.

Thisisatrickyproblem.Assumingcomplementsignalslike~Aarenotavailable,thisisthesolution:

Butifcomplementsignalsareavailable,thereisaslightlysimplersolution:

b) (6%)RedrawthelogicgatediagramofXusingpositivegatesonly(AND,OR)andthesameconstraint

-gatescanhaveamaximumof2inputs.

Noticethata4-inputANDgatecanbedirectlydecomposedintoacascadeoftwo2-inputANDgates

followedbyanotherANDgate.That’sbecause it’sapositivegate.Thesamecannotbedonewithnegativegates.

Question5:a) (3%)Showthetruthtablefora2-inputXORgateandgiveitslogicequation:AXORB=?

AXORB=A.~B+~A.B

b) (10%)A3-bitparitycheckercountsthenumberof1’sinasequenceof3bitsandoutputs1ifodd,0

ifeven.(Example:Iftheinputis101,outputis0,butiftheinputis001,outputis1).Designthiscircuit

usingnegativegatesonlyanddrawthetransistorleveldiagram.Youcanassumethatnegativeinputs

like~Aareavailable.

Thetruthtableoutputslogic1in4cases.Combiningtheseterms,wecanwrite:

Out=~A.~B.C+~A.B.~C+A.~B.~C+A.B.C

Ingeneral,anyXORgateoutputslogic1ifthetotalnumberofinput1’sareodd,otherwiseitoutputs

logic0.Soa3-bitparitycheckerissimplya3-inputXORgate:

(AXORB)XORC=(A.~B+~A.B).~C+~(A.~B+~A.B).C

ThiseventuallysimplifiestotheaboveexpressionforOut.

A B AXORB0 0 0

0 1 1

1 0 1

1 1 0

A B C Out0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

~

Question 6: (10%) Consider the following 2-to-1MUX built using transmission

gatesasshowninclass.The~pickXsignalisgeneratedfromaninverterwhichhas

adelayof2timeunits.Lookatthegiventimingdiagramanddrawthewaveform

forOut frombeginning toend. Is thereanyperiodof timewhenOut isn’twelldefined?

Duetothe2unitinverterdelay,boththetransmissiongatesareONduringthese

timeperiods:10-12,20-22,30-32.Forthefirst2cases,bothinputsarethesame

andthereisnoconflict.For30-32,bothpickXand~pickXarelogic0,sobothPMOS

areconductingandthereisaconflictbetweenXandY.

YoumightexpectXtowintheconflictbecausePMOScanpassstrong1’sandweak0’s.Actuallywedon’tknowwhathappens.SincetheOutsignalmightbedrivingotherpartsofthecircuit,weshouldneverallowsuchaglitchorundefinedstatetooccur.

Question7:(20%)Designalatchwith:

• Inputs=D,Clock,Set,Reset

• Output=~Q

• Active-highasynchronousReset• Active-highsynchronousSet

Thismeansthat:

Reset Clock Set ~Q1 Don’tcare Don’tcare 1

0 1 1 0

0 1 0 Loadnew~D

0 0 Don’tcare Retainprevious~Q

Noticethebasicstructureofthelatch–transmissiongatefollowedbyaloopconsistingof2negativegates

andatransmissiongate.TheNANDisadded insidethe loop toensureAsynchronousReset,whiletheORoutsidetheloopimplementsSynchronousSet.

Note:SetsetsoutputQto1,that’swhy~Qis0.SimilarlyResetshouldmakeQ=0,so~Q=1.

Note:GenerallypositivegateslikeORaren’trecommended.It’sbettertoreplacethemwithnegativelogic

dependingonthetechnology/circuitsused.