how to use the vhdl and schematic design entry tools
Post on 19-Dec-2015
244 views
TRANSCRIPT
![Page 1: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/1.jpg)
How to use the VHDL and schematic design entry tools.
![Page 2: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/2.jpg)
ABSTRACT
Demonstrates how to create a top-level schematic that contains instantiations of the modules, and describe how to wire together the modules, and determine the circuit behavior by computer simulation.
![Page 3: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/3.jpg)
Starting the Xilinx’s Software
For PC users, start Xilinx program from the Start menu by selecting the following path: Start Programs Xilinx Foundation Series 2.1i Project Manager
![Page 4: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/4.jpg)
Creating New Project
Select OKNew Project dialog box comes outGive “Name”—Lab5; create the directory path —a:\lab5; Select OK
![Page 5: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/5.jpg)
Creating a New Schematic
Click on the third item named Schematic Editor in the first flow chart box.
Schematic Editor
![Page 6: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/6.jpg)
Schematic Editor Window
Symbol Toolbox
![Page 7: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/7.jpg)
Libraries
Click on the Symbols Toolbox iconClick on Select Libraries
![Page 8: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/8.jpg)
Instantiating VHDL Modules
• Select FJKSRE from the SC Symbols Window.• Place four FJKSREs in the schematic editor
window by simply dragging from the SC Symbols Window.
![Page 9: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/9.jpg)
Instantiating VHDL Modules
Similarly select AND2.Place three AND2’s in the Schematic Editor Window.
![Page 10: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/10.jpg)
Instantiating VHDL Modules
Place one inverter in the Schematic Editor Window.Select VCC and GND and place it on the Schematic Editor Window.
![Page 11: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/11.jpg)
Adding Hierarchy Connectors
Click on the Hierarchy Connector Symbol.
![Page 12: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/12.jpg)
![Page 13: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/13.jpg)
Wiring the Components
• Go to the left toolbar and click on Draw wires Symbol.• To make a connection:1. Click once at the vertex of a pin; 2. Extend the wire to the desired length; 3. Click on the location you want the wire to terminate.
Draw Wires
![Page 14: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/14.jpg)
Simulation
Click on the Simulator button in the taskbar on the top of the workspace.
Simulator
![Page 15: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/15.jpg)
Simulation
Inside the Waveform Viewer Window click on Add Signals.
Double Click
![Page 16: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/16.jpg)
Setting the Field Values
Click on the text that says Clock, then click on the Select Simulator button in the Waveform Viewer Window.
Select Simulators
Click
Double Click
Click
Click
![Page 17: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/17.jpg)
Setting the Field Values
Click on the text that says Reset, then click the Logic States Button.
Logic StatesClick
Simulation Step
![Page 18: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/18.jpg)
Final Output
![Page 19: How to use the VHDL and schematic design entry tools](https://reader036.vdocuments.net/reader036/viewer/2022081503/56649d405503460f94a19c0f/html5/thumbnails/19.jpg)
Reference
Lab Manual