howtocheck complexpcbs forsi/pi/emc issues public | etas/ehs2-grävinghoff | 2015-11-23 | © etas...

1 Public | ETAS/EHS2-Grävinghoff | 2015-11-23 | © ETAS GmbH 2015. All rights reserved, also regarding any disposal, exploitation,

reproduction, editing, distribution, as well as in the event of applications for industrial property rights.

How to check complex PCBs for SI/PI/EMC Issues



− Motivation & History

− EDA Import

− Rule Setup & EMC/SI/PI Rules

− Results Review & Documentation

− Additional Checks

− Summary & Outlook

Outline


Outline



− 1 FPGA / 1 CPLD / 3 Memories / 1 Ethernet Phy

− 6 power supplies / 12 supply voltages

− 5 connectors / 1000BaseT / Aurora

− 60mmx45mm, 14 Layers, complex via structure

ETAS uses complex PCB technology


Motivation



− 2008 : Bruce Archambeault mentions IBM EMSAT

− 2009 : ETAS evaluates SimLab EMBoardcheck (based on EMSAT)

− 2009 : ETAS acquires license to SimLab EMBoardCheck

− 2009 : SimLab is acquired by CST

− 2011 : First integration of EMBoardcheck/EMSAT into CST PCB Studio

− 2013 : EMBoardcheck/EMSAT is fully integrated into CST Studio Suite

ETAS switched from manual to automated PCB layout checks in 2009


History



− Supported Formats:

− ODB++

− Zuken CR-5000/8000

− Mentor Graphics HyperLynx

− Mentor Graphics PADS

− Mentor Graphics Expedition

− Cadence Allegro/ADP/SIP

− SimLab PCBMod

− CST Layout Database

ODB++ is recommended as EDA import format


EDA Import (1/5)

Source: CST



− Check & Export PCB stackup data after first PCB import

− Import PCB stackup data on subsequent PCB imports

Always check & correct PCB stackup data


EDA Import (2/5)

Source: CST



− Correct any R, L, C shown as „Undefined Vendor Device“

− Add simulation models for active & passive components (optional)

Always check & correct component data


EDA Import (3/5)

Source: CST



− Need to tag Clocks, Differential, Power & Ground nets

Net naming convention simplifies auto-tagging


EDA Import (4/5)

Source: CST



− One rule set

− small designs

− similar technologies

− single run

− less effort

− pessimistic result (more effort)

− Multiple rule sets

− large design

− different technologies

− multiple runs

− more effort

− realistic results

Choose Rule Setup strategy depending on design & preference


Rule Setup (1/3)

Source: CST



− IC Standard/Fast-Switching/NA

− Capacitor Type Bypass/Stitching

− Passive Type Resistor/ResistorPack/Filter/Jumper

− I/O Connector Class 1L/1H/2/3

− Clock Driver Yes/No

− Oscillator Yes/No

− Critical Net Yes/No

Component & Net naming conventions simplify auto-tagging


Rule Setup (2/3)

Source: CST



Adapt Rule Parameters to Design


Rule Setup (3/3)

Source: CST



− Net Crossing Split

− Net Changing Reference

− Exposed Critical Trace Length

− Net Near Edge of Reference

EMC Rules


EMC Rules (1/2)

Source: CSTSource: CST




− Critical Net near I/O Net

− Critical Net Isolation

− Critical Differential Net Isolation

− Critical Differential Net Matching

− I/O Filter Distance

EMC Rules


EMC Rules (2/2)

Source: CST

Source: CST




− Net Length

− Net to Net Coupling

− Between Reference Plane Routing

− Net Stub

− Differential Running Skew

Signal Integrity Rules


Signal Integrity Rules (1/2)

Source: CST



− Via to Net Coupling

− Via Stub

− Unconnected Via Pads

− Via Clearance Overlap

Signal Integrity Rules


Signal Integrity Rules (2/2)

Source: CST

Source: CST Source: CST

Source: CST



− Power Pin Capacitor Distance

− IC Power/Ground Pin-Via Distance

− Power/Ground Trace Decoupling

− Decoupling Capacitor Via Distance

Power Integrity Rules


Power Integrity Rules (1/2)

Source: CST

Source: CST

Source: CST

Source: CST



− Wide Power/Ground Traces

− Power Via Density

− Decoupling Capacitor Density

Power Integrity Rules


Power Integrity Rules (2/2)

Source: CST

Source: CST

Source: CST



− sorting and/or filtering of results possible

− use cursor keys to step through results

− use fit violation & fit factor to view violations

− Export to Excel for documentation

2 Large Displays recommended to view results


Results Review & Documentation (1/2)

Source: CST



− Fail

− suggest schematics/layout changes to fix violation

− Inconclusive

− use (additional) simulations to make sure the design is OK

− Pass

− check whether rule set can be improved

Use color codes to characterize violations


Results Review & Documentation (2/2)

Source: WikiMedia



− Trace Impedances

− Power Supplies

− I/O Connectors

− Power & I/O Filters

− Analog Circuits

− Connections to Housing/Shielding

− Creepage/Clearance (Safety)

Automated Rule Checks are augmented by manual checks


Manual checks



− enable increased level of detail and/or reduced time/effort for PCB reviews

− CST Studio integration facilitates subsequent SI/PI/EMC simulation

− Reduced risk of failing SI/PI/EMC compliance tests

Automated Rule checks are essential for in-depth PCB reviews


Summary & Outlook

− Extension to multiple PCBs

− Extension to Housing, Cables, …

Move from PCB-level checks to system-level checks

howtocheck complexpcbs forsi/pi/emc issues public | etas/ehs2-grävinghoff | 2015-11-23 | © etas...

Documents