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http://nano.ece.duke.eduC. Dwyer, Duke University
Self-assembled Materials for Computer Architectures
Chris DwyerAssociate ProfessorDepartment of Electrical and Computer Engineering, Department of Computer Science
HPEC, 2011
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http://nano.ece.duke.eduC. Dwyer, Duke University
Lab Overview
[DNA] self-assembly is a technology that enables next-generation materials, computers, sensors, and systems
Self-organizing computerarchitectures
Sensors
“Taggants” andDevices
A Subsidiary of Parabon Computation,Inc.A Subsidiary of Parabon Computation,Inc.
Targeted Chemotherapies
Precise chemical patterning
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http://nano.ece.duke.eduC. Dwyer, Duke University
Outline
Architectural Drivers
Disruptive Technology
Self-organizing Architectures
Economics of Performance
New Computational Domains
DNA Self-assembly
Devices & Logic Elements
Multiplexed Sensing
Design study: SOSA
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http://nano.ece.duke.eduC. Dwyer, Duke University
Economics of CMOS vs. DNA
Fab. Cost*Year
~$1B2000=$1.6B2002
=$2B2004
=$3B2006
…
*EE Times, †2004 U.S. Census, ‡ Yahoo! Finance
…
=$4B2009
… …
(32 nm)
(65 nm)
(90 nm)
(180 nm)
$1,170B
$ 260B Semiconductors
Drug Manufacturing
Specialized Chemical Mfg. $ 247B
$ 349BBiotechnology
Market Capitalization‡
Value of goods sold†
~$75B Semiconductors
~$400B (Non-petrol.) Chemical mfg.
$1,766B+
Conven.
DNA self-assembly
Microelectronics
=$6-8B2010(22 nm)
=?2014+(<10 nm)
=$5B+?2013(14 nm)
(<1 nm)
… …
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http://nano.ece.duke.eduC. Dwyer, Duke University
Why? To Enable New Domains for Computation
• New Systems– Novel materials to introduce computing to entirely new domains
• Hybrid Systems– Novel materials to enhance existing CMOS– Augmented optical computing on chip (e.g., w/ optical NOCs)
Intel 8088 HIV-1 budding from lymphocyte (CDC)
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http://nano.ece.duke.eduC. Dwyer, Duke University
ATTGCCGA
TAACGGCT
Source credit: Wikipedia
Source credit: Wikipedia
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http://nano.ece.duke.eduC. Dwyer, Duke University
DNA Scaffolds - Geometry
• The geometric properties of double strands can form specific, controlled self-assembled nanostructures:
T 3.4 Å
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http://nano.ece.duke.eduC. Dwyer, Duke University
DNA Motifs
9 strands
Two double-helicesper arm
A strand “crosses-over”to another at a “junction”
“Sticky-ends” sequencescan be unique
T
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http://nano.ece.duke.eduC. Dwyer, Duke University
DNA Motifs
9 strands
1
T
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http://nano.ece.duke.eduC. Dwyer, Duke University
DNA Motifs
16151413
1211109
8765
4321
Atomic Force Microscopy (AFM) Image (360nm X 360nm)
20.0 nm
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http://nano.ece.duke.eduC. Dwyer, Duke University
DNA Nano-grids
Manufacturing scale: >1015 grids/mL(< 8 hours)
60nm
Self-assembled grids with sub-nm resolution (3.4 Å)
16-tiles Patterned grid
Multiple DNA grids deposited on flat mica plane
64-tiles
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http://nano.ece.duke.eduC. Dwyer, Duke University
Next-step: Add active, functional components
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http://nano.ece.duke.eduC. Dwyer, Duke University
Outline
Architectural Drivers
Disruptive Technology
Self-organizing Architectures
Economics of Performance
New Computational Domains
DNA Self-assembly
Devices & Logic Elements
Multiplexed Sensing
Design study: SOSA
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http://nano.ece.duke.eduC. Dwyer, Duke University
Operational Overviewfor RET Logic
C. Pistol, et al., Small, 2010.
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http://nano.ece.duke.eduC. Dwyer, Duke University
X
Y X + Y
OR X
Y X Y
R
AND
•OR / AND primitives, good but…•Inversion by dual-rail encoding OR new devices
•New opportunity to integrate logic into molecular scale processes
RET Circuit Theory
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http://nano.ece.duke.eduC. Dwyer, Duke University
D0+A0+hvD
AD
hvA
D0+A0
hv1
RET
D*+A0
D0+A* D0+A0+hvA
ADhv1
AD AD
hvD
ADRET
RET-Logic: Resonance Energy Transfer
T
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http://nano.ece.duke.eduC. Dwyer, Duke University
•Energy transfer efficiency
D0+A0
hv1 RETD*+A0 D0+A* D0+A0+hvA
60
6
60
Rr
RADT
R0 : Förster Radius
r : D – A distanceκ : D – A alignmentη : index of refractionQD : Donor quant. yieldJ(λ) : Overlap integral
QM + EM derivation
T. Förster, "Intermolecular energy migration and fluorescence," Annals of Physics, vol. 2, pp. 55-75, 1948.
RET Efficiency
6/1420 ))((211.0 JQR D
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http://nano.ece.duke.eduC. Dwyer, Duke University
RNR
RT
X Z
RCross-Ex.
VF < VFT
VF > VFT
)1( TT
TEF
R
RIV
(1)
(2)
(3)
X Z (energy migration)
CP
RET Circuit Theory
Other elements
RET Cascades
0N
EI
I0
I1
I2
0P
FV
R1
R2
+
-
VF0VF=VF0·R2/(R1+R2)
IE=VF0/(R1+R2)
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http://nano.ece.duke.eduC. Dwyer, Duke University
Simple Application: Logic + Sensors
R2
X
Y X Y R2/(R1+R2)R1
1. XY forms a distinct “address”2. Output depends on R2/(R1+R2)
RL
RH
XY X
Z
DECODERX Y Z “address”0 0 0 N/A0 0 1 Z0 1 0 Y0 1 1 YZ1 0 0 X1 0 1 XZ (#2)1 1 0 XY (#1)1 1 1 XY,XZ,YZ
Receptor #1 Receptor #2
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http://nano.ece.duke.eduC. Dwyer, Duke University
Logic and Sensors
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
SA SB
A-/B- A+/B- A-/B+ A+/B+L1+/L2+ L1-/L2+ L1+/L2- L1-/L2-
XY XZ
XY X
Z
Receptor 1 Receptor 2
R2/(R1+R2)
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http://nano.ece.duke.eduC. Dwyer, Duke University
Design Study: SOSA and New Constraints
• Self-assembly introduces chaos at the microscale:– (>1-10 m)
• DNA hybridization restores order at the nanoscale:– (< 1 m) sub-nm resolution
• Three fundamental assumptions must change:– Availability of long-range interconnect (toward none!)
• No large-scale interconnect networks / limited local comm.– Area vs. cost tradeoff (toward an even worse exponential!)
• Large (> ~5 m on a side) circuit footprints are impractical– Reliable devices (toward error prone!)
• The substrate can have defects• The devices can have defects
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http://nano.ece.duke.eduC. Dwyer, Duke University
Self-Organizing Architectures
• Conventional architectures do not self-assemble
• Several new architectures can exploit self-assembly:– Oracles: DNA computing with a device twist that enables
rapid (electrical) re-use of a DNA computation– DAMP: Distributed Array Multi-processor, SIMD without an
interconnection network for embarrassingly parallel codes.– NANA: Nanoscale Active Network Architecture, general
purpose but imbalanced due to a large communication / execution ratio- under utilized resources.
– SOSA: Self-organizing SIMD Architecture, a SIMD model on a reconfigurable network topology. Utilization is high due to a depth first network traversal.
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http://nano.ece.duke.eduC. Dwyer, Duke University
Tangent: Interconnect, even if limited…
1• Self-assemble grids, ... , randomly deposit
on smooth surface.
2
• Self-assemble nanotracks between grids on surface.
3 Metallize tracks...
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http://nano.ece.duke.eduC. Dwyer, Duke University
Self-Organizing Architectures
Self-assembledComputational nodes
(minimal computational power & defect-prone)
Self-assembledInterconnect(defect-prone)
Defect model includes:• Rotation, position• Connectivity• Defective devices on nodes
Distant micro-scaleI/O contact
(low bandwidth)
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http://nano.ece.duke.eduC. Dwyer, Duke University
Strategy
1. Map out both topology and defective links and nodes in the network (i.e., configure)
2. Group nodes together to form more powerful computational elements
3. Provide a convenient programming abstraction
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http://nano.ece.duke.eduC. Dwyer, Duke University
Major Design Challenges (w/ Self-assembly)
• Conventional approaches to defect tolerance fail– Global defect maps are
impractical if:– System is large (>1012
nodes),– Nodes are weak– I/O bandwidth is limited
• The network topology is unknown and random– Every system instance is different!
• Nodes will have defective pieces– Functional and performance binning impractical
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http://nano.ece.duke.eduC. Dwyer, Duke University
Design Solution
• Use the reverse path forwarding (RPF) algorithm to create a tree
• Use Euler paths (EP) to create an abstract ring
• Use lightweight built-in self-test per node to protect connectivity
• Asynchronous! (no global clock)• Instructions and data are broadcast to all nodes in
network-order, down the RPF tree.
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SOSA Configuration: RPF
Micro-scale Via
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SOSA Configuration: EP
Micro-scale Via
2 12
5 7 9
1,3,11
4,6,8,10
(DFS visit time)
12
4
5
7
9
3
6 8
10
11
12
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http://nano.ece.duke.eduC. Dwyer, Duke University
SOSA Configuration: the ring
RPF & EP
Microscale Contact
Head Bit 0 ... Bit N-1 Tail
Random and dis-ordered
Ring abstraction
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http://nano.ece.duke.eduC. Dwyer, Duke University
SOSA Execution Model Overview
• Instructions are broadcast to all PEs from the microscale I/O contact
• Partial instruction re-use is permitted to reduce instruction broadcast overhead
• Predicated instructions serialize through a synchronization signal sent from the head node of the PE (the head node holds predicate flags)– Why? out-of-order inst. arrival at nodes within a PE
• PESHIFT operations (left, right) enable PE communications on the ring
Head Bit 0 ... Bit N-1 Tail
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http://nano.ece.duke.eduC. Dwyer, Duke University
Performance Comparison
SOSA Configuration
Parameter Value
Register File 16 entry, 2-bits per node (32 bits wide)
Time Quantum 1 ns (Synchronous equivalent: 1GHz)
ALU Latency 1 time quanta
Inst. buffer size
1 entry
Link type Full duplex with 3 virtual channels
We compare SOSA against:• P4 at 3GHz • Ideal SOSA• Ideal Superscalar• Ideal 16-way CMP
Ideal SOSA (I-SOSA): • 1 time quanta instruction execution latency• No communication overhead
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http://nano.ece.duke.eduC. Dwyer, Duke University
Performance Comparison
Ideal Superscalar (I-SS) Configuration
Parameter Value Parameter Value
Width 128 (Fetch/Dec./Iss./Commit)
Branch prediction
Perfect
Inst. Fetch Queue
1024 Entries Memory latency 1 cycle
ROB/LSQ 8192 entries, 1 cycle access Memory ports 128
Integer ALU 128 Add, 128 Mult. Frequency 10 GHz
FP ALU 128 Add, 128 Mult.
Ideal 16-way CMP (16CMP): • Linear scaling of I-SS performance
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http://nano.ece.duke.eduC. Dwyer, Duke University
Benchmark Highlights
Application Class Description
Scientific Multiply integer NxN matrices (N2 PEs)
Image Processing (Filters)
1. Generic 3x3 filter2. Separable Gaussian filter3. Median noise reduction filter Each over an NxN image (N2 PEs)
General PurposeOdd-Even transposition sort. Parallel sort with nearest neighbor communication (N PEs for sorting N keys)
CryptographyTiny Encryption Algorithm (TEA) used in XBox IP security.
SearchSearch a database for a match with an input 32 bit string. O(N) PEs for N strings.
Bin-PackingPipelined version of bin-packing with first-fit heuristic (N PEs for N bins)
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Highlight 1 of 2 – Matrix Multiply
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Highlight 2 of 2– Gaussian Filter
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http://nano.ece.duke.eduC. Dwyer, Duke University
Conclusions
• Early days of self-assembled computing and the devices are nascent– However, we have demonstrated the fundamental
building blocks and are moving toward more powerful devices
• Self-assembly disrupts the conventional paradigm for computer architecture– Fortunately, self-organization as a principle can be
applied in a defect-prone, distributed setting
• Despite significantly higher defect rates higher-performance self-organizing architectures are possible
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http://nano.ece.duke.eduC. Dwyer, Duke University
Students and Sponsors
Jaidev PatwardhanCostantin PistolVincent MaoViresh ThusuMohammad MottaghiJun PangVishwa NelloreSiyang WangHeather DuschlArjun RallipalliCraig LaBoda
Dr. Perumal RamasamyDr. Wanqiu Shen
Thank you!