hybrid analog-digital sample-averaging computer for astrac ii
TRANSCRIPT
~_76 Anna/es de l'Ass)ciation internationale pour le CalcM analogiqae N" 4 --- Octobre 1967
H Y B R I D A N A L O G . D I G I T A L S A M P L E . A V E R A G I N G
C O M P U T E R F O R A S T R A C II *
by R,L. M A Y B A C H ~":';'
ABSTRACT. - - This report describes the circuit design of a new hybrid analog- digital statistical averaging computer used to calculate statistical averages of analog vol- tages presented to it. The unit, with a dynamic range of +- 10 volts, an acucracy of + 0.25 percent, and a maximum speed of 1000 samples per second, is particularly well suited for use with modern high-speed iterative analog computers. The output is prima- rily visual, but electrical signals are also available for use by digital computers, printers, punches, and the like. Circuit simplifications have resulted in an inexpensive unit which requires few adjustments. Digital storage of sums eliminates the drift present in pure analog averaging schemes if the summation time is long.
Introduction.
In the investigation of random processes on an analog computer or in the instrumentation of a random process in the physical world, one is usually interested only in the statistical parameters of some variable or variables. Suitable estimates of these parameters are the sample ensemble average of f [x (tk)],
/ l= (t,,)] = ( y n ) E / Ix, (/,,)], i = l
and the time average of /[x (t)],
't'
< f [ x (~)1 > , = 0 / T ) f , f [x (t)l at.
Some of the most common are estimates of the mean by
o r
l l
.,: (t,<) = ( l /n) E ~, (t,<) 1=1
T
< ~ (t) >.r = ( i / ' r ) fo " (0 ,#,
estimates of the variance by
o r
[x (6, ) - - .~ (t, ,) l" = ( i / n ) ~, [x, (tk) - - x ( tk)]" i = l
< [~ (,) - - < x (,) >.,.]-~ > ~.
j , T
= ( l /T) [x (t) - - < x ( t )> , r ] '2 d't 0
and estimates of correlation by
u
x (t,) y (t.,) = (1/,,) E x, (t,) y, (t=) 1=1
Manuscript received October 4th 1966 Electrical Engineering Department, College of Enginee- ring Analog/Hybrid Computer Laboratory - University Of Arizona.
or .p
< ,, (t) y (t + ,) >,r = (t/Wlf0 x (0 Y (t + ,) d t .
As suggested by these examples, one may use two general types of averages, time averages and ensemble averages. Time averages are easier to implement, since they require only integration of the desired function; this is easily accomplished with an operational amplifier. The general approach is shown in figure 1 a. If the
Function ln legrator Generalor (/nlegrole for o(t.< r
hold for T<t)
a, Circuit to oblain t ime average
Sample at t=t k
~dt~
Function Generator
Digital I Accurnulaloq '1 I I Converter L_. I
SlatiMic5 Computer
b, Current to obtain ensemble average
• Fig. 1. - - Circuit Used to Obtain Statistical Estimates
process is not stationary, however, the t ime average is not suitable, and one is forced to the ensemble average. Sum over n sample values x (t) is not easily obtained by pure analog techniques since n is usually large (typically 100 to 10,000), but can be accumulated by the hybrid configurat ion of figure 1 b. Although not shown in the figure, it is implied that the random
R.L. Naybach : Hybrid sample-averaging codlputer 177
process and instrumentation share timing information so that- the s:,.mpling time t k can be determined. The sample-hold may not be necessary if the A-to-D con- verter is fast cnough. It should aso be noted that the circuit of figure 1 b can be used to obtain time averages if the circuits are fast enough to sample at a high rate compared to the signal bandwidth. In this case
11
< f ix (t)] >,r is approximately (l/n) Y. f ix (i~XT]; [=t
where AT is the sampling interval, and T = n aT . Thus a statistics computer such as the one defined by the dashed lines in figure 1 b is very useful in random.. process studies and instrumentation.
This paper describes the design of a sample-averag- ing computer requiring lm sec to process each analog voltage sample. It can accumulate up to 10,000 samples and has an accuracy within -t- 0.25 percent of half- scale ( + 10 v). These properties make it suitable for taking sample averages in modern high-speed iterative analog computers or audio-frequency instrumentation I2, 31. It can also be used for time averaging in real- time computers or slow random-process instrumentation. Since the accumulation is done digitally, the averaging circuit is usable for extremely slow processes in which the drift of an analog integrator would be object- ionable.
Ein .~{ Analog-to-rime eo[_g~.t Cbnverter J
x - r Reset
1 RS ~ SequentialLogic I "~-
Count I T"--
4 Mo Clock
Schrnidt Trigger
5- Tout
P (sign)
PR (prese4)
i[ I ~ I I I I I I
7-deorJdelBCD Fount~r ! i I
[ I
I I I Reodout I
This statistics computer was developed for the ASTRAC II iterative differential analyzer and uses the supply voltages available there. Power-supply volt- ages, as well as the signal range of __+ 10 volts, could be easily changed for other applications.
Statistics Computer Operation.
The statistics-computer block diagram is shown in figure 2 and the associated signals in figure 3. The command to start a series of samplings is given by R, which properly presets the counter and enables the sequential logic. E~,,,~ is taken from an external sample- hold circuit which is controlled by the sampling wave- form S. Each positive transition of S also initiates one sample of Ezx. in the averaging computer. As long as S is a logical zero, ETa is held constant. The analog- to-time converter is allowed a time Tr~ to become pro- perly reset, after which it integrates a reference voltage down to a fixed limit. As a result, the time interval between the positive transition of A-T RESET and the negative transition of the Schmitt-trigger output S-T OUT is proportional to Ee,,. During this time inter- val, the logic output referred to as COUNT gates the frequency-stable 4 Mc. clock into the counter.
There are two interesting features of this statistics computer. The analog-to.time converter provides a
25 millivolt accuracy over a range of ± i0 volts af sampling rates tip to 1 Kc and requires only one operational rm=plifier, The counter with its associated logic sums both positive and negative sample values using only a simple nonreversible binary.coded-decimal counter, thus eliminating the expense and complexity of an up-down counter.
Fig. 2 , - Statistics Computcr Block Diagram
0 R
1
0 ,5
1
Ei n
P, ! 0
A-T Reset I
Eou!
0 5 - T out
0 Count
1
H I I
I
I
[..J, I
I I I I I
I I
I I I / ' \ I I J ,,---~ ! \ I l/ ;\ ~/ \ I J
I f
Fig. 3, - - Statistics Computer Signals
Analog-to-time Converter.
The analog-to-time converter is shown in figure 4 together with the associated waveforms. This circuit is a modification of the familiar voltage-to-time con-
178 Annales de l'Association i,2ter~aatioJaale pour le Calc,'d " N . . . . . . . a,z,t,c.glq, c 4 Octobre 1967
- I O ~ K ~
5K R2
E in 9% 8K ~
+1o
Note~: -15 ~denotes I% component All other are 10% All diodea 1N-4003
T1- 2N 1304
5.6K R3-4K *
f
+15 ~ R 7- 500 .n- ~"
1 5 ~ . I0 t__ T3-2N 1305 D7
" ' S6K . . 180-~
K I( -
-lo ooTpF
Burr-Brown 1607,4
÷I0 ~ R4 ~ ra 5K 27,4K DE
Fig. 4. - - Analog- to- t ime Conver ter
DS.
Eout
P5 22.K
R 6
3.9K +15
verter [3, 4] and combines an electronically resettable integrator with a precision limiter. The circuit is reset when the diode bridge (D1, D2, D3, D4) is switched ON as its driving transistors (T2, T3) are turned OFF. At the same time, T1 is also turned OFF. The integ- rator then resets to 0.8 EIN plus a positive bias de- termined by the currents through R1 and R4. To start the integrating period, T2 and T3 are switched ON, so that ,"he diode bridge is abruptly switched OFF. This is followed after a short delay by the switching ON of T1. The delay results from the absence of a speed-up capacitor at the input of T1 and preven`"s a reset error due to the grounding of the summing junc- tion of the amplifier.
The voltage ae which integration stops is determined by the precision-limiter network (R3, R7, DS, D7). The current discharging capacitor C must flow through R7, since D5 prevents the amplifier from supplying negative current. The function of the amplifier here is that of a shunt regulator. It supplies the proper current to the precision limiter network to maintain an accurate integrator input wave-form in EouT, as indeed it must, for with D5 ON the circuit is just an integrator with a constant input voltage. When EouT drops within t volt of the open-circuit voltage of the voltage divider R7-R3, the forward resistance of D5 begins to increase because the current flowing through it is not sufficient to keep it fully ON. This causes Eou~e to decrease at a faster rate in an attempt to maintain a constant current, 10/R4, through C, causing a further increase in the forward resistance of DS. As a result, when Eou~ drops within 1 volt of the open- circuit voltage of R7-R3, an abrupt negative transition t~es place at the amplifier output. This transition is limi`"ed by a standard feedback.limiter network (RS, R6, 136). TI is required to keep the summing junction at zero when the diode bridge is OFF; if this were not done, the transition point of the precision limiter wouId depend on Eix and the internal impedance of
the source of E~s. D7 and D8 provide a slight negative bias for the diode bridge to insure that it turns OFF securely.
The point at which the transition associated with the precision limiter occurs varies with the ambient temper- ature due to the dependence of the forward character- istics of D5 on temperature. D7 compensates for this by introducing at similar change in the reference voltage applied to the limiter. With the values shown the drift with temperature is reduced to less than 5 ns/degC, which corresponds to an input drift of 200 microvolts/ deg C.
Previous circuits of this type have accepted only one polarity of E~s and have integrated to zero. A typical
eri5 tic
/ ~ f ~ Actual Charocteriatic
Ein
Fig. 5. - - Convers ion Character is t ic of a Typical Ana log- to - t ime Conver te r
Conversion characteristic is shown in figure 5 [1, 3, 4] . Note that the greatest error occurs near zero, the point at which it does the greatest harm. This is especially serious in statistical studies, since an amplitude-limited
R.L. At,ohac/). H1'/,w/
signal that has an approximately gaussian distribution must have a small variance if the approximation is to be close. Thus in many cases Ef.~ seldom strays far from zero. The primary improvement of the new analog-to- time converter over these previous circuits is that the comparator actio[1 take~ place at ---8 vohs instead of at zero. This (orrcsponds to an Erx of -t-11 volts. As a result dae accuracy near zero is not degraded. In fact, errors of this type do not occur until E~x has exceeded its acceptable range of :2 10 volts.
Auxiliary circuits for the A-T converter are shown in figure 6, Schmitt Trigger and figure 7, A-T Driver.
250pF 1
- t 8
tK 1N4009 I.SK
OUT
2.3K
2N 1305
- t 8 -
a,wJp/e-avera,q, ing comp#ter
F", 7r - - ~ so ---rr .Z.8 Sb= #"
&
8 4 S 4Me Clock~
i
s- r ~ . g I eo:*b= cs- roue).a* g I A ~ Count --,4
B A' r Reset
~ 2N I305 R ~ ~ - Pr 5., )
"--~ 200pF[ ~ One- One-
÷t2 ~ot, ~ ~ ~oo~,~ r~
tOK ÷ t2 Fig. 8. - - Sequential Logic
179
Fig. 6. -.-- S c h m i t t " l ' r i ggc r
-18 t
Out-B I 22K n¢~oo91 o.oot~,r
I ~ 2 N 1305
22K I 600n}÷ 12
22K I Out- A
2N 1305
68K
Fig . 7. - - A - T C o n v e r t e r D r i v e r
The Schmitt trigger detects the - - 8 to - - tO volt tran- sition of the A-T converter and presents it to the logic circuitry as (S-T OUT) with standard logic levels (0, .... 6). The A-T driver is also a Schmitt trigger that converts the standard logic levels to push-pull pulses with levels -!- 6, - - 6.
Sequential Logic.
The sequential logic and its governing equations are shown in figure 8. The basic element used is the N A N D gate. The ~tate of a flip-flop is altered by placing a logical zero (0 volts) on the level input and a positive trans;tion (--. 6 to 0 volts) on the clock input of the desired pedest:d gate. A positive transition
triggers the one.shots [61. That the sequential logic provides the proper operation can be verified by com- paring the logic with the signals shown in figure 3.
The flip-flop (A) that controls the stepping of the counter is synchronized to the signal that it gates. The start of the integrating period is thus tied to the clock. This eliminates the ambiguity of pulse length of COUNT that would result if the integration were free to start immediately at the end of the delay period "I']~. The resetting of A is also clocked. This insures that either a complete clock pulse or none at all will be gated into the counter and prevents a partial from possible causing an error.
Counter.
The pulse.width of the COUNT wave[otto (fig. 2 ;rod 3) varies from 0, corresponding to Eh~ = + 11 volts to 550 microseconds, corresponding to EI,~ = - - 1 t volts. 'I'he number of counts is therefore equal to 100 (tt-E~x) .This 11 volts offset is removed by presetting the counter to the complement of 1100 (number of samples). This restricts the versatility of the statistics computer somewhat, for only a small num- her of sample s~zes can be accomodated without making the presetting logic ctm3bersome. The complexity of the counter i~, however, reduced considerably since, instead of an up-down counter, it needs to be just an up-only one. The table for the presetting logic is shown in table I. The logic is implemented with a &position switch which directs the presetting pulse, Pa , to the proper inputs of the counter flip-flops. As indicated in tabIe I, there is an overflow bit to allow
180 Annales de l'Association internationale pour le Calcul analogique N" 4 - - Octobre 1967
the 7-decade counter to be present to 11,000,000 (de- cimal).
As a result of the above, at the start of each sampl- ing run, the counter is preset to the complement of 1'100 (number of samples), and the sign bit is preset to plus. As samples are taken, the counter counts up. Should the mean of the sample values be positive, the complement of the readout must be taken to obtain the true sample mean. To reduce operator error the re- quired complementing is done automatically by the statistics computer. The logic for a counter stage with readout is shown in table II. It should be noted that the true complement is not provided by the conversion logic: because no carries are made, there is an error in the least significant bit. Since only the 5 most significant digits are read out, the error of 1 least significant digit is, however, completely negligible. This scheme results in an appreciable saving in the logic required.
The overflow and sign logic is shown in figure 9. The overflow (OF) flip-flop can be considered as the
Carry Pulse from Counter
-&,
6 - - OF TP
i o
~ Overflow ldicalion
Fig. 9. - - Overflow and Sign Logic
last stage of the counter. The sign flip-flop (P) is reset by the resetting of OF. An overflow indication is provided whenever the count exceeds 9,999,999. Note that once the computer goes into a negative overflow condition, it will remain there until it is reset for a new sample run.
Acknowledgement .
The project described in this report is part of a hybrid analog-digital computer study directed by Pro- fessor G.A. Korn. The writer is grateful to the Office of Aerospace Research, Information Research Division, Air Force Office of Scientific Research and to the Office of Space Sciences, National Aeronautics and Space Ad-
ministration for their continuing support of this study under grants AF-AFOSR-89-64 and NSG464; and to Professors H.S. Coleman, Dean of Engineering, and H.E. Stewart, Head, Depart of Electrical Engineering, for their contribution of University facilities.
TABLE I
Presetting Logic Operation
Sample Size Preset Number Preset State (Decimal) (Decimal)
0 00000000 00000000 100 0110000 9890000 500 0550000 9450000
1000 1100000 8900000 5000 5500000 4500000
I0000 I000000 9000000
Plus overflow bit.
m 1
Dz - - two's bit D.~ ~ four's bit Ds ~ eight's bit
TABLE II
Conversion Logic for Stages with Readout
- - one's bit P - - sign bit = 1 for q- = 0 for
D.,. D1 .P
I 3 , . , . D , .
D 1 . P
D, .P
D1 • P
D 1 . P
D, .P
D 1 . P
P
Zero : D s . D I
One = D~ D4
Two = ID, D2
Three = [)4 D2
Four = D., D._,
Five : D4 El.,
Six = D, D.,
Seven : D., D.,
Eight = Ds D,
Nine : D, D1
q- D s . D 1 . P
q- Ds 13, . P
q - D 4 D~. .D t P
+ D 4 D~ ,DI P
+ D., E)2.D1 P
q - D ~ Da . D 1 P
-If-[)4 D ~ . D 1 P
q- I34 D e . D , P
-{- D s D.~.D. D 1 . P
-b D8 D . , . D , D 1 . P
Accuracy of
1000 E,x E (E,x),
J=l
Measured
--10.000 ---9998 - - 9.000 ---8999 - - 8.000 - -8000 - - 7.000 - -7001 - - 6.000 - -6002 - - 5,000 - -5003 - - 4.000 ---4002 - - 3.000 - -3005
2.000 - -2006 1.000 - -1007
Statistics Computer
1000 error, --lO00E,x -~ E (E,x) '% of
l=, full scale
2 0.02 I 0.01 0 0
--I --0.01 - - 2 --0.0'2 - - 3 - -0 .03 - - 2 - -0 ,02 - - 5 - -0 .05 - - 6 --0~.06 - - 7 - -0 .07
R.L. Naybach : Hybrid sample-avcragi~g computer 181
0 8 8 0.08 1.000 989 - - 1 1 - -0 .11 2.000 1989 - - 1 1 - -0 .11 3.000 2988 - - 1 2 - -0 .12 4.000 3987 - - 1 3 --O.13 5.000 4989 - - 1 1 - -0 .11 6.000 5985 - - 1 5 - -0 .15 7.000 6994 ' - - 6 ----0.06 8.000 7993 - - 7 - -0 .07 9.000 8999 - - 1 - - 0 . 0 1
10.000 10,001 1 0.01
REFERENCES [1] CONANT, B.K. : <{A Hybrid Analog-digital Statistics
Computer >>, ACL Memo No. 45, Department of Electri- cal Engineering, University of Arizona, Tucson, Arizona.
[2] KORN, G.A. : Fast Analog-hybrid Computation with Digital Control : The ASTRAC II System, P~'oc. 4th AICA Co*~/erep¢ce. Brighton, England, 1964, Presses Aca- dSmiques Europ6ennes, Brussels, 1965.
[3] KORN, G.A. and T.M. KORN : Electronic Analog and Hybrid Comptaers, McGraw-Hill, New York 1964
[4] BARKER, B. and McMAHAN : aA New Analog-to- Digital Converter ~>, Electronics, April, 1961.
[5] KORN, G.A. : Ensemble-parameter Estimates Obtained by Periodic Sampling or Continuous Integration of a Statio- nary Random Process~), ACL Memo No. 16, Depart- ment of Electrical Engineering, University of Arizona, Tucson, Arizona.
([6] InstructioJ~ Nanz~al For S-Pac DigBal k~lodHles, Compu- ter Control Company, Inc. Framingham, Mass., 1962.