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1 Table of Contents

1 Table of Contents ....................................................................................... 4 2 List of Figures ............................................................................................ 5 3 List of Tables .............................................................................................. 5 4 Document Revision History ...................................................................... 6 5 Introduction ............................................................................................... 7 6 Functional Description .............................................................................. 7 7 Module Management Interface Description ........................................... 10 8 Electrical Specifications ........................................................................... 10

8.1 Operating Case Temperature ............................................................ 10 8.2 Electrical Power Supply and Power Dissipation .............................. 10 8.3 High Speed Pin Electrical Specifications .......................................... 11 8.4 Control Pins (non-MDIO) Functional Description ........................... 13 8.5 Alarm Pins (non-MDIO) Functional Description ............................. 16 8.6 Module Management Interface Pins (MDIO) Description .............. 19 8.7 Hardware Signaling Pin Electrical Specifications ............................ 21 8.8 Hardware Signaling Pin Timing Specifications ............................... 23

9 Mechanical Specifications ....................................................................... 25 9.1 Mechanical Overview ........................................................................ 25 9.2 Electrical Connector ........................................................................... 25 9.3 Module Dimensions .......................................................................... 28 9.4 Host System Dimensions .................................................................. 33 9.5 Module Optical Fiber Ports ............................................................... 34 9.6 Pin Assignment ................................................................................. 35

10 References ................................................................................................ 40 10.1 Normative references ........................................................................ 40 10.2 Informative references ...................................................................... 40

11 Appendix A: Glossary .............................................................................. 40 12 Appendix B: Open Issues / current work items ....................................... 41 13 Appendix C: List of companies belonging to OIF when document is approved ......................................................................................................... 42


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2 List of Figures FIGURE 1: 100G LONG-HAUL DWDM TRANSMISSION MODULE (MSA-100GLH) FUNCTIONAL

DIAGRAM ................................................................................................................................ 8 FIGURE 2: HIGH SPEED I/O FOR DATA AND CLOCKS .................................................................... 12 FIGURE 3: TRANSMITTER DISABLE (TX_DIS) TIMING DIAGRAM ................................................ 15 FIGURE 4: MODULE LOW POWER (MOD_LOPWR) TIMING DIAGRAM ....................................... 16 FIGURE 5: RECEIVER LOSS OF SIGNAL (RX_LOS) TIMING DIAGRAM .......................................... 18 FIGURE 6: GLOBAL ALARM (GLB_ALRMN) TIMING DIAGRAM .................................................. 19 FIGURE 7: MODULE MDIO & MDC TIMING DIAGRAM ................................................................ 21 FIGURE 8: REFERENCE +3.3V LVCMOS INPUT/OUTPUT TERMINATIONS .................................... 22 FIGURE 9: REFERENCE MDIO INTERFACE TERMINATION............................................................. 23 FIGURE 10: MSA-100GLH SIMPLIFIED START-UP FLOW DIAGRAM ............................................ 24 FIGURE 11: HIROSE FX10A-168S-SV(83) RECEPTACLE CONNECTOR ASSEMBLY ...................... 26 FIGURE 12: HIROSE FX10A-168P-SV(83) HEADER CONNECTOR ASSEMBLY .............................. 27 FIGURE 13: FX10 CONNECTOR ALIGNMENT ................................................................................. 28 FIGURE 14: MSA-100GLH NON-CONDUCTIVE SHEET DIMENSIONS ............................................ 29 FIGURE 15: MSA-100GLH FLATTOP MECHANICAL DIMENSIONS - BOTTOM/SIDE VIEWS ............. 30 FIGURE 16: MSA-100GLH FLATTOP MECHANICAL DIMENSIONS - TOP VIEW .............................. 31 FIGURE 17: MECHANICAL DIMENSIONS OF MSA-100GLH WITH INTEGRATED HEAT SINK ........ 32 FIGURE 18: MSA-100GLH WITH INTEGRATED HEAT SINK - TOP VIEW ........................................ 33 FIGURE 19: RECOMMENDED HOST SYSTEM LAYOUT FOR MSA-100GLH ................................... 34 FIGURE 20: MSA-100GLH OPTICAL FIBER PORT LOCATION AND DIMENSIONS ......................... 35

3 List of Tables TABLE 1: MSA-100GLH PERFORMANCE SPECIFICATIONS ........................................................... 10 TABLE 2: MSA-100GLH REFERENCE CLOCK (REFCLK) CHARACTERISTICS ............................. 12 TABLE 3: OPTIONAL TXMCLK AND RXMCLK CHARACTERISTICS ............................................ 13 TABLE 4: MSA-100GLH CONTROL PINS (NON-MDIO) ................................................................ 14 TABLE 5: MSA-100GLH ALARM PINS (NON-MDIO) ................................................................... 17 TABLE 6: MSA-100GLH MDIO MANAGEMENT INTERFACE PINS ............................................... 20 TABLE 7: 3.3V LVCMOS ELECTRICAL CHARACTERISTICS .......................................................... 21 TABLE 8: 1.2V LVCMOS ELECTRICAL CHARACTERISTICS .......................................................... 22 TABLE 9: HARDWARE SIGNALING PINS TIMING PARAMETERS SUMMARY ................................... 24 TABLE 10: MSA-100GLH PIN-MAP .............................................................................................. 37 TABLE 11: MSA-100GLH ELECTRICAL CONNECTOR - ROW B PIN DESCRIPTION ....................... 38 TABLE 12: MSA-100GLH ELECTRICAL CONNECTOR - ROW A PIN DESCRIPTION ....................... 39


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4 Document Revision History Working Group: Physical and Link Layer (PLL) Working Group SOURCE: TECHNICAL EDITOR WORKING GROUP CHAIR Atul Srivastava, Ph. D. David R. Stauffer, Ph. D. NEL America, Inc. IBM Corporation 250 Pehie Ave., Suite 706 1000 River Road, MC 862J Saddle Brook, NJ 07663 Essex Jct., VT 05452

Phone: +1-201-556-1770 Phone: +1-802-769-6914 Email: [email protected] Email: [email protected]

WORKING GROUP VICE CHAIR

Karl Gass TriQuint Semiconductor Phone: +1-505-844-8849 Email: [email protected]

DATE: January 14, 2013 Revision Date Change Notes By Preliminary draft Jan. 14, 2013 Preliminary draft B

Apr. 23, 2013 Location of PIN A1 indicate in Figure 15, 17 and 19 9.6 Pin Assignment Information delete of Appendix D and E 10.2 Informative references [I5] Revision update to latest version

Atul Srivastava

Preliminary draft IA # OIF-MSA-100GLH-EM-02.0

Aug. 27,2013 Draft IA Release Atul Srivastava

Draft IA # OIF-MSA-100GLH-EM-02.1

Jul. 31,2014 Modify document as per ballot comments in oif2014.182.00 6 Functional Description Comment add of Figure 1A-1D Error of repetition delete of Figure 1A-1D 8.3 High Speed Pin Electrical Specifications Comment add 10.2 Informative references [I2] [I4] [I5] Revision update to latest version

Atul Srivastava


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13 Appendix C Update to latest Members


Jan. 20,2015 Incorporating principal members ballot comments (oif2014.442.00)

Atul Srivastava


May 4, 2015 13 Appendix C Updated list of current members

Atul Srivastava

5 Introduction This document details an Implementation Agreement (IA) for a Generation 2.0 100G Long-Haul DWDM Transmission Module – Electromechanical (MSA-100GLH) for optical line interface applications. While specifically addressing 100G PM-QPSK long-haul DWDM transmission applications [I1], this IA strives to remain modulation format and data rate agnostic whenever practical to maximize applicability to future market requirements. This IA specifies key electromechanical aspects of the Generation 2.0 100G Long-Haul DWDM Transmission Module (hereafter termed MSA-100GLH) that include the following: module mechanical dimensions, electrical connector and pin map, module hardware signaling pins, high-speed electrical characteristics, power supply, power dissipation, and management interface. 6 Functional Description A functional block diagram of the MSA-100GLH is illustrated in Figure 1: Generation 2.0 100G Long-Haul DWDM Transmission Module (MSA-100GLH) Functional Diagram. Key module functions include transmitter optics, receiver optics, interface ICs, module controller supporting an MDIO/MDC management interface, and power conversion for a single +12V DC power supply from the host. The MSA-100GLH is not hot pluggable, but is fastened to the host system board during line card assembly. The interface IC(s) and module electrical interface are generically specified to allow vendor specific customization of multilane “M-lane” ~ 11 Gbit/s interfaces. Module electrical interfaces include but are not limited to the following:

a) Simple bit multiplex b) OTL4.10 [I2] c) SFI-S [I3] d) OTL3.4 [I2] (for 40G applications, see informative Appendix D)

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7 Module Management Interface Description The MSA-100GLH utilizes MDIO IEEE 802.3 Clause 45 [N1] for its management interface. The MSA-100GLH MDIO hardware implementation is specified in Section 8.6. The MSA-100GLH MDIO register set specifications are defined in [I5]. When multiple MSA-100GLH are connected via a single bus, a particular MSA-100GLH may be selected by using the MDIO Physical Port Address pins. 8 Electrical Specifications 8.1 Operating Case Temperature The MSA-100GLH operating case temperature is specified in Table 1. 8.2 Electrical Power Supply and Power Dissipation The MSA-100GLH is powered by a single +12V DC supply from the host board. This power supply is specified in Table 1. All voltages are measured at the electrical connector interface. The MSA-100GLH power dissipation is specified in Table 1.

Table 1: MSA-100GLH Performance Specifications

Parameter Symbol Min Typ Max Unit Note +12V DC Supply Voltage VCC 11.4 12.0 12.6 V +/- 5% +12V DC Supply Current ICC 4.0 A Notes 1 & 2 Power Supply Noise Vrip 1

%p-p 1Hz – 20MHz

Power Dissipation Pw 45 W Operating Case Temperature 0 70 °C

Note: The parameter min and max values are specified End-of-Life within the overall relevant operating case temperature range. The typical values are referenced to +25°C, nominal power supply, Beginning-of -Life. Note 1: Maximum current per pin shall not exceed 750mA. Note 2: Icc max specified for current rating purposes. Normal operating current (Icc) must not exceed Pw / Vcc.


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8.3 High Speed Pin Electrical Specifications 8.3.1 Transmitter Data (TX) The Transmitter Data (TX) signals shall comply with CEI-11G-MR Low Swing option as per Clauses 9.3.1. and 9.3.1.2 [N2]. Full Swing support is not required. The recommended termination of the TX pins is given in Figure 3. 8.3.2 Receiver Data (RX) The Receiver Data (RX) signals shall comply with CEI-11G-MR Clause 9.3.3 [N2]. The recommended termination of the RX pins is given in Figure 3. 8.3.3 Reference Clock (REFCLK) The host shall supply a reference clock (REFCLK) at 1/16 of the electrical lane rate. The host shall optionally supply a reference clock (REFCLK) at 1/64 of the electrical lane rate. The REFCLK shall be CML differential AC coupled and terminated with 50 Ohm internal VTT within the MSA-100GLH, as shown in Figure 3. A frequency locked relationship is required between the transmit data lanes (TX/TXDSC) and the reference clock (REFCLK). There is no required phase relationship between the data lanes and the reference clock. The REFCLK frequency shall not deviate from nominal by more than ±20 ppm. Detailed reference clock characteristics for the MSA-100GLH are given in Table 2. When the two MSA client interfaces are connected back-to-back for regenerator application then the two DC blocking capacitors are used in series and this will change the filter cutoff frequency.

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applications1. This rate is optimized for triggering high-speed sampling scopes. Clock termination is shown in Figure 3. TXMCLK characteristics are summarized in Table 3. 8.3.5 Receiver Monitor Clock (RXMCLK) The MSA-100GLH optionally may supply a receiver monitor clock (RXMCLK). This clock is intended to be used as a reference for measurements of the module receive data. If provided, the clock shall operate at 1/16 of the receiver electrical lane data rate. The RXMCLK may optionally operate at 1/64 of the receiver electrical lane data rate. Clock termination is shown in Figure 3. RXMCLK characteristics are summarized in Table 3.

Table 3: Optional TXMCLK and RXMCLK Characteristics

Parameter Symbol Min Typ Max Unit Notes Impedance Zd 80 100 120 Ω Frequency - TXMCLK

1/8 Of TX optical symbol rate - default

Frequency - RXMCLK

1/16 Of RX electrical lane data rate - default

1/64 Of RX electrical lane data rate - optional

Output Differential Voltage

VDIFF 400 1600 mV Peak-to-Peak Differential

Clock Duty Cycle CDC 40 60 % 8.4 Control Pins (non-MDIO) Functional Description The control functions between a host and a MSA-100GLH are conducted through a set of dedicated, non-data hardware signal pins on the 168-pin electrical connector and via an MDIO interface. The signal pins work together with the MDIO interface to form a complete HOST/MSA-100GLH management interface. Upon module initialization, the control functions are available. Pins allocated to control functions in the 168-pin electrical connector are listed in Table 4.

1 For 40G applications, other clock rates may be necessary for operating with available test equipment.


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Table 4: MSA-100GLH Control Pins (non-MDIO)

Pin #

Symbol Description I/O

Logic “H” “L” Pull-up /down

B20 PRG_CNTL1 Programmable Control 1 Default: TRXIC_RSTn, TX & RX ICs reset, “0”: reset, “1” or NC: enabled

I 3.3V LVCMOS

Per MDIO document

Pull–Up1

B19 PRG_CNTL2 Programmable Control 2 For Future Use

I 3.3V LVCMOS

Pull–Up1

B18 PRG_CNTL3 Programmable Control 3 For Future Use

I 3.3V LVCMOS

Pull–Up1

B13 PM_SYNC Performance Monitoring Sync Rising edge synchronizes PM statistics counters

I 3.3V LVCMOS

Pull-Down2

B11 TX_DIS Transmitter Disable “0”: transmitter enabled “1” or NC: transmitter disabled

I 3.3V LVCMOS

Disable Enable Pull-Up1

B10 MOD_LOPWR Module Low Power “0”: power-on enabled “1” or NC: module in low power (safe) mode

I 3.3V LVCMOS

Low Power

Enable Pull–Up1

B9 MOD_ RSTn Module Reset “0”: resets the module “1”: module enabled

I 3.3V LVCMOS

Enable Reset Pull-Down2

Note 1: Pull-Up resistor (4.7k - 10kOhm) is located within the MSA-100GLH. Note 2: Pull-Down resistor (4.7k - 10kOhm) is located within the MSA-100GLH. 8.4.1 Programmable Control Pins (PRG_CNTLs) The Programmable Control pins (PRG_CNTL) allow the host to program certain MSA-100GLH control functions via a hardware pin. The intention is to allow for maximum design and debug flexibility. The default setting for Control 1 is control of the Transmit & Receive Reset. Controls 2 and 3 are for future use.

8.4.1.1 Programmable Control 1 Pin (PRG_CNTL1) Programmable Control 1 Pin (PRG_CNTL1) is an input pin from the host, operating with programmable logic. It is pulled up in the MSA-100GLH. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. The default function is Transmit & Receive circuitry reset (TRXIC_RSTn) with active-low logic. When TRXIC_RSTn is asserted (driven low), the digital transmit and receive circuitry is reset clearing all FIFOs and/or resetting all CDRs. When de-asserted, the digital transmit and receive circuitry shall resume normal operation.

8.4.1.2 Programmable Control 2 Pin (PRG_CNTL2) Programmable Control 2 Pin (PRG_CNTL2) is an input from the host, operating with programmable logic. It is pulled up in the MSA-100GLH. It can be re-programmed over MDIO registers to another MDIO control register while the module is in any steady state except Reset. It is reserved for future use.

8.4.1.3 Programmable Control 3 Pin (PRG_CNTL3)

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www.oiforum.com 17

Table 5: MSA-100GLH Alarm Pins (non-MDIO)

Pin #


Logic “H” “L” Pull-up/down

B16 PRG_ALRM1 Programmable Alarm 1 set over MDIO

O 3.3V LVCMOS


O 3.3V LVCMOS


O 3.3V LVCMOS

B8 RX_LOS Receiver Loss of Signal O 3.3V LVCMOS

LOS OK

A78 MOD_ABS Module Absent “0”: module present “1” or NC: module absent

O GND Absent Present Pull-Down1

B7 GLB_ALRMn Global Alarm O 3.3V LVCMOS w/ Open Drain

OK Alarm Note 2

A11 RX_ALRM_OUT

Receiver Alarm transfer output for Re-generator mode

O 3.3V LVCMOS

OK Alarm

A12 RX_ALRM_IN Receiver Alarm transfer input for Re-generator mode

I 3.3V LVCMOS

OK Alarm

Note 1: Pull-down resistor (<100Ohm) is located within the MSA-100GLH. A Pull-Up resistor should be located on the host. Note 2: Pull-Up resistor on host. 8.5.1 Programmable Alarm Pins (PRG_ALRMs) The Programmable Alarm pins enable the host system to program MSA-100GLH supported alarms to dedicated hardware pins.

8.5.1.1 Programmable Alarm 1 Pin (PRG_ALRM1) Programmable Alarm 1 Pin (PRG_ALRM1) is an output to the host, operating with programmable logic. It can be re-programmed over MDIO registers to another MDIO alarm register while the MSA-100GLH is in any steady state except Reset. The default function is High Power On (HIPWR_ON) indicator with active-high logic.

8.5.1.2 Programmable Alarm 2 Pin (PRG_ALRM2) Programmable Alarm 2 Pin (PRG_ALRM2) is an output to the host, operating with programmable logic. It can be re-programmed over MDIO registers to another MDIO alarm register while the MSA-100GLH is in any steady state except Reset. The default function is Module Ready (MOD_READY) indicator with active-high logic. The default function MOD_READY is used by the MSA-100GLH during the module initialization. When asserted, it indicates the MSA-100GLH has completed the necessary initialization process and is ready to transmit and receive data.

8.5.1.3 Programmable Alarm 3 Pin (PRG_ALRM3)

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www.oiforum.com 20

Table 6: MSA-100GLH MDIO Management Interface Pins

Pin #


Logic “H” “L” Pull-up /down

A28 MDIO Management Data I/O bi-directional I/O

1.2V LVCMOS

A27 MDC MDIO Clock I 1.2V LVCMOS

B21 PRTADR0 MDIO Physical Port Address bit 0 I 1.2V LVCMOS





8.6.1 Management Data Input/Output Pin (MDIO) The MDIO specification is defined in IEEE 802.3 Clause 45 [N1]. The MSA-100GLH shall support 4.0 Mbit/s maximum data rate. The MSA-100GLH uses an MDIO with 1.2V LVCMOS logic. 8.6.2 Management Data Clock Pin (MDC) The host specifies a maximum MDC rate of 4.0 MHz and MSA-100GLH hence shall support a maximum MDC rate up to 4.0 MHz. The timing diagram for the MDIO and MDC pins is illustrated in Figure 8: Module MDIO & MDC Timing Diagram

The MSA-100GLH shall support a minimal setup (tsetup) and hold (thold) time in its MDIO implementation (see Table 9).


www.oiforum.com 21

Figure 8: Module MDIO & MDC Timing Diagram

Note: Measured at Module MDIO & MDC pins. 8.6.3 MDIO Physical Port Address Pins (PRTADRs) The MDIO Physical Port Address pins (PRTADRs) are used by the host system to address all of the MSA-100GLHs contained within its management domain. PRTADR0 corresponds to the LSB in the physical port addressing scheme. The 5-pin Physical Port Address lines are driven by the host to set the module Physical Port Address which should match the address specified in the MDIO Frame. It is recommended that the Physical Port Addresses not be changed while the MSA-100GLH is powered on. 8.7 Hardware Signaling Pin Electrical Specifications 8.7.1 Control & Alarm Pins: 3.3V LVCMOS Electrical Characteristics The hardware control and alarm pins specified as 3.3V LVCMOS functionality described above shall meet the electrical characteristics described in Table 7. Figure 9 illustrates the recommended reference pin input and output terminations.

Table 7: 3.3V LVCMOS Electrical Characteristics

Parameter Symbol Min Typ Max Unit Supply Voltage VCC 3.2 3.3 3.4 V Input High Voltage VIH 2 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Input Leakage Current IIN -10 - +10 µA Output High Voltage (IOH=-100 µA) VOH VCC-0.2 - - V Output Low Voltage (IOL= 100 µA) VOL - - 0.2 V

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put Capacitan

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Interface P

specified as ristics describut termination

Table 8: 1

age age Current oltage ltage

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nce +3.3V LV

Pins: 1.2V

1.2V LVCMbed in Table ns.

1.2V LVCM

SymVVI

VVII

VCMOS Inp

LVCMOS

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OS Electrica

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Min Ty.84 -0.3 -100 -1.0 -0.3 -- -

+4 -- -

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ristics

yp Max- 1.5 - 0.36- +100- 1.5 - 0.2 - -4 - - - 10

0GLH-EM-02

2

ns

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shall meet thnded referenc

x Unit V 6 V 0 µA V V

mA mA

pF

2.1

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Figure 11: MSA-100GLH Simplified Start-Up Flow Diagram

The MSA-100GLH is designed to support a range of optical transport applications. Many of the timing parameters associated with the module hardware control and alarm pins are application specific and thus are not specified in this IA. A summary of the timing parameters for the MSA-100GLH is given in Table 9.

Table 9: Hardware Signaling Pins Timing Parameters Summary

Parameter Symbol Min Max Unit Notes Transmitter Disabled (TX_DIS asserted)

t_off Application specific. Defined by module vendor.

Transmitter Enabled (TX_DIS de-asserted)

t_on Application specific. Defined by module vendor.

MOD_LOPWR on t_MOD_LOPWR_on Application specific. Defined by module vendor.

MOD_LOPWR off t_MOD_LOPWR_off Application specific. Defined by module vendor.

Module Reset Assert MOD_RSTn Application specific. Defined by module vendor.

Module Reset De-assert MOD_RSTn Application specific. Defined by module vendor.

Module Absent MOD_ABS Application specific. Defined by module vendor.

Receiver Loss of Signal Assert Time

t_loss_on Application specific. Defined by module vendor.

Receiver Loss of Signal t_loss_off Application specific.


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De-assert Time Defined by module vendor.

Global Alarm Assert Delay Time

t_GLB_ALRMn_on This is a logical “OR” of associated MDIO alarm & status registers. See MDIO spec for details.

Global Alarm De-assert Delay Time

t_GLB_ALRMn_off This is a logical “OR” of associated MDIO alarm & status registers. See MDIO spec for details.

Management Interface Clock Period

tprd 250 ns MDC is 4 MHz rate; duty cycle = 50% ± 10% (typ.)

Host MDIO setup time tsetup 10 ns Host MDIO hold time thold 10 ns Module MDIO delay time

tdelay 175 ns

Performance Monitoring Synchronization (PM_SYNC) (optional)

Default period=1 sec. ; min high/low time = 100msec.

9 Mechanical Specifications 9.1 Mechanical Overview The MSA-100GLH is designed to be assembled into a host system line card. The MSA-100GLH is electrically connected to the host line card by a 168 position connector specified herein and is physically fastened to the host line card by mounting screws through the host line card PCB. The MSA-100GLH supports two optical fiber pigtails, one for optical transmit and one for optical receive. These optical fiber pigtails are terminated and attached to host line card face plate. The MSA-100GLH is not designed to be hot-pluggable. Its power and initialization sequencing in the host line card are specified by the host line card and transponder vendors. 9.2 Electrical Connector The Hirose FX10A-168P/S-SV(83) connector assembly [N3] is specified for the host line card – MSA-100GLH electrical connector. This connector is a two component (header, receptacle), 168 position, board mounted style assembly. It meets CEI-11G-MR [N2] signal integrity performance and provides 4mm - 8mm mated stack height flexibility by header component changes only, i.e. the MSA-100GLH receptacle component remains fixed. Detailed mechanical specifications and layout design application notes may be found at [N3]. The Hirose FX10B-168P/S-SV(83) connector assembly [N3] is also specified as an option for the host line card – MSA-100GLH electrical connector. The FX10A connector style has guidepost

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9.2.2 The hassemFX10

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O

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Figure 14: FX10 Connector Alignment

9.3 Module Dimensions Two options are specified for the MSA-100GLH mechanical dimensions:

1) Flattop 2) Integrated Heat Sink

The flattop option is specified to allow customization of the MSA-100GLH bolt-on heat sink for supporting a wide array of optical transport applications. With this option, the bolt-on heat sink is specified by the host system designer, allowing maximum flexibility in their system design while maintaining a common module form factor. The integrated heat sink option is specified to simplify the host system design and supports module thermal performance per the maximum power consumption specified in Section 8.2. Mechanical dimensions of the MSA-100GLH with non-conductive sheet are specified in Figure 15. If a non-conductive sheet is used, the thickness is specified as 0.15 +/- 0.05mm.

Maximum Gap should be

Maximum allowable misalignment of the FX10

αφ ±GP

βφ ±GH

χ±pitchpin Guide

δ±pitch holepin Guide

ε±accuracy mounting CN

ϕ±accuracy mounting CN

αφ ±GP

βφ ±GH

χ±pitchpin Guide

δ±pitch holepin Guide

ε±accuracy mounting CN

ϕ±accuracy mounting CN

( ) ( ) ϕεδχαφβφ+++≥

+−=

2GP-GH

Gap Maximum

( )( )

22

2GP-GH

2GPGHβαϕεδχφφβαϕεδχφφ

++×+++≥

++×++++≥

( ) CN theofnt misalignme Maximum2

2≤

++×+++ βαϕεδχ

( ) 03.02

2≤

++×+++ βαϕεδχ [mm] 0.42


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Figure 15: MSA-100GLH Non-conductive Sheet Dimensions

Note: The module vendor must ensure the module connector receptacle component is placed to enable the module to properly mate with the host connector header when the minimum height header component (i.e. C=4mm) is used by the host. 9.3.1 Flattop Mechanical dimensions of the MSA-100GLH flattop module are specified in Figure 16. The maximum module size is specified as: 101.6mm x 127.0mm (4” x 5”) Figure 16 also specifies the receptacle connector position, connector guide pin locations and module mounting hole locations.

Module and Host PCB dimensions and tolerances in mm.

MSA Module PCB

Host PCB

Header Recept.

Sheet Thickness : S +/- s Module base: B +/- b Conn. stacking height: C +/- c Solder paste thickness: P +/- p

MSA Module

B P

S C

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3

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Figure 17: MSA-100GLH Flattop mechanical dimensions - top view

9.3.2 Integrated Heat Sink Mechanical dimensions of the MSA-100GLH with integrated heat sink are specified in Figure 17. The maximum module size is specified as: 101.6mm x 127.0mm (4” x 5”) Figure 17 also specifies the receptacle connector position, connector guide pin locations and module mounting hole locations.

RX TX

18.0 MAX

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Figure 19: MSA-100GLH with Integrated Heat Sink - top view

9.4 Host System Dimensions The recommended host system dimensions including host board layout are given in Figure 20. PCB design guidelines for the Hirose FX10 connector assembly may be found at Reference [I4].

RX TX

18.0 MAX


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Figure 20: Recommended Host System Layout for MSA-100GLH

9.5 Module Optical Fiber Ports The MSA-100GLH optical transmit and receive fiber pigtail port location, dimensions and orientation are specified in Figure 21. The fiber pigtail type, length and connector type parameters are vendor specified and not specified in this document. The fiber boot exit area is solely for the purpose of indicating where the fibers are to exit the module side-wall with fiber boots for strain relief.

18.0 MAX


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Figure 21: MSA-100GLH Optical Fiber Port Location and Dimensions

9.6 Pin Assignment The MSA-100GLH electrical connector has 168 pin positions that are arranged in a dual-row assembly. The pin assignment is specified in Table 10. Detailed description of the pin assignment is given in

18.0 MAX


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Table 11 and Table 12. The pin orientation is illustrated in Figure 17.


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Table 10: MSA-100GLH Pin-Map (Note: Pins for future use (FFU) should be left unconnected on both the host board and the MSA module)

RX_ALRM_OUTRX_ALRM_IN

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Table

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e 11: MSA-1100GLH Elecctrical Conn

nector - Row

O

w B Pin Desc

OIF-MSA-100

cription

0GLH-EM-02

3

2.1

38


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Table 12: MSA-100GLH Electrical Connector - Row A Pin Description (Note: Pins for future use (FFU) should be left unconnected on both the host board and the module)

O LVCMOSI LVCMOS ‐

RX_ALRM_OUTRX_ALRM_IN Receiver Alarm transfer input for Re-generator mode

Receiver Alarm transfer output for Re-generator mode


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10 References 10.1 Normative references [N1] IEEE 802.3ba™ -2010 “Amendment: Media Access Control Parameters, Physical Layers and Management Parameters for 40Gb/s and 100Gb/s Operation”, Clause 45 – MDIO (March, 2010) [N2] OIF-CEI-02.0 - Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps and 11G+ bps I/O (February 2005) [N3] Hirose FX10 Datasheets: http://www.hiroseusa.com/Special_downloads18.asp 10.2 Informative references [I1] OIF-FD-100G-DWDM-01.0 - 100G Ultra Long Haul DWDM Framework Document (June 2009) [I2] ITU-T Rec. G.709/Y.1331 (v4.2 – Feb. 2012) Interfaces for the Optical Transport Network (OTN) [I3] OIF-SFI-S-01.0 – Scalable Serdes Framer Interface (SFI-S): Implementation for Interfaces Beyond 40G for Physical Layer Devices (Nov. 2008) [I4] Hirose FX10 PCB Routing Guideline: http://www.hiroseusa.com/FX10_PCB_routing_guideline_v1.2.pdf [I5] CFP MSA Management Interface Specification V2.2, r06a (July 1, 2013) 11 Appendix A: Glossary ADC Analog Digital Converter CDR Clock and Data Recovery CN Connector CML Current Mode Logic CMOS Complementary Metal Oxide Semiconductor DEC Decoder DSP Digital Signal Processor DWDM Dense Wavelength Division Multiplex ENC Encoder FEC Forward Error Correction FFU For Future Use Gbaud 109 Symbols Per Second GH Guide pin Hole GND Ground GP Guide Pin IA Implementation Agreement LVCMOS Low Voltage CMOS MDC Management Data Clock MDIO Management Data Input/Output NC No Connect OIF Optical Internetworking Forum OTL Optical channel Transport Lane PCB Printed Circuit Board PM-QPSK Polarization Multiplexed Quaternary Phase Shift Keying RX Receiver


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SFI Serdes Framer Interface TX Transmitter VND Vendor 12 Appendix B: Open Issues / current work items None.


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13 Appendix C: List of companies belonging to OIF when

document is approved Acacia Communications Kaiam ADVA Optical Networking Kandou Alcatel-Lucent KDDI R&D Laboratories Altera Keysight Technologies, Inc. AMCC LeCroy Amphenol Corp. Luxtera Analog Devices M/A-COM Technology Solutions Anritsu Mellanox Technologies Applied Communication Sciences Microsemi Inc. Avago Technologies Inc. Microsoft Corporation Broadcom Mitsubishi Electric Corporation Brocade Molex BRPhotonics MoSys, Inc. BTI Systems MultiPhy Ltd China Telecom NEC Ciena Corporation NeoPhotonics Cisco Systems NTT Corporation ClariPhy Communications Oclaro Coriant R&G GmbH Orange CPqD PacketPhotonics Deutsche Telekom PETRA Dove Networking Solutions Picometrix EMC Corp PMC Sierra Emcore QLogic Corporation Ericsson Qorvo ETRI Ranovus FCI USA LLC Rockley Photonics Fiberhome Technologies Group Samtec Inc. Finisar Corporation Semtech Fujikura Spirent Communications Fujitsu Sumitomo Electric Industries Furukawa Electric Japan Sumitomo Osaka Cement Google TE Connectivity Hewlett Packard Tektronix Hitachi TELUS Communications, Inc. Huawei Technologies TeraXion IBM Corporation Texas Instruments


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Infinera Time Warner Cable Inphi US Conec Intel Verizon Ixia Xilinx JDSU Yamaichi Electronics Ltd. Juniper Networks ZTE Corporation

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ia # oif-m sa-100g - optical internetworking forum · 08.05.2015 · 100 orig ia p imp g lon mod...

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