Accurate Estimation of Analog Test Metrics WithExtreme Circuits

Kamel Beznia†, Ahcène Bounceur†, Louay Abdallah‡, Ke Huang‡, Salvador Mir‡, Reinhardt Euler††Lab-STICC Laboratory - European University of Britanny - University of Brest

20, Avenue Victor Le Gorgeu, 29238, Brest, FranceEmail: {Kamel.Beznia, Ahcene.Bounceur, Reinhardt.Euler}@univ-brest.fr

‡TIMA Laboratory, 46, Avenue Félix Viallet, 38031, Grenoble Cedex, FranceEmail: {Salvador.Mir, Louay.Abdallah, Ke.Huang}@imag.fr

Abstract— Specification-based testing of analog/RF circuits isvery costly due to lengthy test times and highly sophisticatedtest equipment. Alternative test measures, extracted by meansof Built-In Test (BIT) techniques, are a promising approach toreplace standard specification-based tests. However, these testmeasures must be evaluated at the design stage, before the realproduction, by estimating parametric test errors such as TestEscapes (TE) and Yield Loss (YL). An accurate estimation of thesemetrics requires a large non-biased sample of circuit instancesincluding parametric defective ones. Since these extreme circuitsare rare events, they cannot be obtained with a Monte Carlosimulation of an affordable size. However, statistical learningtechniques, in combination with Monte Carlo simulation, canallow the generation of such a sample for multivariate test metricsestimation. In this paper, we will demonstrate this techniquefor the evaluation of an RF LNA BIT technique for which alarge database of 106 circuits has been simulated for comparisonpurposes.

I. INTRODUCTION

BIT is a promising alternative to replace highly costlyanalog/RF specification-based tests. The integration of a BITtechnique in a real circuit must be validated at the design stageby estimating the test errors that such an approach can leadto. Since there are no manufactured circuits at this stage, testerrors can only be validated by simulation.

Monte Carlo circuit simulation allows the generation ofa relatively small sample of circuit instances under processvariations. Each circuit instance is represented by a vectorof its output parameters (the performances specified in thedata sheet and the test measures). A functional circuit is theone for which all performances meet the specifications. Acircuit is faulty if at least one performance does not meet itsspecifications. Similarly, a circuit passes the test if all its testmeasures are within their pre-defined limits. Otherwise, thecircuit fails the test. A test error occurs when either a faultycircuit escapes the test (i.e. Test Escapes, TE) or a functionalcircuit fails the test (i.e. Yield Loss, YL). The evaluation ofthese test metrics with high precision, at ppm level, can bedone only with a very large sample of circuits. Unfortunately,Monte Carlo circuit simulation is time consuming and cangenerate a relatively small sample in a reasonable time.

Several methods are proposed to overcome this limitation.Most of them are based on the estimation of the joint proba-bility density function (PDF) of the output parameters using a

small sample of circuits generated via Monte Carlo simulation.Next, by sampling this statistical model, it is possible tonumerically generate an arbitrarily large sample of circuits thatfollows the same distribution. This large sample will containa representative set of parametric defective devices, and testmetrics can be calculated using relative frequencies. In [1] thestatistical model is assumed to be a multivariate Gaussian. In[2], a general parametric method is proposed using the theoryof Copulas. A copula is a multivariate distribution that modelsthe dependence structure between the output parameters, inde-pendently of the marginal laws of the parameters. However, thecopula is not easy to identify. When the copula is not known,[3] proposes the use of non-parametric density estimation. Themajor problem with these techniques is that the estimatedPDF of the output parameters is less accurate at the tailsof the distribution, where the defective circuits necessary forestimating test errors are found. This is because in the initialsample of Monte Carlo circuits used for PDF estimation, thereare in general no circuits with output parameters at the tailsof the distribution. Thus, the accuracy at the ppm level of thetest errors may be questionable.

Recently, [4] has presented a technique that uses statisticallearning to accelerate Monte Carlo simulation. First, a mul-tidimensional classifier is used to learn a boundary of theinput parameter space of the circuit under test (CUT) forwhich the output parameters are in the bulk of the distribution.Next, during Monte Carlo simulation, the simulation of aninstance is blocked if the classifier predicts that the outputparameters will fall in the bulk of the distribution. On the otherhand, those circuits for which the classifier predicts that theoutput parameters will fall beyond the boundary are simulated.[4] has considered extreme circuits generated this way andunivariate Extreme Value Theory for the estimation of memoryyield. Later, a similar technique has been considered in [5]to estimate test metrics in a univariate case (a single outputperformance).

In this paper, we will show how extreme circuits can be usedfor an accurate computation of test metrics for a multivariatecase-study, assuming that the statistical learning technique pro-posed in [4] can be used. Section II presents the formulation ofthe test metrics estimation in the case of multivariate extremecircuits. The estimators of these test metrics and the way to

calculate them are presented in Section III. The test vehicule ispresented in Section IV. Section V presents the estimation ofthese metrics considering an RF LNA BIT technique for which106 circuits have been simulated for comparison purposes.Finally, the conclusion is presented in Section VI.

II. PROBLEM FORMULATION

Let us consider a circuit with n performances P =(P1, P2, . . . , Pn) and n specifications s = (s1, s2, . . . , sn).This circuit is designed such that each performance Pi satisfiesthe specification si (i.e. Pi ≤ si). For this circuit, we considera set of m test measures T = (T1, T2, . . . , Tm) and m testlimits l = (l1, l2, . . . , lm). The circuit passes the test if eachtest measure Ti satisfies the test limit li (i.e. Ti ≤ li). As abovementioned, we are interesting in computing the test errors,namely the Test Escapes TE (also called Defect Level) andthe Yield Loss YL.

In the following we will use two notations, TE0and TE ,

that refer to the same quantity (i.e. TE0= TE) but calculated

from different sets of circuits. The first one, TE0, is the value

of the Test Escapes obtained from a set of circuits generatedwith the Monte Carlo circuit simulation. The second one, TE ,is the Test Escapes obtained from a subset of circuits thatpasses the test selected from the circuits generated from theMonte Carlo circuit simulation. We use the same notation forthe Yield Loss (i.e. YL0

and YL with YL0= YL).

In terms of probability, TE0is the probability that a circuit

is faulty knowing that it passes the test, and, YL0 is theprobability that a circuit fails the test knowing that it isfunctional. They are given as follows:

TE0= Pr((P1 > s1 ∨ P2 > s2 ∨ . . . ∨ Pn > sn)

|(T1 ≤ l1 ∧ T2 ≤ l2 ∧ . . . ∧ Tm ≤ lm)) (1)

YL0= Pr((T1 > l1 ∨ T2 > l2 ∨ . . . ∨ Tm > ln)

|(P1 ≤ s1 ∧ P2 ≤ s2 ∧ . . . ∧ Pn ≤ sn)) (2)

By applying Bayes’ theorem we can define TE0as the

probability that a circuit is faulty and passes the test overthe probability that a circuit passes the test. Then, TE0 can beestimated on a set of N circuits as follows:

TE0=Nbp

Np(3)

where Nbp is the number of circuits that are faulty and passthe test, and Np is the number of the circuits that pass thetest.

In the same way, we can define YL0as the probability that

a circuit is functional and fails the test over the probabilitythat a circuit is functional. Then, YL0 can be estimated on aset of N circuits as follows:

YL0=Ngf

Ng(4)

where Ngf is the number of circuits that are functional andfail the test, and, Ng is the number of the circuits that arefunctional.

Now, if we consider only circuits that pass the test then TEcan be defined as the probability that a circuit is faulty. In otherterms, it is the probability to violate at least one specification.

TE = Pr(P1 > s1 ∨ P2 > s2 ∨ . . . ∨ Pn > sn) (5)

If we consider only circuits that are functional then YL canbe defined as the probability that a circuit fails the test. Inother terms, it is the probability to violate at least one testlimit. Formally,YL = Pr(T1 > l1 ∨ T2 > l2 ∨ . . . ∨ Tm > lm) (6)

Henceforth, we will consider the set of circuits that passthe test, to estimate the TE , and the set of circuits that arefunctional, to estimate the YL. The challenge in estimating theresulting TE and YL during the test development phase lies onthe fact that their values are typically very small, in the orderof a few hundred parts per million (ppm) or less. In these cases,the events to violate specifications or test limits are rare. Witha small set of circuits, these test metrics are equal to zero (i.e.TE = 0 and YL = 0). Therefore, it is required to perform atleast one million circuit simulations to obtain ppm precision,which clearly poses a computational burden. To overcome thislimitation, we will consider in this paper only circuits withextreme values of performances and test measures. These arecircuits having values of their performances and test measuresthat exceed a certain high threshold u = (u1, u2, . . . , un)where ui < si, (i = 1, . . . , n). This can be done by thestatistical blockade method proposed in [4].

We can then rewrite the test metrics by taking into accountthe extreme circuits. Hence, let us define A = (P1 > s1∨P2 >s2 ∨ . . . ∨ Pn > sn) and B = (P1 > u1 ∨ P2 > u2 ∨ . . . ∨Pn > un) such that A ⊆ B. Then the probability TE can becalculated as follows:

TE = Pr(A) (7)= Pr(A ∧B) (8)= Pr(A|B)× Pr(B) (9)

We replace A and B in equation 9 and obtain:

TE = Pr

((P1 > s1 ∨ · · · ∨ Pn > sn)

(P1 > u1 ∨ · · · ∨ Pn > un)

)×

Pr(P1 > u1 ∨ · · · ∨ Pn > un) (10)

In the same way, we can write YL as

YL = Pr

((T1 > l1 ∨ · · · ∨ Tn > ln)

(T1 > u1 ∨ · · · ∨ Tn > un)

)×

Pr(T1 > u1 ∨ · · · ∨ Tn > un) (11)

III. ESTIMATION OF TE AND YL

First, note that in this work we will run two Monte Carlosimulations. The first one allows finding the thresholds u of theperformances and test measures and a classifier for speedingup the generation of extreme circuits. The second simulationuses the classifier to simulate only circuits that are in principleextremes. These circuits have performances and test measuresgreater than the thresholds found in the first simulation.

From Equation (10) we conclude that TE can be defined inthe set of circuits that pass the test as the probability thatthe circuit is faulty knowing that it is extreme, times theprobability that the circuit is extreme. Thus, the estimated TEis given as follows :

TE =Ned

Ne× Nu

Np(12)

where Ne is the number of extreme circuits (in the secondMonte Carlo circuit simulation), Ned is the number of thefaulty extreme circuits (in the second Monte Carlo circuitsimulation), Nu is the number of extreme circuits (thoseexceeding the high thresholds ui) (in the first Monte Carlocircuit simulation), and Np is the number of circuits that passthe test (in the first Monte Carlo circuit simulation).

To illustrate these parameters, Figure 1 shows an examplein the bivariate case.

s1

s2

X

Y

u1

u2

Ned Ne

Nu

Np

Fig. 1. Estimate of the TE for the bivariate case.

In the same way and from Equation (11), we conclude thatYL can be defined in the set of circuits that are functional asthe probability that the circuit fails the test knowing that itis extreme, times the probability that the circuit is extreme.Thus, the estimated YL is given as follows :

YL =Nef

Ne× Nu

Ng(13)

where, Ne is the number of extreme circuits (in the secondMonte Carlo circuit simulation), Nef is the number of theextreme circuits that fail the test (in the second Monte Carlocircuit simulation), Nu is the number of extreme circuits(those exceeding the high thresholds ui) (in the first MonteCarlo circuit simulation), Ng is the number of circuits that arefunctional (in the first Monte Carlo circuit simulation).

In summary, the procedure to estimate TE based on Equa-tion (10) is as follows:

1) Run the first Monte Carlo circuit simulation in order togenerate N circuits p1,p2, ...,pN , and build a classifieras in [4].

2) We consider Np ≤ N circuits p1,p2, ...,pNpthat pass

the test with n performances (i.e. pi = (p1i , p2i , ..., p

ni )

where, i = 1, ..., Np).

EDBICS

Fig. 2. Layout of the chip.

3) Calculate thresholds ui for each performance Pi whichare based on the q-quantile. For example, fixing a q-quantile to 97% allows to find the threshold ui so that100 − 97 = 3% of the values pji , j = 1, ..., Np will begreater than ui. Thus Nu

Np≈ 3× 0.03 = 0.09 in the case

of three performances.4) Run the second Monte Carlo circuit simulation in order

to generate Ne extreme circuits using the classifier learntin the first simulation.

5) From this new sample, select the Ned circuits that arefaulty, that is, those that violate at least one specification.

6) Estimate TE using Equation (12).The same procedure is used to estimate YL using Equation(13).

IV. TEST VEHICLE

Our case study is an RF Low Noise Amplifier (LNA)that operates at 2.4 GHz and which is commonly used innarrow band applications like Wifi and Bluetooth. There aretwo different built-in sensors : a) an envelope detector (ED)that consists of a half-wave rectifier followed by a low-passfilter that extracts the DC component from the rectified signal[6]. The output of this sensor is directly related to the RFoutput amplitude of the LNA. And b) a built-in current sensor(BICS), originally proposed in [7], that takes advantage fromthe small resistance of the power line that connects the coreof the LNA to the power supply pad. Whenever a currentICUT flows into the LNA, it generates a small voltage dropacross the resistor. This drop is processed by the sensor inorder to extract an output voltage proportional to the dynamicpower supply current. For measurement, the BICS output isconnected to the input of the envelop detector to extract theDC component.

The chip design and layout are realised using an 0.25 umBiCMOS process technology provided by NXP semiconduc-tors. The layout of the LNA and the BIT sensors is shownin Figure 2. Special care is taken to account for layout-induced parasitics, including capacitive, resistive, inductive, aswell as mutual inductance effects. The extraction of parasiticsis carried out using the Assura tool and the circuits arere-sized to meet the performance requirements. Post-layoutsimulations using Spectre RF show that the nominal mainperformances of the LNA are: S11 = -22 dB, Gain = 16.4dB, Noise Figure = 2.72 dB, IIP1 = -7.5 dBm and IIP3 = 3dBm. Finally, for comparison purposes, a Monte Carlo circuitsimulation of 106 circuits has been carried out to extract

the LNA performances and the BIT sensor outputs. Thissimulation has taken about three months. For each instance,we recorded the output parameters, that is the values ofthe performances (Gain,NF, S11) and the test measurements(TED, TCS). We notice that we have not considered IIP1 andIIP3 performances, since their simulation takes a very longtime and it is not feasible for 106 circuits. The specificationsof the three performances are set at k1σ i.e.

gain ≥ sgain = µgain − k1 · σgainNF ≤ sNF = µNF + k1 · σNF

S11 ≤ sS11= µS11

+ k1 · σS11

The test limits on TED and TCS are set at k2 , i.e.

TED ≥ lTED= µTED

− k2 · σTED

TCS ≥ lTCS= µTCS

− k2 · σTCS

V. TEST METRICS ESTIMATION

In this Section, we will use the proposed method to evaluatethe test metrics of the RF LNA BIT technique presented above.We will compare the results with those obtained using the fullset of data.

A. Direct estimation using the Monte Carlo simulation

Since we have a set of 106 circuits generated from theMonte Carlo circuit simulation, we can directly estimate testmetrics using the estimators given by Equations (3) and (4).We have fixed the specifications at k1 = 4, whereas the testlimits are set at k2 ranging from 2 to 6 with a step of 0.1.The obtained results are illustrated by the red circle curve inFigure 3.

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●●●●●●●●●●●●●●●●●●●●●●●●●

2 3 4 5 6

0100

200

300

400

500

k2/k1=4

ppm

++++++++++++++++++++++++++++++++++++++++

2 3 4 5 6

0100

200

300

400

500

k2/k1=4

ppm

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●●●●●●●●●●●●●●●●●●●●●●

2 3 4 5 6

0100

200

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k2/k1=4

ppm

+

+

+

+

+

+++++++++++++++++++++++

2 3 4 5 6

0100

200

300

400

500

k2/k1=4

ppm

YL

TE

Fig. 3. Test metrics (YE and YL) as a function of k1 = 4 and k2 = 2 to6 with a step of 0.1 (with 40 · 103 extreme circuits).

B. Estimation using the proposed method

Next, we apply the procedure presented in Section III. First,we run N = 3000 Monte Carlo circuit simulations. In practice,we picked up the first 3000 instances from the set of 106. Fordifferent values of the test limits, fixed at k2 = 2 to k2 = 6with a step of 0.1, we will select in each iteration only circuitsthat pass the test. For example, for k2 = 4 the number of thecircuits that pass the test is equal to Np = 3000. Then, this set

will be used to calculate the three thresholds uGain, uNF anduS11 corresponding to each performance with a q-quantile of97%. In this case, Nu

Np≈ 3× 0.03 = 0.09.

Considering these thresholds, we run the second MonteCarlo circuit simulation that requires a classifier in order togenerate a set of Ne = 40 · 103 extreme circuits. In practice,we picked up the first 40 · 103 extreme circuits from the setof 106. Among these, we select Ned circuits that are faulty,that is, those that violate at least one specification. In the casewhere k1 = 4 and k2 = 4 the value of Ned equals 147. Thetest metrics can then be estimated for each value of k2 asmentioned above using Equations (12) and (13).

To estimate the YL we start with the circuits that arefunctional instead of those that pass the test. The obtainedresults of the YL are illustrated by the blue cross curve inFigure 3.

We can see that the results obtained using Ne = 40 · 103extreme circuits are very close to those obtained when the fullset of 106 circuits is used. In summary, an accurate estimationof test metrics is obtained with a fast Monte Carlo simulation.

VI. CONCLUSIONS

A new method to estimate analog test metrics (TE and YL)using a set of extreme circuits is presented. To our knowledge,this is the first time that test metrics are estimated usingextreme circuits for a multivariate problem.

An RF LNA BIT technique is used as a case-study, showingvery accurate results for the estimation of test metrics. With thespecifications set at 4σ, a set of only 40·103 extreme circuits isconsidered instead of the full set of 106 circuits. This set of 40·103 extreme circuits can easily be generated by Monte Carlocircuit simulation, in combination with a statistical learningtechnique. In this work, we have assumed an ideal classifier,since a full set of data of 106 circuits is available. In practice,the classifier will make errors, resulting in an increase of thenumber of required Monte Carlo simulations and a bias of thedistribution of extreme circuits. Future work will evaluate theeffects of these errors.

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