id lab personnel 2 visiting scholars ( nalu scientific) 4 postdocs...

ID Lab Personnel 2 Visiting scholars (Nalu Scientific)

4 Postdocs 1 staff engineer, 1 Faculy

3 PhD, 5 Masters Grad Students Numerous Undergraduates

Some points for discussion • Overview of current projects • An overview of transient waveform Switched

Capacitor Array devices • A couple of recent examples of fast, inexpensive

photosensor readout (Belle II, CTA) • Defining the ‘space-time’ limit • The low-power frontier

1

Instrumentation Dev. Lab Overview – Spring 2017 2

Some Current Projects High intensity

MCP-PMT Charge Sensitive

Amp GRAPH ASIC

Neutron Time Cube

Belle II Construction & Commissioning

(pixel, Silicon Upgrades)

ExaVolt Antenna (EVA) ANITA4/5

Cherenkov Telescope Array (CTA)

A Unifying Theme

3

• ATWD – IceCube

An Easily understood Selling Point

WFS ASIC Commercial Sampling speed 0.1-6 GSa/s 2 GSa/s

Bits/ENOBs 16/9-13+ 8/7.4

Power/Chan. <= 0.05W Few W

Cost/Ch. < $10 (vol) > 100$

• 2 GSa/s, 1GHz ABW Tektronics Scope • 2.56 GSa/s LAB

“oscilloscope on a chip”

4

Belle TOF FM PMT signal

Underlying Technology • Track and Hold (T/H)

• Pipelined storage = array of T/H elements, with output buffering

2 v V1=V Q=Cs.V1

N capacitors Write Bus

Return Bus

1

N caps

Vout=A / (1+A) * Q/Cs =V1 * A/(1+A)

3

Bottom Read BUS

4

Top Read Bus

Cs

C Analog Input

Sampled Data

T/H

5

Switched Capacitor Array Sampling

Input

Channel 1

Channel 2 Few 100ps delay

• Write pointer is ~few switches closed @ once

20fF

Tiny charge: 1mV ~ 100e-

6

Highly integrated services • A severely constrained space

7

Single photon detection for TOP • Single photon timing for MCP-PMTs

σ ~ 38.4ps

σ <~ 10ps (ideal waveform

sampling)

NIM A602 (2009) 438

σ <~ 50ps target

To include T0, clock distrib, timebase ctrl

NOTE: this is single-photon timing, not event start-time “T0”

σT0 = 25ps

8

IRSX ASIC Overview

• 8 channels per chip @ 2.8 GSa/s • Samples stored, 12-bit digitized in groups of 64 • 32k samples per channel (11.6us at 2.8GSa/s) • Compact ASICs implementation:

Trigger comparator and thresholding on chip On chip ADC Multi-hit buffering

Die Photograph

~8m

m

9

iTOP Readout “boardstack” (1 of 4 per TOP Module)

Carrier (x4)

SCROD

HV

Front (x2)

10

iTOP Readout Production Testing

Laser scan

• 2x Carrier test stations at South Carolina, 1x backup in Hawaii

• Laser test stand Hawaii • SCROD test stand in Pittsburgh • Firmware test at PNNL

Carrier test stand

11

Production single photon testing

Use SSTin period constraint to calibrate absolute timebase

~31ps TDC+phase SL-10 TTS ~35ps IRSX electronics:

~33ps

12

Note: CAMAC TDC and phototube TTS contributions included: actual resolution is better

Production – initial single photon timing

• All installed channels • 1 entry per channel

• Limited statistics

13

Instrumentation Dev. Lab Overview – Spring 2017

GCT Camera (CTA) – TARGET ASIC

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TARGET family Synopsis • ~21000 channels of TARGETX deployed for Belle II

K-long and Muon system scintillator upgrade • Each CTA camera 2048 channels • 256k storage cells per ASIC (>300 million tested) • 16 channel density attractive for compact sensor

arrays (e.g. high-density DIRC …) • 64 channel version (SiREAD) in design • Engineering run quantities: $1.40/channel

(ADC and trigger on-chip) • While not for precision timing, < 100ps

15

Looking back on >10 year development

• ASIC costing well understood, very competitive!

Storage Depth Capacity

0.1

1

10

100

0 2 4 6 8 10

Array Linear Dimension [mm]

Stor

age

Dep

th in

[us]

at 1

0GSa

/s

Sam

plin

g

4 Chan

8 Chan

16 Chan

32 Chan

Economy of Scale for Quoted ASICs

0.1

1

10

100

1000

10 100 1000 10000 100000 1000000

Total Number of System Channels

Cost

per

Cha

nnel

[200

7 $]

ASIC cost estimate

Based on actual fabrications or quotations from

foundaries

NIM A591 (2008) 534-345.

16

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One example: modular RICH readout

1) FPGA Controller

2) TARGETX both sides

3) Adapter board: Connects PMT to

digitizers

Bottom of adapter board

256 channel PMT connects directly here No extra cabling

2”

2”

Challenge: Readout of compact H13700 MCP-PMT Compact and dense: 256 channels in 2”x2” Timing resolution: ~100ps Long buffer Abutted Photosensors Likely convert to SiPM array later Minimize analog cabling

Solution: 1st gen prototype based on existing TARGETX ASIC:

1GSa/s full waveform sampling 16 us trigger buffer 16 channels Self triggering capability Low cost 250nm CMOS Upgrade to 64-channel SiREAD chip

2 TARGETX/ daughtercard 8 Daughtercards 16 TARGETXs

16x16=256 channels

Incubated at the Manoa Innovation Center Near University of Hawaii

18 About Nalu Scientific

2800 Woodlawn Dr. Ste #298 Honolulu, HI 96822 [email protected] +1 (888) 717-6484

Photo: http://www.myhawaiirealestateonline.com/manoa-real-estate/

mailto:[email protected]

http://www.myhawaiirealestateonline.com/manoa-real-estate/





ASIC designers working hard!

NALU SCIENTIFIC, LLC 19

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Technology has room to improve

J-F Genat, G. Varner, F. Tang, H. Frisch NIM A607 (2009) 387-393.

G. Varner and L. Ruckman NIM A602 (2009) 438-445.

1GHz analog bandwidth, 5GSa/s Simulation includes detector response

Extending to 1ps and lower, with advanced calibration techniques

Measurement: circa 2014

E. Oberla, J-F Genat, H. Grabas, H. Frisch, K. Nishimura, G. Varner

NIM A735 (2014) 452-461.

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Now pushing to the femtosecond regime

And pushing the space-time limit (new type of PID or DIRC devices?)

P. Orel and G. Varner IEEE Trans. Nucl. Sci. 64 (2017) 1950-1962.

P. Orel, G. Varner and P. Niknejadi

NIM A857 (2017) 31-41.

Pushing sampling speed and analog bandwidth

Strategy for Low Power operation • Only power what

actually need • CMOS intrinsically zero

power when idle • Strategy works for

either strip or pixel geometry

• Places to reduce power: Remove FPGA Low-power

processing Single ASIC

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Advanced Low Power Sampler (ALPS) • Initial concept

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Parameter value

Technology node 250nm CMOS

Channels 64

Trigger Channel pairs

Sampling On demand (delay line)

Digitization On demand

Feature extraction On-die option

Power management

On-die

• Wire signal past input to trigger sampling, sample pulse reflected from unterminated delay line

– FWHM 1-2ns, 5-6ns delay line sufficient

Advanced Low Power Sampler (ALPS) • Rather clear what can probably afford

2

Sampling Trigger Digitizing PSEC4

64 channels 64 channels 180 Feature size (nm) 256 samples 1 uA bias 6 Channels

2 gates 2.5 V Vdd 256 Counters per channel 2.5 V Vdd 0.000025 P_tbias per chan 250 Counter clock rate (MHz) 10 fF Cgate 1.6 P_tbias total [mW] 175 Power (mW), from paper 25 fF Cline 30 Quiescent power (mW) 70 Ctot/ch 145 Counter power (mW)

175 dQ [fC] 0.094401 Power per counter (mW) 5 Gsa/s ALPS

19.53125 f Toggle [MHz] 250 Feature size (nm) 875 dI [uA] per channel 64 Channels

56000 dItot [uA] 256 Counters per channel 140 P_samp [mW] 0.252918 Power per counter (mW)

4143.804 Total power (uW) 100 Trigger rate (Hz) 12 Digitized bits

4096 Counter max 0.001638 Digitizing duty cycle

6.8 Average power (mW)

• Recent studies hint can probably do even better, and at lower power (study item)

25

So you are saying…

“Why didn’t you think of the thing nobody ever though of before??”

I don’t know…

ASoC functionality option (trade study) • Could go with low-power u-Processor, or …

26

Photograph, drawing, or diagram of concept.

Sampling/Storage A->D

Pedestal subtract,

linearization, image

processing

Analog Digital

Data processing flow Low power Acquisition

Detector Interconn

/gain ranging

Nalu Scientific


e- 2.6 A

e+ 3.6 A

To get x40 higher luminosity

Colliding bunches

Damping ring

Low emittance gun

Positron source

New beam pipe & bellows

Belle II

New IR

TiN-coated beam pipe with antechambers

Redesign the lattices of HER & LER to squeeze the emittance

Add / modify RF systems for higher beam current

New positron target / capture section

New superconducting /permanent final focusing quads near the IP

Low emittance electrons to inject

Low emittance positrons to inject

Replace short dipoles with longer ones (LER)

KEKB to SuperKEKB

Nano-beams!


Belle II detector upgrade


Thinking toward the future

• Future Circular Collider in China

• LBNE LHC Upgrades ILC


More about Future

• GAPS, new detector development

• JLAB e-Ion Collider ANITA-V


iTOP Production Testing

Laser scan

• 2x Carrier test stations at South Carolina, 1x backup in Hawaii

• Laser test stand Hawaii • SCROD test stand in Pittsburgh • Firmware test at PNNL

Carrier test stand

32


Borehole Muon Prototype


• 4x parallel Motherboard + DC test stations • Final RHIC test station with 2x Scintillating Fiber trackers

ASIC Pre-screened (ASIC check on MB) and

bar-code entered

34


Now have to actually make work…


Now have to actually make work…

>20,000 Channels

id lab personnel 2 visiting scholars ( nalu scientific) 4 postdocs...

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