A RIETHODOLOGY FOR CONVERTING POLYGON BASED STANDARD CELL FROM BULK CIIOS TO SO1

KeV:I: Y. Wu. Philip C. H. C h n

Department of Electrlcal L Electronics Engineering The Hong Kong University of Science L I-echnoloSy

Clear Water Bay, Kowloon, HOng Kong ?hone: 358 - 7082

Area A : Silicon Process Technology & Devices

Introduction The SO1 (Silicon On Insulator) CMOS has many potential advantages over the traditional

bulk CMOS circuit as i t is free of latch-up and has improved performance and a higher packing density [1.3]. The thin film fully depleted SO1 is the most attractive among other types SO1 technologies not only due to its improved property such as subthreshold slope and reduced parasitic, but also due to its simple fabrication process comparing to bulk CMOS [2, 31. It is becoming a viable technology for ULSI due to recent advances i n high-quality thin-film SO1 wafer technology. It has the same layers as bulk CMOS except the well, the substrate contact and the well contact. In this paper we shall present a methodology to convert a polygon based ful l custom bulk CMOS to SOYCMOS. The objective is to convert existing bulk CMOS layout to SO1 automatically. The methodology is implemented using the Virtuoso Layout System from Cadence Design System [l-91. We shall illustrate the methodology using the Orbit Scalable CMOSN standard cell library [ I O ] .

Conversion hkthodology First, the bulk CMOS is

converted to SO1 by removing well, substrate contacts and well contacts. In the next step a compactor is used to remove the unused space while ensuring the design rules are met. Since our goal is to apply our merhodology to hand-crafted full-custom polygon-based layout, we must first convert the polygons to symbolic layout so that i t can be operated by the compactor. The compaction must be done with proper constraints so that the architecture of the standard cells is retained. The entire conversion process is summarized in Figure I .

Note that this methodology can also be applied to further reduce the SOYCMOS cell area because of I ) decreased transistor sizes due to reduced parasitic capacitance; 2) reduced n and p transistor spacing in SOI; 3) reduced power and ground bus width due to decreased current drive if the SOYCMOS is to operate in lower voltage. We can convert the CMOSN standard cell library to SOYCMOS with an arbitrary set of design rules using this methodology and proper scaling of the original bulk CMOSN standard cell layout.

If all layers of the cell are scaled by the same factor, we simply place an instance of the cell with the scaling factor. The placed cell is flattened since our methodology do not support hierarchy. The scaled bulk CMOS standard cell is then converted to SOI/CMOS as shown i n Figure I . Changes in specific design rules can be handled as follows. If only spacing rules are changed and the width rules remain the same, the SO1 cell can be directly converted to SO1 symbolic layout. The compactor will compact the cell based on the layer properties. If the layer widths are also changed, the changed widths can be incorporated by setting the path width in the symbolic layout. The paths will be generated with the proper widths. If rules related to symbolic devices such as the contact enclosure rules need to be scaled, the symbolic rules in the technology file must be modified. After the last step in Figure I , Layout Versus Schematic (LVS) [8 ] is performed to make sure the connectivity of the cell is correct.

The layout conversion process involves the following steps.

Implementation of the hfethodolQgy \\‘e choose to use Cadence Vinuoso Layout System to implement the methodology instead of

writing our own because it has essentially all the features we need and that we can customize the tool to implement the methodology by SKILL calls to the system kernel [6. 71. We can modify the parameters of data object through SKILL calls. Through SKILL calls, we can integrate our applications to the Cadence environment. For this application. three main sets of SKILL functions are used. They are Database Access, Layout Editor Functions and Graphics Editor.

0-7803-2086-7194154 OOC 1994 IEEE. 8

>lost full-custom 1a)outs are constructed using polygons. Polyfons must he converted to symbolic layout hefore i t can be operated by a compactor. We ha\e developed heuristics to convert specific layers from polygon to symbolic depends on the characteristics of each layer. The heuristics are too detailed to be described here. The results are shown in Figure 2.

The Symbolic layout generated from the above conversion is compatible with the Cadence compactor [9]. The compaction is based on the design rules set in the layer property and symbollc rules. There are many compaction heuristics that must be tuned to generate desirable results. The heuristics include many types of constraints such as separation. width and alignment constraints. Hard and soft fences are used to control the relative position within certain area. A soft fence keeps a group of objects together during compaction, but still allows them to be compacted. Objects inside the hard fence retain their relative positions during compaction. They are not compacted relative to each other, but the entire fenced area is compacted relative to objects outside the hard fence. It affects the relationship between the symbolic path that would be eventually flattened to geometry shape during compaction. Wire length minimization is used to guarantee the wire length is minimized. All of the cell pins must remain at the cell boundary throughout the compaction. The result of compaction also depends on individual cell layout.

Results The conversion methodology is illustrated in Figure 2. The cell presented is DEL-2 that has

eight inverters connected in series. Figure 2(a) shows the original bulk CMOS from the Orbit Scalable CMOSN library. Figure 2(b) shows the cell converted to SOI. The SO1 cell is converted to symbolic layout in Figure 2(c). Figure 2(d) shows the compacted cell. The symbolic layout is converted back to polygon in Figure 2(e).

We have experimented the above methodology using five cells. We use the same design rule for both the bulk CMOS cell and SOVCMOS. That is the design rules used i n bulk CMOS are also applied to SOI/CMOS except that there is no well, substrate contact, well contact related design rules. The results are shown in Tables 1 to 3. The first row of Table 1 is the original cell size that is the size of SO1 symbolic cell before compaction. The second row is the cell size after compaction. T h e third row is the percentage reduction of cell area, that is (cell size after compaction - original cell size) / original cell size * 100%.

I

(micron"2) Cell Size After

Compaction (micron"2)

area% Reduction

Item\Cell Name I MUXl I hlUX3 I DEL2 I COMS I DFFR Original Cell Size I 18340 I 34060 I 18340 I 206980 I 23580

14664 3 1796 12675 217412 23023

-20 -6.6 -30.9 +5. I -2.4

9

(micron"2) r original Cell Size I 18340 1 34060 I 18340 I 23580 I

Compaction (micron"2) area% reduction

Net area% reduction coming from scaling

down active area

-23.3 -6.8 -36.5 -7.7 -3.3 -0.2 -5.6 -5.3

ItemWell Name RlUXl hlUX3 DEL2 Original Cell Size 18340 34060 18340

Cell Size after 11241 30750 10980

area% reduced -21.4 -9.7 -37.3

(micron"2)

Compaction (micron"2)

Net area% reduction -2.3 -3.1 -6.4 coming from scaling

down power and ground

Table 3 Compaction results from reducing all power and ground buses by 20%

DFFR 23580

21796

-3.3 -0.9

Conclusion We have developed a methodology to convert polygon-based full-custom bulk CMOS cells to

SOKMOS. This methodology is implemented using the Cadence Design Systems Virtuoso environment. We have demonstrated the methodology by converting the Orbit Scalable CMOSN standard cells. The results are quite good for small cells. However, for complex and highly optimized cell, this methodology may lead to a slight increase in the cell area. We have also demonstrated that this methodology can also be applied to further reduce the cell areas if the SOYCMOS cells are resigned to tale advantage of the low-power and high-performance capability of SOYCMOS.

Acknowledgments The authors wlish to thank Prof. P.K.Ko. Mr. Jack Lau for many useful discussions

REFERENCES [ I ] P.K.Vasudev. "Ultrathin Silicon-On-Insulator for high speed submicrometer CMOS technoloey". Solid-state Technol. PP 61-65. NOV. 1990. [2] K.K.Young. "Analysis of conduction in fully depleted SO1 MOSFETs". IEEE Trans. Electron De\,ices. Vol. 36, PP 504-506, 1989. [3] Colinge, Jean-Pierre. "Silicon-On-Insulator Technology: materials to VLSI". [4] Cadence Design Framework 11, Reference Manual, version 4.2, October 1991. [SI Cadence Technology File, Reference Manual, version 4.2, October IO91 [6] Cadence Skill Reference hlanual, Language Fundamentals, Volume I - 111, version 4.2.2, June I993 [7] Cadence Skill Reference Manual, Custom Layout and Physical Verification, Volume I - 11, version 4.2.2, June 1993 [SI Cadence Diva, Reference Manual, Volume I - 11, version 4.2, January 1992 191 Cadence Virtuoso Compactor. Reference Manual,. version 4.2.1, September 1992. [lo] ChfOSN Cell Notebook. Scalable 2.0 and 1.2 Micron CMOS/BuIk Cell Family. Release 2.0A. Distributed b j Orbit Semiconductor, Inc. August 1989.

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