Low S/D Resistance FDSOI MOSFETs Using Polysilicon and CMP

Chunshan Yin, Victor W.C. Chan, Philip C. H. Chan Dept. of EEE, Hong Kong University of Science and Technology, Clear Water Bay, Hong Kong

Tel: (852)-2358-704 1, Fax: (852)-2358- 1485, e-mail: yincs@ust.hk

Abstract In this paper, we report the fully depleted

silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S / D region. Silicide can be used to further reduce the active resistance.

Index terms - CMOS, MOSFETs, Fully depleted SOI, Poly raised source/drain, CMP.

Introduction Thin body FDSOI is considered to be one

of the potential solutions for the deep sub- micron ULSI era due to good short channel effect (SCE) and low junction capacitance. One of the challenges introduced by thin silicon layer is the extremely high series resistance and contact resistance at the source and drain ( S D ) regions. This is difficult to be reduced by silicide. [ 13

In the past, some researchers reported their raised S/D structures using LOCOS, selective epitaxy growth (SEG) or poly deposition. [2]- [5] LOCOS will introduce large bird’s beak, which diminishes the advantages brought by relative thick S/D; further more, the S/D is not self-aligned to the gate in that structure. Some concerns on SEG, such as poor selectivity between silicon and oxide, the defects caused by dopants, remained as obstacles for production usage.

One of the advantages introduced by poly raised S/D is its independent to the origmal body silicon layer, which makes it more flexible in the process integration. Our experimental results showed that the typical sheet resistance of titanium polycide is 2.2Wsq, which is quite

close to that of silicide (1.6Cl/sq). Previous researchers used photoresist planarization [4] or V-shape gate [5] to implement the self-aligned gate, but all of them lack at least one of the following features: a) source & drain are self- aligned and symmetrical to the gate; b) thicker film for silicidation and not introduce extra parasitic capacitance between the gate and S/D region; c) flat wafer surface to make the subsequent lithography easier and; d) CMOS compatible process.

Device fabrication The fabrication process was summarized in

Fig.1. 189nm SlMOX SO1 film (BOX =360nm) was reduced to 30nm by thermal oxidation and completely oxide removal (Fig. la). LOCOS isolation and Vt adjustment implantation were performed. The gate electrode consisted of lOnm gate oxide, 200nm doped polysilicon and lOOnm cap oxide. This cap oxide protects the poly film during later CMP process. E-beam lithography and plasma etching defined the gate electrode pattern.

Both LPCVD oxide and nitride were deposited and blankly etched to form tail-like oxide spacer (Fig. lb). The nitride was thicker than the later deposited S/D poly, and it was removed using wet method after the tail-like oxide spacer formation. The tail-like oxide spacer acts as an etch stop layer during the subsequent poly etch back. After spacer formation, 801x11 polysilicon was deposited implanted (Fig. IC) and patterned. The thickness of deposited thin poly layer was selected so that it will be totally consumed by silicide. 300nm oxide was deposited to protect the small size gate stack under high stress during CMP process (Fig. Id).

CMP was used to polish away the covered oxide over the gate stack. Fig2 shows the top view of patterns after CMP, which indicated that stress caused by CMP would not break the small size gates protected by thick oxide. After

CMP, oxide etch back was used to further expose the deposited thin poly layer, and the exposed poly was blankly etched to the bottom of tail-like oxide spacer. SEM picture in Fig.3 shows that these poly beside the oxide spacer was totally etched away. The extra parasitic capacitance between gate and S / D , which was introduced by the raised S / D , can be eliminated by this step (Fig. le). Contact opening and metal interconnect were defined in the same manner as conventional CMOS processes. No silicide was processed in this run.

Conventional FDSOI with channel thickness 30nm and PDSOI with channel thickness 134nm were fabricated following standard CMOS SO1 process. Our new structures do not require any extra mask.

Experimental results The NMOS Id-Vg characteristic is shown

in Fig.4. The sub-threshold slope of poly raised NMOS was 65 mv/dec, which was almost the same as the conventional FDSOI devices with same channel thickness, but was much better than the conventional PDSOI. Edge transistors caused the kinks of Id-Vg curves. The threshold voltage roll-off characteristic is shown in Fig. 5. The Vt of the poly-raised structures was close to that of FDSOI devices, but was smaller than that of PDSOI devices due to the thinner channels. It also had less Vt roll off because of less lateral doping diffusion of raised S / D structure. Id-Vd characteristic of NMOS is shown in Fig.6. Better drive current and steeper triode region revealed that the raised S / D structure had less S / D series resistance. In Fig.7, we show well-behaved Id-Vd curve of NMOS with gate length of 0.2um, which further indicates that CMP can be used to polish away the oxide over small size and long width gate. Figs.8-9 show the Idsat and Gmsat dependence on the gate length for different types of MOSFETs. When the gate length scaled down, the drive current became larger and the S / D series resistances became more significant. The short channel device performance would degrade much if the S/D series resistances were too high. The performance of poly raised S / D structure proved its advantages again.

Figs.10-11 show Id-Vg and Id-Vd characteristic of pMOSFET. Same conclusions can be drawn as for nMOSFET.

The extracted series resistance at S / D region are given in Figs.12-13, which were around 250 and 1000R/um for N and PMOS of poly raised structures, respectively. These values were relatively large due to several reasons: 1) the source and drain extension (SDE) doping was not optimized; 2) the distance fiom contact to gate was relatively large (2um), due to the limitation of our lithography system.

Table.1 summarize the performance of MOSFETs fabricated with different technologies. The typical value of measured sheet resistance of poly raised S / D structure were 100 and 400R/sq for n and p-type, respectively; and contact resistance (1.5um* 1 . 5 ~ 1 ) were 50 and 80 Wcontact for n and p-type, respectively. These values were much smaller than that of FDSOI devices with same channel silicon thickness. The series resistance at S / D can be further reduced if silicide is deployed.

Conclusion Both NMOS and PMOS FDSOI with poly

raised S / D were demonstrated. The S / D structure was self-aligned and was achieved using CMP. The tail-like oxide spacer was designed to protect the S / D silicon layer during poly etch back. Well-behaved Id-Vg and Id-Vd characteristics demonstrated that the raised S / D structure had less S / D series resistance. The process was compatible with the existing CMOS processes, including silicidation for further reducing the source/drain series resistance.

Acknowledgement: This research is supported by RGC grant HKUST 6130/00E.

Reference [ 11 Harvey I.Liu et al, IEEE Trans. Electron Devices,

[2] Mansun Chan et al, IEEE Electron Device Lett, Vol.

[3] J.M.Hwang et al, VLSI Tech. Dig, p.33-34, 1994 [4] Y.K. Choi et al., IEDM Tech. Digest, p. 919-921,

[5 ] J. SONLW et al, IEEE Int. SO1 Conference

Vol. 45, p.1099-1104, 1998

15, p.22-24, 1994

1999

proceedings, p120-121,1996

90

Fig. 1 Fabrication process of the proposed structure: (a) conventional FDSOI process with cap oxide; (b) Tail-like oxide spacer formation; (c) Poly deposition; (d) Poly patterning and oxide deposition; (e) CMP, oxide etch back and poly etch back.

Fig. 2 Optical micrographs of poly raised SiD structure after CMP (buffer, L=0.3um, W=30um), which showed that the long gate width and short channel devices could still survive after CMP.

1. OE-05 - 1.OE-07

5 1.OE-09 v

; ~ 1 1.OE-11

1. OE-13

1.OE-15

-Poly raised -Poly raised

-1 0 1 2

vg (V)

Fig. 4 NMOS Id-Vg curves of conventional FD, PDSOI and poly raised S/D SOI. L/W=0.35/10um.

5 0 . 6

2 0 . 4

O m 2 0 * 0 0.2 0.4 0.6 0.8 1

Gate length (um) Fig. 5 NMOS threshold voltage dependence on the channel length, for conventional FD, PDSOI and poly raised S/D SOI.

---- 250 4 IVg-Vt/=O, 0. 5, 1.0, 1. 5, 2. OV __-- 200 -

4 150

100

\ 2 v

3

50

0 0 0.5 1 1.5 2 2.5

Vds (VI Fig. 6 NMOS Id-Vd characteristics of conventional FD, PDSOl and poly raised S/D SOL L/W=0.35/10um.

91

250

200

3 150

100

50

0

- < v

U U

NPMOS FDSOI PDSOI

Poly raised

0 0. 5 1 1. 5 2 2. 5 Vd (V)

Fig. 7 NMOS Id-Vd characteristics of poly raised S/D SO1 MOSFETs. L/W=O.2/lOum

Rs Rc s.s Idsat

204216704 800t2460 65/95 97/36 (!2/cont) (mvldec) (I")

123/132 84/50 87/99 2411151 95/381 58/84 65/94 2021109

160 --. jvg-Vtl=O, 0.5, 1.0, 1.5, 2.ov

120 a 2 80 .. U +-

40

0 -2. 5 -2 -1. 5 -1 -0. 5 0

Vds (V)

Fig. 11 PMOS Id-Vd characteristics of conventional FD, PDSOI and poly raised S/D SOI. L/W=0.35/10um.

I Vg-Vt 1 =2. OV, Vd~2 .5V

\

v

0 0. 2 0. 4 0. 6 0.8 1 Gate length (um)

Fig. 8 Idsat dependence on gate length for three types nMOSFETs. Measured Idsat @ Vg-Ve2.OV, Vds=2.5V.

140 1 Vg-Vt 1 =2. OV, Vds=2.5V I

0 0. 2 0.4 0. 6 0.8 1

Gate l e n g t h (um) Fig. 9 Gmsat dependence on gate length for three types

nMOSFETs. Measured Gmsat @Vg-Vt=2.OV, Vds=2.5V.

1.OE-05

1.OE-07

5 1.OE-09

1.OE-11

1.OE-13

1.OE-15

h

v

Poly raised. \ FDSOI

- - -PDSOI

- -

-2. 5 -1.25 0 1.25

vg (V)

Fig. 10 PMOS Id-Vg curves of conventional FD, PDSOI and poly raised S / D SOI. L/W=0.35/10um.

3.00

2. 50 h 3 2.00 0

1 1.50 t I - m 2 1.00

0. 50

0.00 4 0 0. 1 0. 2 0. 3 0.4 0. 5 0.6

Gate length (um)

Fig. 12 Extracted parasitic S/D series resistance of NMOS W=lOum.

1 Vg-Vt I =O. 8, 1. 2, 1.6V

2 6.00

Poly raised - 4.00 U

0.00 4 1 0 0. 1 0.2 0 . 3 0. 4 0. 5 0.6

Gate length (um)

Fig. 13 Extracted parasitic S/D series resistance of PMOS. W=lOm.

Table 1 Summary of Rs, Rc, S.S and Idsat

~~~~

Note: The MOSFETs demonstrated have Tox=lOnm, L=0.35um. Sub-threshold swing (S.S) was measured at Vds=O. 1V. Idsat was measured at IVg-Vtl=2.0V. The channel thickness of FDSOI, PDSOI and poly raised structure are 30- 134nm and 301x11, respectively.

92