[ieee 2008 ieee international symposium on nanoscale architectures (nanoarch) - anaheim, ca, usa...

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Abstract—This paper starts from very fresh analyses comparing brain’s connectivity with those of well-known network topologies, based on the latest interpretation of Rent’s rule. Those analyses have revealed how close the brain comes to the latest Rent’s rule averages. On the other hand, all the known network topologies seems to fall short of being strong contenders for mimicking the brain. That is why this paper performs a detailed Rent-based (top-down) connectivity analysis of many two-level hybrid network topologies. This analysis aims to identify those two-level hybrid network topologies which are able to closely mimic brain’s connectivity. The ranges of granularity (as given by the total number of gates and the number of processors) where this mimicking is happening are identified. These results should have implications for the design of networks(-on-chip) and for the burgeoning field of multi/many- core processors (in the short to medium term), as well as for investigations on future nano-architectures (in the long run). Complementary results using a bottom-up approach have also been obtained, and will be mentioned. Index Terms—Connectivity, interconnect topology, network topology, communication, nanotechnology, nano-architecture, Rent’s rule, neural network, brain. “Small devices carry small currents and are therefore essentially high-impedance (and low-capacitance) devices, both for outputs and inputs, but electrical transmission is unavoidably low impedance (or high capacitance per unit length).” “the miniaturization of interconnects, unlike transistors, does not enhance their performance” i.e. “How should the interconnect topology look like?” 54 978-1-4244-2553-2/08/$20.00 c 2008 IEEE

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Page 1: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

Abstract—This paper starts from very fresh analysescomparing brain’s connectivity with those of well-knownnetwork topologies, based on the latest interpretation of Rent’srule. Those analyses have revealed how close the brain comes tothe latest Rent’s rule averages. On the other hand, all the knownnetwork topologies seems to fall short of being strong contendersfor mimicking the brain. That is why this paper performs a detailed Rent-based (top-down) connectivity analysis of manytwo-level hybrid network topologies. This analysis aims to identify those two-level hybrid network topologies which are able to closely mimic brain’s connectivity. The ranges of granularity(as given by the total number of gates and the number of processors) where this mimicking is happening are identified.These results should have implications for the design ofnetworks(-on-chip) and for the burgeoning field of multi/many-core processors (in the short to medium term), as well as for investigations on future nano-architectures (in the long run).Complementary results using a bottom-up approach have also been obtained, and will be mentioned.

Index Terms—Connectivity, interconnect topology, networktopology, communication, nanotechnology, nano-architecture,Rent’s rule, neural network, brain.

“Small devices carry small currents and are thereforeessentially high-impedance (and low-capacitance) devices,both for outputs and inputs, but electrical transmission isunavoidably low impedance (or high capacitance per unitlength).”

“the miniaturization of interconnects,unlike transistors, does not enhance their performance”

i.e.

“How should the interconnecttopology look like?”

54

978-1-4244-2553-2/08/$20.00 c©2008 IEEE

Page 2: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

A. Rent’s Rule

NN

pNkN

p p kp

p

“historically-equivalentinterpretation” et al.

N N

RpR NkN

k pk

p

F fan-in

NN

iiF FN

N RpR Nk

FN RpR Nk

F RpR Nk

fan-in p

N pp

fan-in

B. Network Topologies

NN

O N NO N

O N

C. Brain’s Connectivity

(i.e. i.e.

W G

i.e.

N W

N G NG

i.e.

Network(of size N)

Number of connections NCONN (as a function of N)

Cube Connected Cycles (CCC) N

Nlog2N

NlogwN

NlogwN × w

NlogwN w

Nlog2N N

Nlog2 N c

Nlog10N

NlogwN

N log2N

N log2 N w w

Crossbar (XB) N N

2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008) 55

Page 3: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

WG

GW

GW

i.e. N k Np

a cortical (equivalent of) Rent’srule k p

i.e. WG

the brain of humans consumes 20% of the energy, which isvery expensive!

N WG

fain-in fan-outN W G

NN N

NN N

N NN

N

N N

56 2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008)

Page 4: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

k p

NN N

N NN N N

N N

N

D. When Electrons Start Showing Their True Colors

“Our present [1952] treatment of error isunsatisfactory and ad hoc. It is the author’s conviction […]that error should be treated by thermodynamic methods, and be the subject of a thermodynamic theory …”

classicP TkE Bb

approxquantumP bEam

quantumPEVE

EVmaV

aa

a e.g. a La L n n n a

2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008) 57

Page 5: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

Pdevice Pclassic Pquantum PclassicPquantum

Pgate Pdevicen

nPclassic

Pdevice_approx Pdevice

P

wireP

outfanNelectrons

L

a

fan-out

n i.e.

n a

O NO N N O N

i.e.N

N N NN

N

Ni.e. N

Nm

N N m

n n

N N m m m N m N m mN N m m

N n n nn

N N m m + N/m N m mN N m

N

N

N m

N N

N

m N

N m NN m

N mN m

NN m

O N NN

N

N m

58 2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008)

Page 6: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

N fan-in N Ntransistors

2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008) 59

Page 7: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

Ndevices

Nneurons

fan-infan-in

i.e.

n

Proc. Conf. Design Circ. & ICs (DCIS’07)

UAEU Annual Research Conference (ARC-9)

Proc. Intl. Symp. Circ. & Sys. (ISCAS’08)

60 2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008)

Page 8: [IEEE 2008 IEEE International Symposium on Nanoscale Architectures (NANOARCH) - Anaheim, CA, USA (2008.06.12-2008.06.13)] 2008 IEEE International Symposium on Nanoscale Architectures

Proc. Intl. Symp. Info. Electr. Syst. (IES’08)

Proc. Intl. Conf. Embedded Comp. Sys.: Arch., Modeling, & Sim. (IC-SAMOS)International Technology Roadmap for Semiconductors (ITRS)

J. Nanoparticle Res.

PhDdissertation

PhD dissertation

Proc. IEEE

Optics Lett.Proc. Asia &

South Pacific Design Autom. Conf. (ASP-DAC’00)

Proc. IEEE

Comp. in Sci. & Eng.

IEEETrans. Reliab.

Handbook of Nano and Molecular Electronics

EE Times

ACM J. Emerg. Tech. Comp. Sys.

IEEE Trans. Reliab.

IEEE Trans. CAS I

Phys. Lett. A

IEEE Trans. Comp.

IBMMemoranda

IEEE Trans. VLSI Sys.

IBM J. R&D

Proc. Syst.-Level Interconn. Predict. Workshop (SLIP’01)

IEEE Trans. VLSI Syst.

Proc. Intl. Symp.Defect & Fault Tolerance VLSI Sys. (DFT’04)

Proc. Intl. Workshop Sys. Level Interconn. Predict. (SLIP’05)

Proc. Intl. Workshop Syst. Level Interconn. Predict. (SLIP’07)

Topological Structure and Analysis of Interconnection Networks

PLoS Comp.Biol.,

Science

Proc. Natl. Acad. Sci. USA

CANDE’07

Automata Studies

Proc.IEEE

The Computer and the Brain

NeuralInfo. Proc. Sys. NIPS’87

VLSI Interconnects: A DesignPerspective

PhD dissertation

Workshop on On- and Off-ChipInterconn. Nets for Multicore Syst. (OCIN’06)

Proc. Natl. Acad. Sci. PNAS

Proc. Natl. Acad. Sci. PNAS

Neurocomp.

2008 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2008) 61